From b35e888cddbdf382444e598c791c5322deffd4b9 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Mon, 17 Dec 2018 10:35:19 +0800 Subject: [PATCH 01/14] [bsp][stm32] optimize docs --- bsp/stm32/docs/STM32系列BSP添加教程.md | 2 ++ bsp/stm32/docs/figures/linker_scripts.png | Bin 10911 -> 11023 bytes 2 files changed, 2 insertions(+) diff --git a/bsp/stm32/docs/STM32系列BSP添加教程.md b/bsp/stm32/docs/STM32系列BSP添加教程.md index 2ac0f6b48e..4d6f25dc71 100644 --- a/bsp/stm32/docs/STM32系列BSP添加教程.md +++ b/bsp/stm32/docs/STM32系列BSP添加教程.md @@ -129,6 +129,8 @@ STM32 BSP 由三部分组成，分别是 (1) 通用库、(2) BSP 模板和 (3) ![修改启动文件和芯片型号](./figures/SConscript.png) +注意：如果在文件夹中找不到相应系列的 .s 文件，可能是多个系列的芯片重用了相同的启动文件，此时可以在 CubeMX 中生成目标芯片的工程，查看使用了哪个启动文件，然后再修改启动文件名。 + #### 修改工程模板 **template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK4/MDK5/IAR 的工程模板文件，如下图所示： diff --git a/bsp/stm32/docs/figures/linker_scripts.png b/bsp/stm32/docs/figures/linker_scripts.png index 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z#=-Zs1wKxu*{Dd)9CxcFGlYgUf){BjLR`1PI73$$b43r#*8BaeXw3z!?A-c<`^}6c z%)~fJKGv#@{k#~VWa60m=rMb_Vi!1;D*k0+<(b@HCO2X2NpDJh!n~8p$-a^T4c7l7 z?66QWRu-n8cze^=9ps9iFZNueRvKz>ieRGmV^_LQHDM)OfZ>xl2Mn8h9ZCRxL0op5 z46eS`4+0ic)o`^xJ#UNqqUqX08- nef$4g{x`2O{GaPH3S?+OE}zbd1m9|%>t2+etH~9}nEL(~Rzr@P From 71751eb6f1dada410ab404d5ee8ae501db70b022 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Mon, 17 Dec 2018 10:38:15 +0800 Subject: [PATCH 02/14] [bsp][stm32] add sdio, hw_timer and pwm drivers --- bsp/stm32/libraries/HAL_Drivers/SConscript | 16 +- .../HAL_Drivers/config/f1/pwm_config.h | 60 ++ .../HAL_Drivers/config/f1/sdio_config.h | 36 + .../HAL_Drivers/config/f1/tim_config.h | 70 ++ .../HAL_Drivers/config/f4/pwm_config.h | 60 ++ .../HAL_Drivers/config/f4/sdio_config.h | 38 + .../HAL_Drivers/config/f4/tim_config.h | 59 ++ .../HAL_Drivers/config/l4/pwm_config.h | 60 ++ .../HAL_Drivers/config/l4/tim_config.h | 59 ++ bsp/stm32/libraries/HAL_Drivers/drv_config.h | 8 + bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c | 525 +++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_pwm.c | 480 ++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_sdio.c | 846 ++++++++++++++++++ bsp/stm32/libraries/HAL_Drivers/drv_sdio.h | 178 ++++ 14 files changed, 2490 insertions(+), 5 deletions(-) create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_pwm.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_sdio.c create mode 100644 bsp/stm32/libraries/HAL_Drivers/drv_sdio.h diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index c37704bb80..ff0725e3b0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -13,7 +13,13 @@ if GetDepend(['RT_USING_PIN']): if GetDepend(['RT_USING_SERIAL']): src += ['drv_usart.c'] - + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] @@ -22,10 +28,7 @@ if GetDepend(['RT_USING_QSPI']): if GetDepend(['RT_USING_USB_DEVICE']): src += ['drv_usb.c'] - -if GetDepend(['RT_USING_SDCARD']): - src += ['drv_sdcard.c'] - + if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): src += ['drv_soft_i2c.c'] @@ -53,6 +56,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']): if GetDepend(['BSP_USING_WDT']): src += ['drv_wdt.c'] +if GetDepend(['BSP_USING_SDIO']): + src += ['drv_sdio.c'] + src += ['drv_common.c'] path = [cwd] diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h new file mode 100644 index 0000000000..2474460ccd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h new file mode 100644 index 0000000000..5bee78d7fa --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32f1xx_hal.h" + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDIO, \ + .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Channel4, \ + .dma_rx.dma_irq = DMA2_Channel4_IRQn, \ + .dma_tx.Instance = DMA2_Channel4, \ + .dma_tx.dma_irq = DMA2_Channel4_IRQn, \ + } + +#define SPI1_DMA_RX_IRQHandler DMA2_Channel4_IRQHandler +#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h new file mode 100644 index 0000000000..75a3e0b84a --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 2000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM2 +#ifndef TIM2_CONFIG +#define TIM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .tim_irqn = TIM2_IRQn, \ + .name = "timer2", \ + } +#endif /* TIM2_CONFIG */ +#endif /* BSP_USING_TIM2 */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CONFIG +#define TIM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .tim_irqn = TIM3_IRQn, \ + .name = "timer3", \ + } +#endif /* TIM3_CONFIG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM4 +#ifndef TIM4_CONFIG +#define TIM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .tim_irqn = TIM4_IRQn, \ + .name = "timer4", \ + } +#endif /* TIM4_CONFIG */ +#endif /* BSP_USING_TIM4 */ + +#ifdef BSP_USING_TIM5 +#ifndef TIM5_CONFIG +#define TIM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .tim_irqn = TIM5_IRQn, \ + .name = "timer5", \ + } +#endif /* TIM5_CONFIG */ +#endif /* BSP_USING_TIM5 */ + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h new file mode 100644 index 0000000000..2474460ccd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h new file mode 100644 index 0000000000..40f3d03e10 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32f4xx_hal.h" + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDIO, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Stream3, \ + .dma_rx.channel = DMA_CHANNEL_4, \ + .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ + .dma_tx.Instance = DMA2_Stream6, \ + .dma_tx.channel = DMA_CHANNEL_4, \ + .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + } + +#define SPI1_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI1_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h new file mode 100644 index 0000000000..169d07a7a4 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM11 +#ifndef TIM11_CONFIG +#define TIM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \ + .name = "timer11", \ + } +#endif /* TIM11_CONFIG */ +#endif /* BSP_USING_TIM11 */ + +#ifdef BSP_USING_TIM13 +#ifndef TIM13_CONFIG +#define TIM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .tim_irqn = TIM8_UP_TIM13_IRQn, \ + .name = "timer13", \ + } +#endif /* TIM13_CONFIG */ +#endif /* BSP_USING_TIM13 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h new file mode 100644 index 0000000000..2474460ccd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CONFIG +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = 0 \ + } +#endif /* PWM2_CONFIG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CONFIG +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = 0 \ + } +#endif /* PWM3_CONFIG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CONFIG +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = 0 \ + } +#endif /* PWM4_CONFIG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CONFIG +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = 0 \ + } +#endif /* PWM5_CONFIG */ +#endif /* BSP_USING_PWM5 */ + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h new file mode 100644 index 0000000000..fe857cc360 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-12 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 2000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM15 +#ifndef TIM15_CONFIG +#define TIM15_CONFIG \ + { \ + .tim_handle.Instance = TIM15, \ + .tim_irqn = TIM1_BRK_TIM15_IRQn, \ + .name = "timer15", \ + } +#endif /* TIM15_CONFIG */ +#endif /* BSP_USING_TIM15 */ + +#ifdef BSP_USING_TIM16 +#ifndef TIM16_CONFIG +#define TIM16_CONFIG \ + { \ + .tim_handle.Instance = TIM16, \ + .tim_irqn = TIM1_UP_TIM16_IRQn, \ + .name = "timer16", \ + } +#endif /* TIM16_CONFIG */ +#endif /* BSP_USING_TIM16 */ + +#ifdef BSP_USING_TIM17 +#ifndef TIM17_CONFIG +#define TIM17_CONFIG \ + { \ + .tim_handle.Instance = TIM17, \ + .tim_irqn = TIM1_TRG_COM_TIM17_IRQn, \ + .name = "timer17", \ + } +#endif /* TIM17_CONFIG */ +#endif /* BSP_USING_TIM17 */ + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index 5a1aae7b40..1887d12ffa 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -18,14 +18,22 @@ #include "f1/uart_config.h" #include "f1/spi_config.h" #include "f1/adc_config.h" +#include "f1/tim_config.h" +#include "f1/sdio_config.h" +#include "f1/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) #include "f4/uart_config.h" #include "f4/spi_config.h" #include "f4/adc_config.h" +#include "f4/tim_config.h" +#include "f4/sdio_config.h" +#include "f4/pwm_config.h" #elif defined(SOC_SERIES_STM32L4) #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/adc_config.h" +#include "l4/tim_config.h" +#include "l4/pwm_config.h" #endif #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c new file mode 100644 index 0000000000..4f17425d86 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 zylx first version + */ + +#include +#ifdef BSP_USING_TIM +#include "drv_config.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.hwtimer" +#include + +#ifdef RT_USING_HWTIMER +enum +{ +#ifdef BSP_USING_TIM1 + TIM1_INDEX, +#endif +#ifdef BSP_USING_TIM2 + TIM2_INDEX, +#endif +#ifdef BSP_USING_TIM3 + TIM3_INDEX, +#endif +#ifdef BSP_USING_TIM4 + TIM4_INDEX, +#endif +#ifdef BSP_USING_TIM5 + TIM5_INDEX, +#endif +#ifdef BSP_USING_TIM6 + TIM6_INDEX, +#endif +#ifdef BSP_USING_TIM7 + TIM7_INDEX, +#endif +#ifdef BSP_USING_TIM8 + TIM8_INDEX, +#endif +#ifdef BSP_USING_TIM9 + TIM9_INDEX, +#endif +#ifdef BSP_USING_TIM10 + TIM10_INDEX, +#endif +#ifdef BSP_USING_TIM11 + TIM11_INDEX, +#endif +#ifdef BSP_USING_TIM12 + TIM12_INDEX, +#endif +#ifdef BSP_USING_TIM13 + TIM13_INDEX, +#endif +#ifdef BSP_USING_TIM14 + TIM14_INDEX, +#endif +#ifdef BSP_USING_TIM15 + TIM15_INDEX, +#endif +#ifdef BSP_USING_TIM16 + TIM16_INDEX, +#endif +#ifdef BSP_USING_TIM17 + TIM17_INDEX, +#endif +}; + +struct stm32_hwtimer +{ + rt_hwtimer_t time_device; + TIM_HandleTypeDef tim_handle; + IRQn_Type tim_irqn; + char *name; +}; + +static struct stm32_hwtimer stm32_hwtimer_obj[] = +{ +#ifdef BSP_USING_TIM1 + TIM1_CONFIG, +#endif + +#ifdef BSP_USING_TIM2 + TIM2_CONFIG, +#endif + +#ifdef BSP_USING_TIM3 + TIM3_CONFIG, +#endif + +#ifdef BSP_USING_TIM4 + TIM4_CONFIG, +#endif + +#ifdef BSP_USING_TIM5 + TIM5_CONFIG, +#endif + +#ifdef BSP_USING_TIM6 + TIM6_CONFIG, +#endif + +#ifdef BSP_USING_TIM7 + TIM7_CONFIG, +#endif + +#ifdef BSP_USING_TIM8 + TIM8_CONFIG, +#endif + +#ifdef BSP_USING_TIM9 + TIM9_CONFIG, +#endif + +#ifdef BSP_USING_TIM10 + TIM10_CONFIG, +#endif + +#ifdef BSP_USING_TIM11 + TIM11_CONFIG, +#endif + +#ifdef BSP_USING_TIM12 + TIM12_CONFIG, +#endif + +#ifdef BSP_USING_TIM13 + TIM13_CONFIG, +#endif + +#ifdef BSP_USING_TIM14 + TIM14_CONFIG, +#endif + +#ifdef BSP_USING_TIM15 + TIM15_CONFIG, +#endif + +#ifdef BSP_USING_TIM16 + TIM16_CONFIG, +#endif + +#ifdef BSP_USING_TIM17 + TIM17_CONFIG, +#endif +}; + +static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + uint32_t prescaler_value = 0; + TIM_HandleTypeDef *tim = RT_NULL; + struct stm32_hwtimer *tim_device = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + if (state) + { + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + tim_device = (struct stm32_hwtimer *)timer; + + /* time init */ +#if defined(SOC_SERIES_STM32F4) + if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { + prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1; + } + else + { + prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * 2 / 10000) - 1; + } + tim->Init.Period = 10000 - 1; + tim->Init.Prescaler = prescaler_value; + tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + { + tim->Init.CounterMode = TIM_COUNTERMODE_UP; + } + else + { + tim->Init.CounterMode = TIM_COUNTERMODE_DOWN; + } + tim->Init.RepetitionCounter = 0; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) + tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +#endif + if (HAL_TIM_Base_Init(tim) != HAL_OK) + { + LOG_E("%s init failed", tim_device->name); + return; + } + else + { + /* set the TIMx priority */ + HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0); + + /* enable the TIMx global Interrupt */ + HAL_NVIC_EnableIRQ(tim_device->tim_irqn); + + /* clear update flag */ + __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE); + /* enable update request source */ + __HAL_TIM_URS_ENABLE(tim); + + LOG_D("%s init success", tim_device->name); + } + } +} + +static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +{ + rt_err_t result = RT_EOK; + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* set tim cnt */ + __HAL_TIM_SET_AUTORELOAD(tim, t); + + if (opmode == HWTIMER_MODE_ONESHOT) + { + /* set timer to single mode */ + tim->Instance->CR1 |= TIM_OPMODE_SINGLE; + } + + /* start timer */ + if (HAL_TIM_Base_Start_IT(tim) != HAL_OK) + { + LOG_E("TIM2 start failed"); + result = -RT_ERROR; + } + + return result; +} + +static void timer_stop(rt_hwtimer_t *timer) +{ + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* stop timer */ + HAL_TIM_Base_Stop_IT(tim); +} + +static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + TIM_HandleTypeDef *tim = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint16_t val; + + /* set timer frequence */ + freq = *((rt_uint32_t *)arg); + +#if defined(SOC_SERIES_STM32F4) + if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { +#if defined(SOC_SERIES_STM32L4) + val = HAL_RCC_GetPCLK2Freq() / freq; +#else + val = HAL_RCC_GetPCLK2Freq() * 2 / freq; +#endif + } + else + { + val = HAL_RCC_GetPCLK1Freq() * 2 / freq; + } + __HAL_TIM_SET_PRESCALER(tim, val - 1); + + /* Update frequency value */ + tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE; + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +{ + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + return tim->Instance->CNT; +} + +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; + +static const struct rt_hwtimer_ops _ops = +{ + .init = timer_init, + .start = timer_start, + .stop = timer_stop, + .count_get = timer_counter_get, + .control = timer_ctrl, +}; + +#ifdef BSP_USING_TIM2 +void TIM2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM3 +void TIM3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM4 +void TIM4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM5 +void TIM5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM11 +void TIM1_TRG_COM_TIM11_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM13 +void TIM8_UP_TIM13_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM14 +void TIM8_TRG_COM_TIM14_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM15 +void TIM1_BRK_TIM15_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM16 +void TIM1_UP_TIM16_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM17 +void TIM1_TRG_COM_TIM17_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ +#ifdef BSP_USING_TIM2 + if (htim->Instance == TIM2) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM3 + if (htim->Instance == TIM3) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM4 + if (htim->Instance == TIM4) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM5 + if (htim->Instance == TIM5) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM11 + if (htim->Instance == TIM11) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM13 + if (htim->Instance == TIM13) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM14 + if (htim->Instance == TIM14) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM15 + if (htim->Instance == TIM15) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM16 + if (htim->Instance == TIM16) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device); + } +#endif +#ifdef BSP_USING_TIM17 + if (htim->Instance == TIM17) + { + rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device); + } +#endif +} + +static int stm32_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++) + { + stm32_hwtimer_obj[i].time_device.info = &_info; + stm32_hwtimer_obj[i].time_device.ops = &_ops; + if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK) + { + LOG_D("%s register success", stm32_hwtimer_obj[i].name); + } + else + { + LOG_E("%s register failed", stm32_hwtimer_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(stm32_hwtimer_init); + +#endif /* RT_USING_HWTIMER */ +#endif /* BSP_USING_TIM */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c new file mode 100644 index 0000000000..5fa290c1bb --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c @@ -0,0 +1,480 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + */ + +#include +#ifdef RT_USING_PWM +#include "drv_config.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.pwm" +#include + +#define MAX_PERIOD 65535 +#define MIN_PERIOD 3 +#define MIN_PULSE 2 + +extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +enum +{ +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + PWM7_INDEX, +#endif +#ifdef BSP_USING_PWM8 + PWM8_INDEX, +#endif +#ifdef BSP_USING_PWM9 + PWM9_INDEX, +#endif +#ifdef BSP_USING_PWM10 + PWM10_INDEX, +#endif +#ifdef BSP_USING_PWM11 + PWM11_INDEX, +#endif +#ifdef BSP_USING_PWM12 + PWM12_INDEX, +#endif +#ifdef BSP_USING_PWM13 + PWM13_INDEX, +#endif +#ifdef BSP_USING_PWM14 + PWM14_INDEX, +#endif +#ifdef BSP_USING_PWM15 + PWM15_INDEX, +#endif +#ifdef BSP_USING_PWM16 + PWM16_INDEX, +#endif +#ifdef BSP_USING_PWM17 + PWM17_INDEX, +#endif +}; + +struct stm32_pwm +{ + struct rt_device_pwm pwm_device; + TIM_HandleTypeDef tim_handle; + rt_uint8_t channel; + char *name; +}; + +static struct stm32_pwm stm32_pwm_obj[] = +{ +#ifdef BSP_USING_PWM1 + PWM1_CONFIG, +#endif + +#ifdef BSP_USING_PWM2 + PWM2_CONFIG, +#endif + +#ifdef BSP_USING_PWM3 + PWM3_CONFIG, +#endif + +#ifdef BSP_USING_PWM4 + PWM4_CONFIG, +#endif + +#ifdef BSP_USING_PWM5 + PWM5_CONFIG, +#endif + +#ifdef BSP_USING_PWM6 + PWM6_CONFIG, +#endif + +#ifdef BSP_USING_PWM7 + PWM7_CONFIG, +#endif + +#ifdef BSP_USING_PWM8 + PWM8_CONFIG, +#endif + +#ifdef BSP_USING_PWM9 + PWM9_CONFIG, +#endif + +#ifdef BSP_USING_PWM10 + PWM10_CONFIG, +#endif + +#ifdef BSP_USING_PWM11 + PWM11_CONFIG, +#endif + +#ifdef BSP_USING_PWM12 + PWM12_CONFIG, +#endif + +#ifdef BSP_USING_PWM13 + PWM13_CONFIG, +#endif + +#ifdef BSP_USING_PWM14 + PWM14_CONFIG, +#endif + +#ifdef BSP_USING_PWM15 + PWM15_CONFIG, +#endif + +#ifdef BSP_USING_PWM16 + PWM16_CONFIG, +#endif + +#ifdef BSP_USING_PWM17 + PWM17_CONFIG, +#endif +}; + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static struct rt_pwm_ops drv_ops = +{ + drv_pwm_control +}; + +static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + /* Converts the channel number to the channel number of Hal library */ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + + if (!enable) + { + HAL_TIM_PWM_Stop(htim, channel); + } + else + { + HAL_TIM_PWM_Start(htim, channel); + } + + return RT_EOK; +} + +static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) +{ + /* Converts the channel number to the channel number of Hal library */ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + rt_uint64_t tim_clock; + +#if defined(SOC_SERIES_STM32F4) + if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { + tim_clock = HAL_RCC_GetPCLK2Freq() * 2; + } + else + { +#if defined(SOC_SERIES_STM32L4) + tim_clock = HAL_RCC_GetPCLK1Freq(); +#else + tim_clock = HAL_RCC_GetPCLK1Freq() * 2; +#endif + } + + if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) + { + tim_clock = tim_clock / 2; + } + else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4) + { + tim_clock = tim_clock / 4; + } + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; + configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; + + return RT_EOK; +} + +static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t tim_clock, psc; + /* Converts the channel number to the channel number of Hal library */ + rt_uint32_t channel = 0x04 * (configuration->channel - 1); + +#if defined(SOC_SERIES_STM32F4) + if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11) +#elif defined(SOC_SERIES_STM32L4) + if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17) +#elif defined(SOC_SERIES_STM32F1) + if (0) +#endif + { + tim_clock = HAL_RCC_GetPCLK2Freq() * 2; + } + else + { +#if defined(SOC_SERIES_STM32L4) + tim_clock = HAL_RCC_GetPCLK1Freq(); +#else + tim_clock = HAL_RCC_GetPCLK1Freq() * 2; +#endif + } + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL ; + psc = period / MAX_PERIOD + 1; + period = period / psc; + __HAL_TIM_SET_PRESCALER(htim, psc - 1); + + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + __HAL_TIM_SET_AUTORELOAD(htim, period - 1); + + pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1); + __HAL_TIM_SET_COUNTER(htim, 0); + + /* Update frequency value */ + HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE); + + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(htim, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(htim, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(htim, configuration); + case PWM_CMD_GET: + return drv_pwm_get(htim, configuration); + default: + return RT_EINVAL; + } +} + +static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device) +{ + rt_err_t result = RT_EOK; + TIM_HandleTypeDef *tim = RT_NULL; + TIM_OC_InitTypeDef oc_config = {0}; + TIM_MasterConfigTypeDef master_config = {0}; + TIM_ClockConfigTypeDef clock_config = {0}; + + RT_ASSERT(device != RT_NULL); + + tim = (TIM_HandleTypeDef *)&device->tim_handle; + + /* configure the timer to pwm mode */ + tim->Init.Prescaler = 0; + tim->Init.CounterMode = TIM_COUNTERMODE_UP; + tim->Init.Period = 0; + tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) + tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +#endif + if (HAL_TIM_Base_Init(tim) != HAL_OK) + { + LOG_E("%s time base init failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK) + { + LOG_E("%s clock init failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + if (HAL_TIM_PWM_Init(tim) != HAL_OK) + { + LOG_E("%s pwm init failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + master_config.MasterOutputTrigger = TIM_TRGO_RESET; + master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK) + { + LOG_E("%s master config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + + oc_config.OCMode = TIM_OCMODE_PWM1; + oc_config.Pulse = 0; + oc_config.OCPolarity = TIM_OCPOLARITY_HIGH; + oc_config.OCFastMode = TIM_OCFAST_DISABLE; + + /* config pwm channel */ + if (device->channel & 0x01) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK) + { + LOG_E("%s channel1 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + if (device->channel & 0x02) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK) + { + LOG_E("%s channel2 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + if (device->channel & 0x04) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK) + { + LOG_E("%s channel3 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + if (device->channel & 0x08) + { + if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK) + { + LOG_E("%s channel4 config failed", device->name); + result = -RT_ERROR; + goto __exit; + } + } + + /* pwm pin configuration */ + HAL_TIM_MspPostInit(tim); + + /* enable update request source */ + __HAL_TIM_URS_ENABLE(tim); + +__exit: + return result; +} + +static void pwm_get_channel(void) +{ +#ifdef BSP_USING_PWM2_CH4 + stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3; +#endif +#ifdef BSP_USING_PWM3_CH1 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0; +#endif +#ifdef BSP_USING_PWM3_CH2 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM3_CH3 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2; +#endif +#ifdef BSP_USING_PWM3_CH4 + stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3; +#endif +#ifdef BSP_USING_PWM4_CH2 + stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM4_CH3 + stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2; +#endif +#ifdef BSP_USING_PWM5_CH1 + stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM5_CH2 + stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2; +#endif +#ifdef BSP_USING_PWM5_CH3 + stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3; +#endif +} + +static int stm32_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + pwm_get_channel(); + + for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++) + { + /* pwm init */ + if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", stm32_pwm_obj[i].name); + result = -RT_ERROR; + goto __exit; + } + else + { + LOG_D("%s init success", stm32_pwm_obj[i].name); + + /* register pwm device */ + if (rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK) + { + + LOG_D("%s register success", stm32_pwm_obj[i].name); + } + else + { + LOG_E("%s register failed", stm32_pwm_obj[i].name); + result = -RT_ERROR; + } + } + } + +__exit: + return result; +} +INIT_DEVICE_EXPORT(stm32_pwm_init); +#endif /* RT_USING_PWM */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c new file mode 100644 index 0000000000..f2d6867343 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-06-22 tyx first + * 2018-12-12 balanceTWK change to new framework + */ + +#include "board.h" +#include "drv_sdio.h" +#include "drv_config.h" + +#ifdef BSP_USING_SDIO + +//#define DRV_DEBUG +#define LOG_TAG "drv.sdio" +#include + +static struct stm32_sdio_config sdio_config = SDIO_BUS_CONFIG; +static struct stm32_sdio_class sdio_obj; +static struct rt_mmcsd_host *host; + +#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000) + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct stm32_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +ALIGN(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; + +static rt_uint32_t stm32_sdio_clk_get(struct stm32_sdio *hw_sdio) +{ + return SDIO_CLOCK_FREQ; +} + +/** + * @brief This function get order from sdio. + * @param data + * @retval sdio order + */ +static int get_order(rt_uint32_t data) +{ + int order = 0; + + switch (data) + { + case 1: + order = 0; + break; + case 2: + order = 1; + break; + case 4: + order = 2; + break; + case 8: + order = 3; + break; + case 16: + order = 4; + break; + case 32: + order = 5; + break; + case 64: + order = 6; + break; + case 128: + order = 7; + break; + case 256: + order = 8; + break; + case 512: + order = 9; + break; + case 1024: + order = 10; + break; + case 2048: + order = 11; + break; + case 4096: + order = 12; + break; + case 8192: + order = 13; + break; + case 16384: + order = 14; + break; + default : + order = 0; + break; + } + + return order; +} + +/** + * @brief This function wait sdio completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + cmd->resp[0] = hw_sdio->resp1; + cmd->resp[1] = hw_sdio->resp2; + cmd->resp[2] = hw_sdio->resp3; + cmd->resp[3] = hw_sdio->resp4; + + if (status & HW_SDIO_ERRORS) + { + if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & HW_SDIO_IT_CTIMEOUT) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & HW_SDIO_IT_DCRCFAIL) + { + data->err = -RT_ERROR; + } + + if (status & HW_SDIO_IT_DTIMEOUT) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "", + status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "", + status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "", + status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "", + status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "", + status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "", + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + } + } + else +{ + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function transfer data by dma. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_data *data; + int size; + void *buff; + struct stm32_sdio *hw_sdio; + + if ((RT_NULL == pkg) || (RT_NULL == sdio)) + { + LOG_E("rthw_sdio_transfer_by_dma invalid args"); + return; + } + + data = pkg->cmd->data; + if (RT_NULL == data) + { + LOG_E("rthw_sdio_transfer_by_dma invalid args"); + return; + } + + buff = pkg->buff; + if (RT_NULL == buff) + { + LOG_E("rthw_sdio_transfer_by_dma invalid args"); + return; + } + hw_sdio = sdio->sdio_des.hw_sdio; + size = data->blks * data->blksize; + + if (data->flags & DATA_DIR_WRITE) + { + sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size); + hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE; + } + else if (data->flags & DATA_DIR_READ) + { + sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size); + hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE; + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + + /* config cmd reg */ + reg_cmd = cmd->cmd_code | HW_SDIO_CPSM_ENABLE; + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= HW_SDIO_RESPONSE_NO; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= HW_SDIO_RESPONSE_LONG; + else + reg_cmd |= HW_SDIO_RESPONSE_SHORT; + + /* config data reg */ + if (data != RT_NULL) +{ + rt_uint32_t dir = 0; + rt_uint32_t size = data->blks * data->blksize; + int order; + + hw_sdio->dctrl = 0; + hw_sdio->dtimer = HW_SDIO_DATATIMEOUT; + hw_sdio->dlen = size; + order = get_order(data->blksize); + dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0; + hw_sdio->dctrl = HW_SDIO_IO_ENABLE | (order << 4) | dir; + } + + /* transfer config */ + if (data != RT_NULL) + { + rthw_sdio_transfer_by_dma(sdio, pkg); + } + + /* open irq */ + hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS; + if (data != RT_NULL) + { + hw_sdio->mask |= HW_SDIO_IT_DATAEND; + } + + /* send cmd */ + hw_sdio->arg = cmd->arg; + hw_sdio->cmd = reg_cmd; + + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* Waiting for data to be sent to completion */ + if (data != RT_NULL) + { + volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS; + + while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT))) + { + count--; + } + + if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS)) + { + cmd->err = -RT_ERROR; + } + } + + /* close irq, keep sdio irq */ + hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00; + + /* clear pkg */ + sdio->pkg = RT_NULL; +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + pkg.buff = data->buf; + if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) + { + pkg.buff = cache_buf; + if (data->flags & DATA_DIR_WRITE) + { + memcpy(cache_buf, data->buf, size); + } + } + } + + rthw_sdio_send_command(sdio, &pkg); + + if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) + { + memcpy(data->buf, cache_buf, data->blksize * data->blks); + } + } + + if (req->stop != RT_NULL) + { + memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t clkcr, div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); + if (clk_src < 400 * 1000) + { + LOG_E("The clock rate is too low! rata:%d", clk_src); + return; + } + + if (clk > host->freq_max) clk = host->freq_max; + + if (clk > clk_src) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = clk_src; + } + + LOG_D("clk:%d width:%s%s%s power:%s%s%s", + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "" + ); + + RTHW_SDIO_LOCK(sdio); + + div = clk_src / clk; + if ((clk == 0) || (div == 0)) + { + clkcr = 0; + } + else + { + if (div < 2) + { + div = 2; + } + else if (div > 0xFF) + { + div = 0xFF; + } + div -= 2; + clkcr = div | HW_SDIO_CLK_ENABLE; + } + + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + clkcr |= HW_SDIO_BUSWIDE_8B; + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + clkcr |= HW_SDIO_BUSWIDE_4B; + } + else + { + clkcr |= HW_SDIO_BUSWIDE_1B; + } + + hw_sdio->clkcr = clkcr; + + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + hw_sdio->power = HW_SDIO_POWER_OFF; + break; + case MMCSD_POWER_UP: + hw_sdio->power = HW_SDIO_POWER_UP; + break; + case MMCSD_POWER_ON: + hw_sdio->power = HW_SDIO_POWER_ON; + break; + default: + LOG_W("unknown power_mode %d", io_cfg->power_mode); + break; + } + + RTHW_SDIO_UNLOCK(sdio); +} + +/** + * @brief This function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + + if (enable) + { + LOG_D("enable sdio irq"); + hw_sdio->mask |= HW_SDIO_IT_SDIOIT; + } + else + { + LOG_D("disable sdio irq"); + hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT; + } +} + +/** + * @brief This function delect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + int complete = 0; + struct rthw_sdio *sdio = host->private_data; + struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->sta; + + if (intstatus & HW_SDIO_ERRORS) + { + hw_sdio->icr = HW_SDIO_ERRORS; + complete = 1; + } + else + { + if (intstatus & HW_SDIO_IT_CMDREND) + { + hw_sdio->icr = HW_SDIO_IT_CMDREND; + + if (sdio->pkg != RT_NULL) + { + if (!sdio->pkg->cmd->data) + { + complete = 1; + } + else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE)) + { + hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE; + } + } + } + + if (intstatus & HW_SDIO_IT_CMDSENT) + { + hw_sdio->icr = HW_SDIO_IT_CMDSENT; + + if (resp_type(sdio->pkg->cmd) == RESP_NONE) + { + complete = 1; + } + } + + if (intstatus & HW_SDIO_IT_DATAEND) + { + hw_sdio->icr = HW_SDIO_IT_DATAEND; + complete = 1; + } + } + + if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT)) + { + hw_sdio->icr = HW_SDIO_IT_SDIOIT; + sdio_irq_wakeup(host); + } + + if (complete) + { + hw_sdio->mask &= ~HW_SDIO_ERRORS; + rt_event_send(&sdio->event, intstatus); + } +} + +static const struct rt_mmcsd_host_ops ops = +{ + rthw_sdio_request, + rthw_sdio_iocfg, + rthw_sd_delect, + rthw_sdio_irq_update, +}; + +/** + * @brief This function create mmcsd host. + * @param sdio_des stm32_sdio_des + * @retval rt_mmcsd_host + */ +struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + { + LOG_E("L:%d F:%s %s %s %s", + (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), + (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "") + ); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des)); + sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct stm32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio); + sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? stm32_sdio_clk_get : sdio_des->clk_get); + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + + /* set host defautl attributes */ + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */ +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rthw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +/** + * @brief This function configures the DMATX. + * @param BufferSRC: pointer to the source buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) +{ +#if defined(SOC_SERIES_STM32F1) + static uint32_t size = 0; + size += BufferSize * 4; + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + /* DMA_PFCTRL */ + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#else + static uint32_t size = 0; + size += BufferSize * 4; + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel; + sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; + sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; + /* DMA_PFCTRL */ + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#endif +} + +/** + * @brief This function configures the DMARX. + * @param BufferDST: pointer to the destination buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) +{ +#if defined(SOC_SERIES_STM32F1) + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Direction = DMA_PERIPH_TO_MEMORY; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#else + sdio_obj.cfg = &sdio_config; + sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance; + sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel; + sdio_obj.dma.handle_tx.Init.Direction = DMA_PERIPH_TO_MEMORY; + sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE; + sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE; + sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL; + sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4; + sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; + + HAL_DMA_DeInit(&sdio_obj.dma.handle_tx); + HAL_DMA_Init(&sdio_obj.dma.handle_tx); + + HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize); +#endif + +} + +/** + * @brief This function get stm32 sdio clock. + * @param hw_sdio: stm32_sdio + * @retval PCLK2Freq + */ +static rt_uint32_t stm32_sdio_clock_get(struct stm32_sdio *hw_sdio) +{ + return HAL_RCC_GetPCLK2Freq(); +} + +static rt_err_t DMA_TxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size) +{ + SD_LowLevel_DMA_TxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4); + return RT_EOK; +} + +static rt_err_t DMA_RxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size) +{ + SD_LowLevel_DMA_RxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4); + return RT_EOK; +} + +void SDIO_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct stm32_sdio_des sdio_des; + SD_HandleTypeDef hsd; + hsd.Instance = SDIO; + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc); +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) + SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc); +#endif + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDIO_IRQn); + HAL_SD_MspInit(&hsd); + + sdio_des.clk_get = stm32_sdio_clock_get; + sdio_des.hw_sdio = (struct stm32_sdio *)SDIO; + sdio_des.rxconfig = DMA_RxConfig; + sdio_des.txconfig = DMA_TxConfig; + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return -1; + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h new file mode 100644 index 0000000000..f0b3cdb347 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef _DRV_SDIO_H +#define _DRV_SDIO_H +#include +#include "rtdevice.h" +#include +#include +#include "drv_dma.h" +#include +#include +#include + +#define SDIO_BUFF_SIZE 4096 +#define SDIO_MAX_FREQ 2000000 +#define SDIO_ALIGN_LEN 32 + +#ifndef SDIO_BASE_ADDRESS +#define SDIO_BASE_ADDRESS (0x40012800U) +#endif + +#ifndef SDIO_CLOCK_FREQ +#define SDIO_CLOCK_FREQ (48U * 1000 * 1000) +#endif + +#ifndef SDIO_BUFF_SIZE +#define SDIO_BUFF_SIZE (4096) +#endif + +#ifndef SDIO_ALIGN_LEN +#define SDIO_ALIGN_LEN (32) +#endif + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (24 * 1000 * 1000) +#endif + +#define HW_SDIO_IT_CCRCFAIL (0x01U << 0) +#define HW_SDIO_IT_DCRCFAIL (0x01U << 1) +#define HW_SDIO_IT_CTIMEOUT (0x01U << 2) +#define HW_SDIO_IT_DTIMEOUT (0x01U << 3) +#define HW_SDIO_IT_TXUNDERR (0x01U << 4) +#define HW_SDIO_IT_RXOVERR (0x01U << 5) +#define HW_SDIO_IT_CMDREND (0x01U << 6) +#define HW_SDIO_IT_CMDSENT (0x01U << 7) +#define HW_SDIO_IT_DATAEND (0x01U << 8) +#define HW_SDIO_IT_STBITERR (0x01U << 9) +#define HW_SDIO_IT_DBCKEND (0x01U << 10) +#define HW_SDIO_IT_CMDACT (0x01U << 11) +#define HW_SDIO_IT_TXACT (0x01U << 12) +#define HW_SDIO_IT_RXACT (0x01U << 13) +#define HW_SDIO_IT_TXFIFOHE (0x01U << 14) +#define HW_SDIO_IT_RXFIFOHF (0x01U << 15) +#define HW_SDIO_IT_TXFIFOF (0x01U << 16) +#define HW_SDIO_IT_RXFIFOF (0x01U << 17) +#define HW_SDIO_IT_TXFIFOE (0x01U << 18) +#define HW_SDIO_IT_RXFIFOE (0x01U << 19) +#define HW_SDIO_IT_TXDAVL (0x01U << 20) +#define HW_SDIO_IT_RXDAVL (0x01U << 21) +#define HW_SDIO_IT_SDIOIT (0x01U << 22) + +#define HW_SDIO_ERRORS \ + (HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \ + HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \ + HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR) + +#define HW_SDIO_POWER_OFF (0x00U) +#define HW_SDIO_POWER_UP (0x02U) +#define HW_SDIO_POWER_ON (0x03U) + +#define HW_SDIO_FLOW_ENABLE (0x01U << 14) +#define HW_SDIO_BUSWIDE_1B (0x00U << 11) +#define HW_SDIO_BUSWIDE_4B (0x01U << 11) +#define HW_SDIO_BUSWIDE_8B (0x02U << 11) +#define HW_SDIO_BYPASS_ENABLE (0x01U << 10) +#define HW_SDIO_IDLE_ENABLE (0x01U << 9) +#define HW_SDIO_CLK_ENABLE (0x01U << 8) + +#define HW_SDIO_SUSPEND_CMD (0x01U << 11) +#define HW_SDIO_CPSM_ENABLE (0x01U << 10) +#define HW_SDIO_WAIT_END (0x01U << 9) +#define HW_SDIO_WAIT_INT (0x01U << 8) +#define HW_SDIO_RESPONSE_NO (0x00U << 6) +#define HW_SDIO_RESPONSE_SHORT (0x01U << 6) +#define HW_SDIO_RESPONSE_LONG (0x03U << 6) + +#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU) + +#define HW_SDIO_IO_ENABLE (0x01U << 11) +#define HW_SDIO_RWMOD_CK (0x01U << 10) +#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9) +#define HW_SDIO_RWSTART_ENABLE (0x01U << 8) +#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4) +#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4) +#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4) +#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4) +#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4) +#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4) +#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4) +#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4) +#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4) +#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4) +#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4) +#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4) +#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4) +#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4) +#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4) +#define HW_SDIO_DMA_ENABLE (0x01U << 3) +#define HW_SDIO_STREAM_ENABLE (0x01U << 2) +#define HW_SDIO_TO_HOST (0x01U << 1) +#define HW_SDIO_DPSM_ENABLE (0x01U << 0) + +#define HW_SDIO_DATATIMEOUT (0xF0000000U) + +struct stm32_sdio +{ + volatile rt_uint32_t power; + volatile rt_uint32_t clkcr; + volatile rt_uint32_t arg; + volatile rt_uint32_t cmd; + volatile rt_uint32_t respcmd; + volatile rt_uint32_t resp1; + volatile rt_uint32_t resp2; + volatile rt_uint32_t resp3; + volatile rt_uint32_t resp4; + volatile rt_uint32_t dtimer; + volatile rt_uint32_t dlen; + volatile rt_uint32_t dctrl; + volatile rt_uint32_t dcount; + volatile rt_uint32_t sta; + volatile rt_uint32_t icr; + volatile rt_uint32_t mask; + volatile rt_uint32_t reserved0[2]; + volatile rt_uint32_t fifocnt; + volatile rt_uint32_t reserved1[13]; + volatile rt_uint32_t fifo; +}; + +typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size); +typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio); + +struct stm32_sdio_des +{ + struct stm32_sdio *hw_sdio; + dma_txconfig txconfig; + dma_rxconfig rxconfig; + sdio_clk_get clk_get; +}; + +struct stm32_sdio_config +{ + SDIO_TypeDef *Instance; + struct dma_config dma_rx, dma_tx; +}; + +/* stm32 sdio dirver class */ +struct stm32_sdio_class +{ + struct stm32_sdio_des *des; + const struct stm32_sdio_config *cfg; + struct rt_mmcsd_host host; + struct + { + DMA_HandleTypeDef handle_rx; + DMA_HandleTypeDef handle_tx; + } dma; +}; + +#endif From ba83d6c90e6eea4b7d3368c56bf17eee740ac71e Mon Sep 17 00:00:00 2001 From: SummerGift Date: Mon, 17 Dec 2018 10:44:30 +0800 Subject: [PATCH 03/14] [bsp][stm32] add stm32l475-atk-pandora bsp --- bsp/stm32/stm32f103-atk-nano/.config | 38 +- .../board/CubeMX_Config/Inc/main.h | 2 + .../CubeMX_Config/Inc/stm32f1xx_hal_conf.h | 2 +- .../board/CubeMX_Config/Src/main.c | 165 +- .../CubeMX_Config/Src/stm32f1xx_hal_msp.c | 123 +- .../board/CubeMX_Config/stm32f103rbt6.ioc | 52 +- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 38 +- bsp/stm32/stm32f103-atk-nano/board/board.c | 13 +- bsp/stm32/stm32f103-atk-nano/rtconfig.h | 13 +- bsp/stm32/stm32f103-fire-arbitrary/.config | 42 +- .../board/CubeMX_Config/.mxproject | 8 +- .../board/CubeMX_Config/Inc/main.h | 2 + .../CubeMX_Config/Inc/stm32f1xx_hal_conf.h | 4 +- .../board/CubeMX_Config/Src/main.c | 256 ++ .../CubeMX_Config/Src/stm32f1xx_hal_msp.c | 230 +- .../board/CubeMX_Config/stm32f103zet6.ioc | 93 +- .../stm32f103-fire-arbitrary/board/Kconfig | 68 + .../stm32f103-fire-arbitrary/board/SConscript | 3 + .../stm32f103-fire-arbitrary/board/board.c | 61 +- bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h | 13 +- bsp/stm32/stm32f407-atk-explorer/.config | 20 +- .../board/CubeMX_Config/.mxproject | 4 +- .../board/CubeMX_Config/CubeMX_Config.ioc | 119 +- .../board/CubeMX_Config/Inc/main.h | 2 + .../CubeMX_Config/Inc/stm32f4xx_hal_conf.h | 4 +- .../board/CubeMX_Config/Src/main.c | 245 +- .../CubeMX_Config/Src/stm32f4xx_hal_msp.c | 286 +- .../stm32f407-atk-explorer/board/Kconfig | 53 +- .../stm32f407-atk-explorer/board/SConscript | 3 + .../stm32f407-atk-explorer/board/board.c | 56 +- bsp/stm32/stm32f407-atk-explorer/rtconfig.h | 10 +- bsp/stm32/stm32f429-atk-apollo/.config | 40 +- .../board/CubeMX_Config/.mxproject | 8 +- .../board/CubeMX_Config/Inc/main.h | 2 + .../CubeMX_Config/Inc/stm32f4xx_hal_conf.h | 6 +- .../board/CubeMX_Config/STM32F429IG.ioc | 212 +- .../board/CubeMX_Config/Src/main.c | 333 +- .../CubeMX_Config/Src/stm32f4xx_hal_msp.c | 400 ++- bsp/stm32/stm32f429-atk-apollo/board/Kconfig | 52 +- .../stm32f429-atk-apollo/board/SConscript | 3 + bsp/stm32/stm32f429-atk-apollo/board/board.c | 46 +- bsp/stm32/stm32f429-atk-apollo/rtconfig.h | 13 +- bsp/stm32/stm32f429-fire-challenger/.config | 41 +- .../board/CubeMX_Config/.mxproject | 8 +- .../board/CubeMX_Config/CubeMX_Config.ioc | 116 +- .../board/CubeMX_Config/Inc/main.h | 2 + .../CubeMX_Config/Inc/stm32f4xx_hal_conf.h | 4 +- .../board/CubeMX_Config/Src/main.c | 211 +- .../CubeMX_Config/Src/stm32f4xx_hal_msp.c | 234 +- .../stm32f429-fire-challenger/board/Kconfig | 67 +- .../board/SConscript | 3 + .../stm32f429-fire-challenger/board/board.c | 14 +- .../stm32f429-fire-challenger/rtconfig.h | 13 +- bsp/stm32/stm32l475-atk-pandora/.config | 364 +++ bsp/stm32/stm32l475-atk-pandora/.gitignore | 42 + bsp/stm32/stm32l475-atk-pandora/Kconfig | 21 + bsp/stm32/stm32l475-atk-pandora/README.md | 142 + bsp/stm32/stm32l475-atk-pandora/SConscript | 14 + bsp/stm32/stm32l475-atk-pandora/SConstruct | 58 + .../applications/SConscript | 9 + .../stm32l475-atk-pandora/applications/main.c | 24 + .../board/CubeMX_Config/.mxproject | 13 + .../board/CubeMX_Config/Inc/main.h | 93 + .../CubeMX_Config/Inc/stm32l4xx_hal_conf.h | 434 +++ .../board/CubeMX_Config/Inc/stm32l4xx_it.h | 84 + .../board/CubeMX_Config/STM32L475VE.ioc | 261 ++ .../board/CubeMX_Config/Src/main.c | 777 +++++ .../CubeMX_Config/Src/stm32l4xx_hal_msp.c | 660 ++++ .../board/CubeMX_Config/Src/stm32l4xx_it.c | 217 ++ .../CubeMX_Config/Src/system_stm32l4xx.c | 353 ++ bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 210 ++ .../stm32l475-atk-pandora/board/SConscript | 37 + bsp/stm32/stm32l475-atk-pandora/board/board.c | 85 + bsp/stm32/stm32l475-atk-pandora/board/board.h | 41 + .../board/linker_scripts/link.icf | 33 + .../board/linker_scripts/link.lds | 144 + .../board/linker_scripts/link.sct | 15 + .../board/ports/drv_qspi_flash.c | 77 + .../board/ports/fal_cfg.h | 34 + .../board/ports/sdcard_port.c | 75 + .../stm32l475-atk-pandora/figures/board.png | Bin 0 -> 488034 bytes bsp/stm32/stm32l475-atk-pandora/project.ewd | 2834 +++++++++++++++++ bsp/stm32/stm32l475-atk-pandora/project.ewp | 2497 +++++++++++++++ bsp/stm32/stm32l475-atk-pandora/project.eww | 10 + .../stm32l475-atk-pandora/project.uvoptx | 196 ++ .../stm32l475-atk-pandora/project.uvprojx | 1373 ++++++++ bsp/stm32/stm32l475-atk-pandora/rtconfig.h | 173 + bsp/stm32/stm32l475-atk-pandora/rtconfig.py | 133 + bsp/stm32/stm32l475-atk-pandora/template.ewp | 2031 ++++++++++++ bsp/stm32/stm32l475-atk-pandora/template.eww | 10 + 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bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/system_stm32l4xx.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/Kconfig create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/SConscript create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/board.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/board.h create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.sct create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h create mode 100644 bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/figures/board.png create mode 100644 bsp/stm32/stm32l475-atk-pandora/project.ewd create mode 100644 bsp/stm32/stm32l475-atk-pandora/project.ewp create mode 100644 bsp/stm32/stm32l475-atk-pandora/project.eww create mode 100644 bsp/stm32/stm32l475-atk-pandora/project.uvoptx create mode 100644 bsp/stm32/stm32l475-atk-pandora/project.uvprojx create mode 100644 bsp/stm32/stm32l475-atk-pandora/rtconfig.h create mode 100644 bsp/stm32/stm32l475-atk-pandora/rtconfig.py create mode 100644 bsp/stm32/stm32l475-atk-pandora/template.ewp create mode 100644 bsp/stm32/stm32l475-atk-pandora/template.eww create mode 100644 bsp/stm32/stm32l475-atk-pandora/template.uvoptx create mode 100644 bsp/stm32/stm32l475-atk-pandora/template.uvprojx diff --git a/bsp/stm32/stm32f103-atk-nano/.config b/bsp/stm32/stm32f103-atk-nano/.config index efe60afe64..781bcbb652 100644 --- a/bsp/stm32/stm32f103-atk-nano/.config +++ b/bsp/stm32/stm32f103-atk-nano/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -61,9 +63,11 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -108,15 +112,18 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set @@ -174,12 +181,15 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -246,7 +256,6 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_BEEPPLAYER is not set # # tools packages @@ -273,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -287,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -302,10 +313,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set -# -# sample package -# - # # samples: kernel and components samples # @@ -313,10 +320,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y @@ -329,10 +332,10 @@ CONFIG_SOC_STM32F103RB=y # # Onboard Peripheral Drivers # - -# -# Offboard Peripheral Drivers -# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_EEPROM is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_POT is not set # # On-chip Peripheral Drivers @@ -342,7 +345,16 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_UART_USING_DMA_RX is not set +# CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_SPI2 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/main.h index d956854a25..35b4a0c569 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/main.h +++ b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/main.h @@ -70,6 +70,8 @@ extern "C" { /* USER CODE END EM */ +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); diff --git a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h index 33b73bfdd9..174f9e3828 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h +++ b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h @@ -78,7 +78,7 @@ /*#define HAL_SMARTCARD_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c index 72a722e235..a58f4196b4 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c @@ -70,6 +70,10 @@ RTC_HandleTypeDef hrtc; SPI_HandleTypeDef hspi2; +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim4; + UART_HandleTypeDef huart1; /* USER CODE BEGIN PV */ @@ -85,6 +89,9 @@ static void MX_SPI2_Init(void); static void MX_RTC_Init(void); static void MX_IWDG_Init(void); static void MX_ADC1_Init(void); +static void MX_TIM2_Init(void); +static void MX_TIM3_Init(void); +static void MX_TIM4_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -128,6 +135,9 @@ int main(void) MX_RTC_Init(); MX_IWDG_Init(); MX_ADC1_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_TIM4_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -186,7 +196,7 @@ void SystemClock_Config(void) } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); @@ -334,6 +344,159 @@ static void MX_SPI2_Init(void) } +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 0; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + +} + +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 0; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None diff --git a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 18d37d8f24..a38a7f26b1 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -78,7 +78,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -287,6 +289,125 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) } +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PC6 ------> TIM3_CH1 + PC7 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM3_ENABLE(); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc index 9f7f2d1c35..2a53c93b0b 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc +++ b/bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc @@ -10,31 +10,39 @@ KeepUserPlacement=false Mcu.Family=STM32F1 Mcu.IP0=ADC1 Mcu.IP1=IWDG +Mcu.IP10=USART1 Mcu.IP2=NVIC Mcu.IP3=RCC Mcu.IP4=RTC Mcu.IP5=SPI2 Mcu.IP6=SYS -Mcu.IP7=USART1 -Mcu.IPNb=8 +Mcu.IP7=TIM2 +Mcu.IP8=TIM3 +Mcu.IP9=TIM4 +Mcu.IPNb=11 Mcu.Name=STM32F103R(8-B)Tx Mcu.Package=LQFP64 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PA13 -Mcu.Pin11=PA14 -Mcu.Pin12=VP_IWDG_VS_IWDG -Mcu.Pin13=VP_RTC_VS_RTC_Activate -Mcu.Pin14=VP_SYS_VS_Systick +Mcu.Pin10=PA9 +Mcu.Pin11=PA10 +Mcu.Pin12=PA13 +Mcu.Pin13=PA14 +Mcu.Pin14=VP_IWDG_VS_IWDG +Mcu.Pin15=VP_RTC_VS_RTC_Activate +Mcu.Pin16=VP_SYS_VS_Systick +Mcu.Pin17=VP_TIM2_VS_ClockSourceINT +Mcu.Pin18=VP_TIM3_VS_ClockSourceINT +Mcu.Pin19=VP_TIM4_VS_ClockSourceINT Mcu.Pin2=PD0-OSC_IN Mcu.Pin3=PD1-OSC_OUT Mcu.Pin4=PB1 Mcu.Pin5=PB13 Mcu.Pin6=PB14 Mcu.Pin7=PB15 -Mcu.Pin8=PA9 -Mcu.Pin9=PA10 -Mcu.PinsNb=15 +Mcu.Pin8=PC6 +Mcu.Pin9=PC7 +Mcu.PinsNb=20 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103RBTx @@ -70,6 +78,10 @@ PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC6.Locked=true +PC6.Signal=S_TIM3_CH1 +PC7.Locked=true +PC7.Signal=S_TIM3_CH2 PCC.Checker=false PCC.Line=STM32F103 PCC.MCU=STM32F103R(8-B)Tx @@ -109,8 +121,9 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true -RCC.ADCFreqValue=36000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_TIM2_Init-TIM2-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true,10-MX_TIM4_Init-TIM4-false-HAL-true +RCC.ADCFreqValue=12000000 +RCC.ADCPresc=RCC_ADCPCLK2_DIV6 RCC.AHBFreq_Value=72000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 RCC.APB1Freq_Value=36000000 @@ -120,7 +133,7 @@ RCC.APB2TimFreq_Value=72000000 RCC.FCLKCortexFreq_Value=72000000 RCC.FamilyName=M RCC.HCLKFreq_Value=72000000 -RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value +RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value RCC.MCOFreq_Value=72000000 RCC.PLLCLKFreq_Value=72000000 RCC.PLLMCOFreq_Value=36000000 @@ -135,11 +148,18 @@ RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 SH.ADCx_IN9.0=ADC1_IN9,IN9 SH.ADCx_IN9.ConfNb=1 +SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1 +SH.S_TIM3_CH1.ConfNb=1 +SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2 +SH.S_TIM3_CH2.ConfNb=1 SPI2.CalculateBaudRate=18.0 MBits/s SPI2.Direction=SPI_DIRECTION_2LINES SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate SPI2.Mode=SPI_MODE_MASTER SPI2.VirtualType=VM_MASTER +TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +TIM3.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM3.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2 USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC VP_IWDG_VS_IWDG.Mode=IWDG_Activate @@ -148,4 +168,10 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +VP_TIM3_VS_ClockSourceINT.Mode=Internal +VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT board=custom diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index f253c76091..2b6d6b3fc1 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -58,6 +58,43 @@ menu "On-chip Peripheral Drivers" bool "Enable UART RX DMA support" default n + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output pwm" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH1 + bool "Enable PWM3 channel1" + default n + + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + endif + endif + config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI @@ -101,7 +138,6 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC2 bool "Enable ADC2" default n - endif config BSP_USING_ON_CHIP_FLASH diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c index b0db19b1ec..28bb36889c 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.c +++ b/bsp/stm32/stm32f103-atk-nano/board/board.c @@ -14,13 +14,17 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; /**Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; @@ -41,6 +45,13 @@ void SystemClock_Config(void) { Error_Handler(); } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } void MX_GPIO_Init(void) diff --git a/bsp/stm32/stm32f103-atk-nano/rtconfig.h b/bsp/stm32/stm32f103-atk-nano/rtconfig.h index c9087c09a6..8bae9ebc30 100644 --- a/bsp/stm32/stm32f103-atk-nano/rtconfig.h +++ b/bsp/stm32/stm32f103-atk-nano/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -38,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 @@ -76,6 +78,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -147,13 +150,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F1 @@ -163,11 +161,14 @@ /* Onboard Peripheral Drivers */ -/* Offboard Peripheral Drivers */ +#define BSP_USING_USB_TO_USART /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO #define BSP_USING_UART1 +/* Board extended module Drivers */ + + #endif diff --git a/bsp/stm32/stm32f103-fire-arbitrary/.config b/bsp/stm32/stm32f103-fire-arbitrary/.config index f67ab34e10..8e22229f4a 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/.config +++ b/bsp/stm32/stm32f103-fire-arbitrary/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -61,9 +63,11 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -108,15 +112,18 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set @@ -174,12 +181,15 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -246,7 +256,6 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_BEEPPLAYER is not set # # tools packages @@ -273,6 +282,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -287,6 +297,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -302,10 +313,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set -# -# sample package -# - # # samples: kernel and components samples # @@ -313,10 +320,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y @@ -329,10 +332,13 @@ CONFIG_SOC_STM32F103ZE=y # # Onboard Peripheral Drivers # - -# -# Offboard Peripheral Drivers -# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_RS485_OR_RS232 is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_POT is not set +# CONFIG_BSP_USING_EEPROM is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers @@ -342,8 +348,18 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_UART_USING_DMA_RX is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_SPI2 is not set # CONFIG_BSP_USING_SPI3 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject index 6e18ecf569..cd96a5d50d 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject @@ -1,13 +1,13 @@ [PreviousGenFiles] -HeaderPath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc +HeaderPath=D:/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h; -SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src +SourcePath=D:/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null; HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc; diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/main.h index d956854a25..35b4a0c569 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/main.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/main.h @@ -70,6 +70,8 @@ extern "C" { /* USER CODE END EM */ +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h index 33b73bfdd9..2d008d8024 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h @@ -72,13 +72,13 @@ /*#define HAL_PWR_MODULE_ENABLED */ /*#define HAL_RCC_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED -/*#define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c index 8af499226d..21a0786131 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c @@ -68,9 +68,16 @@ IWDG_HandleTypeDef hiwdg; RTC_HandleTypeDef hrtc; +SD_HandleTypeDef hsd; + SPI_HandleTypeDef hspi1; SPI_HandleTypeDef hspi2; +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim4; +TIM_HandleTypeDef htim5; + UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; @@ -91,6 +98,11 @@ static void MX_USART3_UART_Init(void); static void MX_ADC1_Init(void); static void MX_RTC_Init(void); static void MX_IWDG_Init(void); +static void MX_TIM2_Init(void); +static void MX_TIM3_Init(void); +static void MX_TIM4_Init(void); +static void MX_TIM5_Init(void); +static void MX_SDIO_SD_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -137,6 +149,11 @@ int main(void) MX_ADC1_Init(); MX_RTC_Init(); MX_IWDG_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_TIM4_Init(); + MX_TIM5_Init(); + MX_SDIO_SD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -305,6 +322,42 @@ static void MX_RTC_Init(void) } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + /** * @brief SPI1 Initialization Function * @param None @@ -381,6 +434,208 @@ static void MX_SPI2_Init(void) } +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 0; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + +} + +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 0; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + +} + +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 0; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 0; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None @@ -492,6 +747,7 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); } diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 4de0950dca..b2f18b01ac 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -78,7 +78,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -214,6 +216,90 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) } +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ + +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + /** * @brief SPI MSP Initialization * This function configures the hardware resources used in this example @@ -334,6 +420,148 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) } +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + else if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ + + /* USER CODE END TIM5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PB0 ------> TIM3_CH3 + PB1 ------> TIM3_CH4 + PB5 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM3_PARTIAL(); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ + + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ + + /* USER CODE END TIM5_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc index ba9498c4be..f9d2fafc6a 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/stm32f103zet6.ioc @@ -10,41 +10,59 @@ KeepUserPlacement=false Mcu.Family=STM32F1 Mcu.IP0=ADC1 Mcu.IP1=IWDG -Mcu.IP10=USART3 +Mcu.IP10=TIM3 +Mcu.IP11=TIM4 +Mcu.IP12=TIM5 +Mcu.IP13=USART1 +Mcu.IP14=USART2 +Mcu.IP15=USART3 Mcu.IP2=NVIC Mcu.IP3=RCC Mcu.IP4=RTC -Mcu.IP5=SPI1 -Mcu.IP6=SPI2 -Mcu.IP7=SYS -Mcu.IP8=USART1 -Mcu.IP9=USART2 -Mcu.IPNb=11 +Mcu.IP5=SDIO +Mcu.IP6=SPI1 +Mcu.IP7=SPI2 +Mcu.IP8=SYS +Mcu.IP9=TIM2 +Mcu.IPNb=16 Mcu.Name=STM32F103Z(C-D-E)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PB10 -Mcu.Pin11=PB11 -Mcu.Pin12=PB13 -Mcu.Pin13=PB14 -Mcu.Pin14=PB15 -Mcu.Pin15=PA9 -Mcu.Pin16=PA10 -Mcu.Pin17=PA13 -Mcu.Pin18=PA14 -Mcu.Pin19=VP_IWDG_VS_IWDG +Mcu.Pin10=PB0 +Mcu.Pin11=PB1 +Mcu.Pin12=PB10 +Mcu.Pin13=PB11 +Mcu.Pin14=PB13 +Mcu.Pin15=PB14 +Mcu.Pin16=PB15 +Mcu.Pin17=PC8 +Mcu.Pin18=PC9 +Mcu.Pin19=PA9 Mcu.Pin2=OSC_IN -Mcu.Pin20=VP_RTC_VS_RTC_Activate -Mcu.Pin21=VP_SYS_VS_Systick +Mcu.Pin20=PA10 +Mcu.Pin21=PA13 +Mcu.Pin22=PA14 +Mcu.Pin23=PC10 +Mcu.Pin24=PC11 +Mcu.Pin25=PC12 +Mcu.Pin26=PD2 +Mcu.Pin27=PB5 +Mcu.Pin28=VP_IWDG_VS_IWDG +Mcu.Pin29=VP_RTC_VS_RTC_Activate Mcu.Pin3=OSC_OUT +Mcu.Pin30=VP_SYS_VS_Systick +Mcu.Pin31=VP_TIM2_VS_ClockSourceINT +Mcu.Pin32=VP_TIM3_VS_ClockSourceINT +Mcu.Pin33=VP_TIM4_VS_ClockSourceINT +Mcu.Pin34=VP_TIM5_VS_ClockSourceINT Mcu.Pin4=PC1 Mcu.Pin5=PA2 Mcu.Pin6=PA3 Mcu.Pin7=PA5 Mcu.Pin8=PA6 Mcu.Pin9=PA7 -Mcu.PinsNb=22 +Mcu.PinsNb=35 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103ZETx @@ -83,6 +101,8 @@ PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PB0.Signal=S_TIM3_CH3 +PB1.Signal=S_TIM3_CH4 PB10.Mode=Asynchronous PB10.Signal=USART3_TX PB11.Mode=Asynchronous @@ -93,12 +113,23 @@ PB14.Mode=Full_Duplex_Master PB14.Signal=SPI2_MISO PB15.Mode=Full_Duplex_Master PB15.Signal=SPI2_MOSI +PB5.Signal=S_TIM3_CH2 PC1.Locked=true PC1.Signal=ADCx_IN11 +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Line=STM32F103 PCC.MCU=STM32F103Z(C-D-E)Tx @@ -107,6 +138,8 @@ PCC.Seq0=0 PCC.Series=STM32F1 PCC.Temperature=25 PCC.Vdd=3.3 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false @@ -134,7 +167,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true,11-MX_TIM2_Init-TIM2-false-HAL-true,12-MX_TIM3_Init-TIM3-false-HAL-true,13-MX_TIM4_Init-TIM4-false-HAL-true,14-MX_TIM5_Init-TIM5-false-HAL-true,15-MX_SDIO_SD_Init-SDIO-false-HAL-true RCC.ADCFreqValue=12000000 RCC.ADCPresc=RCC_ADCPCLK2_DIV6 RCC.AHBFreq_Value=72000000 @@ -166,6 +199,12 @@ RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 SH.ADCx_IN11.0=ADC1_IN11,IN11 SH.ADCx_IN11.ConfNb=1 +SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2 +SH.S_TIM3_CH2.ConfNb=1 +SH.S_TIM3_CH3.0=TIM3_CH3,PWM Generation3 CH3 +SH.S_TIM3_CH3.ConfNb=1 +SH.S_TIM3_CH4.0=TIM3_CH4,PWM Generation4 CH4 +SH.S_TIM3_CH4.ConfNb=1 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4 SPI1.CalculateBaudRate=18.0 MBits/s SPI1.Direction=SPI_DIRECTION_2LINES @@ -177,6 +216,10 @@ SPI2.Direction=SPI_DIRECTION_2LINES SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate SPI2.Mode=SPI_MODE_MASTER SPI2.VirtualType=VM_MASTER +TIM3.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM3.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM3.IPParameters=Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC USART2.IPParameters=VirtualMode @@ -189,4 +232,12 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +VP_TIM3_VS_ClockSourceINT.Mode=Internal +VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT +VP_TIM5_VS_ClockSourceINT.Mode=Internal +VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT board=custom diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig index f7f8c82880..ae55be5fab 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig @@ -24,6 +24,16 @@ menu "Onboard Peripheral Drivers" select RT_SFUD_USING_SFDP default n + config BSP_USING_RGB + bool "Enable RGB LED (timer3 channel2 - 4)" + select RT_USING_PWM + select BSP_USING_PWM + select BSP_USING_PWM3 + select BSP_USING_PWM3_CH2 + select BSP_USING_PWM3_CH3 + select BSP_USING_PWM3_CH4 + default n + config BSP_USING_POT bool "Enable potentiometer" select BSP_USING_ADC @@ -63,6 +73,13 @@ menu "Onboard Peripheral Drivers" endif + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + endmenu menu "On-chip Peripheral Drivers" @@ -131,6 +148,51 @@ menu "On-chip Peripheral Drivers" default 23 endif + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + + config BSP_USING_TIM5 + bool "Enable TIM5" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output pwm" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + + config BSP_USING_PWM3_CH3 + bool "Enable PWM3 channel3" + default n + + config BSP_USING_PWM3_CH4 + bool "Enable PWM3 channel4" + default n + endif + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n @@ -160,6 +222,12 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + endmenu menu "Board extended module Drivers" diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/SConscript b/bsp/stm32/stm32f103-fire-arbitrary/board/SConscript index 24b0a3b97a..30d93fa3d4 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/SConscript +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_ETH']): if GetDepend(['BSP_USING_SPI_FLASH']): src += Glob('ports/spi_flash_init.c') +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c index 2d4ad3f5db..3188bdb616 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c @@ -13,31 +13,46 @@ void SystemClock_Config(void) { - rt_err_t ret = RT_EOK; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = 16; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; - ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); - RT_ASSERT(ret == HAL_OK); + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK | - RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); - RT_ASSERT(ret == HAL_OK); - - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RT_TICK_PER_SECOND); - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } void MX_GPIO_Init(void) diff --git a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h index fdd6a747f4..b26cc15cae 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -38,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 @@ -76,6 +78,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -148,13 +151,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F1 @@ -164,11 +162,14 @@ /* Onboard Peripheral Drivers */ -/* Offboard Peripheral Drivers */ +#define BSP_USING_USB_TO_USART /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO #define BSP_USING_UART1 +/* Board extended module Drivers */ + + #endif diff --git a/bsp/stm32/stm32f407-atk-explorer/.config b/bsp/stm32/stm32f407-atk-explorer/.config index 4f44d6b3af..1b83652dcf 100644 --- a/bsp/stm32/stm32f407-atk-explorer/.config +++ b/bsp/stm32/stm32f407-atk-explorer/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -110,6 +111,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -179,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -293,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -308,10 +313,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set -# -# sample package -# - # # samples: kernel and components samples # @@ -319,10 +320,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -341,6 +338,7 @@ CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_EEPROM is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_MPU6050 is not set +# CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers @@ -350,12 +348,18 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_SPI2 is not set # CONFIG_BSP_USING_SPI3 is not set # CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject index 5992acc289..7e119922f0 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject @@ -5,9 +5,9 @@ SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f407-atk-explorer/ SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc index edf6c481c1..770acec332 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc @@ -12,44 +12,64 @@ KeepUserPlacement=false Mcu.Family=STM32F4 Mcu.IP0=ADC1 Mcu.IP1=ETH +Mcu.IP10=TIM2 +Mcu.IP11=TIM11 +Mcu.IP12=TIM13 +Mcu.IP13=TIM14 +Mcu.IP14=USART1 +Mcu.IP15=USART3 Mcu.IP2=IWDG Mcu.IP3=NVIC Mcu.IP4=RCC Mcu.IP5=RTC -Mcu.IP6=SPI1 -Mcu.IP7=SYS -Mcu.IP8=USART1 -Mcu.IP9=USART3 -Mcu.IPNb=10 +Mcu.IP6=SDIO +Mcu.IP7=SPI1 +Mcu.IP8=SPI2 +Mcu.IP9=SYS +Mcu.IPNb=16 Mcu.Name=STM32F407Z(E-G)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PC5 -Mcu.Pin11=PB10 -Mcu.Pin12=PB11 -Mcu.Pin13=PA9 -Mcu.Pin14=PA10 -Mcu.Pin15=PA13 -Mcu.Pin16=PA14 -Mcu.Pin17=PG11 -Mcu.Pin18=PG13 -Mcu.Pin19=PG14 +Mcu.Pin10=PA5 +Mcu.Pin11=PA7 +Mcu.Pin12=PC4 +Mcu.Pin13=PC5 +Mcu.Pin14=PB10 +Mcu.Pin15=PB11 +Mcu.Pin16=PB13 +Mcu.Pin17=PC8 +Mcu.Pin18=PC9 +Mcu.Pin19=PA9 Mcu.Pin2=PH0-OSC_IN -Mcu.Pin20=PB3 -Mcu.Pin21=PB4 -Mcu.Pin22=PB5 -Mcu.Pin23=VP_IWDG_VS_IWDG -Mcu.Pin24=VP_RTC_VS_RTC_Activate -Mcu.Pin25=VP_SYS_VS_Systick +Mcu.Pin20=PA10 +Mcu.Pin21=PA13 +Mcu.Pin22=PA14 +Mcu.Pin23=PC10 +Mcu.Pin24=PC11 +Mcu.Pin25=PC12 +Mcu.Pin26=PD2 +Mcu.Pin27=PG11 +Mcu.Pin28=PG13 +Mcu.Pin29=PG14 Mcu.Pin3=PH1-OSC_OUT +Mcu.Pin30=PB3 +Mcu.Pin31=PB4 +Mcu.Pin32=PB5 +Mcu.Pin33=VP_IWDG_VS_IWDG +Mcu.Pin34=VP_RTC_VS_RTC_Activate +Mcu.Pin35=VP_SYS_VS_Systick +Mcu.Pin36=VP_TIM2_VS_ClockSourceINT +Mcu.Pin37=VP_TIM11_VS_ClockSourceINT +Mcu.Pin38=VP_TIM13_VS_ClockSourceINT +Mcu.Pin39=VP_TIM14_VS_ClockSourceINT Mcu.Pin4=PC1 -Mcu.Pin5=PA1 -Mcu.Pin6=PA2 -Mcu.Pin7=PA5 -Mcu.Pin8=PA7 -Mcu.Pin9=PC4 -Mcu.PinsNb=26 +Mcu.Pin5=PC2 +Mcu.Pin6=PC3 +Mcu.Pin7=PA1 +Mcu.Pin8=PA2 +Mcu.Pin9=PA3 +Mcu.PinsNb=40 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F407ZGTx @@ -77,6 +97,7 @@ PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK PA2.Mode=RMII PA2.Signal=ETH_MDIO +PA3.Signal=S_TIM2_CH4 PA5.Locked=true PA5.Signal=ADCx_IN5 PA7.Mode=RMII @@ -87,6 +108,8 @@ PB10.Mode=Asynchronous PB10.Signal=USART3_TX PB11.Mode=Asynchronous PB11.Signal=USART3_RX +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK PB3.Locked=true PB3.Mode=Full_Duplex_Master PB3.Signal=SPI1_SCK @@ -98,14 +121,28 @@ PB5.Mode=Full_Duplex_Master PB5.Signal=SPI1_MOSI PC1.Mode=RMII PC1.Signal=ETH_MDC +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC2.Mode=Full_Duplex_Master +PC2.Signal=SPI2_MISO +PC3.Mode=Full_Duplex_Master +PC3.Signal=SPI2_MOSI PC4.Mode=RMII PC4.Signal=ETH_RXD0 PC5.Mode=RMII PC5.Signal=ETH_RXD1 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Line=STM32F407/417 PCC.MCU=STM32F407Z(E-G)Tx @@ -114,6 +151,8 @@ PCC.Seq0=0 PCC.Series=STM32F4 PCC.Temperature=25 PCC.Vdd=3.3 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD PG11.Locked=true PG11.Mode=RMII PG11.Signal=ETH_TX_EN @@ -154,8 +193,8 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true -RCC.48MHZClocksFreq_Value=84000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM2_Init-TIM2-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 RCC.AHBFreq_Value=168000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 RCC.APB1Freq_Value=42000000 @@ -171,13 +210,14 @@ RCC.HCLKFreq_Value=168000000 RCC.HSE_VALUE=8000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=192000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S RCC.LSI_VALUE=32000 RCC.MCO2PinFreq_Value=168000000 RCC.PLLCLKFreq_Value=168000000 RCC.PLLM=4 RCC.PLLN=168 -RCC.PLLQCLKFreq_Value=84000000 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE @@ -191,11 +231,20 @@ RCC.VCOOutputFreq_Value=336000000 RCC.VcooutputI2S=192000000 SH.ADCx_IN5.0=ADC1_IN5,IN5 SH.ADCx_IN5.ConfNb=1 +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +SH.S_TIM2_CH4.ConfNb=1 SPI1.CalculateBaudRate=42.0 MBits/s SPI1.Direction=SPI_DIRECTION_2LINES SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate SPI1.Mode=SPI_MODE_MASTER SPI1.VirtualType=VM_MASTER +SPI2.CalculateBaudRate=21.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM2.IPParameters=Channel-PWM Generation4 CH4 USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC USART3.IPParameters=VirtualMode @@ -206,4 +255,12 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT board=custom diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/main.h index c9d0c58eab..7641bf3d51 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/main.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/main.h @@ -70,6 +70,8 @@ extern "C" { /* USER CODE END EM */ +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 42f834b278..37853623c2 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -71,10 +71,10 @@ /* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED /* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c index efc54ca543..2577da8b41 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c @@ -70,7 +70,15 @@ IWDG_HandleTypeDef hiwdg; RTC_HandleTypeDef hrtc; +SD_HandleTypeDef hsd; + SPI_HandleTypeDef hspi1; +SPI_HandleTypeDef hspi2; + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; UART_HandleTypeDef huart1; UART_HandleTypeDef huart3; @@ -90,6 +98,12 @@ static void MX_USART3_UART_Init(void); static void MX_ADC1_Init(void); static void MX_RTC_Init(void); static void MX_IWDG_Init(void); +static void MX_TIM14_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM11_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_TIM2_Init(void); +static void MX_SPI2_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -135,6 +149,12 @@ int main(void) MX_ADC1_Init(); MX_RTC_Init(); MX_IWDG_Init(); + MX_TIM14_Init(); + MX_TIM13_Init(); + MX_TIM11_Init(); + MX_SDIO_SD_Init(); + MX_TIM2_Init(); + MX_SPI2_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -178,7 +198,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 168; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 7; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -361,6 +381,42 @@ static void MX_RTC_Init(void) } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + /** * @brief SPI1 Initialization Function * @param None @@ -399,6 +455,192 @@ static void MX_SPI1_Init(void) } +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_8BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None @@ -478,6 +720,7 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); } diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index ba4fa3a128..258ea04acc 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -78,7 +78,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -310,6 +312,94 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) } +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ + +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + /** * @brief SPI MSP Initialization * This function configures the hardware resources used in this example @@ -348,6 +438,39 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspInit 1 */ } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB13 ------> SPI2_SCK + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } } @@ -382,6 +505,167 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE END SPI1_MspDeInit 1 */ } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PC2 ------> SPI2_MISO + PC3 ------> SPI2_MOSI + PB13 ------> SPI2_SCK + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } } diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index c34e98a24c..319cb49c92 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -45,6 +45,13 @@ menu "Onboard Peripheral Drivers" select BSP_USING_I2C1 select PKG_USING_MPU6XXX + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + endmenu menu "On-chip Peripheral Drivers" @@ -73,7 +80,40 @@ menu "On-chip Peripheral Drivers" bool "Enable UART6" select RT_USING_SERIAL default n - + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output pwm" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH4 + bool "Enable PWM2 channel4" + default n + endif + endif + config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n @@ -92,11 +132,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SPI default n - config BSP_USING_SPI3 - bool "Enable SPI3 BUS" - select RT_USING_SPI - default n - config BSP_SPI_USING_DMA bool "Enable SPI DMA support" default n @@ -147,6 +182,12 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + endmenu menu "Board extended module Drivers" diff --git a/bsp/stm32/stm32f407-atk-explorer/board/SConscript b/bsp/stm32/stm32f407-atk-explorer/board/SConscript index ee12fe4ce6..65f3b2aad6 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/SConscript +++ b/bsp/stm32/stm32f407-atk-explorer/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_ETH']): if GetDepend(['BSP_USING_SPI_FLASH']): src += Glob('ports/spi_flash_init.c') +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c index 4e400eea6a..52145fe832 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c @@ -12,34 +12,33 @@ void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /**Configure the main internal regulator output voltage - */ + /**Configure the main internal regulator output voltage + */ __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = 16; + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 168; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 7; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - _Error_Handler(__FILE__, __LINE__); + Error_Handler(); } - - /**Initializes the CPU, AHB and APB busses clocks - */ + /**Initializes the CPU, AHB and APB busses clocks + */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -49,19 +48,14 @@ void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - _Error_Handler(__FILE__, __LINE__); + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); } - - /**Configure the Systick interrupt time - */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - - /**Configure the Systick - */ - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); } void MX_GPIO_Init(void) { diff --git a/bsp/stm32/stm32f407-atk-explorer/rtconfig.h b/bsp/stm32/stm32f407-atk-explorer/rtconfig.h index 948a7a65d7..e628397b54 100644 --- a/bsp/stm32/stm32f407-atk-explorer/rtconfig.h +++ b/bsp/stm32/stm32f407-atk-explorer/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -76,6 +77,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -147,16 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - - -/* rtpkgs online packages */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 diff --git a/bsp/stm32/stm32f429-atk-apollo/.config b/bsp/stm32/stm32f429-atk-apollo/.config index 1ad45f888b..99e2a7651d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/.config +++ b/bsp/stm32/stm32f429-atk-apollo/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -110,6 +111,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -179,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -278,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -292,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -307,10 +313,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set -# -# sample package -# - # # samples: kernel and components samples # @@ -318,30 +320,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -360,6 +339,7 @@ CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_SPI_FLASH is not set # CONFIG_BSP_USING_MPU9250 is not set # CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers @@ -369,11 +349,17 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_UART_USING_DMA_RX is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_SPI2 is not set # CONFIG_BSP_USING_SPI5 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject index 77224685af..f86413cb62 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject @@ -1,16 +1,16 @@ [PreviousGenFiles] -HeaderPath=D:/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc +HeaderPath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=D:/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src +SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [] SourceFiles=;; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config//MDK-ARM/startup_stm32f429xx.s; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/main.h index 9d41187606..f1494d6236 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/main.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/main.h @@ -70,6 +70,8 @@ extern "C" { /* USER CODE END EM */ +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 9058fdf15a..eb06eacdbb 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -71,10 +71,10 @@ /* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED /* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc index 57498627a0..f73131a428 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc @@ -12,77 +12,105 @@ KeepUserPlacement=false Mcu.Family=STM32F4 Mcu.IP0=ADC1 Mcu.IP1=ETH +Mcu.IP10=SPI5 +Mcu.IP11=SYS +Mcu.IP12=TIM2 +Mcu.IP13=TIM11 +Mcu.IP14=TIM13 +Mcu.IP15=TIM14 +Mcu.IP16=USART1 Mcu.IP2=FMC Mcu.IP3=IWDG Mcu.IP4=NVIC Mcu.IP5=RCC Mcu.IP6=RTC -Mcu.IP7=SYS -Mcu.IP8=USART1 -Mcu.IPNb=9 +Mcu.IP7=SDIO +Mcu.IP8=SPI1 +Mcu.IP9=SPI2 +Mcu.IPNb=17 Mcu.Name=STM32F429I(E-G)Tx Mcu.Package=LQFP176 Mcu.Pin0=PC14/OSC32_IN Mcu.Pin1=PC15/OSC32_OUT -Mcu.Pin10=PC0 -Mcu.Pin11=PC1 -Mcu.Pin12=PC2 -Mcu.Pin13=PC3 -Mcu.Pin14=PA1 -Mcu.Pin15=PA2 -Mcu.Pin16=PA5 -Mcu.Pin17=PA7 -Mcu.Pin18=PC4 -Mcu.Pin19=PC5 +Mcu.Pin10=PF9 +Mcu.Pin11=PH0/OSC_IN +Mcu.Pin12=PH1/OSC_OUT +Mcu.Pin13=PC0 +Mcu.Pin14=PC1 +Mcu.Pin15=PC2 +Mcu.Pin16=PC3 +Mcu.Pin17=PA1 +Mcu.Pin18=PA2 +Mcu.Pin19=PA3 Mcu.Pin2=PF0 -Mcu.Pin20=PF11 -Mcu.Pin21=PF12 -Mcu.Pin22=PF13 -Mcu.Pin23=PF14 -Mcu.Pin24=PF15 -Mcu.Pin25=PG0 -Mcu.Pin26=PG1 -Mcu.Pin27=PE7 -Mcu.Pin28=PE8 -Mcu.Pin29=PE9 +Mcu.Pin20=PA5 +Mcu.Pin21=PA6 +Mcu.Pin22=PA7 +Mcu.Pin23=PC4 +Mcu.Pin24=PC5 +Mcu.Pin25=PF11 +Mcu.Pin26=PF12 +Mcu.Pin27=PF13 +Mcu.Pin28=PF14 +Mcu.Pin29=PF15 Mcu.Pin3=PF1 -Mcu.Pin30=PE10 -Mcu.Pin31=PE11 -Mcu.Pin32=PE12 -Mcu.Pin33=PE13 -Mcu.Pin34=PE14 -Mcu.Pin35=PE15 -Mcu.Pin36=PB11 -Mcu.Pin37=PD8 -Mcu.Pin38=PD9 -Mcu.Pin39=PD10 +Mcu.Pin30=PG0 +Mcu.Pin31=PG1 +Mcu.Pin32=PE7 +Mcu.Pin33=PE8 +Mcu.Pin34=PE9 +Mcu.Pin35=PE10 +Mcu.Pin36=PE11 +Mcu.Pin37=PE12 +Mcu.Pin38=PE13 +Mcu.Pin39=PE14 Mcu.Pin4=PF2 -Mcu.Pin40=PD14 -Mcu.Pin41=PD15 -Mcu.Pin42=PG2 -Mcu.Pin43=PG4 -Mcu.Pin44=PG5 -Mcu.Pin45=PG8 -Mcu.Pin46=PA9 -Mcu.Pin47=PA10 -Mcu.Pin48=PA13 -Mcu.Pin49=PA14 +Mcu.Pin40=PE15 +Mcu.Pin41=PB10 +Mcu.Pin42=PB11 +Mcu.Pin43=PB14 +Mcu.Pin44=PB15 +Mcu.Pin45=PD8 +Mcu.Pin46=PD9 +Mcu.Pin47=PD10 +Mcu.Pin48=PD14 +Mcu.Pin49=PD15 Mcu.Pin5=PF3 -Mcu.Pin50=PD0 -Mcu.Pin51=PD1 -Mcu.Pin52=PG13 -Mcu.Pin53=PG14 -Mcu.Pin54=PG15 -Mcu.Pin55=PE0 -Mcu.Pin56=PE1 -Mcu.Pin57=VP_IWDG_VS_IWDG -Mcu.Pin58=VP_RTC_VS_RTC_Activate -Mcu.Pin59=VP_SYS_VS_Systick +Mcu.Pin50=PG2 +Mcu.Pin51=PG4 +Mcu.Pin52=PG5 +Mcu.Pin53=PG8 +Mcu.Pin54=PC8 +Mcu.Pin55=PC9 +Mcu.Pin56=PA9 +Mcu.Pin57=PA10 +Mcu.Pin58=PA13 +Mcu.Pin59=PA14 Mcu.Pin6=PF4 +Mcu.Pin60=PC10 +Mcu.Pin61=PC11 +Mcu.Pin62=PC12 +Mcu.Pin63=PD0 +Mcu.Pin64=PD1 +Mcu.Pin65=PD2 +Mcu.Pin66=PG13 +Mcu.Pin67=PG14 +Mcu.Pin68=PG15 +Mcu.Pin69=PB3 Mcu.Pin7=PF5 -Mcu.Pin8=PH0/OSC_IN -Mcu.Pin9=PH1/OSC_OUT -Mcu.PinsNb=60 +Mcu.Pin70=PB5 +Mcu.Pin71=PE0 +Mcu.Pin72=PE1 +Mcu.Pin73=VP_IWDG_VS_IWDG +Mcu.Pin74=VP_RTC_VS_RTC_Activate +Mcu.Pin75=VP_SYS_VS_Systick +Mcu.Pin76=VP_TIM2_VS_ClockSourceINT +Mcu.Pin77=VP_TIM11_VS_ClockSourceINT +Mcu.Pin78=VP_TIM13_VS_ClockSourceINT +Mcu.Pin79=VP_TIM14_VS_ClockSourceINT +Mcu.Pin8=PF7 +Mcu.Pin9=PF8 +Mcu.PinsNb=80 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F429IGTx @@ -109,16 +137,36 @@ PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK PA2.Mode=RMII PA2.Signal=ETH_MDIO +PA3.Locked=true +PA3.Signal=S_TIM2_CH4 PA5.Signal=ADCx_IN5 +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO PA7.Mode=RMII PA7.Signal=ETH_CRS_DV PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PB10.Mode=Full_Duplex_Master +PB10.Signal=SPI2_SCK PB11.Mode=RMII PB11.Signal=ETH_TX_EN +PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI1_SCK +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI1_MOSI PC0.Signal=FMC_SDNWE PC1.Mode=RMII PC1.Signal=ETH_MDC +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK PC14/OSC32_IN.Mode=LSE-External-Oscillator PC14/OSC32_IN.Signal=RCC_OSC32_IN PC15/OSC32_OUT.Mode=LSE-External-Oscillator @@ -131,6 +179,10 @@ PC4.Mode=RMII PC4.Signal=ETH_RXD0 PC5.Mode=RMII PC5.Signal=ETH_RXD1 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Line=STM32F429/439 PCC.MCU=STM32F429I(E-G)Tx @@ -144,6 +196,8 @@ PD1.Signal=FMC_D3_DA3 PD10.Signal=FMC_D15_DA15 PD14.Signal=FMC_D0_DA0 PD15.Signal=FMC_D1_DA1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD PD8.Signal=FMC_D13_DA13 PD9.Signal=FMC_D14_DA14 PE0.Signal=FMC_NBL0 @@ -168,6 +222,12 @@ PF2.Signal=FMC_A2 PF3.Signal=FMC_A3 PF4.Signal=FMC_A4 PF5.Signal=FMC_A5 +PF7.Mode=Full_Duplex_Master +PF7.Signal=SPI5_SCK +PF8.Mode=Full_Duplex_Master +PF8.Signal=SPI5_MISO +PF9.Mode=Full_Duplex_Master +PF9.Signal=SPI5_MOSI PG0.Signal=FMC_A10 PG1.Signal=FMC_A11 PG13.Locked=true @@ -212,8 +272,8 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true -RCC.48MHZClocksFreq_Value=90000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_TIM11_Init-TIM11-false-HAL-true,10-MX_TIM13_Init-TIM13-false-HAL-true,11-MX_TIM14_Init-TIM14-false-HAL-true,12-MX_SDIO_SD_Init-SDIO-false-HAL-true,13-MX_TIM2_Init-TIM2-false-HAL-true,14-MX_SPI1_Init-SPI1-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true,16-MX_SPI5_Init-SPI5-false-HAL-true +RCC.48MHZClocksFreq_Value=45000000 RCC.AHBFreq_Value=180000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 RCC.APB1Freq_Value=45000000 @@ -229,16 +289,19 @@ RCC.HCLKFreq_Value=180000000 RCC.HSE_VALUE=25000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=160000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ RCC.LCDTFTFreq_Value=20416666.666666668 RCC.LSI_VALUE=32000 RCC.MCO2PinFreq_Value=180000000 RCC.PLLCLKFreq_Value=180000000 RCC.PLLM=15 RCC.PLLN=216 -RCC.PLLQCLKFreq_Value=90000000 +RCC.PLLQ=8 +RCC.PLLQCLKFreq_Value=45000000 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.RTCFreq_Value=32000 +RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE +RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 RCC.RTCHSEDivFreq_Value=12500000 RCC.SAI_AClocksFreq_Value=20416666.666666668 RCC.SAI_BClocksFreq_Value=20416666.666666668 @@ -328,6 +391,25 @@ SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1 SH.FMC_SDNRAS.ConfNb=1 SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1 SH.FMC_SDNWE.ConfNb=1 +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +SH.S_TIM2_CH4.ConfNb=1 +SPI1.CalculateBaudRate=45.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +SPI2.CalculateBaudRate=22.5 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +SPI5.CalculateBaudRate=45.0 MBits/s +SPI5.Direction=SPI_DIRECTION_2LINES +SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI5.Mode=SPI_MODE_MASTER +SPI5.VirtualType=VM_MASTER +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM2.IPParameters=Channel-PWM Generation4 CH4 USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC VP_IWDG_VS_IWDG.Mode=IWDG_Activate @@ -336,4 +418,12 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +VP_TIM2_VS_ClockSourceINT.Mode=Internal +VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT board=custom diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c index 04c57b6696..76ce5a89e6 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c @@ -70,6 +70,17 @@ IWDG_HandleTypeDef hiwdg; RTC_HandleTypeDef hrtc; +SD_HandleTypeDef hsd; + +SPI_HandleTypeDef hspi1; +SPI_HandleTypeDef hspi2; +SPI_HandleTypeDef hspi5; + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; + UART_HandleTypeDef huart1; SDRAM_HandleTypeDef hsdram1; @@ -88,6 +99,14 @@ static void MX_FMC_Init(void); static void MX_RTC_Init(void); static void MX_IWDG_Init(void); static void MX_ADC1_Init(void); +static void MX_TIM11_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM14_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_TIM2_Init(void); +static void MX_SPI1_Init(void); +static void MX_SPI2_Init(void); +static void MX_SPI5_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -132,6 +151,14 @@ int main(void) MX_RTC_Init(); MX_IWDG_Init(); MX_ADC1_Init(); + MX_TIM11_Init(); + MX_TIM13_Init(); + MX_TIM14_Init(); + MX_SDIO_SD_Init(); + MX_TIM2_Init(); + MX_SPI1_Init(); + MX_SPI2_Init(); + MX_SPI5_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -165,15 +192,17 @@ void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /**Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 15; RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -198,7 +227,7 @@ void SystemClock_Config(void) Error_Handler(); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); @@ -362,6 +391,304 @@ static void MX_RTC_Init(void) } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_8BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief SPI5 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI5_Init(void) +{ + + /* USER CODE BEGIN SPI5_Init 0 */ + + /* USER CODE END SPI5_Init 0 */ + + /* USER CODE BEGIN SPI5_Init 1 */ + + /* USER CODE END SPI5_Init 1 */ + /* SPI5 parameter configuration*/ + hspi5.Instance = SPI5; + hspi5.Init.Mode = SPI_MODE_MASTER; + hspi5.Init.Direction = SPI_DIRECTION_2LINES; + hspi5.Init.DataSize = SPI_DATASIZE_8BIT; + hspi5.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi5.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi5.Init.NSS = SPI_NSS_SOFT; + hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi5.Init.TIMode = SPI_TIMODE_DISABLE; + hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi5.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI5_Init 2 */ + + /* USER CODE END SPI5_Init 2 */ + +} + +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index be70559b9c..5d3dcf0a51 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -78,7 +78,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -320,6 +322,402 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) } +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ + +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA6 ------> SPI1_MISO + PB3 ------> SPI1_SCK + PB5 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PB10 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + else if(hspi->Instance==SPI5) + { + /* USER CODE BEGIN SPI5_MspInit 0 */ + + /* USER CODE END SPI5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI5_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**SPI5 GPIO Configuration + PF7 ------> SPI5_SCK + PF8 ------> SPI5_MISO + PF9 ------> SPI5_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI5_MspInit 1 */ + + /* USER CODE END SPI5_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA6 ------> SPI1_MISO + PB3 ------> SPI1_SCK + PB5 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_5); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PB10 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + else if(hspi->Instance==SPI5) + { + /* USER CODE BEGIN SPI5_MspDeInit 0 */ + + /* USER CODE END SPI5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI5_CLK_DISABLE(); + + /**SPI5 GPIO Configuration + PF7 ------> SPI5_SCK + PF8 ------> SPI5_MISO + PF9 ------> SPI5_MOSI + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN SPI5_MspDeInit 1 */ + + /* USER CODE END SPI5_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PA3 ------> TIM2_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index 161ccf19a9..9d85754053 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -16,7 +16,7 @@ menu "Onboard Peripheral Drivers" bool "Enable COM2 (uart2 pin conflict with Ethernet)" select BSP_USING_UART2 default n - + config BSP_USING_COM3 bool "Enable COM3 (uart3)" select BSP_USING_UART3 @@ -32,7 +32,7 @@ menu "Onboard Peripheral Drivers" select RT_USING_SFUD select RT_SFUD_USING_SFDP default n - + config BSP_USING_MPU9250 bool "Enable MPU 9250 (i2c1)" select BSP_USING_I2C1 @@ -50,7 +50,14 @@ menu "Onboard Peripheral Drivers" hex default 0x00 endif - + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + endmenu menu "On-chip Peripheral Drivers" @@ -120,6 +127,39 @@ menu "On-chip Peripheral Drivers" default 117 endif + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output pwm" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH4 + bool "Enable PWM2 channel4" + default n + endif + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n @@ -149,6 +189,12 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + endmenu menu "Board extended module Drivers" diff --git a/bsp/stm32/stm32f429-atk-apollo/board/SConscript b/bsp/stm32/stm32f429-atk-apollo/board/SConscript index e67a62e1e8..bfe1107e3f 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/SConscript +++ b/bsp/stm32/stm32f429-atk-apollo/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_ETH']): if GetDepend(['BSP_USING_SPI_FLASH']): src += Glob('ports/spi_flash_init.c') +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c index 030926aa8e..91cde7a95d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c @@ -14,54 +14,56 @@ */ void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - + /**Configure the main internal regulator output voltage + */ __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 360; + RCC_OscInitStruct.PLL.PLLM = 15; + RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - + /**Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; - PeriphClkInitStruct.PLLSAI.PLLSAIN = 260; - PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; - PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } - - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RT_TICK_PER_SECOND); - - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); } /** Pinout Configuration diff --git a/bsp/stm32/stm32f429-atk-apollo/rtconfig.h b/bsp/stm32/stm32f429-atk-apollo/rtconfig.h index d236ab8d53..f3f451258a 100644 --- a/bsp/stm32/stm32f429-atk-apollo/rtconfig.h +++ b/bsp/stm32/stm32f429-atk-apollo/rtconfig.h @@ -39,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -76,6 +77,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -147,19 +149,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 diff --git a/bsp/stm32/stm32f429-fire-challenger/.config b/bsp/stm32/stm32f429-fire-challenger/.config index 8bab59ba52..5165730ff4 100644 --- a/bsp/stm32/stm32f429-fire-challenger/.config +++ b/bsp/stm32/stm32f429-fire-challenger/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -110,6 +111,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -179,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -278,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -292,6 +297,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -307,10 +313,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set -# -# sample package -# - # # samples: kernel and components samples # @@ -318,30 +320,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -359,6 +338,8 @@ CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_SPI_FLASH is not set # CONFIG_BSP_USING_MPU6050 is not set # CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_POT is not set +# CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers @@ -368,11 +349,17 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_UART_USING_DMA_RX is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_SPI2 is not set # CONFIG_BSP_USING_SPI5 is not set # CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/.mxproject index ed2f57d7ca..9bddc2835f 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/.mxproject @@ -1,13 +1,13 @@ [PreviousGenFiles] -HeaderPath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc +HeaderPath=D:/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src +SourcePath=D:/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config//MDK-ARM/startup_stm32f429xx.s; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc index 9e40ddce40..0757e09ae6 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc @@ -12,15 +12,20 @@ KeepUserPlacement=false Mcu.Family=STM32F4 Mcu.IP0=ADC1 Mcu.IP1=ETH +Mcu.IP10=TIM5 +Mcu.IP11=TIM11 +Mcu.IP12=TIM13 +Mcu.IP13=TIM14 +Mcu.IP14=USART1 Mcu.IP2=FMC Mcu.IP3=IWDG Mcu.IP4=NVIC Mcu.IP5=RCC Mcu.IP6=RTC -Mcu.IP7=SPI5 -Mcu.IP8=SYS -Mcu.IP9=USART1 -Mcu.IPNb=10 +Mcu.IP7=SDIO +Mcu.IP8=SPI5 +Mcu.IP9=SYS +Mcu.IPNb=15 Mcu.Name=STM32F429I(E-G)Tx Mcu.Package=LQFP176 Mcu.Pin0=PC14/OSC32_IN @@ -58,34 +63,47 @@ Mcu.Pin37=PB11 Mcu.Pin38=PH6 Mcu.Pin39=PH7 Mcu.Pin4=PF2 -Mcu.Pin40=PD8 -Mcu.Pin41=PD9 -Mcu.Pin42=PD10 -Mcu.Pin43=PD14 -Mcu.Pin44=PD15 -Mcu.Pin45=PG4 -Mcu.Pin46=PG5 -Mcu.Pin47=PG8 -Mcu.Pin48=PA9 -Mcu.Pin49=PA10 +Mcu.Pin40=PH10 +Mcu.Pin41=PH11 +Mcu.Pin42=PH12 +Mcu.Pin43=PD8 +Mcu.Pin44=PD9 +Mcu.Pin45=PD10 +Mcu.Pin46=PD14 +Mcu.Pin47=PD15 +Mcu.Pin48=PG4 +Mcu.Pin49=PG5 Mcu.Pin5=PF3 -Mcu.Pin50=PA13 -Mcu.Pin51=PA14 -Mcu.Pin52=PD0 -Mcu.Pin53=PD1 -Mcu.Pin54=PG13 -Mcu.Pin55=PG14 -Mcu.Pin56=PG15 -Mcu.Pin57=PE0 -Mcu.Pin58=PE1 -Mcu.Pin59=VP_IWDG_VS_IWDG +Mcu.Pin50=PG8 +Mcu.Pin51=PC8 +Mcu.Pin52=PC9 +Mcu.Pin53=PA9 +Mcu.Pin54=PA10 +Mcu.Pin55=PA13 +Mcu.Pin56=PA14 +Mcu.Pin57=PC10 +Mcu.Pin58=PC11 +Mcu.Pin59=PC12 Mcu.Pin6=PF4 -Mcu.Pin60=VP_RTC_VS_RTC_Activate -Mcu.Pin61=VP_SYS_VS_Systick +Mcu.Pin60=PD0 +Mcu.Pin61=PD1 +Mcu.Pin62=PD2 +Mcu.Pin63=PG13 +Mcu.Pin64=PG14 +Mcu.Pin65=PG15 +Mcu.Pin66=PE0 +Mcu.Pin67=PE1 +Mcu.Pin68=VP_IWDG_VS_IWDG +Mcu.Pin69=VP_RTC_VS_RTC_Activate Mcu.Pin7=PF5 +Mcu.Pin70=VP_SYS_VS_Systick +Mcu.Pin71=VP_TIM5_VS_ClockSourceINT +Mcu.Pin72=VP_TIM11_VS_ClockSourceINT +Mcu.Pin73=VP_TIM13_VS_ClockSourceINT +Mcu.Pin74=VP_TIM14_VS_ClockSourceINT Mcu.Pin8=PF7 Mcu.Pin9=PF8 -Mcu.PinsNb=62 +Mcu.PinsNb=75 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F429IGTx @@ -121,6 +139,12 @@ PB11.Signal=ETH_TX_EN PC0.Signal=FMC_SDNWE PC1.Mode=RMII PC1.Signal=ETH_MDC +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK PC14/OSC32_IN.Mode=LSE-External-Oscillator PC14/OSC32_IN.Signal=RCC_OSC32_IN PC15/OSC32_OUT.Mode=LSE-External-Oscillator @@ -131,6 +155,10 @@ PC4.Mode=RMII PC4.Signal=ETH_RXD0 PC5.Mode=RMII PC5.Signal=ETH_RXD1 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Line=STM32F429/439 PCC.MCU=STM32F429I(E-G)Tx @@ -144,6 +172,8 @@ PD1.Signal=FMC_D3_DA3 PD10.Signal=FMC_D15_DA15 PD14.Signal=FMC_D0_DA0 PD15.Signal=FMC_D1_DA1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD PD8.Signal=FMC_D13_DA13 PD9.Signal=FMC_D14_DA14 PE0.Signal=FMC_NBL0 @@ -192,6 +222,10 @@ PH0/OSC_IN.Mode=HSE-External-Oscillator PH0/OSC_IN.Signal=RCC_OSC_IN PH1/OSC_OUT.Mode=HSE-External-Oscillator PH1/OSC_OUT.Signal=RCC_OSC_OUT +PH10.Locked=true +PH10.Signal=S_TIM5_CH1 +PH11.Signal=S_TIM5_CH2 +PH12.Signal=S_TIM5_CH3 PH6.Mode=SdramChipSelect2_1 PH6.Signal=FMC_SDNE1 PH7.Mode=SdramChipSelect2_1 @@ -223,8 +257,8 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_SPI5_Init-SPI5-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true -RCC.48MHZClocksFreq_Value=90000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_SPI5_Init-SPI5-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM5_Init-TIM5-false-HAL-true +RCC.48MHZClocksFreq_Value=45000000 RCC.AHBFreq_Value=180000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 RCC.APB1Freq_Value=45000000 @@ -240,16 +274,18 @@ RCC.HCLKFreq_Value=180000000 RCC.HSE_VALUE=25000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=160000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ RCC.LCDTFTFreq_Value=20416666.666666668 RCC.LSI_VALUE=32000 RCC.MCO2PinFreq_Value=180000000 RCC.PLLCLKFreq_Value=180000000 RCC.PLLM=15 RCC.PLLN=216 -RCC.PLLQCLKFreq_Value=90000000 +RCC.PLLQ=8 +RCC.PLLQCLKFreq_Value=45000000 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE +RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE RCC.RTCFreq_Value=32768 RCC.RTCHSEDivFreq_Value=12500000 RCC.SAI_AClocksFreq_Value=20416666.666666668 @@ -338,11 +374,21 @@ SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1 SH.FMC_SDNRAS.ConfNb=1 SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1 SH.FMC_SDNWE.ConfNb=1 +SH.S_TIM5_CH1.0=TIM5_CH1,PWM Generation1 CH1 +SH.S_TIM5_CH1.ConfNb=1 +SH.S_TIM5_CH2.0=TIM5_CH2,PWM Generation2 CH2 +SH.S_TIM5_CH2.ConfNb=1 +SH.S_TIM5_CH3.0=TIM5_CH3,PWM Generation3 CH3 +SH.S_TIM5_CH3.ConfNb=1 SPI5.CalculateBaudRate=45.0 MBits/s SPI5.Direction=SPI_DIRECTION_2LINES SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate SPI5.Mode=SPI_MODE_MASTER SPI5.VirtualType=VM_MASTER +TIM5.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +TIM5.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM5.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM5.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3 USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC VP_IWDG_VS_IWDG.Mode=IWDG_Activate @@ -351,4 +397,12 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +VP_TIM5_VS_ClockSourceINT.Mode=Internal +VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT board=custom diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/main.h index 9d41187606..f1494d6236 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/main.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/main.h @@ -70,6 +70,8 @@ extern "C" { /* USER CODE END EM */ +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 884f137629..eb06eacdbb 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -71,10 +71,10 @@ /* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED /* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c index f458d370ad..fc5ca269ae 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/main.c @@ -70,8 +70,15 @@ IWDG_HandleTypeDef hiwdg; RTC_HandleTypeDef hrtc; +SD_HandleTypeDef hsd; + SPI_HandleTypeDef hspi5; +TIM_HandleTypeDef htim5; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim13; +TIM_HandleTypeDef htim14; + UART_HandleTypeDef huart1; SDRAM_HandleTypeDef hsdram1; @@ -90,6 +97,11 @@ static void MX_FMC_Init(void); static void MX_ADC1_Init(void); static void MX_RTC_Init(void); static void MX_IWDG_Init(void); +static void MX_TIM14_Init(void); +static void MX_TIM13_Init(void); +static void MX_TIM11_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_TIM5_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -134,6 +146,11 @@ int main(void) MX_ADC1_Init(); MX_RTC_Init(); MX_IWDG_Init(); + MX_TIM14_Init(); + MX_TIM13_Init(); + MX_TIM11_Init(); + MX_SDIO_SD_Init(); + MX_TIM5_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -175,7 +192,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 15; RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -364,6 +381,42 @@ static void MX_RTC_Init(void) } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + /** * @brief SPI5 Initialization Function * @param None @@ -402,6 +455,162 @@ static void MX_SPI5_Init(void) } +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 0; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 0; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + HAL_TIM_MspPostInit(&htim5); + +} + +/** + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 0; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + +} + +/** + * @brief TIM13 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM13_Init(void) +{ + + /* USER CODE BEGIN TIM13_Init 0 */ + + /* USER CODE END TIM13_Init 0 */ + + /* USER CODE BEGIN TIM13_Init 1 */ + + /* USER CODE END TIM13_Init 1 */ + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = 0; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM13_Init 2 */ + + /* USER CODE END TIM13_Init 2 */ + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None diff --git a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 77f1396dbe..ff0bd06d02 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -78,7 +78,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -320,6 +322,94 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) } +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ + +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + /** * @brief SPI MSP Initialization * This function configures the hardware resources used in this example @@ -390,6 +480,148 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) } +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ + + /* USER CODE END TIM5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspPostInit 0 */ + + /* USER CODE END TIM5_MspPostInit 0 */ + + __HAL_RCC_GPIOH_CLK_ENABLE(); + /**TIM5 GPIO Configuration + PH10 ------> TIM5_CH1 + PH11 ------> TIM5_CH2 + PH12 ------> TIM5_CH3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM5_MspPostInit 1 */ + + /* USER CODE END TIM5_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ + + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ + + /* USER CODE END TIM5_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig index ecc175f4f5..0323f139ce 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig @@ -44,11 +44,29 @@ menu "Onboard Peripheral Drivers" default 0x00 endif + config BSP_USING_RGB + bool "Enable RGB LED (timer5 channel1 - 3)" + select RT_USING_PWM + select BSP_USING_PWM + select BSP_USING_PWM5 + select BSP_USING_PWM5_CH1 + select BSP_USING_PWM5_CH2 + select BSP_USING_PWM5_CH3 + default n + config BSP_USING_POT bool "Enable potentiometer" select BSP_USING_ADC select BSP_USING_ADC1 - default n + default n + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + select RT_USING_PIN + default n endmenu @@ -101,6 +119,47 @@ menu "On-chip Peripheral Drivers" bool "Enable SPI DMA support" default n + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM5 + bool "Enable timer5 output pwm" + default n + if BSP_USING_PWM5 + config BSP_USING_PWM5_CH1 + bool "Enable PWM5 channel1" + default n + + config BSP_USING_PWM5_CH2 + bool "Enable PWM5 channel2" + default n + + config BSP_USING_PWM5_CH3 + bool "Enable PWM5 channel3" + default n + endif + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n @@ -148,6 +207,12 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + endmenu menu "Board extended module Drivers" diff --git a/bsp/stm32/stm32f429-fire-challenger/board/SConscript b/bsp/stm32/stm32f429-fire-challenger/board/SConscript index 7345e4e191..530a967740 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/SConscript +++ b/bsp/stm32/stm32f429-fire-challenger/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_ETH']): if GetDepend(['BSP_USING_SPI_FLASH']): src += Glob('ports/spi_flash_init.c') +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c index 623e1e0f04..77961c793c 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c @@ -14,6 +14,7 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; /**Configure the main internal regulator output voltage */ @@ -21,14 +22,17 @@ void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /**Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 15; RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -52,6 +56,12 @@ void SystemClock_Config(void) { Error_Handler(); } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } } void MX_GPIO_Init(void) diff --git a/bsp/stm32/stm32f429-fire-challenger/rtconfig.h b/bsp/stm32/stm32f429-fire-challenger/rtconfig.h index 1357a79922..83dbf4c0d3 100644 --- a/bsp/stm32/stm32f429-fire-challenger/rtconfig.h +++ b/bsp/stm32/stm32f429-fire-challenger/rtconfig.h @@ -39,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -77,6 +78,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -148,19 +150,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 diff --git a/bsp/stm32/stm32l475-atk-pandora/.config b/bsp/stm32/stm32l475-atk-pandora/.config new file mode 100644 index 0000000000..7d6a640f6b --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/.config @@ -0,0 +1,364 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32L4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32L475VE=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_STLINK_TO_USART=y +# CONFIG_BSP_USING_QSPI_FLASH is not set +# CONFIG_BSP_USING_SDCARD is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_UART_USING_DMA_RX is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_SPI_USING_DMA is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_QSPI_USING_DMA is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_I2C3 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32l475-atk-pandora/.gitignore b/bsp/stm32/stm32l475-atk-pandora/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32l475-atk-pandora/Kconfig b/bsp/stm32/stm32l475-atk-pandora/Kconfig new file mode 100644 index 0000000000..d174bcc585 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32l475-atk-pandora/README.md b/bsp/stm32/stm32l475-atk-pandora/README.md new file mode 100644 index 0000000000..70a28eda25 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/README.md @@ -0,0 +1,142 @@ +# STM32L475 潘多拉开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 STM32L475 潘多拉开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +潘多拉 STM32L475 是正点原子推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 80Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32L475 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32L475VET6，主频 80MHz，512KB FLASH ，128KB RAM +- 外部 FLASH：W25Q128（SPI，16MB） +- 常用外设 + - RGB 状态指示灯：1个，（红、绿、蓝三色） + - 按键：4个，KEY_UP（兼具唤醒功能，PC13），K0（PD10），K1（PD9），K2（PD8） + - 红外发射头，红外接收头 + - 有源蜂鸣器：1个 + - 光环境传感器：1个 + - 贴片电机：1个 + - 六轴传感器：1个 + - 高性能音频解码芯片：1个 + - 温湿度传感器（AHT10）：1个 + - TFTLCD 显示屏：1个 + - WIFI 模块（AP6181）：1个 + - 板载 ST LINK V2.1 功能 +- 常用接口：SD 卡接口、USB OTG Micro USB 接口 +- 调试接口，ST-LINK Micro USB 接口 + +开发板更多详细信息请参考正点原子 [STM32 潘多拉开发板介绍](https://eboard.taobao.com/index.htm)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| 板载 ST-LINK 转串口 | 支持 | | +| QSPI_FLASH | 支持 | | +| SD卡 | 支持 | | +| 贴片电机 | 暂不支持 |即将支持 | +| 温湿度传感器 | 暂不支持 |即将支持 | +| 六轴传感器 | 暂不支持 |即将支持 | +| 光环境传感器 | 暂不支持 |即将支持 | +| 音频解码 | 不支持 | | +| TFTLCD | 不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | | +| SPI | 支持 | | +| QSPI | 支持 | | +| I2C | 支持 | | +| TIM | 支持 | | +| ADC | 支持 | | +| RTC | 支持 | | +| WDT | 支持 | | +| PWM | 支持 | | +| USB Device | 暂不支持 | 即将支持 | +| USB Host | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | +| ATK-ESP8266 模块 | 暂不支持 | 即将支持 | +| enc28j60 模块 | 暂不支持 | 即将支持 | + +使用该开发板的更多高级功能请参考 RT-Thread 代码仓库： [RT-Thread IoT-Board SDK](https://github.com/RT-Thread/IoT_Board)。 + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 ST-LINK 下载程序，只需一根 USB 线连接开发板，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LED 会周期性闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [BSP 进阶使用指南](../docs/BSP进阶使用指南.md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [SummerGift](https://github.com/SummerGGift) \ No newline at end of file diff --git a/bsp/stm32/stm32l475-atk-pandora/SConscript b/bsp/stm32/stm32l475-atk-pandora/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32l475-atk-pandora/SConstruct b/bsp/stm32/stm32l475-atk-pandora/SConstruct new file mode 100644 index 0000000000..f28e552248 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/SConstruct @@ -0,0 +1,58 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map rt-thread.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32L4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/SConscript b/bsp/stm32/stm32l475-atk-pandora/applications/SConscript new file mode 100644 index 0000000000..4939638d41 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [str(Dir('#')), cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c new file mode 100644 index 0000000000..a802fd07e8 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift change to new framework + */ + +#include +#include +#include + +int main(void) +{ + int count = 1; + while (count++) + { + rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_thread_mdelay(500); + } + return RT_EOK; +} diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..19b0ffa4c5 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/.mxproject @@ -0,0 +1,13 @@ +[PreviousGenFiles] +HeaderPath=D:/BspFramework/rt-thread/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc +HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; +SourcePath=D:/BspFramework/rt-thread/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src +SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null; +HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc; + diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..9c54f82425 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,93 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h new file mode 100644 index 0000000000..f67587d479 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -0,0 +1,434 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_CONF_H +#define __STM32L4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DFSDM_MODULE_ENABLED */ +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_FIREWALL_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +#define HAL_IWDG_MODULE_ENABLED +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +#define HAL_QSPI_MODULE_ENABLED +/*#define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_SWPMI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +/*#define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @brief External clock source for SAI2 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l4xx_hal_rcc.h" + #include "stm32l4xx_hal_rcc_ex.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l4xx_hal_dma.h" + #include "stm32l4xx_hal_dma_ex.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32l4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32l4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32l4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32l4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l4xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32l4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l4xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32l4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32l4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32l4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32l4xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l4xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h new file mode 100644 index 0000000000..29156563cb --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_it.h @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_IT_H +#define __STM32L4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc new file mode 100644 index 0000000000..1ab8ead3de --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/STM32L475VE.ioc @@ -0,0 +1,261 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_14 +ADC1.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,OffsetNumber-15\#ChannelRegularConversion,NbrOfConversionFlag,master +ADC1.NbrOfConversionFlag=1 +ADC1.OffsetNumber-15\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.Rank-15\#ChannelRegularConversion=1 +ADC1.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 +ADC1.master=1 +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32L4 +Mcu.IP0=ADC1 +Mcu.IP1=IWDG +Mcu.IP10=TIM15 +Mcu.IP11=TIM16 +Mcu.IP12=TIM17 +Mcu.IP13=USART1 +Mcu.IP14=USART2 +Mcu.IP2=NVIC +Mcu.IP3=QUADSPI +Mcu.IP4=RCC +Mcu.IP5=RTC +Mcu.IP6=SPI1 +Mcu.IP7=SPI2 +Mcu.IP8=SYS +Mcu.IP9=TIM4 +Mcu.IPNb=15 +Mcu.Name=STM32L475V(C-E-G)Tx +Mcu.Package=LQFP100 +Mcu.Pin0=PC14-OSC32_IN (PC14) +Mcu.Pin1=PC15-OSC32_OUT (PC15) +Mcu.Pin10=PE10 +Mcu.Pin11=PE11 +Mcu.Pin12=PE12 +Mcu.Pin13=PE13 +Mcu.Pin14=PE14 +Mcu.Pin15=PE15 +Mcu.Pin16=PB13 +Mcu.Pin17=PB14 +Mcu.Pin18=PB15 +Mcu.Pin19=PA9 +Mcu.Pin2=PH0-OSC_IN (PH0) +Mcu.Pin20=PA10 +Mcu.Pin21=PA13 (JTMS-SWDIO) +Mcu.Pin22=PA14 (JTCK-SWCLK) +Mcu.Pin23=PB7 +Mcu.Pin24=PB8 +Mcu.Pin25=VP_IWDG_VS_IWDG +Mcu.Pin26=VP_RTC_VS_RTC_Activate +Mcu.Pin27=VP_SYS_VS_Systick +Mcu.Pin28=VP_TIM4_VS_ClockSourceINT +Mcu.Pin29=VP_TIM15_VS_ClockSourceINT +Mcu.Pin3=PH1-OSC_OUT (PH1) +Mcu.Pin30=VP_TIM16_VS_ClockSourceINT +Mcu.Pin31=VP_TIM17_VS_ClockSourceINT +Mcu.Pin4=PA2 +Mcu.Pin5=PA3 +Mcu.Pin6=PA5 +Mcu.Pin7=PA6 +Mcu.Pin8=PA7 +Mcu.Pin9=PC5 +Mcu.PinsNb=32 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32L475VETx +MxCube.Version=5.0.0 +MxDb.Version=DB.5.0.0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13\ (JTMS-SWDIO).Mode=Serial_Wire +PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO +PA14\ (JTCK-SWCLK).Mode=Serial_Wire +PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB13.Locked=true +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB14.Locked=true +PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.Locked=true +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI +PB7.Locked=true +PB7.Signal=S_TIM4_CH2 +PB8.Locked=true +PB8.Signal=S_TIM4_CH3 +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT +PC5.Signal=ADCx_IN14 +PCC.Checker=true +PCC.Line=STM32L4x5 +PCC.MCU=STM32L475V(C-E-G)Tx +PCC.PartNumber=STM32L475VETx +PCC.Seq0=0 +PCC.Series=STM32L4 +PCC.Temperature=25 +PCC.Vdd=null +PE10.Mode=Single Bank +PE10.Signal=QUADSPI_CLK +PE11.Mode=Single Bank +PE11.Signal=QUADSPI_NCS +PE12.Locked=true +PE12.Mode=Single Bank +PE12.Signal=QUADSPI_BK1_IO0 +PE13.Locked=true +PE13.Mode=Single Bank +PE13.Signal=QUADSPI_BK1_IO1 +PE14.Locked=true +PE14.Mode=Single Bank +PE14.Signal=QUADSPI_BK1_IO2 +PE15.Locked=true +PE15.Mode=Single Bank +PE15.Signal=QUADSPI_BK1_IO3 +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32L475VETx +ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.13.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STM32L475VE.ioc +ProjectManager.ProjectName=STM32L475VE +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true,11-MX_TIM17_Init-TIM17-false-HAL-true,12-MX_TIM16_Init-TIM16-false-HAL-true,13-MX_TIM15_Init-TIM15-false-HAL-true,14-MX_TIM4_Init-TIM4-false-HAL-true +RCC.ADCFreq_Value=32000000 +RCC.AHBFreq_Value=80000000 +RCC.APB1Freq_Value=80000000 +RCC.APB1TimFreq_Value=80000000 +RCC.APB2Freq_Value=80000000 +RCC.APB2TimFreq_Value=80000000 +RCC.CortexFreq_Value=80000000 +RCC.DFSDMFreq_Value=80000000 +RCC.FCLKCortexFreq_Value=80000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=80000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=80000000 +RCC.I2C2Freq_Value=80000000 +RCC.I2C3Freq_Value=80000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value +RCC.LPTIM1Freq_Value=80000000 +RCC.LPTIM2Freq_Value=80000000 +RCC.LPUART1Freq_Value=80000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=80000000 +RCC.MSI_VALUE=4000000 +RCC.PLLN=20 +RCC.PLLPoutputFreq_Value=22857142.85714286 +RCC.PLLQoutputFreq_Value=80000000 +RCC.PLLRCLKFreq_Value=80000000 +RCC.PLLSAI1PoutputFreq_Value=9142857.142857144 +RCC.PLLSAI1QoutputFreq_Value=32000000 +RCC.PLLSAI1RoutputFreq_Value=32000000 +RCC.PLLSAI2PoutputFreq_Value=9142857.142857144 +RCC.PLLSAI2RoutputFreq_Value=32000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.PWRFreq_Value=80000000 +RCC.RNGFreq_Value=32000000 +RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.SAI1Freq_Value=9142857.142857144 +RCC.SAI2Freq_Value=9142857.142857144 +RCC.SDMMCFreq_Value=32000000 +RCC.SWPMI1Freq_Value=80000000 +RCC.SYSCLKFreq_VALUE=80000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=80000000 +RCC.UART5Freq_Value=80000000 +RCC.USART1Freq_Value=80000000 +RCC.USART2Freq_Value=80000000 +RCC.USART3Freq_Value=80000000 +RCC.USBFreq_Value=32000000 +RCC.VCOInputFreq_Value=8000000 +RCC.VCOOutputFreq_Value=160000000 +RCC.VCOSAI1OutputFreq_Value=64000000 +RCC.VCOSAI2OutputFreq_Value=64000000 +SH.ADCx_IN14.0=ADC1_IN14,IN14-Single-Ended +SH.ADCx_IN14.ConfNb=1 +SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 +SH.S_TIM4_CH2.ConfNb=1 +SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 +SH.S_TIM4_CH3.ConfNb=1 +SPI1.CalculateBaudRate=40.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +SPI2.CalculateBaudRate=40.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation2 CH2 +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +USART2.IPParameters=VirtualMode-Asynchronous +USART2.VirtualMode-Asynchronous=VM_ASYNC +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM15_VS_ClockSourceINT.Mode=Internal +VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT +VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT +VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT +board=custom diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..105588b186 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/main.c @@ -0,0 +1,777 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +IWDG_HandleTypeDef hiwdg; + +QSPI_HandleTypeDef hqspi; + +RTC_HandleTypeDef hrtc; + +SPI_HandleTypeDef hspi1; +SPI_HandleTypeDef hspi2; + +TIM_HandleTypeDef htim4; +TIM_HandleTypeDef htim15; +TIM_HandleTypeDef htim16; +TIM_HandleTypeDef htim17; + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_USART2_UART_Init(void); +static void MX_QUADSPI_Init(void); +static void MX_SPI1_Init(void); +static void MX_SPI2_Init(void); +static void MX_RTC_Init(void); +static void MX_ADC1_Init(void); +static void MX_IWDG_Init(void); +static void MX_TIM17_Init(void); +static void MX_TIM16_Init(void); +static void MX_TIM15_Init(void); +static void MX_TIM4_Init(void); +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_USART2_UART_Init(); + MX_QUADSPI_Init(); + MX_SPI1_Init(); + MX_SPI2_Init(); + MX_RTC_Init(); + MX_ADC1_Init(); + MX_IWDG_Init(); + MX_TIM17_Init(); + MX_TIM16_Init(); + MX_TIM15_Init(); + MX_TIM4_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /**Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1 + |RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_ADC; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + PeriphClkInit.PLLSAI1.PLLSAI1N = 8; + PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_ADC1CLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_MultiModeTypeDef multimode = {0}; + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /**Common config + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc1.Init.LowPowerAutoWait = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc1.Init.OversamplingMode = DISABLE; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /**Configure the ADC multi-mode + */ + multimode.Mode = ADC_MODE_INDEPENDENT; + if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) + { + Error_Handler(); + } + /**Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_14; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + hiwdg.Instance = IWDG; + hiwdg.Init.Prescaler = IWDG_PRESCALER_4; + hiwdg.Init.Window = 4095; + hiwdg.Init.Reload = 4095; + if (HAL_IWDG_Init(&hiwdg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief QUADSPI Initialization Function + * @param None + * @retval None + */ +static void MX_QUADSPI_Init(void) +{ + + /* USER CODE BEGIN QUADSPI_Init 0 */ + + /* USER CODE END QUADSPI_Init 0 */ + + /* USER CODE BEGIN QUADSPI_Init 1 */ + + /* USER CODE END QUADSPI_Init 1 */ + /* QUADSPI parameter configuration*/ + hqspi.Instance = QUADSPI; + hqspi.Init.ClockPrescaler = 255; + hqspi.Init.FifoThreshold = 1; + hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; + hqspi.Init.FlashSize = 1; + hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; + hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; + if (HAL_QSPI_Init(&hqspi) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN QUADSPI_Init 2 */ + + /* USER CODE END QUADSPI_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /**Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_4BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 7; + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 7; + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 0; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + +} + +/** + * @brief TIM15 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM15_Init(void) +{ + + /* USER CODE BEGIN TIM15_Init 0 */ + + /* USER CODE END TIM15_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM15_Init 1 */ + + /* USER CODE END TIM15_Init 1 */ + htim15.Instance = TIM15; + htim15.Init.Prescaler = 0; + htim15.Init.CounterMode = TIM_COUNTERMODE_UP; + htim15.Init.Period = 0; + htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim15.Init.RepetitionCounter = 0; + htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim15) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim15, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM15_Init 2 */ + + /* USER CODE END TIM15_Init 2 */ + +} + +/** + * @brief TIM16 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM16_Init(void) +{ + + /* USER CODE BEGIN TIM16_Init 0 */ + + /* USER CODE END TIM16_Init 0 */ + + /* USER CODE BEGIN TIM16_Init 1 */ + + /* USER CODE END TIM16_Init 1 */ + htim16.Instance = TIM16; + htim16.Init.Prescaler = 0; + htim16.Init.CounterMode = TIM_COUNTERMODE_UP; + htim16.Init.Period = 0; + htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim16.Init.RepetitionCounter = 0; + htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim16) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM16_Init 2 */ + + /* USER CODE END TIM16_Init 2 */ + +} + +/** + * @brief TIM17 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM17_Init(void) +{ + + /* USER CODE BEGIN TIM17_Init 0 */ + + /* USER CODE END TIM17_Init 0 */ + + /* USER CODE BEGIN TIM17_Init 1 */ + + /* USER CODE END TIM17_Init 1 */ + htim17.Instance = TIM17; + htim17.Init.Prescaler = 0; + htim17.Init.CounterMode = TIM_COUNTERMODE_UP; + htim17.Init.Period = 0; + htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim17.Init.RepetitionCounter = 0; + htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim17) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM17_Init 2 */ + + /* USER CODE END TIM17_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + while(1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c new file mode 100644 index 0000000000..bfcfd2d7bd --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -0,0 +1,660 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32l4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PC5 ------> ADC1_IN14 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ + +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PC5 ------> ADC1_IN14 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_5); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief QSPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + + /* USER CODE END QUADSPI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**QUADSPI GPIO Configuration + PE10 ------> QUADSPI_CLK + PE11 ------> QUADSPI_NCS + PE12 ------> QUADSPI_BK1_IO0 + PE13 ------> QUADSPI_BK1_IO1 + PE14 ------> QUADSPI_BK1_IO2 + PE15 ------> QUADSPI_BK1_IO3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 + |GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + } + +} + +/** +* @brief QSPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ + +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) +{ + + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PE10 ------> QUADSPI_CLK + PE11 ------> QUADSPI_NCS + PE12 ------> QUADSPI_BK1_IO0 + PE13 ------> QUADSPI_BK1_IO1 + PE14 ------> QUADSPI_BK1_IO2 + PE15 ------> QUADSPI_BK1_IO3 + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 + |GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ + +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + else if(htim_base->Instance==TIM15) + { + /* USER CODE BEGIN TIM15_MspInit 0 */ + + /* USER CODE END TIM15_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM15_CLK_ENABLE(); + /* USER CODE BEGIN TIM15_MspInit 1 */ + + /* USER CODE END TIM15_MspInit 1 */ + } + else if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspInit 0 */ + + /* USER CODE END TIM16_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM16_CLK_ENABLE(); + /* USER CODE BEGIN TIM16_MspInit 1 */ + + /* USER CODE END TIM16_MspInit 1 */ + } + else if(htim_base->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspInit 0 */ + + /* USER CODE END TIM17_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM17_CLK_ENABLE(); + /* USER CODE BEGIN TIM17_MspInit 1 */ + + /* USER CODE END TIM17_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PB7 ------> TIM4_CH2 + PB8 ------> TIM4_CH3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM15) + { + /* USER CODE BEGIN TIM15_MspDeInit 0 */ + + /* USER CODE END TIM15_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM15_CLK_DISABLE(); + /* USER CODE BEGIN TIM15_MspDeInit 1 */ + + /* USER CODE END TIM15_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspDeInit 0 */ + + /* USER CODE END TIM16_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM16_CLK_DISABLE(); + /* USER CODE BEGIN TIM16_MspDeInit 1 */ + + /* USER CODE END TIM16_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspDeInit 0 */ + + /* USER CODE END TIM17_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM17_CLK_DISABLE(); + /* USER CODE BEGIN TIM17_MspDeInit 1 */ + + /* USER CODE END TIM17_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ + +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c new file mode 100644 index 0000000000..ab5c0b7d8e --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/stm32l4xx_it.c @@ -0,0 +1,217 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32l4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32L4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32l4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/system_stm32l4xx.c b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/system_stm32l4xx.c new file mode 100644 index 0000000000..c76fe45ee1 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Src/system_stm32l4xx.c @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * PLLSAI1_P | NA + *----------------------------------------------------------------------------- + * PLLSAI1_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI1_R | NA + *----------------------------------------------------------------------------- + * PLLSAI2_P | NA + *----------------------------------------------------------------------------- + * PLLSAI2_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI2_R | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** @addtogroup STM32L4xx_System_Private_Includes + * @{ + */ + +#include "stm32l4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000U; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= 0xEAF6FFFFU; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000U; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; + + /* Get MSI Range frequency--------------------------------------------------*/ + if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig new file mode 100644 index 0000000000..61f2c7db74 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -0,0 +1,210 @@ +menu "Hardware Drivers Config" + +config SOC_STM32L475VE + bool + select SOC_SERIES_STM32L4 + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_STLINK_TO_USART + bool "Enable STLINK TO USART (uart1)" + select BSP_USING_UART1 + default y + + config BSP_USING_QSPI_FLASH + bool "Enable QSPI FLASH" + select BSP_USING_QSPI + select RT_USING_SFUD + select RT_SFUD_USING_QSPI + default n + + config BSP_USING_SDCARD + bool "Enable SDCARD (spi1)" + select BSP_USING_SPI1 + select BSP_SPI_USING_DMA + select RT_USING_SPI_MSD + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_UART1 + bool "Enable UART1" + select RT_USING_SERIAL + default y + + config BSP_USING_UART2 + bool "Enable UART2" + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Enable UART3" + select RT_USING_SERIAL + default n + + config BSP_UART_USING_DMA_RX + bool "Enable UART RX DMA support" + default n + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + select RT_USING_SPI + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + select RT_USING_SPI + default n + + config BSP_SPI_USING_DMA + bool "Enable SPI DMA support" + default n + + config BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 15 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 16 + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C2 + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 176 + default 47 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 1 176 + default 48 + endif + + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS (software simulation)" + default n + select RT_USING_I2CS + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C3 + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 1 176 + default 92 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 1 176 + default 93 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM15 + bool "Enable TIM15" + default n + + config BSP_USING_TIM16 + bool "Enable TIM16" + default n + + config BSP_USING_TIM17 + bool "Enable TIM17" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM4 + bool "Enable timer4 output pwm" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4_CH2 + bool "Enable PWM4 channel2" + default n + + config BSP_USING_PWM4_CH3 + bool "Enable PWM4 channel3" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + + config BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32l475-atk-pandora/board/SConscript b/bsp/stm32/stm32l475-atk-pandora/board/SConscript new file mode 100644 index 0000000000..fb51c3cc0a --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/SConscript @@ -0,0 +1,37 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32l4xx_hal_msp.c +''') + +if GetDepend(['BSP_USING_QSPI_FLASH']): + src += Glob('ports/drv_qspi_flash.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l475xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/arm/startup_stm32l475xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/startup_stm32l475xx.s'] + +CPPDEFINES = ['STM32L475xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c new file mode 100644 index 0000000000..4c6d7f61ea --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -0,0 +1,85 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + */ + +#include + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } +} + +void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + +} + +#ifdef RT_USING_PIN +int board_pin_init(void) +{ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + return 0; +} +INIT_BOARD_EXPORT(board_pin_init); +#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h new file mode 100644 index 0000000000..43ea79b4e4 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift change to new framework + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" + +#ifdef BSP_USING_GPIO +#include "drv_gpio.h" +#endif + +#define STM32_SRAM1_SIZE (96) +#define STM32_SRAM1_START (0x20000000) +#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024) + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (512 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define HEAP_BEGIN STM32_SRAM1_START +#define HEAP_END STM32_SRAM1_END + +/* Board Pin definitions */ +#define LED0_PIN GET_PIN(E, 7) +#define LED1_PIN GET_PIN(E, 8) + +void SystemClock_Config(void); +void MX_GPIO_Init(void); + +#endif + diff --git a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf new file mode 100644 index 0000000000..11d1d86df5 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x20017FFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x10007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { section .sram }; +place in RAM2_region { readwrite, block CSTACK}; diff --git a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds new file mode 100644 index 0000000000..91149a6a2f --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.lds @@ -0,0 +1,144 @@ +/* + * linker script for STM32L4XX with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ + RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 32k /* 32K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM2 + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM2 + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM2 + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.sct b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.sct new file mode 100644 index 0000000000..ea1ec95c67 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM2 0x10000000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c new file mode 100644 index 0000000000..1b9120a5c5 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 zylx change to new framework + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_QSPI_FLASH + +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +char w25qxx_read_status_register2(struct rt_qspi_device *device) +{ + /* 0x35 read status register2 */ + char instruction = 0x35, status; + + rt_qspi_send_then_recv(device, &instruction, 1, &status, 1); + + return status; +} + +void w25qxx_write_enable(struct rt_qspi_device *device) +{ + /* 0x06 write enable */ + char instruction = 0x06; + + rt_qspi_send(device, &instruction, 1); +} + +void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) +{ + char status = 0; + /* 0x38 enter qspi mode */ + char instruction = 0x38; + char write_status2_buf[2] = {0}; + + /* 0x31 write status register2 */ + write_status2_buf[0] = 0x31; + + status = w25qxx_read_status_register2(device); + if (!(status & 0x02)) + { + status |= 1 << 1; + w25qxx_write_enable(device); + write_status2_buf[1] = status; + rt_qspi_send(device, &write_status2_buf, 2); + rt_qspi_send(device, &instruction, 1); + rt_kprintf("flash already enter qspi mode\n"); + rt_thread_mdelay(10); + } +} + +static int rt_hw_qspi_flash_with_sfud_init(void) +{ + stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); + + /* init w25q128 */ + if (RT_NULL == rt_sfud_flash_probe("w25q128", "qspi10")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); + +#endif/* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h new file mode 100644 index 0000000000..d7a1db25e9 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal_cfg.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-5 SummerGift first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +extern const struct fal_flash_dev stm32_onchip_flash; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 496 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash", 496* 1024, 16 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c new file mode 100644 index 0000000000..8fdd588372 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-14 balanceTWK add sdcard port file + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include +#include +#include "drv_spi.h" +#include "spi_msd.h" + +#define DBG_ENABLE +#define DBG_SECTION_NAME "app.card" +#define DBG_COLOR + +#define DBG_LEVEL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 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$PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_wwdg.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_adc.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_comp.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crc.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crs.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dac.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma2d.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_fmc.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_i2c.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lptim.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lpuart.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_opamp.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rng.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rtc.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_swpmi.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c + + + diff --git a/bsp/stm32/stm32l475-atk-pandora/project.eww b/bsp/stm32/stm32l475-atk-pandora/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32l475-atk-pandora/project.uvoptx b/bsp/stm32/stm32l475-atk-pandora/project.uvoptx new file mode 100644 index 0000000000..4c989e2d13 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/project.uvoptx @@ -0,0 +1,196 @@ + + + + 1.0 + +

    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF495056867767053013 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + 0 + JL2CM3 + -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32l475-atk-pandora/project.uvprojx b/bsp/stm32/stm32l475-atk-pandora/project.uvprojx new file mode 100644 index 0000000000..0c9187ff6d --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/project.uvprojx @@ -0,0 +1,1373 @@ + + + 2.1 +
    ### uVision Project, (C) Keil Software
    + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32L475VETx + STMicroelectronics + Keil.STM32L4xx_DFP.2.0.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)) + 0 + $$Device:STM32L475VETx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + + + + + + + + + + $$Device:STM32L475VETx$CMSIS\SVD\STM32L4x5.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x10000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER, STM32L475xx + + .;applications;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l475xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l475xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + STM32_HAL + + + system_stm32l4xx.c + 1 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + + + + + stm32l4xx_hal.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + + + stm32l4xx_hal_adc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c + + + + + stm32l4xx_hal_adc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c + + + + + stm32l4xx_hal_can.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c + + + + + stm32l4xx_hal_comp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + + + + stm32l4xx_hal_cortex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + + + + stm32l4xx_hal_crc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + + + + + stm32l4xx_hal_crc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + + + + + stm32l4xx_hal_cryp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + + + + + stm32l4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + + + + + stm32l4xx_hal_dac.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c + + + + + stm32l4xx_hal_dac_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c + + + + + stm32l4xx_hal_dcmi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + + + + + stm32l4xx_hal_dfsdm.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm.c + + + + + stm32l4xx_hal_dfsdm_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm_ex.c + + + + + stm32l4xx_hal_dma.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + + + stm32l4xx_hal_dma2d.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma2d.c + + + + + stm32l4xx_hal_dma_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + + + stm32l4xx_hal_dsi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dsi.c + + + + + stm32l4xx_hal_exti.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + + + + stm32l4xx_hal_firewall.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_firewall.c + + + + + stm32l4xx_hal_flash.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + + + + + stm32l4xx_hal_flash_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + + + + + stm32l4xx_hal_flash_ramfunc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + + + + + stm32l4xx_hal_gfxmmu.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gfxmmu.c + + + + + stm32l4xx_hal_gpio.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + + + stm32l4xx_hal_hash.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hash.c + + + + + stm32l4xx_hal_hash_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hash_ex.c + + + + + stm32l4xx_hal_hcd.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hcd.c + + + + + stm32l4xx_hal_i2c.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + + + + + stm32l4xx_hal_i2c_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + + + + + stm32l4xx_hal_irda.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_irda.c + + + + + stm32l4xx_hal_iwdg.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c + + + + + stm32l4xx_hal_lcd.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lcd.c + + + + + stm32l4xx_hal_lptim.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lptim.c + + + + + stm32l4xx_hal_ltdc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_ltdc.c + + + + + stm32l4xx_hal_ltdc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_ltdc_ex.c + + + + + stm32l4xx_hal_nand.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_nand.c + + + + + stm32l4xx_hal_nor.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_nor.c + + + + + stm32l4xx_hal_opamp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_opamp.c + + + + + stm32l4xx_hal_opamp_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_opamp_ex.c + + + + + stm32l4xx_hal_ospi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_ospi.c + + + + + stm32l4xx_hal_pcd.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c + + + + + stm32l4xx_hal_pcd_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c + + + + + stm32l4xx_hal_pwr.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + + + stm32l4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + + + stm32l4xx_hal_qspi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c + + + + + stm32l4xx_hal_rcc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + + + + stm32l4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + + + stm32l4xx_hal_rng.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + + + + stm32l4xx_hal_rtc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc.c + + + + + stm32l4xx_hal_rtc_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c + + + + + stm32l4xx_hal_sai.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sai.c + + + + + stm32l4xx_hal_sai_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sai_ex.c + + + + + stm32l4xx_hal_sd.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c + + + + + stm32l4xx_hal_sd_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd_ex.c + + + + + stm32l4xx_hal_smartcard.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smartcard.c + + + + + stm32l4xx_hal_smartcard_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smartcard_ex.c + + + + + stm32l4xx_hal_smbus.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smbus.c + + + + + stm32l4xx_hal_spi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + + + + + stm32l4xx_hal_spi_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + + + + + stm32l4xx_hal_sram.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sram.c + + + + + stm32l4xx_hal_swpmi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_swpmi.c + + + + + stm32l4xx_hal_tim.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + + + + + stm32l4xx_hal_tim_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + + + + + stm32l4xx_hal_tsc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tsc.c + + + + + stm32l4xx_hal_uart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + + + + stm32l4xx_hal_uart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + + + + stm32l4xx_hal_usart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c + + + + + stm32l4xx_hal_usart_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + + + + stm32l4xx_hal_wwdg.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_wwdg.c + + + + + stm32l4xx_ll_adc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_adc.c + + + + + stm32l4xx_ll_comp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_comp.c + + + + + stm32l4xx_ll_crc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crc.c + + + + + stm32l4xx_ll_crs.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crs.c + + + + + stm32l4xx_ll_dac.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dac.c + + + + + stm32l4xx_ll_dma.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c + + + + + stm32l4xx_ll_dma2d.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma2d.c + + + + + stm32l4xx_ll_exti.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c + + + + + stm32l4xx_ll_fmc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_fmc.c + + + + + stm32l4xx_ll_gpio.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c + + + + + stm32l4xx_ll_i2c.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_i2c.c + + + + + stm32l4xx_ll_lptim.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lptim.c + + + + + stm32l4xx_ll_lpuart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lpuart.c + + + + + stm32l4xx_ll_opamp.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_opamp.c + + + + + stm32l4xx_ll_pwr.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c + + + + + stm32l4xx_ll_rcc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c + + + + + stm32l4xx_ll_rng.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rng.c + + + + + stm32l4xx_ll_rtc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rtc.c + + + + + stm32l4xx_ll_sdmmc.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c + + + + + stm32l4xx_ll_spi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c + + + + + stm32l4xx_ll_swpmi.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_swpmi.c + + + + + stm32l4xx_ll_tim.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c + + + + + stm32l4xx_ll_usart.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c + + + + + stm32l4xx_ll_usb.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c + + + + + stm32l4xx_ll_utils.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c + + + + + + + + + + + +     diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.h b/bsp/stm32/stm32l475-atk-pandora/rtconfig.h new file mode 100644 index 0000000000..82891ef0a0 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.h @@ -0,0 +1,173 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32L4 + +/* Hardware Drivers Config */ + +#define SOC_STM32L475VE + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_STLINK_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py new file mode 100644 index 0000000000..50c1d8a0f7 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py @@ -0,0 +1,133 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99 -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/stm32/stm32l475-atk-pandora/template.ewp b/bsp/stm32/stm32l475-atk-pandora/template.ewp new file mode 100644 index 0000000000..f390ad7bc1 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32l475-atk-pandora/template.eww b/bsp/stm32/stm32l475-atk-pandora/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32l475-atk-pandora/template.uvoptx b/bsp/stm32/stm32l475-atk-pandora/template.uvoptx new file mode 100644 index 0000000000..4c989e2d13 --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/template.uvoptx @@ -0,0 +1,196 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF495056867767053013 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + 0 + JL2CM3 + -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + +     diff --git a/bsp/stm32/stm32l475-atk-pandora/template.uvprojx b/bsp/stm32/stm32l475-atk-pandora/template.uvprojx new file mode 100644 index 0000000000..10c78ed37e --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/template.uvprojx @@ -0,0 +1,394 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32L475VETx + STMicroelectronics + Keil.STM32L4xx_DFP.2.0.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)) + 0 + $$Device:STM32L475VETx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + + + + + + + + + + $$Device:STM32L475VETx$CMSIS\SVD\STM32L4x5.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x10000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + +     From 87e351538c4092899d0244ef751112a552e16076 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Mon, 17 Dec 2018 10:46:07 +0800 Subject: [PATCH 04/14] [bsp][stm32] add sdcard port file --- .../board/ports/sdcard_port.c | 65 ++++++++++++++++ .../board/ports/sdcard_port.c | 65 ++++++++++++++++ .../board/ports/sdcard_port.c | 65 ++++++++++++++++ .../board/ports/sdcard_port.c | 76 +++++++++++++++++++ 4 files changed, 271 insertions(+) create mode 100644 bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c create mode 100644 bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c create mode 100644 bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c create mode 100644 bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c new file mode 100644 index 0000000000..617379fd4e --- /dev/null +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include +#include + +#define DBG_ENABLE +#define DBG_SECTION_NAME "app.card" +#define DBG_COLOR + +#define DBG_LEVEL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif + diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c new file mode 100644 index 0000000000..617379fd4e --- /dev/null +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include +#include + +#define DBG_ENABLE +#define DBG_SECTION_NAME "app.card" +#define DBG_COLOR + +#define DBG_LEVEL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif + diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c new file mode 100644 index 0000000000..617379fd4e --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include +#include + +#define DBG_ENABLE +#define DBG_SECTION_NAME "app.card" +#define DBG_COLOR + +#define DBG_LEVEL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif + diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c new file mode 100644 index 0000000000..e29a0b8557 --- /dev/null +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include +#include +#include "drv_gpio.h" + +#define DBG_ENABLE +#define DBG_SECTION_NAME "app.card" +#define DBG_COLOR + +#define DBG_LEVEL DBG_INFO +#include + +#define WIFI_RESET_PIN GET_PIN(G, 9) + +int ewm1062_disable(void) +{ + rt_pin_mode(WIFI_RESET_PIN, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_RESET_PIN,PIN_LOW); + return RT_EOK; +} +INIT_BOARD_EXPORT(ewm1062_disable); + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif + From 355783c5faf4a1b594a07b51bff2f605af2c015d Mon Sep 17 00:00:00 2001 From: SummerGift Date: Mon, 17 Dec 2018 11:49:57 +0800 Subject: [PATCH 05/14] [bsp][stm32] modify doc for atk-pandora --- bsp/stm32/README.md | 1 + bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 5 ----- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index a973b8732d..1ffe207b1a 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -9,6 +9,7 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32f407-atk-explorer](stm32f407-atk-explorer/) | 正点原子 F407 探索者开发板 | | [stm32f429-atk-apollo](stm32f429-atk-apollo/) | 正点原子 F429 阿波罗开发板 | | [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 | +| [stm32l475-atk-pandora](stm32l475-atk-pandora/) | 正点原子 L475 潘多拉 IoT 开发板 | 了解每个 BSP 的详细情况可以阅读该 BSP 下的 readme 文件，如需使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档： diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index 61f2c7db74..a389b5beca 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -47,11 +47,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_USING_UART3 - bool "Enable UART3" - select RT_USING_SERIAL - default n - config BSP_UART_USING_DMA_RX bool "Enable UART RX DMA support" default n From 9cd881bf056c63ab10739f2eb7bef5b9e22254fa Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 18 Dec 2018 10:37:57 +0800 Subject: [PATCH 06/14] [bsp][stm32] fix some error --- bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c | 4 ++-- bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c index 617379fd4e..16c7a9e454 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c @@ -10,7 +10,7 @@ #include -#ifdef RT_USING_DFS +#ifdef BSP_USING_SDCARD #include #include @@ -61,5 +61,5 @@ int stm32_sdcard_mount(void) } INIT_APP_EXPORT(stm32_sdcard_mount); -#endif +#endif /* BSP_USING_SDCARD */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf index 11d1d86df5..b89cc8fa4d 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32l475-atk-pandora/board/linker_scripts/link.icf @@ -30,4 +30,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM1_region { section .sram }; -place in RAM2_region { readwrite, block CSTACK}; +place in RAM2_region { readwrite, last block CSTACK}; From cf7292d4e4ebe5be08b6ffad5ebc3d023b568498 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 18 Dec 2018 14:07:38 +0800 Subject: [PATCH 07/14] [bsp][stm32] SD card micro BSP_USING_SDCARD --- bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c | 4 ++-- bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c | 4 ++-- bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c | 4 ++-- bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c index 617379fd4e..3026357b5c 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c @@ -10,7 +10,7 @@ #include -#ifdef RT_USING_DFS +#ifdef BSP_USING_SDCARD #include #include @@ -61,5 +61,5 @@ int stm32_sdcard_mount(void) } INIT_APP_EXPORT(stm32_sdcard_mount); -#endif +#endif /* BSP_USING_SDCARD */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c index 617379fd4e..3026357b5c 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c @@ -10,7 +10,7 @@ #include -#ifdef RT_USING_DFS +#ifdef BSP_USING_SDCARD #include #include @@ -61,5 +61,5 @@ int stm32_sdcard_mount(void) } INIT_APP_EXPORT(stm32_sdcard_mount); -#endif +#endif /* BSP_USING_SDCARD */ diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c index e29a0b8557..0a84162150 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c @@ -10,7 +10,7 @@ #include -#ifdef RT_USING_DFS +#ifdef BSP_USING_SDCARD #include #include @@ -72,5 +72,5 @@ int stm32_sdcard_mount(void) } INIT_APP_EXPORT(stm32_sdcard_mount); -#endif +#endif /* BSP_USING_SDCARD */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c index 8fdd588372..9d40589756 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c @@ -10,7 +10,7 @@ #include -#ifdef RT_USING_DFS +#ifdef BSP_USING_SDCARD #include #include @@ -71,5 +71,5 @@ static int rt_hw_spi1_tfcard(void) } INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard); -#endif +#endif /* BSP_USING_SDCARD */ From d830b6cbf8ccb11ad246661c68d145e6bf4d0b71 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:00:33 +0800 Subject: [PATCH 08/14] [bsp][stm32] modify drv_config.h --- bsp/stm32/libraries/HAL_Drivers/drv_config.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h index f6bcdedb2c..5667b6d05d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h @@ -18,10 +18,16 @@ #include "f1/uart_config.h" #include "f1/spi_config.h" #include "f1/adc_config.h" +#include "f1/tim_config.h" +#include "f1/sdio_config.h" +#include "f1/pwm_config.h" #elif defined(SOC_SERIES_STM32F4) #include "f4/uart_config.h" #include "f4/spi_config.h" #include "f4/adc_config.h" +#include "f4/tim_config.h" +#include "f4/sdio_config.h" +#include "f4/pwm_config.h" #elif defined(SOC_SERIES_STM32F7) #include "f7/uart_config.h" #include "f7/spi_config.h" @@ -30,6 +36,8 @@ #include "l4/uart_config.h" #include "l4/spi_config.h" #include "l4/adc_config.h" +#include "l4/tim_config.h" +#include "l4/pwm_config.h" #endif #endif From 63dbe799120efbed2db25cf3d169086ff389b613 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:50:07 +0800 Subject: [PATCH 09/14] [bsp][stm32] Sync SConscript --- bsp/stm32/libraries/STM32F1xx_HAL/SConscript | 113 ++++++++------- bsp/stm32/libraries/STM32F4xx_HAL/SConscript | 124 +++++++++------- bsp/stm32/libraries/STM32L4xx_HAL/SConscript | 143 ++++++++----------- 3 files changed, 196 insertions(+), 184 deletions(-) diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript index 4ee2fabd48..37101b6c74 100644 --- a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript @@ -8,69 +8,80 @@ cwd = GetCurrentDir() # The set of source files associated with this SConscript file. src = Split(""" CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_irda.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rtc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cec.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac_ex.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c """) -#device options + +if GetDepend(['RT_USING_PIN']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c'] + +if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c'] + +if GetDepend(['RT_USING_MTD_NOR']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c'] + +if GetDepend(['RT_USING_MTD_NAND']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c'] path = [cwd + '/CMSIS/Device/ST/STM32F1xx/Include', - cwd + '/STM32F1xx_HAL_Driver/Inc', + cwd + '/STM32F1xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] if GetDepend(['RT_USING_RTT_CMSIS']): diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript index 9b16e71735..375bf546f8 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript @@ -9,74 +9,92 @@ cwd = GetCurrentDir() src = Split(''' CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c -STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c ''') +if GetDepend(['RT_USING_PIN']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c'] + +if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c'] + +if GetDepend(['RT_USING_MTD_NOR']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c'] + +if GetDepend(['RT_USING_MTD_NAND']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c'] + +if GetDepend(['BSP_USING_SDRAM']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c'] + src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c'] + path = [cwd + '/STM32F4xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32F4xx/Include', cwd + '/CMSIS/Include'] diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript index f8baad95d4..5d6f0d9032 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript @@ -9,103 +9,86 @@ cwd = GetCurrentDir() src = Split(''' CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c ''') +if GetDepend(['RT_USING_PIN']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c'] + +if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c'] + +if GetDepend(['RT_USING_MTD_NOR']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c'] + +if GetDepend(['RT_USING_MTD_NAND']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c'] + path = [cwd + '/STM32L4xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32L4xx/Include', cwd + '/CMSIS/Include'] From d5c7d8d41fe3a1d7b82bb16b42096660036bf451 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:52:32 +0800 Subject: [PATCH 10/14] [bsp][stm32] Sync kconfig --- bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig | 4 ---- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 4 ---- bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig | 4 ---- bsp/stm32/stm32f407-atk-explorer/board/Kconfig | 4 ---- bsp/stm32/stm32f429-atk-apollo/board/Kconfig | 4 ---- bsp/stm32/stm32f429-fire-challenger/board/Kconfig | 4 ---- bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 4 ---- 7 files changed, 28 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig index a15665c848..02454235c7 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index 2b6d6b3fc1..20cbf0ccc6 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -54,10 +54,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - menuconfig BSP_USING_TIM bool "Enable timer" default n diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig index ae55be5fab..4227ae9bf5 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig @@ -103,10 +103,6 @@ menu "On-chip Peripheral Drivers" bool "Enable UART3" select RT_USING_SERIAL default n - - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index 319cb49c92..0f22133a55 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -118,10 +118,6 @@ menu "On-chip Peripheral Drivers" bool "Enable on-chip FLASH" default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index 9d85754053..c88b1efec9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -82,10 +82,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default y - config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig index 0323f139ce..e1c6928049 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig @@ -92,10 +92,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default n - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" default n diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index a389b5beca..cf4bf952f4 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -46,10 +46,6 @@ menu "On-chip Peripheral Drivers" bool "Enable UART2" select RT_USING_SERIAL default n - - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n config BSP_USING_ON_CHIP_FLASH bool "Enable on-chip FLASH" From 938bbb030d5c94e845257e46e020d6bbab8b4fea Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 14:53:46 +0800 Subject: [PATCH 11/14] [bsp][stm32] optimize main func --- .../libraries/templates/stm32f10x/applications/main.c | 11 ++++++++++- bsp/stm32/libraries/templates/stm32f10x/board/board.c | 9 --------- bsp/stm32/libraries/templates/stm32f10x/board/board.h | 6 ------ .../libraries/templates/stm32f4xx/applications/main.c | 11 ++++++++++- bsp/stm32/libraries/templates/stm32f4xx/board/board.c | 9 --------- bsp/stm32/libraries/templates/stm32f4xx/board/board.h | 6 ------ .../libraries/templates/stm32l4xx/applications/main.c | 11 ++++++++++- bsp/stm32/libraries/templates/stm32l4xx/board/board.c | 9 --------- bsp/stm32/libraries/templates/stm32l4xx/board/board.h | 6 ------ bsp/stm32/stm32f103-atk-nano/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f103-atk-nano/board/board.c | 9 +-------- bsp/stm32/stm32f103-atk-nano/board/board.h | 7 ------- .../stm32f103-fire-arbitrary/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f103-fire-arbitrary/board/board.c | 11 ----------- bsp/stm32/stm32f103-fire-arbitrary/board/board.h | 7 ------- bsp/stm32/stm32f407-atk-explorer/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f407-atk-explorer/board/board.c | 11 ----------- bsp/stm32/stm32f407-atk-explorer/board/board.h | 7 ------- bsp/stm32/stm32f429-atk-apollo/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f429-atk-apollo/board/board.c | 11 ----------- bsp/stm32/stm32f429-atk-apollo/board/board.h | 9 --------- .../stm32f429-fire-challenger/applications/main.c | 11 ++++++++++- bsp/stm32/stm32f429-fire-challenger/board/board.c | 11 ----------- bsp/stm32/stm32f429-fire-challenger/board/board.h | 8 -------- bsp/stm32/stm32l475-atk-pandora/applications/main.c | 11 ++++++++++- bsp/stm32/stm32l475-atk-pandora/board/board.c | 9 --------- bsp/stm32/stm32l475-atk-pandora/board/board.h | 8 -------- 27 files changed, 91 insertions(+), 161 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32f10x/applications/main.c b/bsp/stm32/libraries/templates/stm32f10x/applications/main.c index 87a07a6246..7c40c1518d 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f10x/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.c b/bsp/stm32/libraries/templates/stm32f10x/board/board.c index ac55193461..36c127c5b7 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.c @@ -51,12 +51,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -// int board_pin_init(void) -// { -// rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); -// return 0; -// } -// INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.h b/bsp/stm32/libraries/templates/stm32f10x/board/board.h index cc2079f0e7..1c00e71dca 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.h @@ -15,12 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -// #define LED0_PIN GET_PIN(C, 0) -#endif - /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ #define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c b/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c index 87a07a6246..7c40c1518d 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/board.c b/bsp/stm32/libraries/templates/stm32f4xx/board/board.c index 928bbdbbde..b3cf3b0754 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/board.c @@ -56,12 +56,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -// int board_pin_init(void) -// { -// rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); -// return 0; -// } -// INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/board.h b/bsp/stm32/libraries/templates/stm32f4xx/board/board.h index 8cb36267f7..f7944b4ed7 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/board.h @@ -15,12 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -// #define LED0_PIN GET_PIN(C, 0) -#endif - #define STM32_SRAM_SIZE 128 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c b/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c index 87a07a6246..7c40c1518d 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.c b/bsp/stm32/libraries/templates/stm32l4xx/board/board.c index d0e25eaf04..5f8113f4d7 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.c +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.c @@ -66,12 +66,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -// int board_pin_init(void) -// { -// rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); -// return 0; -// } -// INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h index 2b3e8b6cb1..29e1ba4267 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h @@ -15,12 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -// #define LED0_PIN GET_PIN(C, 0) -#endif - #define STM32_SRAM_SIZE 96 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c index 61f0263ca2..e5b96d8280 100644 --- a/bsp/stm32/stm32f103-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PC0 */ +#define LED0_PIN GET_PIN(C, 0) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c index 28bb36889c..981fffc85e 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.c +++ b/bsp/stm32/stm32f103-atk-nano/board/board.c @@ -62,11 +62,4 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); } -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ + diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h index 410414c202..a22d23632a 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.h +++ b/bsp/stm32/stm32f103-atk-nano/board/board.h @@ -15,13 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(C, 0) -#define LED1_PIN GET_PIN(C, 1) -#endif - #define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) #define STM32_FLASH_SIZE (128 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c index 2042a40378..4024c1ae3f 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PF7 */ +#define LED0_PIN GET_PIN(F, 7) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c index 3188bdb616..829addae08 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c @@ -63,14 +63,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h index fc77f71a95..d0718d5525 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h @@ -15,13 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(F, 7) -#define LED1_PIN GET_PIN(F, 8) -#endif - /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c index 5d7f42bdab..b7bd6a1249 100644 --- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c @@ -12,14 +12,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PF9 */ +#define LED0_PIN GET_PIN(F, 9) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED1_PIN, !rt_pin_read(LED1_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c index 52145fe832..cea8c7fff9 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c @@ -67,14 +67,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h index 4dab0eddd3..77928f7f80 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h @@ -15,13 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(F, 9) -#define LED1_PIN GET_PIN(F, 10) -#endif - #define STM32_SRAM_SIZE (128) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c index 768cedfae7..7c40c1518d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PB1 */ +#define LED0_PIN GET_PIN(B, 1) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED1_PIN, !rt_pin_read(LED1_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c index 91cde7a95d..a0d2cd17a5 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c @@ -77,14 +77,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.h b/bsp/stm32/stm32f429-atk-apollo/board/board.h index 5d59b9bd77..8be558340c 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.h @@ -15,10 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -#endif - #define STM32_SRAM_SIZE (192) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) @@ -39,12 +35,7 @@ extern int __bss_end; #define HEAP_END STM32_SRAM_END -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(B, 1) -#define LED1_PIN GET_PIN(B, 0) - void SystemClock_Config(void); void MX_GPIO_Init(void); #endif - diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c index 582e5ed887..cee539b083 100644 --- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c @@ -12,14 +12,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PH10 */ +#define LED0_PIN GET_PIN(H, 10) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED1_PIN, !rt_pin_read(LED1_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c index 77961c793c..19559f4059 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c @@ -76,14 +76,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOG_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.h b/bsp/stm32/stm32f429-fire-challenger/board/board.h index 4348bb5fb7..69a99bf672 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.h @@ -15,10 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -#endif - #define STM32_SRAM_SIZE (192) #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) @@ -39,10 +35,6 @@ extern int __bss_end; #define HEAP_END STM32_SRAM_END -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(H, 10) -#define LED1_PIN GET_PIN(H, 11) - void SystemClock_Config(void); void MX_GPIO_Init(void); diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c index a802fd07e8..208dd4525f 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c @@ -11,14 +11,23 @@ #include #include #include +#include "drv_gpio.h" +/* defined the LED0 pin: PE7 */ +#define LED0_PIN GET_PIN(E, 7) int main(void) { int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { - rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN)); + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } + return RT_EOK; } diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c index 4c6d7f61ea..78eb82025c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -74,12 +74,3 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); } - -#ifdef RT_USING_PIN -int board_pin_init(void) -{ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - return 0; -} -INIT_BOARD_EXPORT(board_pin_init); -#endif /* RT_USING_PIN */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h index 43ea79b4e4..df4023b4bb 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h @@ -15,10 +15,6 @@ #include #include "drv_common.h" -#ifdef BSP_USING_GPIO -#include "drv_gpio.h" -#endif - #define STM32_SRAM1_SIZE (96) #define STM32_SRAM1_START (0x20000000) #define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024) @@ -30,10 +26,6 @@ #define HEAP_BEGIN STM32_SRAM1_START #define HEAP_END STM32_SRAM1_END -/* Board Pin definitions */ -#define LED0_PIN GET_PIN(E, 7) -#define LED1_PIN GET_PIN(E, 8) - void SystemClock_Config(void); void MX_GPIO_Init(void); From 08bc2b3f5d2a6cd3d46b5d4770bfacdc0ed9ba0a Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 15:04:19 +0800 Subject: [PATCH 12/14] [bsp][stm32] fix flash bug --- .../HAL_Drivers/drv_flash/drv_flash_f4.c | 16 +++++++++++++--- .../HAL_Drivers/drv_flash/drv_flash_l4.c | 2 +- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c index 8cbfc040b6..fd704f7362 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c @@ -91,22 +91,30 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_7; } +#if defined(FLASH_SECTOR_8) else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) { sector = FLASH_SECTOR_8; } +#endif +#if defined(FLASH_SECTOR_9) else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9)) { sector = FLASH_SECTOR_9; } +#endif +#if defined(FLASH_SECTOR_10) else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10)) { sector = FLASH_SECTOR_10; } +#endif +#if defined(FLASH_SECTOR_11) else if((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11)) { sector = FLASH_SECTOR_11; } +#endif #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) else if((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12)) { @@ -219,7 +227,7 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size) HAL_FLASH_Unlock(); - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); for (size_t i = 0; i < size; i++, addr++, buf++) { @@ -278,17 +286,19 @@ int stm32_flash_erase(long offset, size_t size) /* Unlock the Flash to enable the flash control register access */ HAL_FLASH_Unlock(); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + /* Get the 1st sector to erase */ FirstSector = GetSector(addr); /* Get the number of sector to erase from 1st sector*/ - NbOfSectors = GetSector(addr + size) - FirstSector + 1; + NbOfSectors = GetSector(addr + size - 1) - FirstSector + 1; /* Fill EraseInit structure*/ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; EraseInitStruct.Sector = FirstSector; EraseInitStruct.NbSectors = NbOfSectors; - if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK) + if (HAL_FLASHEx_Erase(&EraseInitStruct, (uint32_t *)&SECTORError) != HAL_OK) { result = -RT_ERROR; goto __exit; diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c index caafce2466..37fce587a9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c @@ -244,7 +244,7 @@ int stm32_flash_erase(long offset, size_t size) /* Get the 1st page to erase */ FirstPage = GetPage(addr); /* Get the number of pages to erase from 1st page */ - NbOfPages = GetPage(addr + size) - FirstPage + 1; + NbOfPages = GetPage(addr + size - 1) - FirstPage + 1; /* Get the bank */ BankNumber = GetBank(addr); /* Fill EraseInit structure*/ From 8f9c72b05e6320a591c4b620800b9b293151edc5 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 15:56:18 +0800 Subject: [PATCH 13/14] =?UTF-8?q?=E3=80=90=E6=9B=B4=E6=96=B0=E3=80=91?= =?UTF-8?q?=EF=BC=9Amenuconfig=20=E9=85=8D=E7=BD=AE=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/libraries/templates/stm32f10x/.config | 5 ++++- bsp/stm32/libraries/templates/stm32f10x/rtconfig.h | 1 + bsp/stm32/libraries/templates/stm32f4xx/.config | 5 ++++- bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h | 1 + bsp/stm32/libraries/templates/stm32f7xx/.config | 12 ++++++++---- bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h | 11 +++++++++-- bsp/stm32/libraries/templates/stm32l4xx/.config | 5 ++++- bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h | 1 + 8 files changed, 32 insertions(+), 9 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32f10x/.config b/bsp/stm32/libraries/templates/stm32f10x/.config index 4a931cf1e2..b74dd34859 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/.config +++ b/bsp/stm32/libraries/templates/stm32f10x/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y @@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -278,6 +281,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -340,7 +344,6 @@ CONFIG_SOC_STM32F103RB=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h index ed7bf5a5f7..908c0d760d 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 diff --git a/bsp/stm32/libraries/templates/stm32f4xx/.config b/bsp/stm32/libraries/templates/stm32f4xx/.config index 935757f65a..ed06540dab 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/.config +++ b/bsp/stm32/libraries/templates/stm32f4xx/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -279,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -341,7 +345,6 @@ CONFIG_SOC_STM32F407ZG=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h index 21d3064ad0..b8700de08d 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 diff --git a/bsp/stm32/libraries/templates/stm32f7xx/.config b/bsp/stm32/libraries/templates/stm32f7xx/.config index 1491b26f9a..5b2fbd74ae 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/.config +++ b/bsp/stm32/libraries/templates/stm32f7xx/.config @@ -62,9 +62,10 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M4=y +CONFIG_ARCH_ARM_CORTEX_M7=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -110,6 +111,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -179,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -278,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -324,12 +329,12 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_HELLO is not set CONFIG_SOC_FAMILY_STM32=y -CONFIG_SOC_SERIES_STM32F4=y +CONFIG_SOC_SERIES_STM32F7=y # # Hardware Drivers Config # -CONFIG_SOC_STM32F407ZG=y +CONFIG_SOC_STM32F767IG=y # # Onboard Peripheral Drivers @@ -340,7 +345,6 @@ CONFIG_SOC_STM32F407ZG=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h index 01f98d0c58..f1dff62d4b 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h @@ -39,6 +39,9 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 /* RT-Thread Components */ @@ -74,6 +77,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */ @@ -105,6 +109,9 @@ /* Utilities */ +/* ARM CMSIS */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -149,6 +156,8 @@ /* example package: hello */ +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F7 /* Hardware Drivers Config */ @@ -156,8 +165,6 @@ /* Onboard Peripheral Drivers */ -#define BSP_USING_USB_TO_USART - /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO diff --git a/bsp/stm32/libraries/templates/stm32l4xx/.config b/bsp/stm32/libraries/templates/stm32l4xx/.config index 233ed0577f..2ace5a3beb 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/.config +++ b/bsp/stm32/libraries/templates/stm32l4xx/.config @@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40000 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y @@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS # # CONFIG_RT_USING_CMSIS_OS is not set # CONFIG_RT_USING_RTT_CMSIS is not set +# CONFIG_RT_USING_LWP is not set # # RT-Thread online packages @@ -279,6 +282,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -341,7 +345,6 @@ CONFIG_SOC_STM32L475VE=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART_USING_DMA_RX is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_SPI_USING_DMA is not set # CONFIG_BSP_USING_I2C1 is not set diff --git a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h index 1b16eff99f..512a1832ce 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h @@ -38,6 +38,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40000 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 From 96fcf5dc291e9ce459d92e4aabb3bd9bfa48eb2c Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 20 Dec 2018 16:08:57 +0800 Subject: [PATCH 14/14] [bsp][stm32] update templates Kconfig --- bsp/stm32/libraries/templates/stm32f10x/board/Kconfig | 4 ---- bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig | 4 ---- bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig | 4 ---- 3 files changed, 12 deletions(-) diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig b/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig index 20427606ef..39a000d371 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f10x/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig index 7889393544..5ba6059541 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig index 2f87aceeb5..5d0299fe3b 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig @@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL default y - config BSP_UART_USING_DMA_RX - bool "Enable UART RX DMA support" - default n - config BSP_USING_SPI1 bool "Enable SPI1 BUS" select RT_USING_SPI