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Nuvoton release/update. 

(1) Support NK-N9H30 board.
(2) Change Mutex's flag to RT_IPC_FLAG_PRIO from RT_IPC_FLAG_FIFO.
This commit is contained in:
Wayne Lin 2021-05-12 18:49:31 +08:00
parent f068908728
commit d3131ee55f
46 changed files with 3407 additions and 160 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
bsp/nuvoton/README.md
View File

@ -1,10 +1,11 @@
ï»? Nuvoton BSP descriptions
Nuvoton BSP descriptions
Current supported BSP shown in below table:
| **BSP folder** | **Board name** |
| **BSP Folder** | **Board Name** |
|:------------------------- |:-------------------------- |
| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 |
| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
| [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c
View File

@ -94,7 +94,7 @@ rt_err_t nu_crc_init(void)
{
SYS_ResetModule(CRC_RST);
rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
return RT_EOK;
}

6
bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c
View File

@ -82,11 +82,11 @@ static rt_err_t nu_crypto_init(void)
SHA_ENABLE_INT(CRPT);
//init cipher mutex
rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
#if !defined(BSP_USING_TRNG)
PRNG_ENABLE_INT(CRPT);
rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
#endif
return RT_EOK;

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.c
View File

@ -314,7 +314,7 @@ static int nu_fmc_init(void)
FMC_ENABLE_ISP();
SYS_LockReg();
g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_PRIO);
/* PKG_USING_FAL */
#if defined(PKG_USING_FAL)

6
bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c
View File

@ -210,7 +210,7 @@ static void nu_pdma_init(void)
if (nu_pdma_inited)
return;
g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO);
g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_PRIO);
RT_ASSERT(g_mutex_sg != RT_NULL);
nu_pdma_chn_mask = ~(NU_PDMA_CH_Msk);
@ -534,7 +534,7 @@ rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u3
goto exit_nu_pdma_desc_setup;
else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8)))
goto exit_nu_pdma_desc_setup;
else if ( i32TransferCnt > NU_PDMA_MAX_TXCNT )
else if (i32TransferCnt > NU_PDMA_MAX_TXCNT)
goto exit_nu_pdma_desc_setup;
PDMA = NU_PDMA_GET_BASE(i32ChannID);
@ -890,7 +890,7 @@ static void nu_pdma_memfun_actor_init(void)
nu_pdma_memfun_actor_maxnum = i;
nu_pdma_memfun_actor_mask = ~(((1 << i) - 1));
nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO);
}
}

11
bsp/nuvoton/libraries/m2354/rtt_port/drv_qspi.c
View File

@ -161,10 +161,10 @@ exit_nu_qspi_bus_configure:
return -(ret);
}
#if defined(RT_SFUD_USING_QSPI)
static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
{
QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
#if defined(RT_SFUD_USING_QSPI)
if (qspi_lines > 1)
{
if (tx)
@ -199,13 +199,13 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8
}
}
else
#endif
{
QSPI_DISABLE_DUAL_MODE(qspi_base);
QSPI_DISABLE_QUAD_MODE(qspi_base);
}
return qspi_lines;
}
#endif
static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
@ -298,9 +298,11 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
qspi_message->dummy_cycles / (8 / u8last),
1);
}
/* Data stage */
nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
#else
/* Data stage */
nu_qspi_mode_config(qspi_bus, RT_NULL, RT_NULL, 1);
#endif //#if defined(RT_SFUD_USING_QSPI)
if (message->length != 0)
@ -350,8 +352,7 @@ static int rt_hw_qspi_init(void)
#if defined(BSP_USING_SPI_PDMA)
nu_qspi_arr[i].pdma_chanid_tx = -1;
nu_qspi_arr[i].pdma_chanid_rx = -1;
#endif
#if defined(BSP_USING_QSPI_PDMA)
if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
{
if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c
View File

@ -222,7 +222,7 @@ static int rt_hw_slcd_init(void)
{
ret = rt_hw_slcd_register(&nu_slcd_arr[i].dev, nu_slcd_arr[i].name, RT_DEVICE_FLAG_RDWR, NULL);
RT_ASSERT(ret == RT_EOK);
nu_slcd_arr[i].lock = rt_mutex_create(nu_slcd_arr[i].name, RT_IPC_FLAG_FIFO);
nu_slcd_arr[i].lock = rt_mutex_create(nu_slcd_arr[i].name, RT_IPC_FLAG_PRIO);
RT_ASSERT(nu_slcd_arr[i].lock != RT_NULL);
}

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c
View File

@ -50,7 +50,7 @@ rt_err_t nu_trng_init(void)
{
rt_err_t result;
result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
s_i32TRNGEnable = 1;

11
bsp/nuvoton/libraries/m480/StdDriver/src/nu_emac.c
View File

@ -209,7 +209,7 @@ void EMAC_PhyInit(void)
while (!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
{
if (i++ > 80000UL) /* Cable not connected */
if (i++ > 10000UL) /* Cable not connected */
{
EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
@ -217,7 +217,7 @@ void EMAC_PhyInit(void)
}
}
if (i <= 80000UL)
if (i <= 10000UL)
{
/* Configure auto negotiation capability */
EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |
@ -747,7 +747,8 @@ uint32_t EMAC_SendPktDone(void)
desc->u32Next = desc->u32Backup2;
/* go to next descriptor in link */
desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
} while (last_tx_desc != (uint32_t)desc); /* If we reach last sent Tx descriptor, leave the loop */
}
while (last_tx_desc != (uint32_t)desc); /* If we reach last sent Tx descriptor, leave the loop */
/* Save last processed Tx descriptor */
u32CurrentTxDesc = (uint32_t)desc;
@ -1115,7 +1116,7 @@ uint8_t *EMAC_ClaimFreeTXBuf(void)
* @return An data length of avaiable RX buffer.
* @note This API should be called before EMAC_RecvPktDone_WoTrigger calling. Caller will do data-copy.
*/
uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf)
uint32_t EMAC_GetAvailRXBufSize(uint8_t **ppuDataBuf)
{
EMAC_DESCRIPTOR_T *desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
@ -1126,7 +1127,7 @@ uint32_t EMAC_GetAvailRXBufSize(uint8_t** ppuDataBuf)
/* It is good and no CRC error. */
if ((status & EMAC_RXFD_RXGD) && !(status & EMAC_RXFD_CRCE))
{
*ppuDataBuf = (uint8_t*)desc->u32Backup1;
*ppuDataBuf = (uint8_t *)desc->u32Backup1;
return desc->u32Status1 & 0xFFFFUL;
}
else

156
bsp/nuvoton/libraries/m480/StdDriver/src/nu_qspi.c
View File

@ -46,9 +46,9 @@ uint32_t QSPI_Open(QSPI_T *qspi,
uint32_t u32DataWidth,
uint32_t u32BusClock)
{
uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U;
uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue = 0U;
if(u32DataWidth == 32U)
if (u32DataWidth == 32U)
{
u32DataWidth = 0U;
}
@ -56,7 +56,7 @@ uint32_t QSPI_Open(QSPI_T *qspi,
/* Get system clock frequency */
u32HCLKFreq = CLK_GetHCLKFreq();
if(u32MasterSlave == QSPI_MASTER)
if (u32MasterSlave == QSPI_MASTER)
{
/* Default setting: slave selection signal is active low; disable automatic slave selection function. */
qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
@ -64,7 +64,7 @@ uint32_t QSPI_Open(QSPI_T *qspi,
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
if(u32BusClock >= u32HCLKFreq)
if (u32BusClock >= u32HCLKFreq)
{
/* Select PCLK as the clock source of QSPI */
if (qspi == QSPI0)
@ -76,15 +76,15 @@ uint32_t QSPI_Open(QSPI_T *qspi,
/* Check clock source of QSPI */
if (qspi == QSPI0)
{
if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
{
/* Clock source is PCLK0 */
u32ClkSrc = CLK_GetPCLK0Freq();
@ -96,15 +96,15 @@ uint32_t QSPI_Open(QSPI_T *qspi,
}
else if (qspi == QSPI1)
{
if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
{
/* Clock source is PCLK1 */
u32ClkSrc = CLK_GetPCLK1Freq();
@ -115,21 +115,21 @@ uint32_t QSPI_Open(QSPI_T *qspi,
}
}
if(u32BusClock >= u32HCLKFreq)
if (u32BusClock >= u32HCLKFreq)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0U;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if(u32BusClock >= u32ClkSrc)
else if (u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0U;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if(u32BusClock == 0U)
else if (u32BusClock == 0U)
{
/* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@ -139,7 +139,7 @@ uint32_t QSPI_Open(QSPI_T *qspi,
else
{
u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
if(u32Div > 0xFFU)
if (u32Div > 0xFFU)
{
u32Div = 0xFFU;
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@ -272,7 +272,7 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
/* Get system clock frequency */
u32HCLKFreq = CLK_GetHCLKFreq();
if(u32BusClock >= u32HCLKFreq)
if (u32BusClock >= u32HCLKFreq)
{
/* Select PCLK as the clock source of QSPI */
if (qspi == QSPI0)
@ -284,15 +284,15 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
/* Check clock source of QSPI */
if (qspi == QSPI0)
{
if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
{
/* Clock source is PCLK0 */
u32ClkSrc = CLK_GetPCLK0Freq();
@ -304,15 +304,15 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
}
else if (qspi == QSPI1)
{
if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
{
/* Clock source is PCLK1 */
u32ClkSrc = CLK_GetPCLK1Freq();
@ -323,21 +323,21 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
}
}
if(u32BusClock >= u32HCLKFreq)
if (u32BusClock >= u32HCLKFreq)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0U;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if(u32BusClock >= u32ClkSrc)
else if (u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0U;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if(u32BusClock == 0U)
else if (u32BusClock == 0U)
{
/* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@ -347,7 +347,7 @@ uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
else
{
u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
if(u32Div > 0x1FFU)
if (u32Div > 0x1FFU)
{
u32Div = 0x1FFU;
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
@ -389,7 +389,7 @@ void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold
uint32_t QSPI_GetBusClock(QSPI_T *qspi)
{
uint32_t u32Div;
uint32_t u32ClkSrc;
uint32_t u32ClkSrc = 0;
/* Get DIVIDER setting */
u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
@ -397,15 +397,15 @@ uint32_t QSPI_GetBusClock(QSPI_T *qspi)
/* Check clock source of QSPI */
if (qspi == QSPI0)
{
if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
{
/* Clock source is PCLK0 */
u32ClkSrc = CLK_GetPCLK0Freq();
@ -417,15 +417,15 @@ uint32_t QSPI_GetBusClock(QSPI_T *qspi)
}
else if (qspi == QSPI1)
{
if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
else if ((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1)
{
/* Clock source is PCLK1 */
u32ClkSrc = CLK_GetPCLK1Freq();
@ -463,61 +463,61 @@ uint32_t QSPI_GetBusClock(QSPI_T *qspi)
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
{
/* Enable unit transfer interrupt flag */
if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
{
qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
}
/* Enable slave selection signal active interrupt flag */
if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
}
/* Enable slave selection signal inactive interrupt flag */
if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
}
/* Enable slave TX under run interrupt flag */
if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
}
/* Enable slave bit count error interrupt flag */
if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
}
/* Enable slave TX underflow interrupt flag */
if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
}
/* Enable TX threshold interrupt flag */
if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
}
/* Enable RX threshold interrupt flag */
if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
}
/* Enable RX overrun interrupt flag */
if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
}
/* Enable RX time-out interrupt flag */
if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
}
@ -546,61 +546,61 @@ void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
{
/* Disable unit transfer interrupt flag */
if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
{
qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
}
/* Disable slave selection signal active interrupt flag */
if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
}
/* Disable slave selection signal inactive interrupt flag */
if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
}
/* Disable slave TX under run interrupt flag */
if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
}
/* Disable slave bit count error interrupt flag */
if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
}
/* Disable slave TX underflow interrupt flag */
if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
}
/* Disable TX threshold interrupt flag */
if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
}
/* Disable RX threshold interrupt flag */
if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
}
/* Disable RX overrun interrupt flag */
if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
}
/* Disable RX time-out interrupt flag */
if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
}
@ -632,70 +632,70 @@ uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk;
/* Check unit transfer interrupt flag */
if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_UNIT_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk;
/* Check slave selection signal active interrupt flag */
if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SSACT_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk;
/* Check slave selection signal inactive interrupt flag */
if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SSINACT_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk;
/* Check slave TX under run interrupt flag */
if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SLVUR_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk;
/* Check slave bit count error interrupt flag */
if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SLVBE_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk;
/* Check slave TX underflow interrupt flag */
if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_TXUF_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk;
/* Check TX threshold interrupt flag */
if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk;
/* Check RX threshold interrupt flag */
if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk;
/* Check RX overrun interrupt flag */
if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk;
/* Check RX time-out interrupt flag */
if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
}
@ -723,42 +723,42 @@ uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
*/
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
{
if(u32Mask & QSPI_UNIT_INT_MASK)
if (u32Mask & QSPI_UNIT_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
}
if(u32Mask & QSPI_SSACT_INT_MASK)
if (u32Mask & QSPI_SSACT_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
}
if(u32Mask & QSPI_SSINACT_INT_MASK)
if (u32Mask & QSPI_SSINACT_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
}
if(u32Mask & QSPI_SLVUR_INT_MASK)
if (u32Mask & QSPI_SLVUR_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
}
if(u32Mask & QSPI_SLVBE_INT_MASK)
if (u32Mask & QSPI_SLVBE_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
}
if(u32Mask & QSPI_TXUF_INT_MASK)
if (u32Mask & QSPI_TXUF_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
}
if(u32Mask & QSPI_FIFO_RXOV_INT_MASK)
if (u32Mask & QSPI_FIFO_RXOV_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
}
if(u32Mask & QSPI_FIFO_RXTO_INT_MASK)
if (u32Mask & QSPI_FIFO_RXTO_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
}
@ -788,56 +788,56 @@ uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk;
/* Check busy status */
if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_BUSY_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk;
/* Check RX empty flag */
if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_RX_EMPTY_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk;
/* Check RX full flag */
if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_RX_FULL_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk;
/* Check TX empty flag */
if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_TX_EMPTY_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk;
/* Check TX full flag */
if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_TX_FULL_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk;
/* Check TX/RX reset flag */
if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_TXRX_RESET_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk;
/* Check QSPIEN flag */
if((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_QSPIEN_STS_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk;
/* Check QSPIx_SS line status */
if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_SSLINE_STS_MASK;
}

2
bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
View File

@ -100,7 +100,7 @@ rt_err_t nu_crc_init(void)
SYS_ResetModule(CRC_RST);
result = rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
return RT_EOK;

8
bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
View File

@ -91,18 +91,18 @@ static rt_err_t nu_crypto_init(void)
SHA_ENABLE_INT(CRPT);
//init cipher mutex
result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
result = rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
#if !defined(BSP_USING_TRNG)
PRNG_ENABLE_INT(CRPT);
result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
#endif

2
bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c
View File

@ -331,7 +331,7 @@ static int nu_fmc_init(void)
FMC_ENABLE_ISP();
SYS_LockReg();
g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_PRIO);
RT_ASSERT(g_mutex_fmc != RT_NULL);
/* PKG_USING_FAL */

6
bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.c
View File

@ -208,10 +208,10 @@ static void nu_pdma_init(void)
if (nu_pdma_inited)
return;
g_mutex_res = rt_mutex_create("pdmalock", RT_IPC_FLAG_FIFO);
g_mutex_res = rt_mutex_create("pdmalock", RT_IPC_FLAG_PRIO);
RT_ASSERT(g_mutex_res != RT_NULL);
g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO);
g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_PRIO);
RT_ASSERT(g_mutex_sg != RT_NULL);
nu_pdma_chn_mask = ~NU_PDMA_CH_Msk;
@ -894,7 +894,7 @@ static void nu_pdma_memfun_actor_init(void)
nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
RT_ASSERT(nu_pdma_memfun_actor_pool_sem != RT_NULL);
nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO);
RT_ASSERT(nu_pdma_memfun_actor_pool_lock != RT_NULL);
}
}

11
bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c
View File

@ -180,10 +180,10 @@ exit_nu_qspi_bus_configure:
return -(ret);
}
#if defined(RT_SFUD_USING_QSPI)
static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
{
QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
#if defined(RT_SFUD_USING_QSPI)
if (qspi_lines > 1)
{
if (tx)
@ -218,13 +218,13 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8
}
}
else
#endif
{
QSPI_DISABLE_DUAL_MODE(qspi_base);
QSPI_DISABLE_QUAD_MODE(qspi_base);
}
return qspi_lines;
}
#endif
static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
@ -317,9 +317,11 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_
qspi_message->dummy_cycles / (8 / u8last),
1);
}
/* Data stage */
nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
#else
/* Data stage */
nu_qspi_mode_config(qspi_bus, RT_NULL, RT_NULL, 1);
#endif //#if defined(RT_SFUD_USING_QSPI)
if (message->length != 0)
@ -369,8 +371,7 @@ static int rt_hw_qspi_init(void)
#if defined(BSP_USING_SPI_PDMA)
nu_qspi_arr[i].pdma_chanid_tx = -1;
nu_qspi_arr[i].pdma_chanid_rx = -1;
#endif
#if defined(BSP_USING_QSPI_PDMA)
if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
{
if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c
View File

@ -50,7 +50,7 @@ rt_err_t nu_trng_init(void)
{
rt_err_t result;
result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0)

42
bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
View File

@ -83,4 +83,46 @@ static int audio_test(int argc, char **argv)
#ifdef FINSH_USING_MSH
MSH_CMD_EXPORT(audio_test, Audio record / replay);
#endif
static int audio_overnight(int argc, char **argv)
{
#define DEF_MAX_TEST_SECOND 5
struct wavrecord_info info;
char strbuf[128];
struct stat stat_buf;
snprintf(strbuf, sizeof(strbuf), "/test.wav");
while (1)
{
rt_kprintf("Recording file at %s\n", strbuf);
info.uri = strbuf;
info.samplerate = 16000;
info.samplebits = 16;
info.channels = 2;
wavrecorder_start(&info);
rt_thread_mdelay(DEF_MAX_TEST_SECOND * 1000);
wavrecorder_stop();
rt_thread_mdelay(1000);
if (stat((const char *)strbuf, &stat_buf) < 0)
{
rt_kprintf("%s non-exist.\n", strbuf);
break;
}
rt_kprintf("Replay file at %s\n", strbuf);
wavplayer_play(strbuf);
rt_thread_mdelay(DEF_MAX_TEST_SECOND * 1000);
wavplayer_stop();
rt_thread_mdelay(1000);
}
return 0;
}
#ifdef FINSH_USING_MSH
MSH_CMD_EXPORT(audio_overnight, auto test record / replay);
#endif
#endif /* PKG_USING_WAVPLAYER */

2
bsp/nuvoton/libraries/nu_packages/SPINAND/drv_spinand.c
View File

@ -494,7 +494,7 @@ rt_err_t rt_hw_mtd_spinand_init(void)
if (u32IsInited)
return RT_EOK;
result = rt_mutex_init(SPINAND_FLASH_LOCK, "spinand", RT_IPC_FLAG_FIFO);
result = rt_mutex_init(SPINAND_FLASH_LOCK, "spinand", RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
result = spinand_flash_init(SPINAND_FLASH_QSPI);

2
bsp/nuvoton/libraries/nuc980/Driver/Source/nu_crypto.c
View File

@ -2170,6 +2170,8 @@ static uint32_t mpShortDiv(uint32_t q[], const uint32_t u[], uint32_t v,
bitmask >>= 1;
}
if (shift == BITS_PER_DIGIT) return 0; /* Avoid cppcheck false-alarm. */
v <<= shift;
overflow = mpShiftLeft(q, u, shift, ndigits);
uu = q;

4
bsp/nuvoton/libraries/nuc980/Driver/Source/nu_emac.c
View File

@ -191,7 +191,7 @@ void EMAC_PhyInit(EMAC_T *EMAC)
while (!(EMAC_MdioRead(EMAC, PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID))
{
if (i++ > 2000000UL) /* Cable not connected */
if (i++ > 10000UL) /* Cable not connected */
{
EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
@ -199,7 +199,7 @@ void EMAC_PhyInit(EMAC_T *EMAC)
}
}
if (i <= 2000000UL)
if (i <= 10000UL)
{
/* Configure auto negotiation capability */
EMAC_MdioWrite(EMAC, PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |

6
bsp/nuvoton/libraries/nuc980/rtt_port/drv_crypto.c
View File

@ -750,19 +750,19 @@ int nu_hwcrypto_device_init(void)
/* init cipher mutex */
#if defined(RT_HWCRYPTO_USING_AES)
result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
AES_ENABLE_INT(CRPT);
#endif
#if defined(RT_HWCRYPTO_USING_SHA1) || defined(RT_HWCRYPTO_USING_SHA2)
result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
SHA_ENABLE_INT(CRPT);
#endif
#if defined(RT_HWCRYPTO_USING_RNG)
result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
#endif

2
bsp/nuvoton/libraries/nuc980/rtt_port/drv_pdma.c
View File

@ -972,7 +972,7 @@ static void nu_pdma_memfun_actor_init(void)
nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
RT_ASSERT(nu_pdma_memfun_actor_pool_sem != RT_NULL);
nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO);
RT_ASSERT(nu_pdma_memfun_actor_pool_lock != RT_NULL);
}
}

2
bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c
View File

@ -263,6 +263,8 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
case RT_DEVICE_CTRL_RTC_SET_ALARM:
RTC_GetDateAndTime(&hw_alarm);
wkalarm = (struct rt_rtc_wkalarm *) args;
hw_alarm.u32Hour = wkalarm->tm_hour;
hw_alarm.u32Minute = wkalarm->tm_min;

92
bsp/nuvoton/nk-980iot/.config
View File

@ -138,13 +138,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
CONFIG_RT_USING_DFS_UFFS=y
# CONFIG_RT_UFFS_ECC_MODE_0 is not set
# CONFIG_RT_UFFS_ECC_MODE_1 is not set
# CONFIG_RT_UFFS_ECC_MODE_2 is not set
CONFIG_RT_UFFS_ECC_MODE_3=y
CONFIG_RT_UFFS_ECC_MODE=3
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
@ -229,6 +222,7 @@ CONFIG_RT_HWCRYPTO_USING_RNG=y
CONFIG_RT_USING_USB_HOST=y
CONFIG_RT_USBH_MSTORAGE=y
CONFIG_UDISK_MOUNTPOINT="/mnt/udisk"
# CONFIG_RT_USBH_HID is not set
CONFIG_RT_USING_USB_DEVICE=y
CONFIG_RT_USBD_THREAD_STACK_SZ=4096
CONFIG_USB_VENDOR_ID=0x0FFE
@ -453,8 +447,6 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
@ -468,6 +460,13 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
@ -507,6 +506,8 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
@ -520,6 +521,16 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
#
# system packages
@ -528,7 +539,6 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
@ -538,6 +548,18 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
CONFIG_PKG_USING_DFS_UFFS=y
CONFIG_PKG_UFFS_PATH="/packages/system/uffs"
CONFIG_RT_USING_DFS_UFFS=y
# CONFIG_RT_UFFS_ECC_MODE_0 is not set
# CONFIG_RT_UFFS_ECC_MODE_1 is not set
# CONFIG_RT_UFFS_ECC_MODE_2 is not set
CONFIG_RT_UFFS_ECC_MODE_3=y
CONFIG_RT_UFFS_ECC_MODE=3
CONFIG_PKG_USING_DFS_UFFS_LATEST_VERSION=y
CONFIG_PKG_UFFS_VER="latest"
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
@ -562,6 +584,14 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
#
# peripheral libraries and drivers
@ -570,6 +600,7 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
@ -619,6 +650,28 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
@ -626,9 +679,8 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_LIBCSV is not set
CONFIG_PKG_USING_OPTPARSE=y
CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse"
CONFIG_PKG_USING_OPTPARSE_V100=y
# CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION is not set
CONFIG_PKG_OPTPARSE_VER="v1.0.0"
CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION=y
CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_OPTPARSE_USING_DEMO is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
@ -671,24 +723,24 @@ CONFIG_VI_UNDO_QUEUE_MAX=256
CONFIG_PKG_USING_VI_LATEST_VERSION=y
CONFIG_PKG_VI_VER="latest"
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
#
# Nuvoton Packages Config
@ -715,7 +767,6 @@ CONFIG_BSP_USING_MMU=y
CONFIG_BSP_USING_PDMA=y
CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_CLK is not set
CONFIG_BSP_USING_EMAC=y
CONFIG_BSP_USING_EMAC0=y
# CONFIG_BSP_USING_EMAC1 is not set
@ -781,6 +832,7 @@ CONFIG_BSP_USING_SPI1_NONE=y
CONFIG_BSP_USING_I2S=y
CONFIG_NU_I2S_DMA_FIFO_SIZE=4096
CONFIG_BSP_USING_QSPI=y
CONFIG_BSP_USING_QSPI_PDMA=y
CONFIG_BSP_USING_QSPI0=y
CONFIG_BSP_USING_QSPI0_PDMA=y
# CONFIG_BSP_USING_SCUART is not set

9
bsp/nuvoton/nk-980iot/linking_scripts/nuc980.ld
View File

@ -23,18 +23,14 @@ SECTIONS
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
@ -54,6 +50,7 @@ SECTIONS
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(4);
}
. = ALIGN(4);

894
bsp/nuvoton/nk-n9h30/.config Normal file
View File

@ -0,0 +1,894 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=2048
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_SIGNALS=y
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
CONFIG_RT_USING_MEMTRACE=y
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_ARM9=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=16
CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
CONFIG_DFS_FD_MAX=64
CONFIG_RT_USING_DFS_MNTTABLE=y
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=8
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=2048
CONFIG_RT_USING_CAN=y
# CONFIG_RT_CAN_USING_HDR is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
CONFIG_RT_USING_ALARM=y
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
CONFIG_RT_USING_QSPI=y
# CONFIG_RT_USING_SPI_MSD is not set
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
CONFIG_RT_SFUD_USING_QSPI=y
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
CONFIG_RT_USING_WDT=y
CONFIG_RT_USING_AUDIO=y
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048
# CONFIG_RT_USING_SENSOR is not set
CONFIG_RT_USING_TOUCH=y
# CONFIG_RT_TOUCH_PIN_IRQ is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
CONFIG_RT_USING_INPUT_CAPTURE=y
CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
CONFIG_RT_USING_USB_HOST=y
CONFIG_RT_USBH_MSTORAGE=y
CONFIG_UDISK_MOUNTPOINT="/mnt/udisk"
# CONFIG_RT_USBH_HID is not set
CONFIG_RT_USING_USB_DEVICE=y
CONFIG_RT_USBD_THREAD_STACK_SZ=4096
CONFIG_USB_VENDOR_ID=0x0FFE
CONFIG_USB_PRODUCT_ID=0x0001
CONFIG_RT_USB_DEVICE_COMPOSITE=y
CONFIG_RT_USB_DEVICE_CDC=y
CONFIG_RT_USB_DEVICE_NONE=y
CONFIG_RT_USB_DEVICE_MSTORAGE=y
# CONFIG_RT_USB_DEVICE_HID is not set
# CONFIG_RT_USB_DEVICE_RNDIS is not set
# CONFIG_RT_USB_DEVICE_ECM is not set
# CONFIG_RT_USB_DEVICE_WINUSB is not set
# CONFIG_RT_USB_DEVICE_AUDIO is not set
CONFIG_RT_VCOM_TASK_STK_SIZE=512
CONFIG_RT_CDC_RX_BUFSIZE=128
# CONFIG_RT_VCOM_TX_USE_DMA is not set
CONFIG_RT_VCOM_SERNO="32021919830108"
CONFIG_RT_VCOM_SER_LEN=14
CONFIG_RT_VCOM_TX_TIMEOUT=1000
CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1"
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_FIXED_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
CONFIG_SAL_USING_POSIX=y
#
# Network interface device
#
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=32
CONFIG_RT_LWIP_PBUF_NUM=256
CONFIG_RT_LWIP_RAW_PCB_NUM=32
CONFIG_RT_LWIP_UDP_PCB_NUM=32
CONFIG_RT_LWIP_TCP_PCB_NUM=32
CONFIG_RT_LWIP_TCP_SEG_NUM=256
CONFIG_RT_LWIP_TCP_SND_BUF=32768
CONFIG_RT_LWIP_TCP_WND=10240
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
CONFIG_RT_LWIP_NETIF_LOOPBACK=y
CONFIG_LWIP_NETIF_LOOPBACK=1
CONFIG_RT_LWIP_STATS=y
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
CONFIG_PKG_USING_WAVPLAYER=y
CONFIG_PKG_WAVPLAYER_PATH="/packages/multimedia/wavplayer"
CONFIG_PKG_WP_USING_PLAY=y
CONFIG_PKG_WP_PLAY_DEVICE="sound0"
CONFIG_PKG_WP_USING_RECORD=y
CONFIG_PKG_WP_RECORD_DEVICE="sound0"
# CONFIG_PKG_USING_WAVPLAYER_V020 is not set
CONFIG_PKG_USING_WAVPLAYER_LATEST_VERSION=y
CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
CONFIG_PKG_USING_NUEMWIN=y
CONFIG_PKG_NUEMWIN_PATH="/packages/multimedia/NUemWin"
CONFIG_PKG_NUEMWIN_MEM_SIZE=4
CONFIG_PKG_USING_NUEMWIN_EXAMPLE=y
CONFIG_PKG_USING_NUEMWIN_GUIDEMO=y
# CONFIG_PKG_USING_NUEMWIN_SIMPLEDEMO is not set
CONFIG_PKG_USING_NUEMWIN_LATEST_VERSION=y
CONFIG_PKG_NUEMWIN_VER="latest"
CONFIG_PKG_NUEMWIN_VER_NUM=0x99999
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
CONFIG_PKG_USING_MEM_SANDBOX=y
CONFIG_PKG_MEM_SANDBOX_PATH="/packages/tools/mem_sandbox"
CONFIG_PKG_USING_MEM_SANDBOX_LATEST_VERSION=y
CONFIG_PKG_MEM_SANDBOX_VER="latest"
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
CONFIG_PKG_USING_FAL=y
CONFIG_PKG_FAL_PATH="/packages/system/fal"
CONFIG_FAL_DEBUG_CONFIG=y
CONFIG_FAL_DEBUG=1
CONFIG_FAL_PART_HAS_TABLE_CFG=y
CONFIG_FAL_USING_SFUD_PORT=y
CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0"
# CONFIG_PKG_USING_FAL_V00500 is not set
# CONFIG_PKG_USING_FAL_V00400 is not set
# CONFIG_PKG_USING_FAL_V00300 is not set
# CONFIG_PKG_USING_FAL_V00200 is not set
# CONFIG_PKG_USING_FAL_V00100 is not set
CONFIG_PKG_USING_FAL_LATEST_VERSION=y
CONFIG_PKG_FAL_VER="latest"
CONFIG_PKG_FAL_VER_NUM=0x99999
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
CONFIG_PKG_USING_LITTLEVGL2RTT=y
CONFIG_PKG_LITTLEVGL2RTT_PATH="/packages/system/LittlevGL2RTT"
CONFIG_PKG_USING_LITTLEVGL2RTT_V001=y
# CONFIG_PKG_USING_LITTLEVGL2RTT_LATEST_VERSION is not set
CONFIG_PKG_LITTLEVGL2RTT_VER="v0.0.1"
#
# LittlevGL2RTT Options
#
# CONFIG_LV_MEM_STATIC is not set
CONFIG_LV_MEM_DYNAMIC=y
CONFIG_LV_MEM_CUSTOM=1
# CONFIG_LV_COLOR_DEPTH_1 is not set
# CONFIG_LV_COLOR_DEPTH_8 is not set
# CONFIG_LV_COLOR_DEPTH_16 is not set
# CONFIG_LV_COLOR_DEPTH_24 is not set
CONFIG_LV_COLOR_DEPTH_32=y
CONFIG_LV_COLOR_DEPTH=32
CONFIG_LV_HOR_RES=800
CONFIG_LV_VER_RES=480
CONFIG_LV_DPI=50
CONFIG_LV_GC_DISABLE=y
# CONFIG_LV_GC_ENABLE is not set
CONFIG_LV_ENABLE_GC=0
CONFIG_LITTLEVGL2RTT_USING_DEMO=y
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
CONFIG_PKG_USING_RAMDISK=y
CONFIG_PKG_RAMDISK_PATH="/packages/system/ramdisk"
# CONFIG_PKG_USING_RAMDISK_V010 is not set
CONFIG_PKG_USING_RAMDISK_LATEST_VERSION=y
CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
CONFIG_PKG_USING_OPTPARSE=y
CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse"
CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION=y
CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_OPTPARSE_USING_DEMO is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
CONFIG_PKG_USING_VI=y
CONFIG_PKG_VI_PATH="/packages/misc/vi"
CONFIG_VI_SANDBOX_SIZE_KB=20
CONFIG_VI_MAX_LEN=4096
# CONFIG_VI_ENABLE_8BIT is not set
CONFIG_VI_ENABLE_COLON=y
CONFIG_VI_ENABLE_COLON_EXPAND=y
CONFIG_VI_ENABLE_YANKMARK=y
CONFIG_VI_ENABLE_SEARCH=y
CONFIG_VI_ENABLE_DOT_CMD=y
CONFIG_VI_ENABLE_READONLY=y
CONFIG_VI_ENABLE_SETOPTS=y
CONFIG_VI_ENABLE_SET=y
# CONFIG_VI_ENABLE_WIN_RESIZE is not set
CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y
CONFIG_VI_ENABLE_UNDO=y
CONFIG_VI_ENABLE_UNDO_QUEUE=y
CONFIG_VI_UNDO_QUEUE_MAX=256
CONFIG_VI_ENABLE_VERBOSE_STATUS=y
CONFIG_PKG_USING_VI_LATEST_VERSION=y
CONFIG_PKG_VI_VER="latest"
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
#
# Nuvoton Packages Config
#
CONFIG_NU_PKG_USING_UTILS=y
# CONFIG_NU_PKG_USING_DEMO is not set
# CONFIG_NU_PKG_USING_BMX055 is not set
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NAU88L25 is not set
CONFIG_NU_PKG_USING_NAU8822=y
# CONFIG_NU_PKG_USING_ILI9341 is not set
# CONFIG_NU_PKG_USING_SPINAND is not set
#
# Hardware Drivers Config
#
#
# On-chip Peripheral Drivers
#
CONFIG_SOC_SERIES_N9H30=y
# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set
CONFIG_BSP_USING_MMU=y
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_CLK is not set
CONFIG_BSP_USING_EMAC=y
CONFIG_BSP_USING_EMAC0=y
CONFIG_BSP_USING_EMAC1=y
CONFIG_BSP_USING_RTC=y
# CONFIG_NU_RTC_SUPPORT_IO_RW is not set
# CONFIG_NU_RTC_SUPPORT_MSH_CMD is not set
CONFIG_BSP_USING_ADC=y
CONFIG_BSP_USING_ADC_TOUCH=y
CONFIG_BSP_USING_ETMR=y
CONFIG_BSP_USING_ETIMER=y
CONFIG_BSP_USING_ETIMER_CAPTURE=y
CONFIG_BSP_USING_ETMR0=y
CONFIG_BSP_USING_ETIMER0=y
# CONFIG_BSP_USING_ETIMER0_CAPTURE is not set
CONFIG_BSP_USING_ETMR1=y
CONFIG_BSP_USING_ETIMER1=y
# CONFIG_BSP_USING_ETIMER1_CAPTURE is not set
CONFIG_BSP_USING_ETMR2=y
# CONFIG_BSP_USING_ETIMER2 is not set
CONFIG_BSP_USING_ETIMER2_CAPTURE=y
CONFIG_BSP_USING_ETMR3=y
# CONFIG_BSP_USING_ETIMER3 is not set
CONFIG_BSP_USING_ETIMER3_CAPTURE=y
CONFIG_BSP_USING_TMR=y
CONFIG_BSP_USING_TIMER=y
CONFIG_BSP_USING_TIMER0=y
CONFIG_BSP_USING_TIMER1=y
CONFIG_BSP_USING_TIMER2=y
CONFIG_BSP_USING_TIMER3=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_UART8 is not set
# CONFIG_BSP_USING_UART9 is not set
# CONFIG_BSP_USING_UART10 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_BSP_USING_I2C0=y
# CONFIG_BSP_USING_I2C1 is not set
CONFIG_BSP_USING_SDH=y
# CONFIG_BSP_USING_SDH0 is not set
CONFIG_BSP_USING_SDH1=y
CONFIG_NU_SDH_HOTPLUG=y
# CONFIG_NU_SDH_MOUNT_ON_ROOT is not set
CONFIG_BSP_USING_CAN=y
CONFIG_BSP_USING_CAN0=y
# CONFIG_BSP_USING_CAN1 is not set
CONFIG_BSP_USING_PWM=y
CONFIG_BSP_USING_PWM0=y
CONFIG_BSP_USING_QSPI=y
# CONFIG_BSP_USING_QSPI0_NONE is not set
CONFIG_BSP_USING_QSPI0=y
CONFIG_BSP_USING_QSPI1_NONE=y
# CONFIG_BSP_USING_QSPI1 is not set
CONFIG_BSP_USING_I2S=y
CONFIG_NU_I2S_DMA_FIFO_SIZE=2048
# CONFIG_BSP_USING_SCUART is not set
# CONFIG_BSP_USING_CRYPTO is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
CONFIG_BSP_USING_WDT=y
CONFIG_BSP_USING_EBI=y
CONFIG_BSP_USING_VPOST=y
# CONFIG_LCM_USING_E50A2V1 is not set
# CONFIG_LCM_USING_LSA40AT9001 is not set
CONFIG_LCM_USING_FW070TFT=y
CONFIG_VPOST_USING_LCD_IDX=3
CONFIG_LCM_USING_BPP=4
CONFIG_BSP_USING_VPOST_OSD=y
CONFIG_BSP_USING_USBD=y
CONFIG_BSP_USING_USBH=y
#
# On-board Peripheral Drivers
#
CONFIG_BSP_USING_CONSOLE=y
CONFIG_BOARD_USING_IP101GR=y
CONFIG_BOARD_USING_NAU8822=y
CONFIG_BOARD_USING_STORAGE_SDCARD=y
CONFIG_BOARD_USING_STORAGE_SPIFLASH=y
CONFIG_BOARD_USING_BUZZER=y
CONFIG_BOARD_USING_LCM=y
CONFIG_BOARD_USING_USB0_DEVICE_HOST=y
CONFIG_BOARD_USING_USB1_HOST=y
#
# Board extended module drivers
#
CONFIG_BOARD_USE_UTEST=y
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.nk-n9h30.test.utest."

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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
# you can change the RTT_ROOT default "../../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config NU_PKGS_DIR
string
option env="NU_PKGS_ROOT"
default "../libraries/nu_packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"

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# NK-N9H30
## 1. Introduction
Nuvoton offers the emWin platform which is embedded with Nuvoton N9H MPU, it provides complete HMI solutions which are further enhanced by the emWin software. The N9H series with ARM926EJ-S core can operate at up to 300 MHz and can drive up to 1024x768 pixels in parallel port. It integrated TFT LCD controller and 2D graphics accelerator, up to 16 million colors (24-bit) LCD screen output, and provides high resolution and high chroma to deliver gorgeous display effects. To play compressed video in HMI screens smoothly, the N9H series is equipped with H.264 video decompression engine. It also offers built-in voice decoder, which can streamline the peripheral circuits of HMI applications with sound playback. It embedded up to 64 MB DDR memory, along with ample hardware storage and computing space for excellent design flexibility.
[![NK-N9H30](https://i.imgur.com/B04MCCf.png "NK-N9H30")](https://i.imgur.com/B04MCCf.png "NK-N9H30")
### 1.1 MCU specification
| | Features |
| -- | -- |
| Part NO. | N9H30F61IEC (LQFP216 pin MCP package with DDR (64 MB) |
| CPU ARCH. | 32-bit ARM926EJ-S |
| Operation frequency | 300 MHz |
| Embedded SDRAM size | Built-in 64MB |
| Crypto engine | AES, DES,HMAC and SHA crypto accelerator |
| RMII interface | 10/100 Mbps x2 |
| USB 2.0 | High Speed Host/Device x1 |
| Audio | Mono microphone / Stereo headphone |
| Extern storage | 32MB SPI-NOR Flash |
| SD card slot | SD |
### 1.2 Interface
| Interface |
| -- |
| Two RJ45 Ethernet |
| An USB 2.0 HS Dual role(Host/Device) port |
| A microSD slot |
| A 3.5mm Audio connector |
| An ICE connector |
### 1.3 On-board devices
| Device | Description | Driver supporting status |
| -- | -- | -- |
|Ethernet PHY | IP101GR | Supported |
|Keypad | | Supported |
|LEDs | | Supported |
|Audio Codec | NAU8822, Supports MIC and earphone | Supported |
|USB Device | VCOM + MStorage | Supported |
|USB Host | MStorage | Supported |
|SPI NOR flash | W25Q256JVEQ (32 MB) | Supported |
## 2. Supported compiler
Support GCC, MDK4 and MDK5 IDE/compilers. More information of these compiler version as following:
| IDE/Compiler | Tested version |
| ---------- | ---------------------------- |
| MDK5 | 5.26.2 |
| GCC | GCC 5.4.1 20160919 (release) |
Notice: Please install ICE driver for development.
## 3. Program firmware
### 3.1 SDRAM Downloading using NuWriter
You can use NuWriter to download rtthread.bin into SDRAM, then run it.
[![SDRAM Downloading using NuWriter](https://i.imgur.com/UqFvQOb.gif "SDRAM Downloading using NuWriter")](https://i.imgur.com/UqFvQOb.gif "SDRAM Downloading using NuWriter")
<br>
Choose type: DDR/SRAM<br>
<< Press Re-Connect >><br>
Choose file: Specify your rtthread.bin file.<br>
Execute Address: 0x0<br>
Option: Download and run<br>
<< Press Download >><br>
Enjoy!! <br>
<br>
### 3.2 SPI NOR flash using NuWriter
You can use NuWriter to program rtthread.bin into SPI NOR flash.
[![SPI NOR flash](https://i.imgur.com/6Fw3tc7.gif "SPI NOR flash")](https://i.imgur.com/6Fw3tc7.gif "SPI NOR flash using NuWriter")
<br>
Choose type: SPI<br>
<< Press Re-Connect >><br>
Choose file: Specify your rtthread.bin file.<br>
Image Type: Loader<br>
Execute Address: 0x0<br>
<< Press Program >><br>
<< Press OK & Wait it down >><br>
<< Set Power-on setting to SPI NOR booting >><br>
<< Press Reset button on board >><br>
Enjoy!! <br>
<br>
## 4. Test
You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager.
[![Serial settings](https://i.imgur.com/5NYuSNM.png "Serial settings")](https://i.imgur.com/5NYuSNM.png "Serial settings")
## 5. Demo
* Run NUemWin2RTT on NK-N9H30
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build May 12 2021
2006 - 2021 Copyright by rt-thread team
msh /> nu_touch_start
msh /> nuemwin_start
<Enjoy NuemWin with H/W 2D Graphics Accelerating>
msh /> nuemwin_stop
```
[![NUemWin2RTT on NK-N9H30](https://img.youtube.com/vi/TAfkOKpySQk/0.jpg)](https://www.youtube.com/watch?v=TAfkOKpySQk)
* Run LittlevGL2RTT on NK-N9H30
**Please check out modified version with GE2D accelerating from [HERE](https://github.com/wosayttn/LittlevGL2RTT).**
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build May 12 2021
2006 - 2021 Copyright by rt-thread team
msh /> nu_touch_start
msh /> lv_demo
<Enjoy LvGL with H/W 2D Graphics Accelerating>
```
[![LvGL2RTT on NK-N9H30](https://img.youtube.com/vi/djz0jAKrfjs/0.jpg)](https://www.youtube.com/watch?v=djz0jAKrfjs)
## 6. Purchase
* [Nuvoton Direct](https://direct.nuvoton.com/en/numaker-emwin-n9h30)
## 7. Resources
* [Board Schematic](https://www.nuvoton.com/resource-download.jsp?tp_GUID=HL1020201117191514)
* [Download NK-N9H30 Quick Start Guide](https://www.nuvoton.com/resource-download.jsp?tp_GUID=UG1320210329155300)
* [Download NuWriter](https://github.com/OpenNuvoton/NUC970_NuWriter)

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# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
nuvoton_library = 'n9h30'
rtconfig.BSP_LIBRARY_TYPE = nuvoton_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript')))
# include nu_pkgs
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-12 Wayne First version
*
******************************************************************************/
#include <rtconfig.h>
#include <rtdevice.h>
#if defined(RT_USING_PIN)
#include <drv_gpio.h>
/* defined the INDICATOR_LED pin: PH2 */
#define INDICATOR_LED NU_GET_PININDEX(NU_PH, 2)
#define MATRIX_COL_NUM 2
#define MATRIX_ROW_NUM 3
/* defined the KEY_COl_0 pin: PB4 */
#define KEY_COL_0 NU_GET_PININDEX(NU_PB, 4)
/* defined the KEY_COl_1 pin: PB5 */
#define KEY_COL_1 NU_GET_PININDEX(NU_PB, 5)
/* defined the KEY_ROW_0 pin: PF10 */
#define KEY_ROW_0 NU_GET_PININDEX(NU_PF, 10)
/* defined the KEY_ROW_1 pin: PE15 */
#define KEY_ROW_1 NU_GET_PININDEX(NU_PE, 15)
/* defined the KEY_ROW_2 pin: PE14 */
#define KEY_ROW_2 NU_GET_PININDEX(NU_PE, 14)
uint32_t au32KeyMatrix_Col[MATRIX_COL_NUM] = { KEY_COL_0, KEY_COL_1 };
uint32_t au32KeyMatrix_Row[MATRIX_ROW_NUM] = { KEY_ROW_0, KEY_ROW_1, KEY_ROW_2 };
const char *szKeyLabel[] =
{
"K1",
"K2",
"K3",
"K4",
"K5",
"K6"
};
static void nu_key_matrix_cb(void *args)
{
uint32_t ri = (uint32_t)args;
int ci;
for (ci = 0; ci < MATRIX_COL_NUM; ci++)
{
/* Find column bit is low. */
if (!rt_pin_read(au32KeyMatrix_Col[ci]))
{
break;
}
}
rt_kprintf("[%d %d] Pressed %s button.\n", ci, ri, szKeyLabel[(ci) + MATRIX_COL_NUM * ri]);
}
static void nu_key_matrix_switch(uint32_t counter)
{
int i;
for (i = 0; i < MATRIX_COL_NUM; i++)
{
/* set pin value to high */
rt_pin_write(au32KeyMatrix_Col[i], PIN_HIGH);
}
/* set pin value to low */
rt_pin_write(au32KeyMatrix_Col[counter % MATRIX_COL_NUM], PIN_LOW);
}
#endif
int main(int argc, char **argv)
{
#if defined(RT_USING_PIN)
uint32_t counter = 1;
int i = 0;
for (i = 0; i < MATRIX_ROW_NUM; i++)
{
/* set pin mode to input */
rt_pin_mode(au32KeyMatrix_Row[i], PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(au32KeyMatrix_Row[i], PIN_IRQ_MODE_FALLING, nu_key_matrix_cb, (void *)i);
rt_pin_irq_enable(au32KeyMatrix_Row[i], PIN_IRQ_ENABLE);
}
for (i = 0; i < MATRIX_COL_NUM; i++)
{
/* set pin mode to output */
rt_pin_mode(au32KeyMatrix_Col[i], PIN_MODE_OUTPUT);
}
/* set INDICATOR_LED pin mode to output */
rt_pin_mode(INDICATOR_LED, PIN_MODE_OUTPUT);
/* Toggle column pins in key matrix. */
while (counter++ > 0)
{
rt_pin_write(INDICATOR_LED, PIN_HIGH);
rt_thread_mdelay(200);
rt_pin_write(INDICATOR_LED, PIN_LOW);
rt_thread_mdelay(200);
nu_key_matrix_switch(counter);
}
#endif
return 0;
}

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/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-12 Wayne First version
*
******************************************************************************/
#include "rtconfig.h"
#include <rtthread.h>
#define LOG_TAG "mnt"
#define DBG_ENABLE
#define DBG_SECTION_NAME "mnt"
#define DBG_LEVEL DBG_ERROR
#define DBG_COLOR
#include <rtdbg.h>
#if defined(RT_USING_DFS)
#include <dfs_fs.h>
#include <dfs_posix.h>
#endif
#if defined(PKG_USING_FAL)
#include <fal.h>
#endif
#if defined(PKG_USING_RAMDISK)
#define RAMDISK_NAME "ramdisk0"
#define RAMDISK_UDC "ramdisk1"
#define MOUNT_POINT_RAMDISK0 "/"
#endif
#if defined(BOARD_USING_STORAGE_SPIFLASH)
#define PARTITION_NAME_FILESYSTEM "filesystem"
#define MOUNT_POINT_SPIFLASH0 "/mnt/"PARTITION_NAME_FILESYSTEM
#endif
#ifdef RT_USING_DFS_MNTTABLE
/*
const char *device_name;
const char *path;
const char *filesystemtype;
unsigned long rwflag;
const void *data;
*/
const struct dfs_mount_tbl mount_table[] =
{
#if defined(PKG_USING_RAMDISK)
{ RAMDISK_UDC, "/mnt/ram_usbd", "elm", 0, RT_NULL },
#endif
{0},
};
#endif
#if defined(PKG_USING_RAMDISK)
extern rt_err_t ramdisk_init(const char *dev_name, rt_uint8_t *disk_addr, rt_size_t block_size, rt_size_t num_block);
int ramdisk_device_init(void)
{
rt_err_t result = RT_EOK;
/* Create a 8MB RAMDISK */
result = ramdisk_init(RAMDISK_NAME, NULL, 512, 2 * 4096);
RT_ASSERT(result == RT_EOK);
/* Create a 4MB RAMDISK */
result = ramdisk_init(RAMDISK_UDC, NULL, 512, 2 * 4096);
RT_ASSERT(result == RT_EOK);
return 0;
}
INIT_DEVICE_EXPORT(ramdisk_device_init);
/* Recursive mkdir */
static int mkdir_p(const char *dir, const mode_t mode)
{
int ret = -1;
char *tmp = NULL;
char *p = NULL;
struct stat sb;
rt_size_t len;
if (!dir)
goto exit_mkdir_p;
/* Copy path */
/* Get the string length */
len = strlen(dir);
tmp = rt_strdup(dir);
/* Remove trailing slash */
if (tmp[len - 1] == '/')
{
tmp[len - 1] = '\0';
len--;
}
/* check if path exists and is a directory */
if (stat(tmp, &sb) == 0)
{
if (S_ISDIR(sb.st_mode))
{
ret = 0;
goto exit_mkdir_p;
}
}
/* Recursive mkdir */
for (p = tmp + 1; p - tmp <= len; p++)
{
if ((*p == '/') || (p - tmp == len))
{
*p = 0;
/* Test path */
if (stat(tmp, &sb) != 0)
{
/* Path does not exist - create directory */
if (mkdir(tmp, mode) < 0)
{
goto exit_mkdir_p;
}
}
else if (!S_ISDIR(sb.st_mode))
{
/* Not a directory */
goto exit_mkdir_p;
}
if (p - tmp != len)
*p = '/';
}
}
ret = 0;
exit_mkdir_p:
if (tmp)
rt_free(tmp);
return ret;
}
/* Initialize the filesystem */
int filesystem_init(void)
{
rt_err_t result = RT_EOK;
// ramdisk as root
if (!rt_device_find(RAMDISK_NAME))
{
LOG_E("cannot find %s device", RAMDISK_NAME);
goto exit_filesystem_init;
}
else
{
/* Format these ramdisk */
result = (rt_err_t)dfs_mkfs("elm", RAMDISK_NAME);
RT_ASSERT(result == RT_EOK);
/* mount ramdisk0 as root directory */
if (dfs_mount(RAMDISK_NAME, "/", "elm", 0, RT_NULL) == 0)
{
LOG_I("ramdisk mounted on \"/\".");
/* now you can create dir dynamically. */
mkdir_p("/mnt", 0x777);
mkdir_p("/cache", 0x777);
mkdir_p("/download", 0x777);
mkdir_p("/mnt/ram_usbd", 0x777);
#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT)
mkdir_p(UDISK_MOUNTPOINT, 0x777);
#endif
}
else
{
LOG_E("root folder creation failed!\n");
goto exit_filesystem_init;
}
}
if (!rt_device_find(RAMDISK_UDC))
{
LOG_E("cannot find %s device", RAMDISK_UDC);
goto exit_filesystem_init;
}
else
{
/* Format these ramdisk */
result = (rt_err_t)dfs_mkfs("elm", RAMDISK_UDC);
RT_ASSERT(result == RT_EOK);
}
exit_filesystem_init:
return -result;
}
INIT_ENV_EXPORT(filesystem_init);
#endif
#if defined(BOARD_USING_STORAGE_SPIFLASH)
int mnt_init_spiflash0(void)
{
#if defined(PKG_USING_FAL)
extern int fal_init_check(void);
if (!fal_init_check())
fal_init();
#endif
struct rt_device *psNorFlash = fal_blk_device_create(PARTITION_NAME_FILESYSTEM);
if (!psNorFlash)
{
rt_kprintf("Failed to create block device for %s.\n", PARTITION_NAME_FILESYSTEM);
goto exit_mnt_init_spiflash0;
}
else if (mkdir(MOUNT_POINT_SPIFLASH0, 0x777) < 0)
{
rt_kprintf("Failed to make folder for %s.\n", MOUNT_POINT_SPIFLASH0);
goto exit_mnt_init_spiflash0;
}
else if (dfs_mount(psNorFlash->parent.name, MOUNT_POINT_SPIFLASH0, "elm", 0, 0) != 0)
{
rt_kprintf("Failed to mount elm on %s.\n", MOUNT_POINT_SPIFLASH0);
rt_kprintf("Try to execute 'mkfs -t elm %s' first, then reboot.\n", PARTITION_NAME_FILESYSTEM);
goto exit_mnt_init_spiflash0;
}
rt_kprintf("mount %s with elmfat type: ok\n", PARTITION_NAME_FILESYSTEM);
exit_mnt_init_spiflash0:
return 0;
}
INIT_ENV_EXPORT(mnt_init_spiflash0);
#endif

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menu "Hardware Drivers Config"
menu "On-chip Peripheral Drivers"
source "$BSP_DIR/../libraries/n9h30/rtt_port/Kconfig"
endmenu
menu "On-board Peripheral Drivers"
config BSP_USING_CONSOLE
bool "Enable UART0 for RTT Console(uart0)"
select BSP_USING_UART
select BSP_USING_UART0
default y
config BOARD_USING_IP101GR
bool "Enable ethernet phy supporting(over emac/mdio)"
select BSP_USING_EMAC
select BSP_USING_EMAC0
select BSP_USING_EMAC1
default n
config BOARD_USING_NAU8822
bool "NAU8822 Audio Codec supporting(over i2s, i2c0)"
select NU_PKG_USING_NAU8822
select BSP_USING_I2C0
select BSP_USING_I2S
select BSP_USING_I2S0
default n
config BOARD_USING_STORAGE_SDCARD
bool "SDCARD supporting(over sdh1)"
select BSP_USING_SDH
select BSP_USING_SDH1
default y
config BOARD_USING_STORAGE_SPIFLASH
bool "SPIFLASH supporting(over qspi0)"
select BSP_USING_QSPI
select BSP_USING_QSPI0
default y
config BOARD_USING_BUZZER
bool "BUZZER.(over pwm0_ch1)"
select BSP_USING_PWM
select BSP_USING_PWM0
default n
config BOARD_USING_LCM
bool "NuDesign TFT-LCD7(over vpost)"
select BSP_USING_VPOST
select LCM_USING_FW070TFT
default y
config BOARD_USING_USB0_DEVICE_HOST
select BSP_USING_USBH
select BSP_USING_USBD
bool "Enable USB0 Device/Host"
help
Choose this option if you need USB device or host function mode.
If you need USB host, please remember short to ground on JP1 jumper.
config BOARD_USING_USB1_HOST
select BSP_USING_USBH
bool "Enable USB1 Host"
help
Choose this option if you need USB1 HOST.
endmenu
menu "Board extended module drivers"
endmenu
endmenu

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# RT-Thread building script for component
from building import *
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [ cwd ]
group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-1-16 Wayne First version
*
******************************************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "NuMicro.h"
#include "drv_sys.h"
#if defined(__CC_ARM)
extern int Image$$RW_RAM1$$ZI$$Limit;
#define BOARD_HEAP_START (void*)&Image$$RW_RAM1$$ZI$$Limit
#else
extern int __bss_end;
#define BOARD_HEAP_START ((void *)&__bss_end)
#endif
#define BOARD_SDRAM_START 0x0
#define BOARD_SDRAM_SIZE 0x04000000
#define BOARD_HEAP_END ((void*)BOARD_SDRAM_SIZE)
extern void rt_hw_board_init(void);
extern void nu_clock_init(void);
extern void nu_clock_deinit(void);
extern void nu_pin_init(void);
extern void nu_pin_deinit(void);
#endif /* BOARD_H_ */

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/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-12 Wayne First version
*
******************************************************************************/
#include <rtconfig.h>
#include <rtdevice.h>
#if defined(BOARD_USING_STORAGE_SPIFLASH)
#include <drv_qspi.h>
#if defined(RT_USING_SFUD)
#include "spi_flash.h"
#include "spi_flash_sfud.h"
#endif
#define W25X_REG_READSTATUS (0x05)
#define W25X_REG_READSTATUS2 (0x35)
#define W25X_REG_WRITEENABLE (0x06)
#define W25X_REG_WRITESTATUS (0x01)
#define W25X_REG_QUADENABLE (0x02)
static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
{
rt_uint8_t u8Val;
rt_err_t result = RT_EOK;
rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
RT_ASSERT(result > 0);
return u8Val;
}
static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
{
rt_uint8_t u8Val;
rt_err_t result = RT_EOK;
rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
RT_ASSERT(result > 0);
return u8Val;
}
static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
{
rt_uint8_t w25x_txCMD1;
rt_uint8_t au8Val[2];
rt_err_t result;
struct rt_qspi_message qspi_message = {0};
/* Enable WE */
w25x_txCMD1 = W25X_REG_WRITEENABLE;
result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
if (result != sizeof(w25x_txCMD1))
goto exit_SpiFlash_WriteStatusReg;
/* Prepare status-1, 2 data */
au8Val[0] = u8Value1;
au8Val[1] = u8Value2;
/* 1-bit mode: Instruction+payload */
qspi_message.instruction.content = W25X_REG_WRITESTATUS;
qspi_message.instruction.qspi_lines = 1;
qspi_message.qspi_data_lines = 1;
qspi_message.parent.cs_take = 1;
qspi_message.parent.cs_release = 1;
qspi_message.parent.send_buf = &au8Val[0];
qspi_message.parent.length = sizeof(au8Val);
qspi_message.parent.next = RT_NULL;
if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
{
result = -RT_ERROR;
}
result = RT_EOK;
exit_SpiFlash_WriteStatusReg:
return result;
}
static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
{
volatile uint8_t u8ReturnValue;
do
{
u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
u8ReturnValue = u8ReturnValue & 1;
}
while (u8ReturnValue != 0); // check the BUSY bit
}
static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
{
rt_err_t result = RT_EOK;
uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
u8Status2 |= W25X_REG_QUADENABLE;
result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
RT_ASSERT(result == RT_EOK);
SpiFlash_WaitReady(qspi_device);
}
static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
{
rt_err_t result = RT_EOK;
uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
u8Status2 &= ~W25X_REG_QUADENABLE;
result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
RT_ASSERT(result == RT_EOK);
SpiFlash_WaitReady(qspi_device);
}
static int rt_hw_spiflash_init(void)
{
if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
return -1;
#if defined(RT_USING_SFUD)
if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL)
{
return -(RT_ERROR);
}
#endif
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_spiflash_init);
#endif /* BOARD_USING_STORAGE_SPIFLASH */
#if defined(BOARD_USING_NAU8822) && defined(NU_PKG_USING_NAU8822)
#include <acodec_nau8822.h>
S_NU_NAU8822_CONFIG sCodecConfig =
{
.i2c_bus_name = "i2c0",
.i2s_bus_name = "sound0",
.pin_phonejack_en = 0,
.pin_phonejack_det = 0,
};
int rt_hw_nau8822_port(void)
{
if (nu_hw_nau8822_init(&sCodecConfig) != RT_EOK)
return -1;
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_nau8822_port);
#endif /* BOARD_USING_NAU8822 */
#if defined(BOARD_USING_BUZZER)
#define PWM_DEV_NAME "pwm0"
#define PWM_DEV_CHANNEL (1)
static void PlayRingTone(void)
{
struct rt_device_pwm *pwm_dev;
rt_uint32_t period;
int i, j;
period = 1000;
if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME)) != RT_NULL)
{
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, period);
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
for (j = 0; j < 3; j++)
{
for (i = 0; i < 10; i++)
{
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, period);
rt_thread_mdelay(50);
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, period / 2);
rt_thread_mdelay(50);
}
/* Mute 2 seconds */
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, period);
rt_thread_mdelay(2000);
}
rt_pwm_disable(pwm_dev, PWM_DEV_CHANNEL);
}
else
{
rt_kprintf("Can't find %s\n", PWM_DEV_NAME);
}
}
#if defined(BOARD_USING_LCM)
#if defined(PKG_USING_GUIENGINE)
#include <rtgui/driver.h>
#endif
#if defined(RT_USING_PIN)
#include <drv_gpio.h>
/* defined the LCM_BLEN pin: PH3 */
#define LCM_BLEN NU_GET_PININDEX(NU_PH, 3)
#endif
#define PWM_DEV_NAME "pwm0"
#define LCM_PWM_CHANNEL (0)
static void LCMLightOn(void)
{
struct rt_device_pwm *pwm_dev;
if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME)) != RT_NULL)
{
rt_pwm_enable(pwm_dev, LCM_PWM_CHANNEL);
rt_pwm_set(pwm_dev, LCM_PWM_CHANNEL, 100000, 100);
}
else
{
rt_kprintf("Can't find %s\n", PWM_DEV_NAME);
}
}
#ifdef FINSH_USING_MSH
MSH_CMD_EXPORT(LCMLightOn, LCM - light on panel);
#endif
int rt_hw_lcm_port(void)
{
#if defined(PKG_USING_GUIENGINE)
rt_device_t lcm_vpost;
lcm_vpost = rt_device_find("lcd");
if (lcm_vpost)
{
rtgui_graphic_set_device(lcm_vpost);
}
#endif
#if defined(RT_USING_PIN)
/* set LCM_BLEN pin mode to output */
rt_pin_mode(LCM_BLEN, PIN_MODE_OUTPUT);
rt_pin_write(LCM_BLEN, PIN_HIGH);
#endif
LCMLightOn();
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_lcm_port);
#endif /* BOARD_USING_LCM */
int buzzer_test(void)
{
PlayRingTone();
return 0;
}
#ifdef FINSH_USING_MSH
MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone);
#endif
#endif /* BOARD_USING_BUZZER */
#if defined(BOARD_USING_RS485)
#include <drv_uart.h>
int test_rs485(int argc, char **argv)
{
rt_device_t serial;
char txbuf[16];
rt_err_t ret;
int str_len;
if (argc < 2)
goto exit_test_rs485;
serial = rt_device_find(argv[1]);
if (!serial)
{
rt_kprintf("Can't find %s. EXIT.\n", argv[1]);
goto exit_test_rs485;
}
/* Interrupt RX */
ret = rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
RT_ASSERT(ret == RT_EOK);
/* Nuvoton private command */
nu_uart_set_rs485aud((struct rt_serial_device *)serial, RT_FALSE);
rt_snprintf(&txbuf[0], sizeof(txbuf), "Hello World!\r\n");
str_len = rt_strlen(txbuf);
/* Say Hello */
ret = rt_device_write(serial, 0, &txbuf[0], str_len);
RT_ASSERT(ret == str_len);
ret = rt_device_close(serial);
RT_ASSERT(ret == RT_EOK);
return 0;
exit_test_rs485:
return -1;
}
MSH_CMD_EXPORT(test_rs485, test rs485 communication);
#endif //defined(BOARD_USING_RS485)

46
bsp/nuvoton/nk-n9h30/board/fal_cfg.h Normal file
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/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-3-03 FYChou First version
*
******************************************************************************/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtconfig.h>
#include <board.h>
/* ===================== Flash device Configuration ========================= */
#if defined(RT_USING_SFUD)
extern struct fal_flash_dev nor_flash0;
/* -flash device table------------------------------------------------------- */
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
}
#else
#define FAL_FLASH_DEV_TABLE \
{ \
0 \
}
#endif
/* ====================== Partition Configuration ============================ */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table------------------------------------------------------------ */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "rtthread", FAL_USING_NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "filesystem", FAL_USING_NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

155
bsp/nuvoton/nk-n9h30/board/nu_pin_init.c Normal file
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/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-12 Wayne First version
*
******************************************************************************/
#include "board.h"
static void nu_pin_uart_init(void)
{
/* UART0: PE[0, 1] */
outpw(REG_SYS_GPE_MFPL, (inpw(REG_SYS_GPE_MFPL) & 0xffffff00) | 0x00000099);
/* UART1: PH[4, 7] */
outpw(REG_SYS_GPH_MFPL, (inpw(REG_SYS_GPH_MFPL) & 0x0000ffff) | 0x99990000);
/* UART2: PF[11, 14] */
outpw(REG_SYS_GPF_MFPH, (inpw(REG_SYS_GPF_MFPH) & 0xf0000fff) | 0x09999000);
/* UART3: PE[12, 13] */
outpw(REG_SYS_GPE_MFPH, (inpw(REG_SYS_GPE_MFPH) & 0xff00ffff) | 0x00990000);
/* UART4: PH[8, 11] */
outpw(REG_SYS_GPH_MFPH, (inpw(REG_SYS_GPH_MFPH) & 0xffff0000) | 0x00009999);
/* UART5: PB[0, 1] */
outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & 0xffffff00) | 0x00000099);
/* UART7: PI[1, 2] */
outpw(REG_SYS_GPI_MFPL, (inpw(REG_SYS_GPI_MFPL) & 0xfffff00f) | 0x00000990);
/* UART8: PH[12, 15] */
outpw(REG_SYS_GPH_MFPH, (inpw(REG_SYS_GPH_MFPH) & 0x0000ffff) | 0x99990000);
/* UART10: PB[12, 15] */
outpw(REG_SYS_GPB_MFPH, (inpw(REG_SYS_GPB_MFPH) & 0x0000ffff) | 0x99990000);
}
static void nu_pin_emac_init(void)
{
/* EMAC0: PF[0, 9] */
outpw(REG_SYS_GPF_MFPL, 0x11111111);
outpw(REG_SYS_GPF_MFPH, (inpw(REG_SYS_GPF_MFPH) & 0xffffff00) | 0x00000011);
/* EMAC1: PE[2, 11] */
outpw(REG_SYS_GPE_MFPL, (inpw(REG_SYS_GPE_MFPL) & 0x000000ff) | 0x11111100);
outpw(REG_SYS_GPE_MFPH, (inpw(REG_SYS_GPE_MFPH) & 0xffff0000) | 0x00001111);
}
static void nu_pin_sdh_init(void)
{
/* SDH0: PD[0, 6] */
outpw(REG_SYS_GPD_MFPL, (inpw(REG_SYS_GPD_MFPL) & 0xf0000000) | 0x06666666);
}
static void nu_pin_spi_init(void)
{
/* QSPI0: PB[6, 11] */
outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & 0x00ffffff) | 0xbb000000);
outpw(REG_SYS_GPB_MFPH, (inpw(REG_SYS_GPB_MFPH) & 0xffff0000) | 0x0000bbbb);
}
static void nu_pin_i2c_init(void)
{
/* I2C0: PG[0, 1] */
outpw(REG_SYS_GPG_MFPL, (inpw(REG_SYS_GPG_MFPL) & 0xffffff00) | 0x00000088);
/* I2C1: PG[2, 3] */
outpw(REG_SYS_GPG_MFPL, (inpw(REG_SYS_GPG_MFPL) & 0xffff00ff) | 0x00008800);
}
static void nu_pin_pwm_init(void)
{
/* PWM0: PB2, LCD_PWM */
outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & 0xfffff0ff) | 0x00000d00);
/* PWM1: PB3, Buzzer */
outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & 0xffff0fff) | 0x0000d000);
}
static void nu_pin_i2s_init(void)
{
/* I2S: PG[10, 14] */
outpw(REG_SYS_GPG_MFPH, (inpw(REG_SYS_GPG_MFPH) & 0xf00000ff) | 0x08888800);
}
static void nu_pin_can_init(void)
{
/* CAN0: PI[3, 4] */
outpw(REG_SYS_GPI_MFPL, (inpw(REG_SYS_GPI_MFPL) & 0xfff00fff) | 0x000cc000);
}
static void nu_pin_usbd_init(void)
{
/* USB0_VBUSVLD, PH0 */
outpw(REG_SYS_GPH_MFPL, (inpw(REG_SYS_GPH_MFPL) & 0xfffffff0) | 0x00000007);
}
static void nu_pin_vpost_init(void)
{
/* CLK: PG6, HSYNC: PG7 */
outpw(REG_SYS_GPG_MFPL, (inpw(REG_SYS_GPG_MFPL) & 0x00ffffff) | 0x22000000);
/* VSYNC: PG8, DEN: PG9 */
outpw(REG_SYS_GPG_MFPH, (inpw(REG_SYS_GPG_MFPH) & 0xffffff00) | 0x00000022);
/* DATA pin: 24bit RGB */
/* PA[0, 7] */
outpw(REG_SYS_GPA_MFPL, 0x22222222);
/* PA[8, 15] */
outpw(REG_SYS_GPA_MFPH, 0x22222222);
#if (LCM_USING_BPP==4)
/* PD[8, 15 ] */
outpw(REG_SYS_GPD_MFPH, 0x22222222);
#endif
}
static void nu_pin_fmi_init(void)
{
/* NAND: PC[0, 14] */
outpw(REG_SYS_GPC_MFPL, 0x55555555);
outpw(REG_SYS_GPC_MFPH, 0x05555555);
}
static void nu_pin_usbh_init(void)
{
}
void nu_pin_init(void)
{
nu_pin_uart_init();
nu_pin_emac_init();
nu_pin_sdh_init();
nu_pin_spi_init();
nu_pin_i2c_init();
nu_pin_pwm_init();
nu_pin_i2s_init();
nu_pin_can_init();
nu_pin_vpost_init();
nu_pin_fmi_init();
nu_pin_usbd_init();
nu_pin_usbh_init();
}
void nu_pin_deinit(void)
{
}

111
bsp/nuvoton/nk-n9h30/linking_scripts/n9h30.ld Normal file
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(system_vectors)
MEMORY
{
RAM (rwx) : ORIGIN = 0x000000, LENGTH = 0x04000000
}
SECTIONS
{
. = 0x0;
. = ALIGN(4);
.text :
{
*(.vectors)
*(.text)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(4);
}
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
__bss_start__ = .;
__bss_start = .;
.bss : { *(.bss)}
. = ALIGN(4);
__bss_end = .;
__bss_end__ = .;
. = ALIGN(4);
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_end = .;
}

11
bsp/nuvoton/nk-n9h30/linking_scripts/n9h30.sct Normal file
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LR_IROM1 0x00000000 0x800000 { ; load region size_region
ER_IROM1 0x00000000 0x800000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_RAM1 +0 { ; RW_RAM1 start address is after ER_ROM1
.ANY (+RW +ZI)
}
}

88
bsp/nuvoton/nk-n9h30/rtconfig.py Normal file
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import os
# toolchains options
ARCH = 'arm'
CPU = 'arm926'
# toolchains options
CROSS_TOOL = 'gcc'
#------- toolchains path -------------------------------------------------------
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:\Keil_v5'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
CORE = 'arm926ej-s'
MAP_FILE = 'rtthread_n9h30.map'
LINK_FILE = 'linking_scripts/n9h30'
TARGET_NAME = 'rtthread.bin'
#------- GCC settings ----------------------------------------------------------
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=arm926ej-s'
CFLAGS = DEVICE
AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
AFLAGS += ' -Iplatform'
LFLAGS = DEVICE
LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
LFLAGS += ' -T ' + LINK_FILE + '.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O0'
POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
POST_ACTION += SIZE + ' $TARGET\n'
#------- Keil settings ---------------------------------------------------------
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
EXEC_PATH += '/arm/armcc/bin/'
DEVICE = ' --cpu=' + CORE
CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
AFLAGS = DEVICE + ' -Iplatform'
LFLAGS = DEVICE + ' --strict'
LFLAGS += ' --info sizes --info totals --info unused --info veneers'
LFLAGS += ' --list ' + MAP_FILE
LFLAGS += ' --scatter ' + LINK_FILE + '.sct'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
POST_ACTION += 'fromelf -z $TARGET\n'

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bsp/nuvoton/nk-n9h30/template.uvproj Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>Nuvoton_ARM9_Series</Device>
<Vendor>Nuvoton</Vendor>
<Cpu></Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>Atmel\SAM9260\</RegisterFilePath>
<DBRegisterFilePath>Atmel\SAM9260\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cAT91SAM9</SimDllArguments>
<SimDlgDll>DARMATS9.DLL</SimDlgDll>
<SimDlgDllArguments>-p91SAM9260</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMATS9.DLL</TargetDlgDll>
<TargetDlgDllArguments>-p91SAM9260</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>0</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>6</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>..\libraries\nuc980\Script\NUC980xx61.ini</InitializationFile>
<Driver>Segger\JLTAgdi.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4098</DriverSelection>
</Flash1>
<bUseTDR>0</bUseTDR>
<Flash2>Segger\JLTAgdi.dll</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType></AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x200000</StartAddress>
<Size>0x1000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x100000</StartAddress>
<Size>0x8000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>3</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls>--c99</MiscControls>
<Define>RT_USING_INTERRUPT_INFO</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x20000000</TextAddressRange>
<DataAddressRange>0x20800000</DataAddressRange>
<ScatterFile>.\linking_scripts\n9h30.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
</Project>

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bsp/nuvoton/nk-n9h30/template.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>Nuvoton_ARM9_Series</Device>
<Vendor>Nuvoton</Vendor>
<Cpu></Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>Atmel\SAM9260\</RegisterFilePath>
<DBRegisterFilePath>Atmel\SAM9260\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil5\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\keil5\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin --output "$L@L.bin" "$L@L.axf"</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cAT91SAM9260</SimDllArguments>
<SimDlgDll>DARMATS9.DLL</SimDlgDll>
<SimDlgDllArguments>-p91SAM9260</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMATS9.DLL</TargetDlgDll>
<TargetDlgDllArguments>-p91SAM9260</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4098</DriverSelection>
</Flash1>
<bUseTDR>0</bUseTDR>
<Flash2>Segger\JLTAgdi.dll</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>ARM926EJ-S</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
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<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x200000</StartAddress>
<Size>0x1000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x100000</StartAddress>
<Size>0x8000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x800000</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x100000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x20800000</StartAddress>
<Size>0x1800000</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x200000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x300000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--c99</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x20000000</TextAddressRange>
<DataAddressRange>0x20800000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\linking_scripts\n9h30.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>

9
bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.ld
View File

@ -23,18 +23,14 @@ SECTIONS
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
@ -54,6 +50,7 @@ SECTIONS
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(4);
}
. = ALIGN(4);

10
bsp/nuvoton/numaker-m2354/Nu_Link_Driver.ini
View File

@ -1,12 +1,12 @@
[Version]
Nu_LinkVersion=V5.14
[Process]
ProcessID=0x00003fc4
ProcessCreationTime_L=0xfa4b822c
ProcessCreationTime_H=0x01d6fb6d
NuLinkID=0x1800002d
ProcessID=0x00009908
ProcessCreationTime_L=0xda6c5f90
ProcessCreationTime_H=0x01d74571
NuLinkID=0x1800003c
NuLinkIDs_Count=0x00000001
NuLinkID0=0x1800002d
NuLinkID0=0x1800003c
[ChipSelect]
;ChipName=<NUC1xx|NUC2xx|M05x|N571|N572|Nano100|N512|Mini51|NUC505|General>
ChipName=M2354