diff --git a/bsp/at32/at32a403a-start/README.md b/bsp/at32/at32a403a-start/README.md index dfe372c1f1..5345b000e1 100644 --- a/bsp/at32/at32a403a-start/README.md +++ b/bsp/at32/at32a403a-start/README.md @@ -41,6 +41,7 @@ AT32A403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32a403a-start/board/Kconfig b/bsp/at32/at32a403a-start/board/Kconfig index 6663e58a41..018b0815bc 100644 --- a/bsp/at32/at32a403a-start/board/Kconfig +++ b/bsp/at32/at32a403a-start/board/Kconfig @@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32a403a-start/board/src/at32_msp.c b/bsp/at32/at32a403a-start/board/src/at32_msp.c index eedc7cc834..7011c578d2 100644 --- a/bsp/at32/at32a403a-start/board/src/at32_msp.c +++ b/bsp/at32/at32a403a-start/board/src/at32_msp.c @@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32a423-start/README.md b/bsp/at32/at32a423-start/README.md index dff31e6b10..069560c7dc 100644 --- a/bsp/at32/at32a423-start/README.md +++ b/bsp/at32/at32a423-start/README.md @@ -41,6 +41,7 @@ AT32A423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF10 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32a423-start/board/Kconfig b/bsp/at32/at32a423-start/board/Kconfig index 4fec6bd8a7..ea24f1513f 100644 --- a/bsp/at32/at32a423-start/board/Kconfig +++ b/bsp/at32/at32a423-start/board/Kconfig @@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32a423-start/board/inc/at32_msp.h b/bsp/at32/at32a423-start/board/inc/at32_msp.h index d53871331d..af1060a15d 100644 --- a/bsp/at32/at32a423-start/board/inc/at32_msp.h +++ b/bsp/at32/at32a423-start/board/inc/at32_msp.h @@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance); void at32_msp_can_init(void *instance); void at32_msp_usb_init(void *instance); void at32_msp_dac_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32a423-start/board/src/at32_msp.c b/bsp/at32/at32a423-start/board/src/at32_msp.c index e5898985dc..3a81f5585c 100644 --- a/bsp/at32/at32a423-start/board/src/at32_msp.c +++ b/bsp/at32/at32a423-start/board/src/at32_msp.c @@ -134,6 +134,68 @@ void at32_msp_spi_init(void *instance) /* add others */ } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) diff --git a/bsp/at32/at32f402-start/README.md b/bsp/at32/at32f402-start/README.md index 0d45c5a80a..9f052ed24a 100644 --- a/bsp/at32/at32f402-start/README.md +++ b/bsp/at32/at32f402-start/README.md @@ -41,6 +41,7 @@ AT32F402-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f402-start/board/Kconfig b/bsp/at32/at32f402-start/board/Kconfig index 30446e35a0..b83b21f261 100644 --- a/bsp/at32/at32f402-start/board/Kconfig +++ b/bsp/at32/at32f402-start/board/Kconfig @@ -288,6 +288,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f402-start/board/src/at32_msp.c b/bsp/at32/at32f402-start/board/src/at32_msp.c index 711a9e8bab..9afbb74cfc 100644 --- a/bsp/at32/at32f402-start/board/src/at32_msp.c +++ b/bsp/at32/at32f402-start/board/src/at32_msp.c @@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f403a-start/README.md b/bsp/at32/at32f403a-start/README.md index f46ec9ab29..3b469c3394 100644 --- a/bsp/at32/at32f403a-start/README.md +++ b/bsp/at32/at32f403a-start/README.md @@ -41,6 +41,7 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f403a-start/board/Kconfig b/bsp/at32/at32f403a-start/board/Kconfig index f3c913d3dc..b0dade514b 100644 --- a/bsp/at32/at32f403a-start/board/Kconfig +++ b/bsp/at32/at32f403a-start/board/Kconfig @@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f403a-start/board/src/at32_msp.c b/bsp/at32/at32f403a-start/board/src/at32_msp.c index 979afdfe66..848ff32cdd 100644 --- a/bsp/at32/at32f403a-start/board/src/at32_msp.c +++ b/bsp/at32/at32f403a-start/board/src/at32_msp.c @@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f405-start/README.md b/bsp/at32/at32f405-start/README.md index 888952cca5..957f63b6ab 100644 --- a/bsp/at32/at32f405-start/README.md +++ b/bsp/at32/at32f405-start/README.md @@ -41,6 +41,7 @@ AT32F405-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f405-start/board/Kconfig b/bsp/at32/at32f405-start/board/Kconfig index f6a196f4e0..5de191fc0f 100644 --- a/bsp/at32/at32f405-start/board/Kconfig +++ b/bsp/at32/at32f405-start/board/Kconfig @@ -307,6 +307,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f405-start/board/src/at32_msp.c b/bsp/at32/at32f405-start/board/src/at32_msp.c index 4ece05a5a5..da12e07a50 100644 --- a/bsp/at32/at32f405-start/board/src/at32_msp.c +++ b/bsp/at32/at32f405-start/board/src/at32_msp.c @@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f407-start/README.md b/bsp/at32/at32f407-start/README.md index 56d9206892..f255f93f44 100644 --- a/bsp/at32/at32f407-start/README.md +++ b/bsp/at32/at32f407-start/README.md @@ -41,6 +41,7 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f407-start/board/Kconfig b/bsp/at32/at32f407-start/board/Kconfig index 78d5ae066a..1032819de2 100644 --- a/bsp/at32/at32f407-start/board/Kconfig +++ b/bsp/at32/at32f407-start/board/Kconfig @@ -282,6 +282,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f407-start/board/src/at32_msp.c b/bsp/at32/at32f407-start/board/src/at32_msp.c index 23ea2a937b..63ef0c2dee 100644 --- a/bsp/at32/at32f407-start/board/src/at32_msp.c +++ b/bsp/at32/at32f407-start/board/src/at32_msp.c @@ -131,6 +131,60 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f413-start/README.md b/bsp/at32/at32f413-start/README.md index d8bfd68310..5042036452 100644 --- a/bsp/at32/at32f413-start/README.md +++ b/bsp/at32/at32f413-start/README.md @@ -41,6 +41,7 @@ AT32F413-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF5 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f413-start/board/Kconfig b/bsp/at32/at32f413-start/board/Kconfig index b184fd5e38..19b148f6f8 100644 --- a/bsp/at32/at32f413-start/board/Kconfig +++ b/bsp/at32/at32f413-start/board/Kconfig @@ -253,6 +253,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f413-start/board/src/at32_msp.c b/bsp/at32/at32f413-start/board/src/at32_msp.c index a2e137a632..fc0498c408 100644 --- a/bsp/at32/at32f413-start/board/src/at32_msp.c +++ b/bsp/at32/at32f413-start/board/src/at32_msp.c @@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f415-start/README.md b/bsp/at32/at32f415-start/README.md index 2727ce40b4..3201f54c59 100644 --- a/bsp/at32/at32f415-start/README.md +++ b/bsp/at32/at32f415-start/README.md @@ -41,6 +41,7 @@ AT32F415-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF5 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f415-start/board/Kconfig b/bsp/at32/at32f415-start/board/Kconfig index 57d365d634..e7861dc72d 100644 --- a/bsp/at32/at32f415-start/board/Kconfig +++ b/bsp/at32/at32f415-start/board/Kconfig @@ -268,6 +268,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f415-start/board/src/at32_msp.c b/bsp/at32/at32f415-start/board/src/at32_msp.c index 5fc183eaa7..64db65da7a 100644 --- a/bsp/at32/at32f415-start/board/src/at32_msp.c +++ b/bsp/at32/at32f415-start/board/src/at32_msp.c @@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f421-start/README.md b/bsp/at32/at32f421-start/README.md index 80ceadbfa2..d8b987553c 100644 --- a/bsp/at32/at32f421-start/README.md +++ b/bsp/at32/at32f421-start/README.md @@ -41,6 +41,7 @@ AT32F421-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1 | diff --git a/bsp/at32/at32f421-start/board/Kconfig b/bsp/at32/at32f421-start/board/Kconfig index 85b3a545e6..16abb90011 100644 --- a/bsp/at32/at32f421-start/board/Kconfig +++ b/bsp/at32/at32f421-start/board/Kconfig @@ -203,6 +203,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f421-start/board/inc/at32_msp.h b/bsp/at32/at32f421-start/board/inc/at32_msp.h index a5bb12535b..69de853e72 100644 --- a/bsp/at32/at32f421-start/board/inc/at32_msp.h +++ b/bsp/at32/at32f421-start/board/inc/at32_msp.h @@ -16,5 +16,6 @@ void at32_msp_spi_init(void *instance); void at32_msp_tmr_init(void *instance); void at32_msp_adc_init(void *instance); void at32_msp_hwtmr_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f421-start/board/src/at32_msp.c b/bsp/at32/at32f421-start/board/src/at32_msp.c index e321e050b8..a5221a799d 100644 --- a/bsp/at32/at32f421-start/board/src/at32_msp.c +++ b/bsp/at32/at32f421-start/board/src/at32_msp.c @@ -116,6 +116,50 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f423-start/README.md b/bsp/at32/at32f423-start/README.md index cf029f9a09..c574adbca5 100644 --- a/bsp/at32/at32f423-start/README.md +++ b/bsp/at32/at32f423-start/README.md @@ -41,6 +41,7 @@ AT32F423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF10 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f423-start/board/Kconfig b/bsp/at32/at32f423-start/board/Kconfig index 2f3caa16f6..13d3a8b173 100644 --- a/bsp/at32/at32f423-start/board/Kconfig +++ b/bsp/at32/at32f423-start/board/Kconfig @@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f423-start/board/inc/at32_msp.h b/bsp/at32/at32f423-start/board/inc/at32_msp.h index fad72d455c..e072121a29 100644 --- a/bsp/at32/at32f423-start/board/inc/at32_msp.h +++ b/bsp/at32/at32f423-start/board/inc/at32_msp.h @@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance); void at32_msp_can_init(void *instance); void at32_msp_usb_init(void *instance); void at32_msp_dac_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f423-start/board/src/at32_msp.c b/bsp/at32/at32f423-start/board/src/at32_msp.c index e109cede2b..396e8622e8 100644 --- a/bsp/at32/at32f423-start/board/src/at32_msp.c +++ b/bsp/at32/at32f423-start/board/src/at32_msp.c @@ -135,6 +135,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f425-start/README.md b/bsp/at32/at32f425-start/README.md index d03cd087fe..46cdceda87 100644 --- a/bsp/at32/at32f425-start/README.md +++ b/bsp/at32/at32f425-start/README.md @@ -41,6 +41,7 @@ AT32F425-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f425-start/board/Kconfig b/bsp/at32/at32f425-start/board/Kconfig index 7937f438d2..4a517ac6f5 100644 --- a/bsp/at32/at32f425-start/board/Kconfig +++ b/bsp/at32/at32f425-start/board/Kconfig @@ -277,6 +277,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f425-start/board/inc/at32_msp.h b/bsp/at32/at32f425-start/board/inc/at32_msp.h index c2eb468175..c002259b47 100644 --- a/bsp/at32/at32f425-start/board/inc/at32_msp.h +++ b/bsp/at32/at32f425-start/board/inc/at32_msp.h @@ -18,5 +18,6 @@ void at32_msp_adc_init(void *instance); void at32_msp_hwtmr_init(void *instance); void at32_msp_can_init(void *instance); void at32_msp_usb_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f425-start/board/src/at32_msp.c b/bsp/at32/at32f425-start/board/src/at32_msp.c index 1c781af19f..4f0ba76955 100644 --- a/bsp/at32/at32f425-start/board/src/at32_msp.c +++ b/bsp/at32/at32f425-start/board/src/at32_msp.c @@ -135,6 +135,50 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f435-start/README.md b/bsp/at32/at32f435-start/README.md index 4217a3ba91..3dae129767 100644 --- a/bsp/at32/at32f435-start/README.md +++ b/bsp/at32/at32f435-start/README.md @@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PH7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f435-start/board/Kconfig b/bsp/at32/at32f435-start/board/Kconfig index 4c245df038..828d66eba4 100644 --- a/bsp/at32/at32f435-start/board/Kconfig +++ b/bsp/at32/at32f435-start/board/Kconfig @@ -314,6 +314,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f435-start/board/src/at32_msp.c b/bsp/at32/at32f435-start/board/src/at32_msp.c index 056ae2266e..dcd558ae8c 100644 --- a/bsp/at32/at32f435-start/board/src/at32_msp.c +++ b/bsp/at32/at32f435-start/board/src/at32_msp.c @@ -126,6 +126,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f437-start/README.md b/bsp/at32/at32f437-start/README.md index 8e43ada974..6ce3bfa7ab 100644 --- a/bsp/at32/at32f437-start/README.md +++ b/bsp/at32/at32f437-start/README.md @@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PH7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f437-start/board/Kconfig b/bsp/at32/at32f437-start/board/Kconfig index 9a9e889270..8dc22159dd 100644 --- a/bsp/at32/at32f437-start/board/Kconfig +++ b/bsp/at32/at32f437-start/board/Kconfig @@ -331,6 +331,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f437-start/board/src/at32_msp.c b/bsp/at32/at32f437-start/board/src/at32_msp.c index 45f8049b16..1a22f367f1 100644 --- a/bsp/at32/at32f437-start/board/src/at32_msp.c +++ b/bsp/at32/at32f437-start/board/src/at32_msp.c @@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/libraries/.ignore_format.yml b/bsp/at32/libraries/.ignore_format.yml new file mode 100644 index 0000000000..43e3e13167 --- /dev/null +++ b/bsp/at32/libraries/.ignore_format.yml @@ -0,0 +1,15 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- AT32A403A_Firmware_Library +- AT32A423_Firmware_Library +- AT32F402_405_Firmware_Library +- AT32F403A_407_Firmware_Library +- AT32F413_Firmware_Library +- AT32F415_Firmware_Library +- AT32F421_Firmware_Library +- AT32F423_Firmware_Library +- AT32F425_Firmware_Library +- AT32F435_437_Firmware_Library \ No newline at end of file diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c index 3ae8ffef98..c5c1fb82e5 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c @@ -179,6 +179,50 @@ void system_core_clock_update(void) system_core_clock = system_core_clock >> div_value; } +/** + * @brief reduce power consumption initialize + * If OTGHS is not used, call this function to reduce power consumption. + * PLL or HEXT should be enabled when calling this function. + * + * If OTGHS is required, initialize OTGHS to reduce power consumption, + * without the need to call this function. + * @param none + * @retval none + */ +void reduce_power_consumption(void) +{ + volatile uint32_t delay = 0x34BC0; + if(CRM->ctrl_bit.hextstbl) + { + *(__IO uint32_t *)0x40023878 = 0x00; + } + else if(CRM->ctrl_bit.pllstbl == SET) + { + CRM->pllcfg_bit.plluen = TRUE; + while(CRM->ctrl_bit.pllstbl != SET || CRM->ctrl_bit.pllustbl != SET); + *(__IO uint32_t *)0x40023878 = 0x10; + } + else + { + /* the pll or hext need to be enable */ + return; + } + CRM->ahben1 |= 1 << 29; + *(__IO uint32_t *)0x40040038 = 0x210000; + *(__IO uint32_t *)0x4004000C |= 0x40000000; + *(__IO uint32_t *)0x40040804 &= ~0x2; + while(delay --) + { + if(*(__IO uint32_t *)0x40040808 & 0x1) + break; + } + *(__IO uint32_t *)0x40040038 |= 0x400000; + *(__IO uint32_t *)0x40040E00 |= 0x1; + *(__IO uint32_t *)0x40040038 &= ~0x10000; + *(__IO uint32_t *)0x40023878 = 0x0; + return; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h index 505accc409..f215decd4f 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h @@ -52,6 +52,7 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock) extern void SystemInit(void); extern void system_core_clock_update(void); +extern void reduce_power_consumption(void); /** * @} diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h index fca7522003..7dbca2ca4e 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h @@ -178,6 +178,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h index 40464531d8..bcf387e511 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h @@ -1,7 +1,7 @@ /** ************************************************************************** - * @file at32f425_adc.h - * @brief at32f425 adc header file + * @file at32f402_405_adc.h + * @brief at32f402_405 adc header file ************************************************************************** * Copyright notice & Disclaimer * @@ -34,7 +34,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "at32f402_405.h" -/** @addtogroup AT32F425_periph_driver +/** @addtogroup AT32F402_405_periph_driver * @{ */ @@ -688,6 +688,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h index 395d84c89e..9bd92caae5 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h @@ -1018,6 +1018,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h index dc3faacc58..8eee924b5d 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h @@ -461,8 +461,7 @@ typedef enum CRM_CLKOUT_ADC = 0x11, /*!< output adcclk to clkout pin */ CRM_CLKOUT_HICK = 0x12, /*!< output high speed internal clock to clkout pin */ CRM_CLKOUT_LICK = 0x13, /*!< output low speed internal clock to clkout pin */ - CRM_CLKOUT_LEXT = 0x14, /*!< output low speed external crystal to clkout pin */ - CRM_CLKOUT_USBHS = 0x15 /*!< output usbhsclk to clkout pin */ + CRM_CLKOUT_LEXT = 0x14 /*!< output low speed external crystal to clkout pin */ } crm_clkout_select_type; /** @@ -1179,6 +1178,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h index 85d2b984c6..954ef3d3aa 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h @@ -113,6 +113,7 @@ typedef struct __IO uint32_t reserved1 : 29;/* [31:3] */ } ctrl_bit; }; + /** * @brief debug apb1 frz register, offset:0x08 */ @@ -145,8 +146,9 @@ typedef struct __IO uint32_t reserved6 : 3;/* [31:29] */ } apb1_frz_bit; }; + /** - * @brief debug apb2 frz register, offset:0x0c + * @brief debug apb2 frz register, offset:0x0C */ union { @@ -163,6 +165,26 @@ typedef struct } apb2_frz_bit; }; + /** + * @brief debug reserved1 register, offset:0x10~0x1C + */ + __IO uint32_t reserved1[4]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h index 71c95cd74b..59cf7e41d7 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h @@ -727,6 +727,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely); void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type *dma_init_struct); void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct); @@ -742,8 +743,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state); void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state); flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag); flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h index 0d17d6f7a9..a2e1a4a6da 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h @@ -1174,6 +1174,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h index 9a428982da..3171859d7c 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h @@ -209,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h index 36263c2c3e..bed3ed62d8 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h @@ -155,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -456,6 +456,7 @@ void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h index f42000a802..10887dfecb 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h @@ -126,8 +126,7 @@ typedef enum typedef enum { PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */ - PWC_REGULATOR_LOW_POWER = 0x01, /*!< voltage regulator state low power when deepsleep mode */ - PWC_REGULATOR_EXTRA_LOW_POWER = 0x02 /*!< voltage regulator state extra low power when deepsleep mode */ + PWC_REGULATOR_EXTRA_LOW_POWER = 0x01 /*!< voltage regulator state extra low power when deepsleep mode */ } pwc_regulator_type ; /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h index 9f87cfbe53..5350ff2e30 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h @@ -121,11 +121,11 @@ typedef enum typedef enum { QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */ + QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */ + QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */ - QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ - QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */ } qspi_clk_div_type; @@ -177,7 +177,7 @@ typedef enum { QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */ - QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */ + QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */ } qspi_dma_fifo_thod_type; /** @@ -185,7 +185,7 @@ typedef enum */ typedef struct { - confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */ + confirm_state pe_mode_enable; /*!< performance enhance mode enable */ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */ uint8_t instruction_code; /*!< instruction code */ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */ @@ -458,9 +458,23 @@ typedef struct }; /** - * @brief qspi reserved register, offset:0x40~4C + * @brief qspi ctrl3 register, offset:0x40 */ - __IO uint32_t reserved2[4]; + union + { + __IO uint32_t ctrl3; + struct + { + __IO uint32_t reserved1 : 8; /* [7:0] */ + __IO uint32_t ispc : 1; /* [8] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ + } ctrl3_bit; + }; + + /** + * @brief qspi reserved register, offset:0x44~4C + */ + __IO uint32_t reserved2[3]; /** * @brief qspi rev register, offset:0x50 @@ -505,13 +519,15 @@ typedef struct * @{ */ +void qspi_reset(qspi_type* qspi_x); void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state); -void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode); +void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode); void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv); void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state); void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state); flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag); -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag); +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag); +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag); void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state); @@ -525,6 +541,7 @@ uint32_t qspi_word_read(qspi_type* qspi_x); void qspi_word_write(qspi_type* qspi_x, uint32_t value); void qspi_half_word_write(qspi_type* qspi_x, uint16_t value); void qspi_byte_write(qspi_type* qspi_x, uint8_t value); +void qspi_auto_ispc_enable(qspi_type* qspi_x); /** * @} */ diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h index a4e5241088..a76d70ef41 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h @@ -55,8 +55,6 @@ extern "C" { typedef enum { SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ } scfg_ir_source_type; /** @@ -277,7 +275,7 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola scfg_mem_map_type scfg_mem_map_get(void); void scfg_i2s_full_duplex_config(scfg_i2s_type i2s_full_duplex); void scfg_pvm_lock_enable(confirm_state new_state); -error_status scfg_sram_operr_status_get(void); +flag_status scfg_sram_operr_status_get(void); void scfg_sram_operr_lock_enable(confirm_state new_state); void scfg_lockup_enable(confirm_state new_state); void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h index 20a5e636fc..18bc75bd0d 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h @@ -508,6 +508,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); void i2sf_full_duplex_mode_enable(spi_type* spi_x, confirm_state new_state); void i2sf_pcm_sample_clock_set(spi_type* spi_x, i2s_pcm_sample_clock_type pcm_sample_clock); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h index 24f03f9ee2..4f12194237 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h @@ -444,7 +444,6 @@ typedef struct */ typedef struct { - uint8_t brk_filter_value; /*!< tmr brake filter value */ uint8_t deadtime; /*!< dead-time generator setup */ tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */ tmr_wp_level_type wp_level; /*!< write protect configuration */ @@ -972,6 +971,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); @@ -993,6 +993,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \ tmr_dma_address_type dma_base_address); void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct); +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value); void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h index b5a738f8b4..df2612e9bf 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h @@ -184,6 +184,15 @@ typedef enum USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */ } usart_identification_bit_num_type; +/** + * @brief usart de polarity type + */ +typedef enum +{ + USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */ + USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */ +} usart_de_polarity_type; + /** * @brief type define usart register all */ @@ -418,11 +427,12 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num); -void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state); +void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity); void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state); void usart_dt_polarity_reverse(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h index 1cecfd0a31..475ac0d8f0 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c index b5a5e20d13..33fa7fb78a 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c @@ -188,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c index 1a3a9f1a72..be97d94305 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c @@ -799,10 +799,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -857,6 +857,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c index ec3a3544b0..3de82fa09a 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c @@ -928,6 +928,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c index 1119b212d8..e2527a4a77 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c @@ -141,6 +141,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -871,7 +929,7 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) } /** - * @brief set crm clkout2 + * @brief set crm clkout * @param clkout * this parameter can be one of the following values: * - CRM_CLKOUT_SCLK @@ -882,7 +940,6 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) * - CRM_CLKOUT_HICK * - CRM_CLKOUT_LICK * - CRM_CLKOUT_LEXT - * - CRM_CLKOUT_USBHS * @retval none */ void crm_clock_out_set(crm_clkout_select_type clkout) @@ -899,7 +956,7 @@ void crm_clock_out_set(crm_clkout_select_type clkout) } /** - * @brief set crm clkout1 division1 + * @brief set crm clkout division1 * @param div1 * this parameter can be one of the following values: * - CRM_CLKOUT_DIV1_1 diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c index 05fb5afbce..792bd30ac2 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c @@ -197,6 +197,52 @@ void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state dmax_channely->ctrl_bit.chen = new_state; } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief dma flag get. * @param dma_flag @@ -599,6 +645,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux sync interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_SYNC_OV1_FLAG + * - DMAMUX_SYNC_OV2_FLAG + * - DMAMUX_SYNC_OV3_FLAG + * - DMAMUX_SYNC_OV4_FLAG + * - DMAMUX_SYNC_OV5_FLAG + * - DMAMUX_SYNC_OV6_FLAG + * - DMAMUX_SYNC_OV7_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + { + tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset)); + } + else + { + tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset)); + } + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + + if(dma_x == DMA1) + { + if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + /** * @brief dmamux sync flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. @@ -641,6 +759,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux request generator interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_GEN_TRIG_OV1_FLAG + * - DMAMUX_GEN_TRIG_OV2_FLAG + * - DMAMUX_GEN_TRIG_OV3_FLAG + * - DMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset)); + else + tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset)); + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + if(dma_x == DMA1) + { + if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + /** * @brief dmamux request generator flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c index 819469cc00..2c28a48091 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c @@ -1482,6 +1482,55 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * - ERTC_TP2F_FLAG: tamper detection 2 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + case ERTC_TP2F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c index 35ebe36125..4f520d0e8c 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c @@ -153,6 +153,36 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c index bf8bc31884..b6d4262ff6 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c @@ -536,7 +536,7 @@ flag_status flash_fap_high_level_status_get(void) } /** - * @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt. + * @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt / ram_prt_chk. * @param usd_ssb: the system setting byte * @note this parameter usd_ssb must contain a combination of all the following 6 types of data * type 1: wdt_ato_en, select the wdt auto start @@ -563,6 +563,10 @@ flag_status flash_fap_high_level_status_get(void) * this data can be one of the following values: * - USD_STDBY_WDT_CONTINUE: wdt continue count when entering in standby * - USD_STDBY_WDT_STOP: wdt stop count when entering in standby + * type 7: ram_prt_chk, ram parity check disable or enable. + * this data can be one of the following values: + * - USD_RAM_PRT_CHK_DISABLE: ram parity check disabled + * - USD_RAM_PRT_CHK_ENABLE: ram parity check enabled * @retval status: the returned value can be: FLASH_PROGRAM_ERROR, * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT. */ @@ -593,7 +597,7 @@ flash_status_type flash_ssb_set(uint8_t usd_ssb) * @brief return the flash system setting byte status. * @param none * @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1), - * stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5) and stdby_wdt(bit6). + * stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5), stdby_wdt(bit6) and ram_prt_chk(bit7). */ uint8_t flash_ssb_status_get(void) { diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c index 38cb5eb7d1..a446678985 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c @@ -120,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -706,6 +706,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c index e9426f4266..91244e188a 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c @@ -207,7 +207,6 @@ void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter) * @param pwc_regulator: set the regulator state. * this parameter can be one of the following values: * - PWC_REGULATOR_ON - * - PWC_REGULATOR_LOW_POWER * - PWC_REGULATOR_EXTRA_LOW_POWER * @retval none */ @@ -215,15 +214,11 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) { switch(pwc_regulator) { - case 0: + case PWC_REGULATOR_ON: PWC->ldoov_bit.vrexlpen = 0; PWC->ctrl_bit.vrsel = 0; break; - case 1: - PWC->ldoov_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 1; - break; - case 2: + case PWC_REGULATOR_EXTRA_LOW_POWER: PWC->ldoov_bit.vrexlpen = 1; PWC->ctrl_bit.vrsel = 1; break; @@ -242,7 +237,7 @@ void pwc_standby_mode_enter(void) PWC->ctrl_bit.clswef = TRUE; PWC->ctrl_bit.lpsel = TRUE; SCB->SCR |= 0x04; -#if defined (__CC_ARM) +#if defined (__ARMCC_VERSION) __force_stores(); #endif while(1) diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c index 8137509255..fb5d13b94c 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c @@ -39,6 +39,21 @@ * @{ */ +/** + * @brief deinitialize the qspi peripheral registers to their default reset values. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1. + * @retval none + */ +void qspi_reset(qspi_type* qspi_x) +{ + { + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE); + } +} + /** * @brief enable/disable encryption for qspi. * @note the function must be configured only when qspi in command-port mode!!! @@ -131,7 +146,7 @@ void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state) * - QSPI_RXFIFORDY_FLAG * - QSPI_TXFIFORDY_FLAG * - QSPI_CMDSTS_FLAG - * @retval the new state of usart_flag (SET or RESET). + * @retval the new state of the flag (SET or RESET). */ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) { @@ -153,6 +168,24 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) return bit_status; } +/** + * @brief get interrupt flags. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1. + * @param flag: only QSPI_CMDSTS_FLAG valid. + * @retval the new state of the flag (SET or RESET). + */ +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag) +{ + if(QSPI_CMDSTS_FLAG != flag) + return RESET; + if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie) + return SET; + else + return RESET; +} + /** * @brief clear flags * @param qspi_x: select the qspi peripheral. @@ -163,7 +196,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) * - QSPI_CMDSTS_FLAG * @retval none */ -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag) { qspi_x->cmdsts = QSPI_CMDSTS_FLAG; } @@ -178,7 +211,7 @@ void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -196,7 +229,7 @@ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_th * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -267,6 +300,7 @@ void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state) { __NOP(); } + /* flush and reset qspi state */ qspi_x->ctrl_bit.xiprcmdf = 1; @@ -425,6 +459,16 @@ void qspi_word_write(qspi_type* qspi_x, uint32_t value) qspi_x->dt = value; } +/** + * @brief enable auto input sampling phase correction + * @param qspi_x: select the qspi peripheral. + * @retval none. + */ +void qspi_auto_ispc_enable(qspi_type* qspi_x) +{ + qspi_x->ctrl3_bit.ispc = TRUE; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c index f01220b024..7ecdceccda 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE @@ -116,18 +114,11 @@ void scfg_pvm_lock_enable(confirm_state new_state) /** * @brief scfg sram odd parity error status get * @param none - * @retval return sram odd parity error status (ERROR or SUCCESS) + * @retval return sram odd parity error status(SET or RESET) */ -error_status scfg_sram_operr_status_get(void) +flag_status scfg_sram_operr_status_get(void) { - error_status status = SUCCESS; - - if(SCFG->cfg2_bit.sram_operr_sts) - status = ERROR; - else - status = SUCCESS; - - return status ; + return (flag_status)SCFG->cfg2_bit.sram_operr_sts; } /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c index 38268bf433..5f161f4b03 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c @@ -674,6 +674,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3, I2SF5 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_I2S_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c index 9335182f68..084ee6c602 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c @@ -160,7 +160,6 @@ void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct) */ void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct) { - tmr_brkdt_struct->brk_filter_value = 0x0; tmr_brkdt_struct->deadtime = 0x0; tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW; tmr_brkdt_struct->wp_level = TMR_WP_OFF; @@ -1346,6 +1345,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, TMR9, TMR10, + * TMR11, TMR13, TMR14 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1766,7 +1799,6 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le */ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) { - tmr_x->brk_bit.bkf = brkdt_struct->brk_filter_value; tmr_x->brk_bit.brken = brkdt_struct->brk_enable; tmr_x->brk_bit.dtc = brkdt_struct->deadtime; tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state; @@ -1776,6 +1808,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) tmr_x->brk_bit.wpc = brkdt_struct->wp_level; } +/** + * @brief set tmr break input filter value + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR9, TMR10, TMR11, TMR13, TRM14 + * @param filter_value (0x0~0xf) + * @retval none + */ +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value) +{ + tmr_x->brk_bit.bkf = filter_value; +} + /** * @brief set tmr2 and tmr14 input channel remap * @param tmr_x: select the tmr peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c index 0b9c450f13..e2291d1ada 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c @@ -607,6 +607,88 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, USART4, USART5, USART6, UART7 or UART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_RTODF_FLAG: receiver time out detection flag + * - USART_CMDF_FLAG: character match detection flag + * - USART_CTSCF_FLAG: cts change flag + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + case USART_RTODF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.retodie; + break; + case USART_CMDF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.cmdie; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -700,17 +782,17 @@ void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type } /** - * @brief enable or disable the usart's de polarity reverse. + * @brief set the usart's de polarity. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: * USART1, USART2, USART3 - * @param new_state: new state of the irda mode. - * this parameter can be: TRUE or FALSE. + * @param de_polarity: the usart de polarity selection. + * this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW. * @retval none */ -void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state) +void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity) { - usart_x->ctrl3_bit.dep = new_state; + usart_x->ctrl3_bit.dep = (uint8_t)de_polarity; } /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c index 1cc0c5d94d..49f796aaba 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c @@ -1063,7 +1063,6 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) { usb_chh->hcchar_bit.chena = TRUE; } - } else { diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c index 3a6ffcc49a..1e6bd9f35f 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c index 1fea754ae4..e88ae74efd 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f403a_407.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer @@ -81,13 +79,13 @@ void SystemInit (void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); + /* reset hexten, hextbyps, cfden and pllen bits */ + CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */ CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ - CRM->ctrl &= ~(0x010D0000U); - /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */ CRM->misc1 = 0; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h index dd23713450..522de08919 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f403a_407.h - * @version v2.0.9 - * @date 2022-04-25 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,11 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h index 5415a248b3..2955fd4706 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_acc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 acc header file ************************************************************************** * Copyright notice & Disclaimer @@ -181,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h index cb072971f5..74c7a4f33c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_adc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -621,6 +619,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint32_t adc_combine_ordinary_conversion_data_get(void); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h index 03235e1068..08e15e3037 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_bpr.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 bpr header file ************************************************************************** * Copyright notice & Disclaimer @@ -761,6 +759,7 @@ typedef struct void bpr_reset(void); flag_status bpr_flag_get(uint32_t flag); +flag_status bpr_interrupt_flag_get(uint32_t flag); void bpr_flag_clear(uint32_t flag); void bpr_interrupt_enable(confirm_state new_state); uint16_t bpr_data_read(bpr_data_type bpr_data); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h index 247dfff393..b7d45564ac 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_can.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -964,6 +962,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h index 99a81578f9..30a8cbf8b6 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h index eaaa59e9b5..a3986aaf3d 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crm.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -1088,6 +1086,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h index 6b80067615..94e6051a8c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dac.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 dac header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h index 7de5a36f5a..86a8d3bbf2 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_debug.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 debug header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h index f54003a42d..a3ec690148 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_def.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h index 7f755bb3ae..79e3a7c54e 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dma.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -527,6 +525,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state); void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type* dma_init_struct); void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h index 7fb82a44ed..6de123086c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_emac.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 emac header file ************************************************************************** * Copyright notice & Disclaimer @@ -46,6 +44,7 @@ extern "C" { */ #define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */ +#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR /** @defgroup EMAC_smi_clock_border_definition * @brief emac smi clock border @@ -99,7 +98,7 @@ extern "C" { * @{ */ -#define EMAC_MAX_PACKET_LENGTH 1520 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */ +#define EMAC_MAX_PACKET_LENGTH 1524 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */ #define EMAC_HEADER 14 /*!< 6 byte dest addr, 6 byte src addr, 2 byte length/ept_type */ #define EMAC_CRC 4 /*!< ethernet crc */ #define EMAC_EXTRA 2 /*!< extra bytes in some cases */ @@ -271,6 +270,15 @@ extern "C" { #define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */ #define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */ +/** + * @brief emac ptp time sign + */ +#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */ +#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */ + +#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */ +#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */ +#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */ /** @defgroup EMAC_exported_types * @{ */ @@ -345,9 +353,10 @@ typedef enum */ typedef enum { - EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ - EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ - EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ + EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ + EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */ + EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ + EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ } emac_control_frames_filter_type; /** @@ -633,6 +642,10 @@ typedef struct { uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */ uint32_t buf1addr; /*!< buffer1 address pointer */ uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */ + uint32_t extendedstatus; + uint32_t reserved1; + uint32_t timestamp_l; + uint32_t timestamp_h; } emac_dma_desc_type; /** @@ -891,7 +904,7 @@ typedef struct __IO uint32_t reserved1 : 8; /* [16:23] */ __IO uint32_t mbc : 6; /* [24:29] */ __IO uint32_t sa : 1; /* [30] */ - __IO uint32_t ae : 1; /* [31] */ + __IO uint32_t ae : 1; /* [31] */ } a1h_bit; }; @@ -1328,7 +1341,7 @@ typedef struct __IO uint32_t swr : 1; /* [0] */ __IO uint32_t da : 1; /* [1] */ __IO uint32_t dsl : 5; /* [2:6] */ - __IO uint32_t reserved1 : 1; /* [7] */ + __IO uint32_t atds : 1; /* [7] */ __IO uint32_t pbl : 6; /* [8:13] */ __IO uint32_t pr : 2; /* [14:15] */ __IO uint32_t fb : 1; /* [16] */ @@ -1336,7 +1349,7 @@ typedef struct __IO uint32_t usp : 1; /* [23] */ __IO uint32_t pblx8 : 1; /* [24] */ __IO uint32_t aab : 1; /* [25] */ - __IO uint32_t reserved2 : 6; /* [26:31] */ + __IO uint32_t reserved : 6; /* [26:31] */ } bm_bit; }; @@ -1628,6 +1641,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil uint32_t emac_received_packet_size_get(void); uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc); void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count); +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count); uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type); void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state); void emac_dma_para_init(emac_dma_config_type *control_para); @@ -1650,6 +1664,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void); uint16_t emac_dma_application_missing_frame_get(void); uint8_t emac_dma_fifo_overflow_bit_get(void); uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type); +void emac_dma_alternate_desc_size(confirm_state new_state); void emac_mmc_counter_reset(void); void emac_mmc_rollover_stop(confirm_state new_state); void emac_mmc_reset_on_read_enable(confirm_state new_state); @@ -1676,19 +1691,19 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state); void emac_ptp_snapshot_master_event_enable(confirm_state new_state); void emac_ptp_clock_node_set(emac_ptp_clock_node_type node); void emac_ptp_mac_address_filter_enable(confirm_state new_state); +flag_status emac_ptp_flag_get(uint32_t flag); void emac_ptp_subsecond_increment_set(uint8_t value); uint32_t emac_ptp_system_second_get(void); uint32_t emac_ptp_system_subsecond_get(void); confirm_state emac_ptp_system_time_sign_get(void); -void emac_ptp_system_second_set(uint32_t second); -void emac_ptp_system_subsecond_set(uint32_t subsecond); -void emac_ptp_system_time_sign_set(confirm_state sign); +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond); void emac_ptp_timestamp_addend_set(uint32_t value); void emac_ptp_target_second_set(uint32_t value); void emac_ptp_target_nanosecond_set(uint32_t value); confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status); void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq); flag_status emac_dma_flag_get(uint32_t dma_flag); +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag); void emac_dma_flag_clear(uint32_t dma_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h index a03d6e169a..cc32cfdd36 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_exint.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -208,6 +206,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h index 1e31aefff2..e41f839d3d 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_flash.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 flash header file ************************************************************************** * Copyright notice & Disclaimer @@ -190,7 +188,7 @@ typedef enum typedef enum { FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */ - FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */ + FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */ } flash_spim_model_type; /** @@ -700,12 +698,14 @@ uint8_t flash_ssb_status_get(void); void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state); void flash_spim_model_select(flash_spim_model_type mode); void flash_spim_encryption_range_set(uint32_t decode_address); +void flash_spim_dummy_read(void); +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt); flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector); error_status flash_slib_disable(uint32_t pwd); uint32_t flash_slib_remaining_count_get(void); flag_status flash_slib_state_get(void); uint16_t flash_slib_start_sector_get(void); -uint16_t flash_slib_datstart_sector_get(void); +uint16_t flash_slib_datastart_sector_get(void); uint16_t flash_slib_end_sector_get(void); uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h index a4c3a9ae3f..00da64b61b 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_gpio.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -215,8 +213,8 @@ extern "C" { #define SPI3_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3), spi3_miso(pb4), spi3_mosi/i2s3_sd(pb5), i2s3_mck(pb10) */ #define SPI3_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */ #define SPI4_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */ -#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pc8) */ -#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pa10) */ +#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pc8) */ +#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pa10) */ /** * @} @@ -914,7 +912,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state); void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h index bb46a0ac34..32f6badcdd 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_i2c.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -381,6 +379,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h index 1f06dc2b18..22e9c2ad8e 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_misc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h index 7b154cd257..4d9e3544a2 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_pwc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 pwc header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,7 +58,7 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h index 5c4671db49..82318c91bf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_rtc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 rtc header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,6 +236,7 @@ uint32_t rtc_divider_get(void); void rtc_alarm_set(uint32_t alarm_value); void rtc_interrupt_enable(uint16_t source, confirm_state new_state); flag_status rtc_flag_get(uint16_t flag); +flag_status rtc_interrupt_flag_get(uint16_t flag); void rtc_flag_clear(uint16_t flag); void rtc_wait_config_finish(void); void rtc_wait_update_finish(void); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h index f9b1238541..2ecbfa2919 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_sdio.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -569,7 +567,10 @@ typedef struct * @} */ +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) #define SDIO1 ((sdio_type *) SDIO1_BASE) +#endif #define SDIO2 ((sdio_type *) SDIO2_BASE) /** @defgroup SDIO_exported_functions @@ -578,7 +579,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -588,6 +589,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h index 205363f454..125f0c9ad0 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_spi.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -478,6 +476,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h index 1404b70177..5b26f8d170 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_tmr.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -888,7 +886,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -900,6 +898,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h index c168b5a771..6c93ab86c7 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usart.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -323,7 +321,10 @@ typedef struct #define UART5 ((usart_type *) UART5_BASE) #define USART6 ((usart_type *) USART6_BASE) #define UART7 ((usart_type *) UART7_BASE) +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) #define UART8 ((usart_type *) UART8_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -357,6 +358,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h index 21431c6eef..7c8976a8fa 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usb.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -195,7 +193,6 @@ typedef enum #ifndef USB_EPT_MAX_NUM #define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */ #endif - /** * @brief endpoint transfer type define */ @@ -692,6 +689,7 @@ void usb_remote_wkup_clear(usbd_type *usbx); uint16_t usb_buffer_malloc(uint16_t maxpacket); void usb_buffer_free(void); flag_status usb_flag_get(usbd_type *usbx, uint16_t flag); +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag); void usb_flag_clear(usbd_type *usbx, uint16_t flag); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h index f870840a7b..b581a567bf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wdt.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h index 8c26c5a8b1..13a3023d0e 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wwdt.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h index 67d26450fc..7f5c967281 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_xmc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 xmc header file ************************************************************************** * Copyright notice & Disclaimer @@ -534,7 +532,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct, xmc_norsram_timing_init_type* xmc_w_timing_struct); void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state); -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); void xmc_nand_reset(xmc_class_bank_type xmc_bank); void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct); void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct, @@ -547,6 +545,7 @@ void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state); uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank); void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state); flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c index 770db6ac86..50ff284b86 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_acc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the acc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -190,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c index 5161242761..d41d31d93d 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_adc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -116,7 +114,7 @@ void adc_combine_mode_select(adc_combine_mode_type combine_mode) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -142,7 +140,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -347,117 +345,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -505,66 +428,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -857,10 +737,10 @@ uint32_t adc_combine_ordinary_conversion_data_get(void) * ADC1, ADC2, ADC3. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -915,6 +795,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1, ADC2, ADC3. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c index 08e1922e1f..82d77a54dd 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_bpr.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the bpr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -72,6 +70,26 @@ flag_status bpr_flag_get(uint32_t flag) } } +/** + * @brief bpr interrupt flag get + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag + * - BPR_TAMPER_EVENT_FLAG: tamper event flag + * @retval state of tamper event flag + */ +flag_status bpr_interrupt_flag_get(uint32_t flag) +{ + if(flag == BPR_TAMPER_INTERRUPT_FLAG) + { + return (flag_status)(BPR->ctrlsts_bit.tpif && BPR->ctrlsts_bit.tpien); + } + else + { + return (flag_status)(BPR->ctrlsts_bit.tpef && BPR->ctrlsts_bit.tpien); + } +} + /** * @brief clear bpr tamper flag * @param flag: specifies the flag to clear. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c index 12e4586d95..15496174fe 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_can.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -934,6 +932,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c index aa81315212..edd02a4898 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c index c3ea29c3ae..8c58d81104 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crm.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,13 +59,13 @@ void crm_reset(void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); + /* reset hexten, hextbyps, cfden and pllen bits */ + CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */ CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ - CRM->ctrl &= ~(0x010D0000U); - /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */ CRM->misc1 = 0; @@ -133,6 +131,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -348,6 +404,7 @@ void crm_flag_clear(uint32_t flag) case CRM_LOWPOWER_RESET_FLAG: case CRM_ALL_RESET_FLAG: CRM->ctrlsts_bit.rstfc = TRUE; + while(CRM->ctrlsts_bit.rstfc == TRUE); break; case CRM_LICK_READY_INT_FLAG: CRM->clkint_bit.lickstblfc = TRUE; @@ -418,6 +475,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 120 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -434,6 +492,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 120 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -525,6 +584,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu if(clock_source == CRM_PLL_SOURCE_HICK) { CRM->cfg_bit.pllrcs = FALSE; + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -559,6 +619,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c index b956361598..5791e8e2c8 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dac.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the dac firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c index 893cd604bd..d04d62a305 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_debug.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the debug firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c index 39e036d0c7..ab2d16d9ab 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dma.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -280,6 +278,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re } } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c index a8b93ce5fe..5d25406723 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_emac.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the emac firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -45,8 +43,10 @@ /** * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors */ -emac_dma_desc_type *dma_tx_desc_to_set; -emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *dma_tx_desc_to_set; +__IO emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *ptp_dma_tx_desc_to_set; +__IO emac_dma_desc_type *ptp_dma_rx_desc_to_get; /* emac private function */ static void emac_delay(uint32_t delay); @@ -525,6 +525,7 @@ void emac_broadcast_frames_disable(confirm_state new_state) * @param condition: set what control frame can pass filter. * this parameter can be one of the following values: * - EMAC_CONTROL_FRAME_PASSING_NO + * - EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE * - EMAC_CONTROL_FRAME_PASSING_ALL * - EMAC_CONTROL_FRAME_PASSING_MATCH * @retval none @@ -984,6 +985,90 @@ void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, ema } } +/** + * @brief set transmit/receive descriptor list address + * @param transfer_type: it will be transmit or receive + * this parameter can be one of the following values: + * - EMAC_DMA_TRANSMIT + * - EMAC_DMA_RECEIVE + * @param dma_desc_tab: pointer on the first tx desc list + * @param buff: pointer on the first tx/rx buffer list + * @param buffer_count: number of the used Tx desc in the list + * @retval none + */ +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count) +{ + uint32_t i = 0; + emac_dma_desc_type *dma_descriptor; + + switch(transfer_type) + { + case EMAC_DMA_TRANSMIT: + { + dma_tx_desc_to_set = dma_desc_tab; + ptp_dma_tx_desc_to_set = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMATXDESC_TCH | EMAC_DMATXDESC_TTSE; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab; + break; + } + case EMAC_DMA_RECEIVE: + { + dma_rx_desc_to_get = dma_desc_tab; + ptp_dma_rx_desc_to_get = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMARXDESC_OWN; + + dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab; + break; + } + } +} /** * @brief enable or disable the specified dma rx descriptor receive interrupt * @param dma_rx_desc: pointer on a rx desc. @@ -1044,7 +1129,7 @@ uint32_t emac_received_packet_size_get(void) ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) && ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET)) { - frame_length = emac_dmarxdesc_frame_length_get(dma_rx_desc_to_get); + frame_length = emac_dmarxdesc_frame_length_get((emac_dma_desc_type*) dma_rx_desc_to_get); } return frame_length; @@ -1655,6 +1740,16 @@ uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_ty return address; } +/** + * @brief alternate dma descriptor size + * @param new_state: TRUE or FALSE + * @retval none + */ +void emac_dma_alternate_desc_size(confirm_state new_state) +{ + EMAC_DMA->bm_bit.atds = new_state; +} + /** * @brief reset all counter * @param none @@ -2034,6 +2129,27 @@ void emac_ptp_mac_address_filter_enable(confirm_state new_state) EMAC_PTP->tsctrl_bit.emafpff = new_state; } +/** + * @brief check whether the specified emac ptp flag is set or not. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - EMAC_PTP_TI_FLAG: time stamp initialized flag + * - EMAC_PTP_TU_FLAG: time stamp updtated flag + * - EMAC_PTP_ARU_FLAG: transmit data buffer empty flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status emac_ptp_flag_get(uint32_t flag) +{ + if(EMAC_PTP->tsctrl & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief set subsecond increment value * @param value: add to subsecond value for every update @@ -2084,42 +2200,19 @@ confirm_state emac_ptp_system_time_sign_get(void) } /** - * @brief set system time second + * @brief set system time + * @param sign: plus or minus * @param second: system time second - * @retval none - */ -void emac_ptp_system_second_set(uint32_t second) -{ - EMAC_PTP->tshud_bit.ts = second; -} - -/** - * @brief set system time subsecond * @param subsecond: system time subsecond * @retval none */ -void emac_ptp_system_subsecond_set(uint32_t subsecond) +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond) { + EMAC_PTP->tslud_bit.ast = sign ? 1 : 0; + EMAC_PTP->tshud_bit.ts = second; EMAC_PTP->tslud_bit.tss = subsecond; } -/** - * @brief set system time sign - * @param sign: TRUE or FALSE. - * @retval none - */ -void emac_ptp_system_time_sign_set(confirm_state sign) -{ - if(sign) - { - EMAC_PTP->tslud_bit.ast = 1; - } - else - { - EMAC_PTP->tslud_bit.ast = 0; - } -} - /** * @brief set time stamp addend * @param value: to achieve time synchronization @@ -2261,6 +2354,62 @@ flag_status emac_dma_flag_get(uint32_t dma_flag) return status; } +/** + * @brief check whether the specified emac dma interrupt flag is set or not. + * @param dma_flag: specifies the emac dma flag to check. + * this parameter can be one of emac dma flag status: + * - EMAC_DMA_TI_FLAG + * - EMAC_DMA_TPS_FLAG + * - EMAC_DMA_TBU_FLAG + * - EMAC_DMA_TJT_FLAG + * - EMAC_DMA_OVF_FLAG + * - EMAC_DMA_UNF_FLAG + * - EMAC_DMA_RI_FLAG + * - EMAC_DMA_RBU_FLAG + * - EMAC_DMA_RPS_FLAG + * - EMAC_DMA_RWT_FLAG + * - EMAC_DMA_ETI_FLAG + * - EMAC_DMA_FBEI_FLAG + * - EMAC_DMA_ERI_FLAG + * - EMAC_DMA_AIS_FLAG + * - EMAC_DMA_NIS_FLAG + * @retval the new state of dma_flag (SET or RESET). + */ +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag) +{ + flag_status status = RESET; + switch(dma_flag) + { + case EMAC_DMA_TI_FLAG: + case EMAC_DMA_TBU_FLAG: + case EMAC_DMA_RI_FLAG: + case EMAC_DMA_ERI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_NIS_FLAG)) + status = SET; + break; + case EMAC_DMA_TPS_FLAG: + case EMAC_DMA_TJT_FLAG: + case EMAC_DMA_OVF_FLAG: + case EMAC_DMA_UNF_FLAG: + case EMAC_DMA_RBU_FLAG: + case EMAC_DMA_RPS_FLAG: + case EMAC_DMA_RWT_FLAG: + case EMAC_DMA_ETI_FLAG: + case EMAC_DMA_FBEI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_AIS_FLAG)) + status = SET; + break; + default: + break; + } + /* return the new state (SET or RESET) */ + return status; +} + /** * @brief clear the emac dma flag. * @param dma_flag: specifies the emac dma flags to clear. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c index c6ef1c335e..0768afd3bf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_exint.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -125,7 +123,15 @@ void exint_init(exint_init_type *exint_struct) */ void exint_flag_clear(uint32_t exint_line) { - EXINT->intsts = exint_line; + if((EXINT->swtrg & exint_line) == exint_line) + { + EXINT->intsts = exint_line; + EXINT->intsts = exint_line; + } + else + { + EXINT->intsts = exint_line; + } } /** @@ -155,6 +161,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_18 + * - EXINT_LINE_19 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c index 98e7cb9922..3e1921e478 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_flash.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -448,62 +446,43 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type status = FLASH_OPERATE_DONE; if((sector_address >= FLASH_BANK1_START_ADDR) && (sector_address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; } else if((sector_address >= FLASH_BANK2_START_ADDR) && (sector_address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.secers = TRUE; + FLASH->addr2 = sector_address; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl2_bit.secers = TRUE; - FLASH->addr2 = sector_address; - FLASH->ctrl2_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl2_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl2_bit.secers = FALSE; } /* spim : external flash */ else if(sector_address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.secers = TRUE; + FLASH->addr3 = sector_address; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl3_bit.secers = TRUE; - FLASH->addr3 = sector_address; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the secers bit */ + FLASH->ctrl3_bit.secers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl3_bit.secers = FALSE; - } - return status; + /* dummy read */ + flash_spim_dummy_read(); } /* return the erase status */ @@ -519,21 +498,16 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } if(status == FLASH_OPERATE_DONE) { /* if the previous operation is completed, continue to erase bank2 */ @@ -559,21 +533,16 @@ flash_status_type flash_internal_all_erase(void) flash_status_type flash_bank1_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -587,21 +556,16 @@ flash_status_type flash_bank1_erase(void) flash_status_type flash_bank2_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl2_bit.bankers = TRUE; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank2 */ - FLASH->ctrl2_bit.bankers = TRUE; - FLASH->ctrl2_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl2_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl2_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -615,21 +579,19 @@ flash_status_type flash_bank2_erase(void) flash_status_type flash_spim_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl3_bit.chpers = TRUE; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase spim */ - FLASH->ctrl3_bit.chpers = TRUE; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the chpers bit */ + FLASH->ctrl3_bit.chpers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); + /* dummy read */ + flash_spim_dummy_read(); - /* disable the chpers bit */ - FLASH->ctrl3_bit.chpers = FALSE; - } /* return the erase status */ return status; } @@ -645,47 +607,43 @@ flash_status_type flash_user_system_data_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; uint16_t fap_val = FAP_RELIEVE_KEY; + /* get the flash access protection status */ if(flash_fap_status_get() != RESET) { fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the erase status */ return status; } @@ -702,52 +660,37 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* spim : external flash */ else if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } /* return the program status */ @@ -766,52 +709,37 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* spim : external flash */ else if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } /* return the program status */ @@ -831,35 +759,23 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -875,24 +791,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + if(address == USD_BASE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; + if(data != 0xA5) + return FLASH_OPERATE_DONE; } + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the user system data program status */ return status; } @@ -915,42 +835,38 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -978,38 +894,36 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - if(new_state == FALSE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + /* return the flash access protection operation status */ return status; } @@ -1050,26 +964,22 @@ flag_status flash_fap_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -1126,6 +1036,9 @@ void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state) void flash_spim_model_select(flash_spim_model_type mode) { FLASH->select = mode; + + /* dummy read */ + flash_spim_dummy_read(); } /** @@ -1140,6 +1053,62 @@ void flash_spim_encryption_range_set(uint32_t decode_address) FLASH->da = decode_address; } +/** + * @brief operate the flash spim dummy read. + * @param none + * @retval none + */ +void flash_spim_dummy_read(void) +{ + UNUSED(*(__IO uint32_t*)FLASH_SPIM_START_ADDR); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x1000)); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x2000)); +} + +/** + * @brief mass program for flash spim. + * @param address: specifies the start address to be programmed, word or halfword alignment is recommended. + * @param buf: specifies the pointer of data to be programmed. + * @param cnt: specifies the data counter to be programmed. + * @retval status: the returned value can be: FLASH_PROGRAM_ERROR, + * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT. + */ +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt) +{ + flash_status_type status = FLASH_OPERATE_DONE; + uint32_t index, temp_offset; + if(address >= FLASH_SPIM_START_ADDR) + { + temp_offset = cnt % 4; + if((temp_offset != 0) && (temp_offset != 2)) + return status; + + FLASH->ctrl3_bit.fprgm = TRUE; + for(index = 0; index < cnt / 4; index++) + { + *(__IO uint32_t*)(address + index * 4) = *(uint32_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + if(status != FLASH_OPERATE_DONE) + return status; + } + if(temp_offset == 2) + { + *(__IO uint16_t*)(address + index * 4) = *(uint16_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + } + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; + + /* dummy read */ + flash_spim_dummy_read(); + } + + /* return the program status */ + return status; +} + /** * @brief enable security library function. * @param pwd: slib password @@ -1153,27 +1122,25 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \ (data_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ + ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ + (start_sector & FLASH_SLIB_START_SECTOR); + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + FLASH->slib_set_range = slib_range; if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ - ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ - (start_sector & FLASH_SLIB_START_SECTOR); - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - FLASH->slib_set_range = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } return status; @@ -1239,7 +1206,7 @@ uint16_t flash_slib_start_sector_get(void) * @param none * @retval uint16_t */ -uint16_t flash_slib_datstart_sector_get(void) +uint16_t flash_slib_datastart_sector_get(void) { return (uint16_t)FLASH->slib_sts1_bit.slib_dat_ss; } diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c index fbff02dd12..0803b4a4eb 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_gpio.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -390,7 +388,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c index 8a55b48b3d..aa37679aaf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_i2c.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -605,6 +603,85 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. @@ -619,11 +696,23 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) * - I2C_PECERR_FLAG: pec receive error flag. * - I2C_TMOUT_FLAG: smbus timeout flag. * - I2C_ALERTF_FLAG: smbus alert flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag. * @retval none */ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag) { - i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x00FFFFFF); + i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00); + + if(i2c_x->sts1 & I2C_ADDR7F_FLAG) + { + UNUSED(i2c_x->sts2); + } + + if(i2c_x->sts1 & I2C_STOPF_FLAG) + { + i2c_x->ctrl1_bit.i2cen = TRUE; + } } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c index 25b34c1253..9691a8b0e9 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_misc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c index fc945a9cf3..da9989a9e8 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_pwc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -228,7 +226,10 @@ void pwc_standby_mode_enter(void) #if defined (__CC_ARM) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c index f6f453cdfb..1573b891b9 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_rtc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the rtc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -76,7 +74,7 @@ uint32_t rtc_counter_get(void) /** * @brief rtc divider set - * @param div_value (0x0000_0000 ~ 0xFFFF_FFFF) + * @param div_value (0x0000_0000 ~ 0x000F_FFFF) * @retval none */ void rtc_divider_set(uint32_t div_value) @@ -174,6 +172,31 @@ flag_status rtc_flag_get(uint16_t flag) return status; } +/** + * @brief rtc interrupt flag get + * @param flag + * this parameter can be one of the following values: + * - RTC_TS_FLAG: time second flag. + * - RTC_TA_FLAG: time alarm flag. + * - RTC_OVF_FLAG: overflow flag. + * @retval state of rtc flag + */ +flag_status rtc_interrupt_flag_get(uint16_t flag) +{ + flag_status status = RESET; + + if (((RTC->ctrll & flag) != (uint16_t)RESET) && ((RTC->ctrlh & flag) != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief rtc flag clear * @param interrupt_flag @@ -181,7 +204,7 @@ flag_status rtc_flag_get(uint16_t flag) * - RTC_TS_FLAG: time second flag. * - RTC_TA_FLAG: time alarm flag. * - RTC_OVF_FLAG: overflow flag. - * - RTC_CFGF_FLAG: rtc configuration finish flag. + * - RTC_UPDF_FLAG: rtc update finish flag. * @retval none */ void rtc_flag_clear(uint16_t flag) diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c index 8b66019283..55edf374c9 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_sdio.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1, SDIO2. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1, SDIO2. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c index 720aa92117..489050c176 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_spi.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -441,7 +439,7 @@ void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct) * @brief enable or disable i2s. * @param spi_x: select the i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param new_state: new state of i2s. * this parameter can be: TRUE or FALSE. * @retval none @@ -455,7 +453,7 @@ void i2s_enable(spi_type* spi_x, confirm_state new_state) * @brief enable or disable the specified spi/i2s interrupts. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled. * this parameter can be one of the following values: * - SPI_I2S_ERROR_INT @@ -481,7 +479,7 @@ void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_sta * @brief enable or disable the spi/i2s dma transmitter mode. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param new_state: new state of the dma request. * this parameter can be: TRUE or FALSE. * @retval none @@ -495,7 +493,7 @@ void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state) * @brief enable or disable the spi/i2s dma receiver mode. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param new_state: new state of the dma request. * this parameter can be: TRUE or FALSE. * @retval none @@ -509,7 +507,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state) * @brief spi/i2s data transmit * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param tx_data: the data to be transmit. * this parameter can be: * - (0x0000~0xFFFF) @@ -524,7 +522,7 @@ void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data) * @brief spi/i2s data receive * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @retval the received data value */ uint16_t spi_i2s_data_receive(spi_type* spi_x) @@ -536,7 +534,7 @@ uint16_t spi_i2s_data_receive(spi_type* spi_x) * @brief get flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param spi_i2s_flag: select the spi/i2s flag * this parameter can be one of the following values: * - SPI_I2S_RDBF_FLAG @@ -563,11 +561,74 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param spi_i2s_flag: select the spi/i2s flag * this parameter can be one of the following values: * - SPI_CCERR_FLAG @@ -583,23 +644,21 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c index e92df95008..94e6e63f5c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_tmr.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -260,11 +258,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) { /* set the repetition counter value */ - if((tmr_x == TMR1) || (tmr_x == TMR8)) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -302,8 +296,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -344,23 +337,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -388,38 +381,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -758,7 +751,8 @@ void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_ * @brief enable or disable tmr one cycle mode * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TMR9, TMR12 + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 * @param new_state (TRUE or FALSE) * @retval none */ @@ -840,6 +834,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -849,6 +844,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -858,6 +854,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -867,6 +864,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1101,15 +1099,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1207,7 +1205,7 @@ void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode) } /** - * @brief select tmr channel dma + * @brief select tmr channel dma request source * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12 @@ -1344,6 +1342,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1729,7 +1761,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR8 diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c index 2fde5c6780..aff174e4fc 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usart.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -86,11 +84,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE); } +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) else if(usart_x == UART8) { crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE); } +#endif } /** @@ -103,6 +104,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -116,7 +120,12 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type crm_clocks_freq_type clocks_freq; uint32_t apb_clock, temp_val; crm_clocks_freq_get(&clocks_freq); - if((usart_x == USART1) || (usart_x == USART6) || (usart_x == UART7) || (usart_x == UART8)) + if((usart_x == USART1) || (usart_x == USART6) || (usart_x == UART7) +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) + || (usart_x == UART8) +#endif + ) { apb_clock = clocks_freq.apb2_freq; } @@ -583,6 +592,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -594,6 +676,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -606,7 +693,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c index a177da5657..5f9dddb8b5 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usb.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -133,6 +131,7 @@ void usb_usbbufs_enable(usbd_type *usbx, confirm_state state) g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS; CRM->misc1_bit.usbbufs = FALSE; } + UNUSED(usbx); } /** @@ -251,6 +250,7 @@ void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE); } } + UNUSED(usbx); } @@ -310,6 +310,7 @@ void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE); } } + UNUSED(usbx); } /** @@ -424,6 +425,7 @@ void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info) { USB_SET_RXSTS(ept_info->eptn, USB_RX_STALL) } + UNUSED(usbx); } /** @@ -525,6 +527,40 @@ flag_status usb_flag_get(usbd_type *usbx, uint16_t flag) return status; } +/** + * @brief get interrupt flag of usb. + * @param usbx: select the usb peripheral + * @param flag: select the usb flag + * this parameter can be one of the following values: + * - USB_LSOF_FLAG + * - USB_SOF_FLAG + * - USB_RST_FLAG + * - USB_SP_FLAG + * - USB_WK_FLAG + * - USB_BE_FLAG + * - USB_UCFOR_FLAG + * - USB_TC_FLAG + * @retval none + */ +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag) +{ + flag_status status = RESET; + + if(flag == USB_TC_FLAG) + { + if(usbx->intsts & USB_TC_FLAG) + status = SET; + } + else + { + if((usbx->intsts & flag) && (usbx->ctrl & flag)) + { + status = SET; + } + } + return status; +} + /** * @brief clear flag of usb. * @param usbx: select the usb peripheral diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c index 782123fbb1..b1c55d483c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wdt.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c index 8b543852c3..03bb3ffc53 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wwdt.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c index 6b215e91fa..723e69011f 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_xmc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the xmc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -218,9 +216,9 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne * @param r2r_timing :read timing * @retval none */ -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) { - XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8; + XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing; XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing; } @@ -470,6 +468,47 @@ flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag return status; } +/** + * @brief check whether the specified xmc interrupt flag is set or not. + * @param xmc_bank: specifies the xmc bank to be used + * this parameter can be one of the following values: + * - XMC_BANK2_NAND + * @param xmc_flag: specifies the flag to check. + * this parameter can be any combination of the following values: + * - XMC_RISINGEDGE_FLAG + * - XMC_LEVEL_FLAG + * - XMC_FALLINGEDGE_FLAG + * @retval none + */ +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag) +{ + flag_status status = RESET; + + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls) + status = SET; + break; + + default: + break; + } + + /* return the flag status */ + return status; +} + /** * @brief clear the xmc's pending flags. * @param xmc_bank: specifies the xmc bank to be used diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c index 846d23e5bc..eb042c5b83 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f413.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h index adc9926592..29e3345c66 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f413.h - * @version v2.0.5 - * @date 2022-05-20 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,11 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h index 3607e36fb5..1cb8f11316 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_acc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 acc header file ************************************************************************** * Copyright notice & Disclaimer @@ -181,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h index 2d16d8c1e5..1bf227c404 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_adc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -596,6 +594,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint32_t adc_combine_ordinary_conversion_data_get(void); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h index c61839a1a3..335f08bc33 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_bpr.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 bpr header file ************************************************************************** * Copyright notice & Disclaimer @@ -118,9 +116,7 @@ typedef enum BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE = 0x080, /*!< output clock before calibration */ BPR_RTC_OUTPUT_ALARM = 0x100, /*!< output alarm event with pluse mode */ BPR_RTC_OUTPUT_SECOND = 0x300, /*!< output second event with pluse mode */ - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER = 0x480, /*!< output clock after calibration */ - BPR_RTC_OUTPUT_ALARM_TOGGLE = 0x900, /*!< output alarm event with toggle mode */ - BPR_RTC_OUTPUT_SECOND_TOGGLE = 0xB00 /*!< output second event with toggle mode */ + BPR_RTC_OUTPUT_CLOCK_CAL_AFTER = 0x480 /*!< output clock after calibration */ } bpr_rtc_output_type; /** @@ -761,6 +757,7 @@ typedef struct void bpr_reset(void); flag_status bpr_flag_get(uint32_t flag); +flag_status bpr_interrupt_flag_get(uint32_t flag); void bpr_flag_clear(uint32_t flag); void bpr_interrupt_enable(confirm_state new_state); uint16_t bpr_data_read(bpr_data_type bpr_data); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h index 5ba05a9704..298c4bb8df 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_can.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -936,7 +934,10 @@ typedef struct */ #define CAN1 ((can_type *) CAN1_BASE) +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) #define CAN2 ((can_type *) CAN2_BASE) +#endif /** @defgroup CAN_exported_functions * @{ @@ -964,6 +965,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h index a3372dfd07..93276aae68 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h index 6cdfba68c4..88a4e7d492 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crm.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -139,7 +137,7 @@ typedef enum CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */ CRM_BPR_PERIPH_CLOCK = MAKE_VALUE(0x1C, 27), /*!< bpr periph clock */ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ - CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 31), /*!< can2 periph clock */ + CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 31) /*!< can2 periph clock */ } crm_periph_clock_type; @@ -183,7 +181,7 @@ typedef enum CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */ CRM_BPR_PERIPH_RESET = MAKE_VALUE(0x10, 27), /*!< bpr periph reset */ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ - CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x10, 31), /*!< can2 periph reset */ + CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x10, 31) /*!< can2 periph reset */ } crm_periph_reset_type; @@ -851,6 +849,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h index f83cde2342..cfe5b0d24b 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_debug.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 debug header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h index a518d683c7..ecb19616bf 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_def.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h index 62b6c6c663..97f1f826fc 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_dma.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -507,6 +505,7 @@ void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number); uint16_t dma_data_number_get(dma_channel_type* dmax_channely); void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h index ff07816442..7c956ab333 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_exint.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -206,6 +204,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h index 790e78b9d6..5c349dcee5 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_flash.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 flash header file ************************************************************************** * Copyright notice & Disclaimer @@ -170,7 +168,7 @@ typedef enum typedef enum { FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */ - FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */ + FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */ } flash_spim_model_type; /** @@ -595,12 +593,14 @@ uint8_t flash_ssb_status_get(void); void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state); void flash_spim_model_select(flash_spim_model_type mode); void flash_spim_encryption_range_set(uint32_t decode_address); +void flash_spim_dummy_read(void); +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt); flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector); error_status flash_slib_disable(uint32_t pwd); uint32_t flash_slib_remaining_count_get(void); flag_status flash_slib_state_get(void); uint16_t flash_slib_start_sector_get(void); -uint16_t flash_slib_datstart_sector_get(void); +uint16_t flash_slib_datastart_sector_get(void); uint16_t flash_slib_end_sector_get(void); uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h index bcc80b275d..ad33b4356a 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_gpio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -767,7 +765,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source); void gpio_event_output_enable(confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h index 6fd86930ec..f10d3472d5 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_i2c.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -380,6 +378,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h index 99e5094817..ec17e71470 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_misc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h index 57fa5b2097..4a24cc1b45 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_pwc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 pwc header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,7 +58,7 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ /** @defgroup PWC_exported_types * @{ @@ -98,15 +96,6 @@ typedef enum PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */ } pwc_deep_sleep_enter_type; -/** - * @brief pwc regulator type - */ -typedef enum -{ - PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */ - PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */ -} pwc_regulator_type; - /** * @brief type define pwc register all */ @@ -120,14 +109,14 @@ typedef struct __IO uint32_t ctrl; struct { - __IO uint32_t vrsel : 1; /* [0] */ + __IO uint32_t reserved1 : 1; /* [0] */ __IO uint32_t lpsel : 1; /* [1] */ __IO uint32_t clswef : 1; /* [2] */ __IO uint32_t clsef : 1; /* [3] */ __IO uint32_t pvmen : 1; /* [4] */ __IO uint32_t pvmsel : 3; /* [7:5] */ __IO uint32_t bpwen : 1; /* [8] */ - __IO uint32_t reserved1 : 23;/* [31:9] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ } ctrl_bit; }; @@ -169,7 +158,6 @@ void pwc_flag_clear(uint32_t pwc_flag); flag_status pwc_flag_get(uint32_t pwc_flag); void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter); void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter); -void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator); void pwc_standby_mode_enter(void); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h index 024b10e0a2..e31e3852a2 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_rtc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 rtc header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,6 +236,7 @@ uint32_t rtc_divider_get(void); void rtc_alarm_set(uint32_t alarm_value); void rtc_interrupt_enable(uint16_t source, confirm_state new_state); flag_status rtc_flag_get(uint16_t flag); +flag_status rtc_interrupt_flag_get(uint16_t flag); void rtc_flag_clear(uint16_t flag); void rtc_wait_config_finish(void); void rtc_wait_update_finish(void); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h index 42c8a1d2fa..c1085ddcda 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_sdio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -569,7 +567,10 @@ typedef struct * @} */ +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) #define SDIO1 ((sdio_type *) SDIO1_BASE) +#endif /** @defgroup SDIO_exported_functions * @{ @@ -577,7 +578,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -587,6 +588,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h index ab2805133d..2fa0222b79 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_spi.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -475,6 +473,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h index 0654ca3432..2506c4b8f1 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_tmr.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -833,11 +831,16 @@ typedef struct #define TMR2 ((tmr_type *) TMR2_BASE) #define TMR3 ((tmr_type *) TMR3_BASE) #define TMR4 ((tmr_type *) TMR4_BASE) +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) #define TMR5 ((tmr_type *) TMR5_BASE) +#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7) #define TMR8 ((tmr_type *) TMR8_BASE) +#endif #define TMR9 ((tmr_type *) TMR9_BASE) #define TMR10 ((tmr_type *) TMR10_BASE) #define TMR11 ((tmr_type *) TMR11_BASE) +#endif /** @defgroup TMR_exported_functions * @{ @@ -883,7 +886,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -895,6 +898,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h index 062f359705..c8d332c29f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usart.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -318,9 +316,13 @@ typedef struct #define USART1 ((usart_type *) USART1_BASE) #define USART2 ((usart_type *) USART2_BASE) +#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7) #define USART3 ((usart_type *) USART3_BASE) +#endif +#if defined (AT32F413Rx) #define UART4 ((usart_type *) UART4_BASE) #define UART5 ((usart_type *) UART5_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -354,6 +356,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h index 96232951d6..56310003bb 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usb.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -195,7 +193,6 @@ typedef enum #ifndef USB_EPT_MAX_NUM #define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */ #endif - /** * @brief endpoint transfer type define */ @@ -691,6 +688,7 @@ void usb_remote_wkup_clear(usbd_type *usbx); uint16_t usb_buffer_malloc(uint16_t maxpacket); void usb_buffer_free(void); flag_status usb_flag_get(usbd_type *usbx, uint16_t flag); +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag); void usb_flag_clear(usbd_type *usbx, uint16_t flag); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h index 39fa082557..c2cdb53e18 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h index 5c26304542..2dcfa2bb9a 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wwdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c index 1eec3f85ef..7947516b7b 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_acc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the acc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -190,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c index ca75cd1cbb..be630faa92 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_adc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -111,7 +109,7 @@ void adc_combine_mode_select(adc_combine_mode_type combine_mode) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -137,7 +135,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -342,117 +340,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -500,66 +423,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -844,10 +724,10 @@ uint32_t adc_combine_ordinary_conversion_data_get(void) * ADC1, ADC2. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -902,6 +782,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1, ADC2. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c index 955b7a3908..ee31381124 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_bpr.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the bpr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -72,6 +70,26 @@ flag_status bpr_flag_get(uint32_t flag) } } +/** + * @brief bpr interrupt flag get + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag + * - BPR_TAMPER_EVENT_FLAG: tamper event flag + * @retval state of tamper event flag + */ +flag_status bpr_interrupt_flag_get(uint32_t flag) +{ + if(flag == BPR_TAMPER_INTERRUPT_FLAG) + { + return (flag_status)(BPR->ctrlsts_bit.tpif && BPR->ctrlsts_bit.tpien); + } + else + { + return (flag_status)(BPR->ctrlsts_bit.tpef && BPR->ctrlsts_bit.tpien); + } +} + /** * @brief clear bpr tamper flag * @param flag: specifies the flag to clear. @@ -144,8 +162,6 @@ void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value) * - BPR_RTC_OUTPUT_ALARM: output alarm event with pluse mode. * - BPR_RTC_OUTPUT_SECOND: output second event with pluse mode. * - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER: output clock after calibration. - * - BPR_RTC_OUTPUT_ALARM_TOGGLE: output alarm event with toggle mode. - * - BPR_RTC_OUTPUT_SECOND_TOGGLE: output second event with toggle mode. * @retval none */ void bpr_rtc_output_select(bpr_rtc_output_type output_source) diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c index feb5e4b7a6..113c8031d7 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_can.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -55,11 +53,14 @@ void can_reset(can_type* can_x) crm_periph_reset(CRM_CAN1_PERIPH_RESET, TRUE); crm_periph_reset(CRM_CAN1_PERIPH_RESET, FALSE); } +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) else if(can_x == CAN2) { crm_periph_reset(CRM_CAN2_PERIPH_RESET, TRUE); crm_periph_reset(CRM_CAN2_PERIPH_RESET, FALSE); } +#endif } /** @@ -933,6 +934,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c index 6eed245d7f..025aa81f9f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c index f4451f9e32..5e54594f3f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crm.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -133,6 +131,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -410,6 +466,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 100 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -426,6 +483,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 100 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -517,6 +575,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu if(clock_source == CRM_PLL_SOURCE_HICK) { CRM->cfg_bit.pllrcs = FALSE; + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -551,6 +610,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c index c46f1fc721..d15d592e62 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_debug.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the debug firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c index fc7c3167bd..bc37f7abfb 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_dma.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -275,6 +273,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re } } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c index 38f6ff27d4..6f9f467c32 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_exint.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -155,6 +153,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_17 + * - EXINT_LINE_18 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c index c5952f9807..6eaac07a62 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_flash.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -275,42 +273,30 @@ flash_status_type flash_sector_erase(uint32_t sector_address) /* spim : external flash */ if(sector_address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.secers = TRUE; + FLASH->addr3 = sector_address; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl3_bit.secers = TRUE; - FLASH->addr3 = sector_address; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the secers bit */ + FLASH->ctrl3_bit.secers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl3_bit.secers = FALSE; - } - return status; + /* dummy read */ + flash_spim_dummy_read(); } else { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; } /* return the erase status */ return status; @@ -325,21 +311,16 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -353,21 +334,19 @@ flash_status_type flash_internal_all_erase(void) flash_status_type flash_spim_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl3_bit.chpers = TRUE; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase spim */ - FLASH->ctrl3_bit.chpers = TRUE; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the chpers bit */ + FLASH->ctrl3_bit.chpers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); + /* dummy read */ + flash_spim_dummy_read(); - /* disable the chpers bit */ - FLASH->ctrl3_bit.chpers = FALSE; - } /* return the erase status */ return status; } @@ -389,41 +368,36 @@ flash_status_type flash_user_system_data_erase(void) fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks == RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the erase status */ return status; } @@ -441,35 +415,26 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) /* spim : external flash */ if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } else { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -488,35 +453,26 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) /* spim : external flash */ if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } else { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -533,19 +489,15 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type flash_byte_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -560,24 +512,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + if(address == USD_BASE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; + if(data != 0xA5) + return FLASH_OPERATE_DONE; } + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the user system data program status */ return status; } @@ -600,42 +556,38 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -663,38 +615,36 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - if(new_state == FALSE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* Wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + /* return the flash access protection operation status */ return status; } @@ -731,26 +681,22 @@ flag_status flash_fap_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -798,6 +744,9 @@ void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state) void flash_spim_model_select(flash_spim_model_type mode) { FLASH->select = mode; + + /* dummy read */ + flash_spim_dummy_read(); } /** @@ -812,6 +761,62 @@ void flash_spim_encryption_range_set(uint32_t decode_address) FLASH->da = decode_address; } +/** + * @brief operate the flash spim dummy read. + * @param none + * @retval none + */ +void flash_spim_dummy_read(void) +{ + UNUSED(*(__IO uint32_t*)FLASH_SPIM_START_ADDR); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x1000)); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x2000)); +} + +/** + * @brief mass program for flash spim. + * @param address: specifies the start address to be programmed, word or halfword alignment is recommended. + * @param buf: specifies the pointer of data to be programmed. + * @param cnt: specifies the data counter to be programmed. + * @retval status: the returned value can be: FLASH_PROGRAM_ERROR, + * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT. + */ +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt) +{ + flash_status_type status = FLASH_OPERATE_DONE; + uint32_t index, temp_offset; + if(address >= FLASH_SPIM_START_ADDR) + { + temp_offset = cnt % 4; + if((temp_offset != 0) && (temp_offset != 2)) + return status; + + FLASH->ctrl3_bit.fprgm = TRUE; + for(index = 0; index < cnt / 4; index++) + { + *(__IO uint32_t*)(address + index * 4) = *(uint32_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + if(status != FLASH_OPERATE_DONE) + return status; + } + if(temp_offset == 2) + { + *(__IO uint16_t*)(address + index * 4) = *(uint16_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + } + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; + + /* dummy read */ + flash_spim_dummy_read(); + } + + /* return the program status */ + return status; +} + /** * @brief enable security library function. * @param pwd: slib password @@ -825,29 +830,29 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \ (data_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ + ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ + (start_sector & FLASH_SLIB_START_SECTOR); + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ - ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ - (start_sector & FLASH_SLIB_START_SECTOR); - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); FLASH->slib_set_range = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } + return status; } @@ -911,7 +916,7 @@ uint16_t flash_slib_start_sector_get(void) * @param none * @retval uint16_t */ -uint16_t flash_slib_datstart_sector_get(void) +uint16_t flash_slib_datastart_sector_get(void) { return (uint16_t)FLASH->slib_sts1_bit.slib_dat_ss; } diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c index cd96b527c6..7041f4b019 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_gpio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -390,7 +388,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c index 6612b6e16e..5590275503 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_i2c.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -597,11 +595,90 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } /** - * @brief clear flag status + * @brief get interrupt flag status * @param i2c_x: to select the i2c peripheral. * this parameter can be one of the following values: * I2C1, I2C2. * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @brief clear flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag * this parameter can be any combination of the following values: * - I2C_BUSERR_FLAG: bus error flag. * - I2C_ARLOST_FLAG: arbitration lost flag. @@ -610,11 +687,23 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) * - I2C_PECERR_FLAG: pec receive error flag. * - I2C_TMOUT_FLAG: smbus timeout flag. * - I2C_ALERTF_FLAG: smbus alert flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag. * @retval none */ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag) { - i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x00FFFFFF); + i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00); + + if(i2c_x->sts1 & I2C_ADDR7F_FLAG) + { + UNUSED(i2c_x->sts2); + } + + if(i2c_x->sts1 & I2C_STOPF_FLAG) + { + i2c_x->ctrl1_bit.i2cen = TRUE; + } } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c index cb58807a86..c6d8560793 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_misc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c index d0c93983aa..83960a0f8f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_pwc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -202,19 +200,6 @@ void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter) SCB->SCR &= (uint32_t)~0x4; } -/** - * @brief regulate low power consumption in the deep sleep mode - * @param pwc_regulator: set the regulator state. - * this parameter can be one of the following values: - * - PWC_REGULATOR_ON - * - PWC_REGULATOR_LOW_POWER - * @retval none - */ -void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) -{ - PWC->ctrl_bit.vrsel = pwc_regulator; -} - /** * @brief enter pwc standby mode * @param none @@ -228,7 +213,10 @@ void pwc_standby_mode_enter(void) #if defined (__CC_ARM) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c index a66158b056..d7211875b0 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_rtc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the rtc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -76,7 +74,7 @@ uint32_t rtc_counter_get(void) /** * @brief rtc divider set - * @param div_value (0x0000_0000 ~ 0xFFFF_FFFF) + * @param div_value (0x0000_0000 ~ 0x000F_FFFF) * @retval none */ void rtc_divider_set(uint32_t div_value) @@ -174,6 +172,31 @@ flag_status rtc_flag_get(uint16_t flag) return status; } +/** + * @brief rtc interrupt flag get + * @param flag + * this parameter can be one of the following values: + * - RTC_TS_FLAG: time second flag. + * - RTC_TA_FLAG: time alarm flag. + * - RTC_OVF_FLAG: overflow flag. + * @retval state of rtc flag + */ +flag_status rtc_interrupt_flag_get(uint16_t flag) +{ + flag_status status = RESET; + + if (((RTC->ctrll & flag) != (uint16_t)RESET) && ((RTC->ctrlh & flag) != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief rtc flag clear * @param interrupt_flag @@ -181,7 +204,7 @@ flag_status rtc_flag_get(uint16_t flag) * - RTC_TS_FLAG: time second flag. * - RTC_TA_FLAG: time alarm flag. * - RTC_OVF_FLAG: overflow flag. - * - RTC_CFGF_FLAG: rtc configuration finish flag. + * - RTC_UPDF_FLAG: rtc update finish flag. * @retval none */ void rtc_flag_clear(uint16_t flag) diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c index 10cfa0501b..e2fdd630d2 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_sdio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c index 656e4be81e..657f785bb1 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_spi.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -559,6 +557,69 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. @@ -579,23 +640,21 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c index 44f3eeb9f3..2b9d367c33 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_tmr.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -71,16 +69,20 @@ void tmr_reset(tmr_type *tmr_x) crm_periph_reset(CRM_TMR4_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR4_PERIPH_RESET, FALSE); } +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) else if(tmr_x == TMR5) { crm_periph_reset(CRM_TMR5_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR5_PERIPH_RESET, FALSE); } +#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7) else if(tmr_x == TMR8) { crm_periph_reset(CRM_TMR8_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR8_PERIPH_RESET, FALSE); } +#endif else if(tmr_x == TMR9) { crm_periph_reset(CRM_TMR9_PERIPH_RESET, TRUE); @@ -96,6 +98,7 @@ void tmr_reset(tmr_type *tmr_x) crm_periph_reset(CRM_TMR11_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR11_PERIPH_RESET, FALSE); } +#endif } /** @@ -235,11 +238,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) { /* set the repetition counter value */ - if((tmr_x == TMR1) || (tmr_x == TMR8)) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -277,8 +276,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10, * TMR11 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -319,23 +317,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -363,38 +361,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -754,7 +752,12 @@ void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state) void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state) { /* tmr 32 bit function(plus mode) enable,only for TMR2/TMR5 */ - if((tmr_x == TMR2) || (tmr_x == TMR5)) + if((tmr_x == TMR2) +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) + || (tmr_x == TMR5) +#endif + ) { tmr_x->ctrl1_bit.pmen = new_state; } @@ -815,6 +818,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -824,6 +828,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -833,6 +838,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -842,6 +848,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1076,15 +1083,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1319,6 +1326,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10, + * TMR11 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1704,7 +1745,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR8 diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c index 14e5210faa..4acbc62d8d 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usart.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,11 +59,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE); } +#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7) else if(usart_x == USART3) { crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE); } +#endif +#if defined (AT32F413Rx) else if(usart_x == UART4) { crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE); @@ -76,6 +77,7 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE); } +#endif } /** @@ -88,6 +90,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -568,6 +573,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -579,6 +657,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -591,7 +674,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c index cea418ed99..5861f145a1 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usb.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -127,6 +125,7 @@ void usb_usbbufs_enable(usbd_type *usbx, confirm_state state) g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS; CRM->misc1_bit.usbbufs = FALSE; } + UNUSED(usbx); } /** @@ -245,6 +244,7 @@ void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE); } } + UNUSED(usbx); } @@ -304,6 +304,7 @@ void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE); } } + UNUSED(usbx); } /** @@ -418,6 +419,7 @@ void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info) { USB_SET_RXSTS(ept_info->eptn, USB_RX_STALL) } + UNUSED(usbx); } /** @@ -519,6 +521,40 @@ flag_status usb_flag_get(usbd_type *usbx, uint16_t flag) return status; } +/** + * @brief get interrupt flag of usb. + * @param usbx: select the usb peripheral + * @param flag: select the usb flag + * this parameter can be one of the following values: + * - USB_LSOF_FLAG + * - USB_SOF_FLAG + * - USB_RST_FLAG + * - USB_SP_FLAG + * - USB_WK_FLAG + * - USB_BE_FLAG + * - USB_UCFOR_FLAG + * - USB_TC_FLAG + * @retval none + */ +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag) +{ + flag_status status = RESET; + + if(flag == USB_TC_FLAG) + { + if(usbx->intsts & USB_TC_FLAG) + status = SET; + } + else + { + if((usbx->intsts & flag) && (usbx->ctrl & flag)) + { + status = SET; + } + } + return status; +} + /** * @brief clear flag of usb. * @param usbx: select the usb peripheral diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c index 94d779c7a8..d8d13dd61e 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c index 6de009cf99..471531a604 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wwdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c index bd1e931849..3d7cfff865 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f415.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h index fee8791971..32f4107388 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f415.h - * @version v2.0.5 - * @date 2022-05-20 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,11 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h index de84b42322..073592c72f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_adc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -571,6 +569,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h index fb37904e87..cd0df047b9 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_can.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -963,6 +961,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h index f53353eeac..0800235613 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_cmp.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 cmp header file ************************************************************************** * Copyright notice & Disclaimer @@ -52,10 +50,9 @@ extern "C" { */ typedef enum { - CMP_NON_INVERTING_PA5 = 0x00, /*!< comparator non-inverting connect to pa5 */ - CMP_NON_INVERTING_PA1 = 0x01, /*!< comparator non-inverting connect to pa1 */ - CMP_NON_INVERTING_PA0 = 0x02, /*!< comparator non-inverting connect to pa0 */ - CMP_NON_INVERTING_VSSA = 0x03 /*!< comparator non-inverting connect to vssa */ + CMP_NON_INVERTING_PA5_PA7 = 0x00, /*!< comparator1/2 non-inverting connect to pa5/pa7 */ + CMP_NON_INVERTING_PA1_PA3 = 0x01, /*!< comparator1/2 non-inverting connect to pa1/pa3 */ + CMP_NON_INVERTING_PA0_PA2 = 0x02, /*!< comparator1/2 non-inverting connect to pa0/pa2 */ } cmp_non_inverting_type; /** @@ -69,8 +66,7 @@ typedef enum CMP_INVERTING_VREFINT = 0x03, /*!< comparator inverting connect to vrefint */ CMP_INVERTING_PA4 = 0x04, /*!< comparator inverting connect to pa4 */ CMP_INVERTING_PA5 = 0x05, /*!< comparator inverting connect to pa5 */ - CMP_INVERTING_PA0 = 0x06, /*!< comparator inverting connect to pa0 */ - CMP_INVERTING_PA2 = 0x07 /*!< comparator inverting connect to pa2 */ + CMP_INVERTING_PA0_PA2 = 0x06, /*!< comparator1/2 inverting connect to pa0/pa2 */ } cmp_inverting_type; /** @@ -79,11 +75,12 @@ typedef enum typedef enum { CMP_SPEED_FAST = 0x00, /*!< comparator selected fast speed */ - CMP_SPEED_MEDIUM = 0x01, /*!< comparator selected medium speed */ - CMP_SPEED_SLOW = 0x02, /*!< comparator selected slow speed */ - CMP_SPEED_ULTRALOW = 0x03 /*!< comparator selected ultralow speed */ + CMP_SPEED_SLOW = 0x01, /*!< comparator selected slow speed */ } cmp_speed_type; +#define CMP_OUTPUT_TMR1CXORAW_OFF CMP_OUTPUT_TMR1CHCLR +#define CMP_OUTPUT_TMR2CXORAW_OFF CMP_OUTPUT_TMR2CHCLR +#define CMP_OUTPUT_TMR3CXORAW_OFF CMP_OUTPUT_TMR3CHCLR /** * @brief cmp output type */ @@ -213,6 +210,7 @@ void cmp_enable(cmp_sel_type cmp_sel, confirm_state new_state); void cmp_input_shift_enable(confirm_state new_state); uint32_t cmp_output_value_get(cmp_sel_type cmp_sel); void cmp_write_protect_enable(cmp_sel_type cmp_sel); +void cmp_double_mode_enable(confirm_state new_state); /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h index 9b4ce4b8ba..980d0f6c27 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h index 60b14931a6..96d9c694ab 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crm.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -135,7 +133,7 @@ typedef enum CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */ - CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ + CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */ } crm_periph_clock_type; @@ -176,7 +174,7 @@ typedef enum CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */ - CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ + CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */ } crm_periph_reset_type; @@ -270,7 +268,7 @@ typedef enum CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */ CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */ CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */ - CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ + CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ } crm_pll_fref_type; /** @@ -866,6 +864,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); @@ -896,7 +895,7 @@ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value); void crm_usb_clock_source_select(crm_usb_clock_source_type value); void crm_clkout_div_set(crm_clkout_div_type clkout_div); void crm_otgfs_ep3_remap_enable(confirm_state new_state); -void crm_usbdiv_reset(confirm_state new_state); +void crm_usbdiv_reset(void); /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h index b44d57ff09..08c7ae6bdf 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_debug.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 debug header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h index f861e3b7f8..33d584f40e 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_def.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h index cf88b9ce99..c94c30ec5f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_dma.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -500,6 +498,7 @@ void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number); uint16_t dma_data_number_get(dma_channel_type* dmax_channely); void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h index 9afe8eb4a3..268654d395 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_ertc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 ertc header file ************************************************************************** * Copyright notice & Disclaimer @@ -89,6 +87,12 @@ extern "C" { #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */ #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */ +/** + * @brief compatible with older versions + */ +#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS +#define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS + /** * @} */ @@ -166,8 +170,8 @@ typedef enum ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01, /*!< the wake up timer clock is ERTC_CLK / 8 */ ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02, /*!< the wake up timer clock is ERTC_CLK / 4 */ ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03, /*!< the wake up timer clock is ERTC_CLK / 2 */ - ERTC_WAT_CLK_CK_A_16BITS = 0x04, /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT */ - ERTC_WAT_CLK_CK_A_17BITS = 0x06 /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT + 65535 */ + ERTC_WAT_CLK_CK_B_16BITS = 0x04, /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT */ + ERTC_WAT_CLK_CK_B_17BITS = 0x06 /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT + 65535 */ } ertc_wakeup_clock_type; /** @@ -1172,6 +1176,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h index 76170acbaa..82cd8d1dc2 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_exint.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -211,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h index 8880db8844..f8ac8aa348 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_flash.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 flash header file ************************************************************************** * Copyright notice & Disclaimer @@ -141,7 +139,7 @@ extern "C" { * - FLASH_WAIT_CYCLE_3 * - FLASH_WAIT_CYCLE_4 */ -#define flash_psr_set(wtcyc) (FLASH->psr |= (uint32_t)(0x150 | wtcyc)) +#define flash_psr_set(wtcyc) (FLASH->psr = (uint32_t)(0x10 | wtcyc)) /** @defgroup FLASH_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h index 8bf9de4c4a..0fcb059383 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_gpio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -789,7 +787,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source); void gpio_event_output_enable(confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h index d3786ba240..1887b2afbd 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_i2c.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -380,6 +378,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h index cc2cb6fb71..5bda9d89de 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_misc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h index 48cb7b9ac6..363cf962ec 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_pwc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 pwc header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,7 +58,7 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h index f8bac257d9..764bf371da 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_sdio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -577,7 +575,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -587,6 +585,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h index d4852dfd16..484a7faeed 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_spi.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -474,6 +472,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h index 6f19fd6485..46e983c445 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_tmr.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -391,6 +389,15 @@ typedef enum TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */ }tmr_wp_level_type; +/** + * @brief tmr output channel switch selection type + */ +typedef enum +{ + TMR_CH_SWITCH_SELECT_EXT = 0x00, /*!< tmr output channel switch select ext pin */ + TMR_CH_SWITCH_SELECT_CXORAW_OFF = 0x01, /*!< tmr output channel switch select cxoraw off signal */ +}tmr_ch_switch_select_type ; + /** * @brief tmr output config type */ @@ -489,7 +496,7 @@ typedef struct struct { __IO uint32_t smsel : 3; /* [2:0] */ - __IO uint32_t reserved1 : 1; /* [3] */ + __IO uint32_t cossel : 1; /* [3] */ __IO uint32_t stis : 3; /* [6:4] */ __IO uint32_t sts : 1; /* [7] */ __IO uint32_t esf : 4; /* [11:8] */ @@ -869,6 +876,7 @@ void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type t confirm_state new_state); void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ confirm_state new_state); +void tmr_output_channel_switch_select(tmr_type *tmr_x, tmr_ch_switch_select_type switch_sel); void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ confirm_state new_state); void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state); @@ -882,7 +890,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -894,6 +902,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h index 20b43c6f99..4236e75311 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usart.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -318,9 +316,13 @@ typedef struct #define USART1 ((usart_type *) USART1_BASE) #define USART2 ((usart_type *) USART2_BASE) +#if defined (AT32F415Cx) || defined (AT32F415Rx) #define USART3 ((usart_type *) USART3_BASE) +#endif +#if defined (AT32F415Rx) #define UART4 ((usart_type *) UART4_BASE) #define UART5 ((usart_type *) UART5_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -354,6 +356,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h index 41ec1d405d..2c02ba5fcc 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usb.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -707,6 +705,7 @@ typedef struct __IO uint32_t nptxfspcavail : 16; /* [15:0] */ __IO uint32_t nptxqspcavail : 8; /* [23:16] */ __IO uint32_t nptxqtop : 7; /* [30:24] */ + __IO uint32_t reserved1 : 1; /* [31] */ } gnptxsts_bit; }; diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h index 3881388747..58afd01f0c 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h index a79ee9348f..8654f02a6f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wwdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c index bb9a9ff73f..d08e298040 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_adc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -84,7 +82,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -314,117 +312,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -472,66 +395,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -807,10 +687,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -865,6 +745,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c index a9c16ccac4..e5ee91b32c 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_can.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -925,6 +923,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c index 6463bd4154..34f31d14c9 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_cmp.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -95,7 +93,7 @@ void cmp_init(cmp_sel_type cmp_sel, cmp_init_type* cmp_init_struct) void cmp_default_para_init(cmp_init_type *cmp_init_struct) { /* reset cmp init structure parameters values */ - cmp_init_struct->cmp_non_inverting = CMP_NON_INVERTING_PA1; + cmp_init_struct->cmp_non_inverting = CMP_NON_INVERTING_PA1_PA3; cmp_init_struct->cmp_inverting = CMP_INVERTING_1_4VREFINT; cmp_init_struct->cmp_speed = CMP_SPEED_FAST; cmp_init_struct->cmp_output = CMP_OUTPUT_NONE; @@ -173,6 +171,16 @@ void cmp_write_protect_enable(cmp_sel_type cmp_sel) } } +/** + * @brief enable or disable double comparator mode + * @param new_state (TRUE or FALSE) + * @retval none + */ +void cmp_double_mode_enable(confirm_state new_state) +{ + CMP->ctrlsts1_bit.dcmpen = new_state; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c index a7826ae60f..3ed9f1f8cd 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c index 989a3d9138..a1a6de1bf0 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crm.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -414,6 +470,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 75 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -430,6 +487,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 75 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -521,6 +579,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu { CRM->cfg_bit.pllrcs = FALSE; pllrcfreq = (HICK_VALUE / 2); + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -610,6 +669,7 @@ void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ if(clock_source == CRM_PLL_SOURCE_HICK) { CRM->cfg_bit.pllrcs = FALSE; + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -644,6 +704,7 @@ void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** @@ -927,12 +988,13 @@ void crm_otgfs_ep3_remap_enable(confirm_state new_state) * * at32f415xx revision C: (support) * usb divider(CRM_CFG[usbdiv]) support to be reset. - * @param new_state (TRUE or FALSE) + * @param none * @retval none */ -void crm_usbdiv_reset(confirm_state new_state) +void crm_usbdiv_reset(void) { - CRM->otg_extctrl_bit.usbdivrst = new_state; + CRM->otg_extctrl_bit.usbdivrst = 1; + CRM->otg_extctrl_bit.usbdivrst = 0; } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c index c05cd3a76e..40f810e92a 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_debug.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the debug firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c index e1aafacb00..436e2f488d 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_dma.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -273,6 +271,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re } } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c index 40517dcb5d..6ee49f4f9e 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_ertc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the ertc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -98,15 +96,9 @@ error_status ertc_wait_update(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - /* clear updf flag */ ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7); - /* enable write protection */ - ertc_write_protect_enable(); - while(ERTC->sts_bit.updf == 0) { if(timeout == 0) @@ -164,9 +156,6 @@ error_status ertc_init_mode_enter(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - if(ERTC->sts_bit.imf == 0) { /* enter init mode */ @@ -331,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -406,7 +395,7 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - (void) (ERTC->sts); + UNUSED(ERTC->sts); reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -724,8 +713,8 @@ uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x) * - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8. * - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4. * - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2. - * - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT - * - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535. + * - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT + * - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535. * @retval none. */ void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock) @@ -1437,6 +1426,53 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1481,13 +1517,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c index 86be50c982..873a6445c5 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_exint.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -155,6 +153,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c index 5922395942..8ab09d2f8e 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_flash.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -173,22 +171,17 @@ void flash_lock(void) flash_status_type flash_sector_erase(uint32_t sector_address) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } /* return the erase status */ return status; } @@ -202,21 +195,16 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -239,41 +227,36 @@ flash_status_type flash_user_system_data_erase(void) fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the erase status */ return status; } @@ -288,19 +271,15 @@ flash_status_type flash_user_system_data_erase(void) flash_status_type flash_word_program(uint32_t address, uint32_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -315,19 +294,15 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) flash_status_type flash_halfword_program(uint32_t address, uint16_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -342,19 +317,15 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type flash_byte_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -369,24 +340,22 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -409,42 +378,38 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -472,38 +437,36 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - if(new_state == FALSE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* Wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + /* return the flash access protection operation status */ return status; } @@ -530,65 +493,63 @@ flag_status flash_fap_status_get(void) flash_status_type flash_fap_high_level_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + if(new_state == FALSE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + FLASH->ctrl_bit.fap_hl_dis = TRUE; + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - if(new_state == FALSE) + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + + if(status == FLASH_OPERATE_DONE) { - FLASH->ctrl_bit.fap_hl_dis = TRUE; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } - } - else - { - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_HIGH_LEVEL_KEY; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + else + { + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + + if(status == FLASH_OPERATE_DONE) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_HIGH_LEVEL_KEY; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + } + } + /* return the flash access protection operation status */ return status; } @@ -625,26 +586,22 @@ flag_status flash_fap_high_level_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -692,29 +649,28 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \ (data_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ + ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ + (start_sector & FLASH_SLIB_START_SECTOR); + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ - ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ - (start_sector & FLASH_SLIB_START_SECTOR); - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); FLASH->slib_set_range = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } + return status; } @@ -824,21 +780,20 @@ void flash_boot_memory_extension_mode_enable(void) flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t data_start_sector) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); FLASH->em_slib_set = (uint32_t)(data_start_sector << 16) + (uint32_t)0x5AA5; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } + return status; } diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c index 5e2cf8036b..8e15cd863f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_gpio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -390,7 +388,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c index 47988ebe5e..ca00f85b02 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_i2c.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -597,11 +595,90 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } /** - * @brief clear flag status + * @brief get interrupt flag status * @param i2c_x: to select the i2c peripheral. * this parameter can be one of the following values: * I2C1, I2C2. * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @brief clear flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag * this parameter can be any combination of the following values: * - I2C_BUSERR_FLAG: bus error flag. * - I2C_ARLOST_FLAG: arbitration lost flag. @@ -610,11 +687,23 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) * - I2C_PECERR_FLAG: pec receive error flag. * - I2C_TMOUT_FLAG: smbus timeout flag. * - I2C_ALERTF_FLAG: smbus alert flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag. * @retval none */ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag) { - i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x00FFFFFF); + i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00); + + if(i2c_x->sts1 & I2C_ADDR7F_FLAG) + { + UNUSED(i2c_x->sts2); + } + + if(i2c_x->sts1 & I2C_STOPF_FLAG) + { + i2c_x->ctrl1_bit.i2cen = TRUE; + } } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c index 90719fde7a..6d31cb3fca 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_misc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c index 75f4134496..28e25dca53 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_pwc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -228,7 +226,10 @@ void pwc_standby_mode_enter(void) #if defined (__CC_ARM) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c index d9d878261e..b5ca274473 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_sdio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c index fc0f41d5ff..b9081f4e41 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_spi.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -559,6 +557,69 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. @@ -579,23 +640,21 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c index 9890d8c563..9fe05200ed 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_tmr.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -225,11 +223,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) { /* set the repetition counter value */ - if(tmr_x == TMR1) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -264,8 +258,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR9, TMR10, TMR11 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -304,23 +297,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if(tmr_x == TMR1) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -348,38 +341,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if(tmr_x == TMR1) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if(tmr_x == TMR1) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -660,6 +653,23 @@ void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type } } +/** + * @brief select tmr output channel switch source + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR3 + * @param switch_sel + * this parameter can be one of the following values: + * - TMR_CH_SWITCH_SELECT_EXT + * - TMR_CH_SWITCH_SELECT_CXORAW_OFF + * @retval none + */ +void tmr_output_channel_switch_select(tmr_type *tmr_x, tmr_ch_switch_select_type switch_sel) +{ + /* select tmr output channel switch source */ + tmr_x->stctrl_bit.cossel = switch_sel; +} + /** * @brief set tmr output channel switch * @param tmr_x: select the tmr peripheral. @@ -788,6 +798,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -797,6 +808,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -806,6 +818,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -815,6 +828,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1046,15 +1060,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1286,6 +1300,39 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR9, TMR10, TMR11 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1666,7 +1713,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1 diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c index 3d5e17263f..b3a4c1d251 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usart.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,11 +59,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE); } +#if defined (AT32F415Cx) || defined (AT32F415Rx) else if(usart_x == USART3) { crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE); } +#endif +#if defined (AT32F415Rx) else if(usart_x == UART4) { crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE); @@ -76,6 +77,7 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE); } +#endif } /** @@ -88,6 +90,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -568,6 +573,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -579,6 +657,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -591,7 +674,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c index cb0c758dda..7ec0a09bae 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usb.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -102,7 +100,7 @@ void usb_global_init(otg_global_type *usbx) */ otg_global_type *usb_global_select_core(uint8_t usb_id) { - /* use otg1 */ + UNUSED(usb_id); return OTG1_GLOBAL; } @@ -442,6 +440,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin uint32_t n_index; uint32_t nhbytes = (nbytes + 3) / 4; uint32_t *pbuf = (uint32_t *)pusr_buf; + UNUSED(num); for(n_index = 0; n_index < nhbytes; n_index ++) { #if defined (__ICCARM__) && (__VER__ < 7000000) @@ -1015,11 +1014,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE) { usb_chh->hcchar_bit.chdis = TRUE; - if((usbx->gnptxsts & 0xFFFF) == 0) + if((usbx->gnptxsts_bit.nptxqspcavail) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) @@ -1034,11 +1032,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) else { usb_chh->hcchar_bit.chdis = TRUE; - if((usb_host->hptxsts & 0xFFFF) == 0) + if((usb_host->hptxsts_bit.ptxqspcavil) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c index 24d1803bb7..cde5251a4d 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c index 9a1e460baa..53d8f0a9b5 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wwdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h b/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h index 26de400131..1a5c2cea5e 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h @@ -44,6 +44,10 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) #define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h index c0585c0500..20b80606bc 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h @@ -252,17 +252,15 @@ typedef struct __IO uint32_t ocdmaen : 1; /* [8] */ __IO uint32_t reserved2 : 2; /* [10:9] */ __IO uint32_t dtalign : 1; /* [11] */ - __IO uint32_t pctesel_l : 3; /* [14:12] */ + __IO uint32_t pctesel : 3; /* [14:12] */ __IO uint32_t pcten : 1; /* [15] */ __IO uint32_t reserved3 : 1; /* [16] */ - __IO uint32_t octesel_l : 3; /* [19:17] */ + __IO uint32_t octesel : 3; /* [19:17] */ __IO uint32_t octen : 1; /* [20] */ __IO uint32_t pcswtrg : 1; /* [21] */ __IO uint32_t ocswtrg : 1; /* [22] */ __IO uint32_t itsrven : 1; /* [23] */ - __IO uint32_t pctesel_h : 1; /* [24] */ - __IO uint32_t octesel_h : 1; /* [25] */ - __IO uint32_t reserved4 : 6; /* [31:26] */ + __IO uint32_t reserved4 : 8; /* [31:24] */ } ctrl2_bit; }; @@ -564,6 +562,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h index 564c171c92..625c622ef9 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h @@ -82,6 +82,8 @@ typedef enum CMP_SPEED_ULTRALOW = 0x03 /*!< comparator selected ultralow speed */ } cmp_speed_type; +#define CMP_OUTPUT_TMR1CXORAW_OFF CMP_OUTPUT_TMR1CHCLR +#define CMP_OUTPUT_TMR3CXORAW_OFF CMP_OUTPUT_TMR3CHCLR /** * @brief cmp output type */ @@ -256,7 +258,7 @@ uint32_t cmp_output_value_get(cmp_sel_type cmp_sel); void cmp_write_protect_enable(cmp_sel_type cmp_sel); void cmp_filter_config(uint16_t high_pulse_cnt, uint16_t low_pulse_cnt, confirm_state new_state); void cmp_blanking_config(cmp_blanking_type blank_sel); -void cmp_scal_brg_config(uint32_t scal_brg); +void cmp_scal_brg_config(cmp_scal_brg_type scal_brg); /** * @} diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h index b7d8d1e860..7a7e2d998a 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h @@ -66,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -105,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -129,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h index da1c269736..bedf1179be 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h @@ -124,7 +124,7 @@ typedef enum CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */ - CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ + CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */ } crm_periph_clock_type; @@ -158,7 +158,7 @@ typedef enum CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */ - CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ + CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */ } crm_periph_reset_type; @@ -252,7 +252,7 @@ typedef enum CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */ CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */ CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */ - CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ + CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ } crm_pll_fref_type; /** @@ -789,6 +789,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h index 58f50e3240..33fd6f779f 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h @@ -366,6 +366,7 @@ uint16_t dma_data_number_get(dma_channel_type* dmax_channely); void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type* dma_init_struct); void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h index 65fc1dcdc2..0038e7a35f 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h @@ -885,6 +885,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h index c29d44abcc..4cfd7c6b80 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h @@ -206,6 +206,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h index 5498dfbf0b..c91f7d73d5 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h @@ -25,45 +25,45 @@ /** porta iomux table -------------------------------------------------------------------------------------------------------------------------------- - pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | + pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | -------------------------------------------------------------------------------------------------------------------------------- - pa0 | | usart2_cts | | | i2c2_scl | tmr1_etr | | comp_out | + pa0 | | usart2_cts | | | i2c2_scl | tmr1_etr | | comp_out | -------------------------------------------------------------------------------------------------------------------------------- - pa1 | eventout | usart2_rts | | | i2c2_sda | tmr15_ch1c | | | + pa1 | eventout | usart2_rts | | | i2c2_sda | tmr15_ch1c | | | -------------------------------------------------------------------------------------------------------------------------------- - pa2 | tmr15_ch1 | usart2_tx | | | | | | | + pa2 | tmr15_ch1 | usart2_tx | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa3 | tmr15_ch2 | usart2_rx | | | | i2s2_mck | | | + pa3 | tmr15_ch2 | usart2_rx | | | | i2s2_mck | | | -------------------------------------------------------------------------------------------------------------------------------- - pa4 | spi1_nss | usart2_ck | | | tmr14_ch1 | | | | - | i2s1_ws | | | | | | | | + pa4 | spi1_nss | usart2_ck | | | tmr14_ch1 | | | | + | i2s1_ws | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa5 | spi1_sck | | | | | | | | - | i2s1_ck | | | | | | | | + pa5 | spi1_sck | | | | | | | | + | i2s1_ck | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa6 | spi1_miso | tmr3_ch1 | tmr1_bkin | i2s2_mck | | tmr16_ch1 | eventout | comp_out | + pa6 | spi1_miso | tmr3_ch1 | tmr1_bkin | i2s2_mck | | tmr16_ch1 | eventout | comp_out | | i2s1_mck | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa7 | spi1_mosi | tmr3_ch2 | tmr1_ch1c | | tmr14_ch1 | tmr17_ch1 | eventout | | - | i2s1_sd | | | | | | | | + pa7 | spi1_mosi | tmr3_ch2 | tmr1_ch1c | | tmr14_ch1 | tmr17_ch1 | eventout | | + | i2s1_sd | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa8 | clkout | usart1_ck | tmr1_ch1 | eventout | usart2_tx | | | i2c2_scl | + pa8 | clkout | usart1_ck | tmr1_ch1 | eventout | usart2_tx | | | i2c2_scl | -------------------------------------------------------------------------------------------------------------------------------- - pa9 | tmr15_bkin | usart1_tx | tmr1_ch2 | | i2c1_scl | clkout | | i2c2_smba | + pa9 | tmr15_bkin | usart1_tx | tmr1_ch2 | | i2c1_scl | clkout | | i2c2_smba | -------------------------------------------------------------------------------------------------------------------------------- - pa10 | tmr17_bkin | usart1_rx | tmr1_ch3 | | i2c1_sda | | | | + pa10 | tmr17_bkin | usart1_rx | tmr1_ch3 | | i2c1_sda | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa11 | eventout | usart1_cts | tmr1_ch4 | | i2c1_smba | i2c2_scl | | comp_out | + pa11 | eventout | usart1_cts | tmr1_ch4 | | i2c1_smba | i2c2_scl | | comp_out | ----------------------------- -------------------------------------------------------------------------------------------------- - pa12 | eventout | usart1_rts | tmr1_etr | | | i2c2_sda | | | + pa12 | eventout | usart1_rts | tmr1_etr | | | i2c2_sda | | | -------------------------------------------------------------------------------------------------------------------------------- - pa13 | swdio | ir_out | | | | | spi2_miso | | + pa13 | swdio | ir_out | | | | | spi2_miso | | | | | | | | | i2s2_mck | | -------------------------------------------------------------------------------------------------------------------------------- - pa14 | swclk | usart2_tx | | | | | spi2_mosi | | + pa14 | swclk | usart2_tx | | | | | spi2_mosi | | | | | | | | | i2s2_sd | | -------------------------------------------------------------------------------------------------------------------------------- - pa15 | spi1_nss | usart2_rx | | | | | spi2_nss | | + pa15 | spi1_nss | usart2_rx | | | | | spi2_nss | | | i2s1_ws | | | eventout | | | i2s2_ws | | -------------------------------------------------------------------------------------------------------------------------------- */ @@ -71,20 +71,20 @@ /** portb iomux table -------------------------------------------------------------------------------------------------------------------------------- - pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | + pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | -------------------------------------------------------------------------------------------------------------------------------- - pb0 | eventout | tmr3_ch3 | tmr1_ch2c | usart2_rx | | | i2s1_mck | | + pb0 | eventout | tmr3_ch3 | tmr1_ch2c | usart2_rx | | | i2s1_mck | | -------------------------------------------------------------------------------------------------------------------------------- - pb1 | tmr14_ch1 | tmr3_ch4 | tmr1_ch3c | | | | spi2_sck | | - | | | | | | | i2s2_ck | | + pb1 | tmr14_ch1 | tmr3_ch4 | tmr1_ch3c | | | | spi2_sck | | + | | | | | | | i2s2_ck | | -------------------------------------------------------------------------------------------------------------------------------- - pb2 | | | tmr3_etr | | | | | | + pb2 | | | tmr3_etr | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pb3 | spi1_sck | eventout | | | | | spi2_sck | | - | i2s1_ck | | | | | | i2s2_ck | | + pb3 | spi1_sck | eventout | | | | | spi2_sck | | + | i2s1_ck | | | | | | i2s2_ck | | -------------------------------------------------------------------------------------------------------------------------------- - pb4 | spi1_miso | tmr3_ch1 | eventout | | | tmr17_bkin | spi2_miso | i2c2_sda | - | i2s1_mck | | | | | | spi2_mck | | + pb4 | spi1_miso | tmr3_ch1 | eventout | | | tmr17_bkin | spi2_miso | i2c2_sda | + | i2s1_mck | | | | | | spi2_mck | | -------------------------------------------------------------------------------------------------------------------------------- pb5 | spi1_mosi | tmr3_ch2 | tmr16_bkin | i2c1_smba | | | spi2_mosi | | | i2s1_sd | | | | | | i2s2_sd | | @@ -120,7 +120,7 @@ /** portf iomux table -------------------------------------------------------------------------------------------------------------------------------- - pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | + pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | -------------------------------------------------------------------------------------------------------------------------------- pf0 | | i2c1_sda | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h index bd3ef09fe5..08ddaba607 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h @@ -378,6 +378,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h index 34a8fdfa34..83dcec74f9 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h @@ -58,10 +58,10 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ -#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6 */ -#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ +#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */ +#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h index 6e16a408ad..d0c85b9958 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h @@ -55,9 +55,7 @@ extern "C" { */ typedef enum { - SCFG_IR_SOURCE_TMR16 = 0x00, /* infrared signal source select tmr16 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR16 = 0x00 /* infrared signal source select tmr16 */ } scfg_ir_source_type; /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h index ceba8caacb..a55543ff61 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h @@ -474,6 +474,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h index f174215f3b..86075ba7e7 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h @@ -236,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -923,6 +923,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h index dc68e6413c..48846d6fe4 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h @@ -351,6 +351,7 @@ void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h index f058944305..d57e0af13c 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c index e48745fce7..be56e90bae 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c @@ -83,7 +83,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -109,7 +109,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -313,117 +313,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -471,66 +396,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -570,13 +452,11 @@ void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_sele { if(adc_ordinary_trig > 7) { - adc_x->ctrl2_bit.octesel_h = 1; - adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7; + adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7; } else { - adc_x->ctrl2_bit.octesel_h = 0; - adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7; + adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7; } adc_x->ctrl2_bit.octen = new_state; } @@ -600,13 +480,11 @@ void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select { if(adc_preempt_trig > 7) { - adc_x->ctrl2_bit.pctesel_h = 1; - adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7; + adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7; } else { - adc_x->ctrl2_bit.pctesel_h = 0; - adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7; + adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7; } adc_x->ctrl2_bit.pcten = new_state; } @@ -804,10 +682,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -862,6 +740,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c index 314ec57009..ec623554bd 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c @@ -206,7 +206,7 @@ void cmp_blanking_config(cmp_blanking_type blank_sel) * - CMP_SCAL_BRG_11: vrefint = 1.2v, 3/4 vrefint = 0.9v, 1/2 vrefint = 0.6v, 1/4 vrefint = 0.3v * @retval none */ -void cmp_scal_brg_config(uint32_t scal_brg) +void cmp_scal_brg_config(cmp_scal_brg_type scal_brg) { uint32_t tmp_scal = 0, tmp_brg = 0; tmp_scal = scal_brg >> 1; diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c index 9bd0a26a8b..7b65324cfe 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c @@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c index aa014455e7..d098fdadc2 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c @@ -134,6 +134,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -621,6 +679,7 @@ void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c index 0fdf519008..80c6eabd5a 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c @@ -145,6 +145,36 @@ void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state dmax_channely->ctrl_bit.chen = new_state; } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + temp = DMA1->sts; + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c index e09a8f23d8..f9a359b5d2 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c @@ -314,7 +314,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -1216,6 +1216,45 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1255,13 +1294,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c index 8d600a63b2..da6c4d204c 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c @@ -151,6 +151,34 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * @retval state of exint flag + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag =0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c index 194482c507..1179dae1c4 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c @@ -655,7 +655,7 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ flash_status_type status = FLASH_OPERATE_DONE; /*check range param limits*/ - if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \ + if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \ (inst_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c index 345b85dd8e..0dea348122 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c @@ -594,6 +594,85 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2. + * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c index 24991eff54..e0e671e72a 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c @@ -216,17 +216,17 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) { switch(pwc_regulator) { - case 0: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 0; + case PWC_REGULATOR_ON: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = FALSE; break; - case 1: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = TRUE; break; - case 2: - PWC->ctrl2_bit.vrexlpen = 1; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_EXTRA_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = TRUE; + PWC->ctrl_bit.vrsel = TRUE; break; default: break; diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c index 26dfa7e2e3..4fc535ac98 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR16 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c index 3b7a09bd1f..0e270de541 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c @@ -559,6 +559,69 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c index fecab82075..71ae0ab299 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c @@ -770,7 +770,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: - tmr_x->cctrl_bit.c1en = FALSE; + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -780,7 +780,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: - tmr_x->cctrl_bit.c2en = FALSE; + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -790,7 +790,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: - tmr_x->cctrl_bit.c3en = FALSE; + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -800,7 +800,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: - tmr_x->cctrl_bit.c4en = FALSE; + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1272,6 +1272,39 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR3, TMR6, TMR14, TMR15, TMR16, TMR17 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1651,7 +1684,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR15, TMR16, TMR17 diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c index 2f115e22cb..19777709be 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c @@ -71,6 +71,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -559,6 +562,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1 or USART2. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c index 718fa9fff8..236b54529e 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c index 554d59dbd1..67641a9e70 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c @@ -91,8 +91,9 @@ void SystemInit (void) /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; - /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_sclk, hick_to_usb, hickdiv */ - CRM->misc1 = 0x000F0000U; + /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_usb */ + CRM->misc1 &= 0x00005000U; + CRM->misc1 |= 0x000F0000U; /* disable all interrupts enable and clear pending bits */ CRM->clkint = 0x009F0000U; @@ -118,7 +119,7 @@ void SystemInit (void) void system_core_clock_update(void) { uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0; - uint32_t temp = 0, div_value = 0; + uint32_t temp = 0, div_value = 0, psc = 0; crm_sclk_type sclk_source; static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; @@ -134,9 +135,14 @@ void system_core_clock_update(void) system_core_clock = HICK_VALUE * 6; else system_core_clock = HICK_VALUE; + + psc = CRM->misc2_bit.hick_to_sclk_div; + system_core_clock = system_core_clock >> psc; break; case CRM_SCLK_HEXT: system_core_clock = HEXT_VALUE; + psc = CRM->misc2_bit.hext_to_sclk_div; + system_core_clock = system_core_clock >> psc; break; case CRM_SCLK_PLL: /* get pll clock source */ @@ -172,6 +178,18 @@ void system_core_clock_update(void) /* ahbclk frequency */ system_core_clock = system_core_clock >> div_value; } + +/** + * @brief take some delay for waiting power stable, delay is about 60ms with frequency 8MHz. + * @param none + * @retval none + */ +void wait_for_power_stable(void) +{ + volatile uint32_t delay = 0; + for(delay = 0; delay < 50000; delay++); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h index e94c0315e2..ddf3f21b26 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h @@ -54,6 +54,7 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock) extern void SystemInit(void); extern void system_core_clock_update(void); +extern void wait_for_power_stable(void); /** * @} diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h index cdf746cf42..451390ffd6 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h @@ -179,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h index 9ada0f9d0e..252b8d6226 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h @@ -646,7 +646,7 @@ typedef struct }; /** - * @brief adc spt3 register, offset:0x10 + * @brief adc spt3 register, offset:0x50 */ union { @@ -666,7 +666,7 @@ typedef struct }; /** - * @brief adc osq4 register, offset:0x34 + * @brief adc osq4 register, offset:0x54 */ union { @@ -684,7 +684,7 @@ typedef struct }; /** - * @brief adc osq5 register, offset:0x34 + * @brief adc osq5 register, offset:0x58 */ union { @@ -702,7 +702,7 @@ typedef struct }; /** - * @brief adc osq6 register, offset:0x34 + * @brief adc osq6 register, offset:0x5c */ union { @@ -860,6 +860,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h index 144a8e298b..e6cb5294be 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h @@ -962,6 +962,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h index 0549818284..af2a297b88 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h @@ -66,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -105,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -129,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h index 88be1015bc..c28177464a 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h @@ -384,7 +384,7 @@ typedef enum CRM_USB_DIV_7 = 0x04, /*!< pllclk div7 to usbclk */ CRM_USB_DIV_6 = 0x05, /*!< pllclk div6 to usbclk */ CRM_USB_DIV_9 = 0x06, /*!< pllclk div9 to usbclk */ - CRM_USB_DIV_8 = 0x07, /*!< pllclk div8 to usbclk */ + CRM_USB_DIV_8 = 0x07 /*!< pllclk div8 to usbclk */ } crm_usb_div_type; /** @@ -1183,6 +1183,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h index c13fd117b6..45756bf3f7 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h @@ -371,6 +371,7 @@ void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data); void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2); void dac_udr_enable(dac_select_type dac_select, confirm_state new_state); flag_status dac_udr_flag_get(dac_select_type dac_select); +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select); void dac_udr_flag_clear(dac_select_type dac_select); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h index 142281933d..d0e1f34761 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h @@ -115,6 +115,7 @@ typedef struct __IO uint32_t reserved1 : 29;/* [31:3] */ } ctrl_bit; }; + /** * @brief debug apb1 frz register, offset:0x08 */ @@ -147,8 +148,9 @@ typedef struct __IO uint32_t reserved5 : 3;/* [31:29] */ } apb1_frz_bit; }; + /** - * @brief debug apb2 frz register, offset:0x0c + * @brief debug apb2 frz register, offset:0x0C */ union { @@ -167,6 +169,26 @@ typedef struct } apb2_frz_bit; }; + /** + * @brief debug reserved1 register, offset:0x10~0x1C + */ + __IO uint32_t reserved1[4]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h index ee390acb8b..8a5304f86a 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h @@ -730,6 +730,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely); void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type *dma_init_struct); void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct); @@ -745,8 +746,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state); void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state); flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag); flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h index 9e2cd2727f..a9c23541cf 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h @@ -1170,6 +1170,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h index ca07a6805d..9819749f22 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h @@ -210,6 +210,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h index 7b2223e1cf..0b623ecb3a 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h @@ -155,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -457,6 +457,7 @@ void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); void i2c_wakeup_enable(i2c_type *i2c_x, confirm_state new_state); void i2c_analog_filter_enable(i2c_type *i2c_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h index a19b269ecc..5e19bbd32e 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h @@ -58,10 +58,10 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ -#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6 */ -#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ +#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */ +#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */ /** * @brief select ldo output voltage. @@ -70,8 +70,7 @@ extern "C" { * - PWC_LDO_OUTPUT_1V3: system clock up to 150MHz. * - PWC_LDO_OUTPUT_1V2: system clock up to 120MHz. * - PWC_LDO_OUTPUT_1V0: system clock up to 64MHz. - * @note useage limited. - * PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V. + * @note none. */ #define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val) diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h index 30c2170587..85235fddea 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h @@ -54,9 +54,7 @@ extern "C" { */ typedef enum { - SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR10 = 0x00 /* infrared signal source select tmr10 */ } scfg_ir_source_type; /** @@ -277,7 +275,7 @@ typedef struct void scfg_reset(void); void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity); -uint8_t scfg_mem_map_get(void); +scfg_mem_map_type scfg_mem_map_get(void); void scfg_i2s_full_duplex_config(scfg_i2s_type i2s_full_duplex); void scfg_pvm_lock_enable(confirm_state new_state); void scfg_lockup_enable(confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h index 20b04d4207..93601d0b73 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h @@ -479,6 +479,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h index 3a2c46c427..5b3333d1cc 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h @@ -804,7 +804,8 @@ typedef struct __IO uint32_t brkv : 1; /* [13] */ __IO uint32_t aoen : 1; /* [14] */ __IO uint32_t oen : 1; /* [15] */ - __IO uint32_t reserved1 : 16; /* [31:16] */ + __IO uint32_t bkf : 4; /* [19:16] */ + __IO uint32_t reserved1 : 12;/* [31:20] */ } brk_bit; }; /** @@ -957,6 +958,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); @@ -977,6 +979,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \ tmr_dma_address_type dma_base_address); void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct); +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value); void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h index c557e0dc46..083ba99fb3 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h @@ -418,8 +418,7 @@ typedef struct #define USART5 ((usart_type *) USART5_BASE) #define USART6 ((usart_type *) USART6_BASE) #define USART7 ((usart_type *) USART7_BASE) -#if defined (AT32F423Kx) || defined (AT32F423Tx) || defined (AT32F423Cx) || \ - defined (AT32F423Rx) || defined (AT32F423Vx) +#if defined (AT32F423Rx) || defined (AT32F423Vx) #define USART8 ((usart_type *) USART8_BASE) #endif @@ -455,6 +454,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h index 674f8c1ac3..68e059cbdb 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h index f741308133..8e70019392 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h @@ -368,7 +368,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct, xmc_norsram_timing_init_type* xmc_w_timing_struct); void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state); -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c index 40286b3e6f..7d1e3d0f38 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c @@ -189,6 +189,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c index 8a4649707f..6a3c970a8f 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c @@ -888,6 +888,54 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * - ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_OCCE_FLAG + * - ADC_PCCE_FLAG + * - ADC_OCCO_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_OCCE_FLAG: + if(adc_x->sts_bit.occe && adc_x->ctrl1_bit.occeien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + case ADC_OCCO_FLAG: + if(adc_x->sts_bit.occo && adc_x->ctrl1_bit.occoien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c index 37ddae02a7..4c73f31804 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c @@ -931,6 +931,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1, CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c index 903c5fa9af..f0fa3b2c7d 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c @@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c index b572e62dd7..da2b3aaf1c 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c @@ -71,8 +71,9 @@ void crm_reset(void) /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; - /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_sclk, hick_to_usb, hickdiv */ - CRM->misc1 = 0x000F0000U; + /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_usb */ + CRM->misc1 &= 0x00005000U; + CRM->misc1 |= 0x000F0000U; /* disable all interrupts enable and clear pending bits */ CRM->clkint = 0x009F0000U; @@ -139,6 +140,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -711,7 +770,22 @@ void crm_adc_clock_select(crm_adc_clock_source_type value) */ void crm_hick_divider_select(crm_hick_div_6_type value) { + __IO uint8_t temp_div = CRM->misc2_bit.hick_to_sclk_div; + __IO uint8_t temp_sclk = CRM->misc1_bit.hick_to_sclk; + + crm_hick_sclk_div_set(CRM_HICK_SCLK_DIV_16); + /* delay */ + { + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + } + + CRM->misc1_bit.hick_to_sclk = TRUE; CRM->misc1_bit.hickdiv = value; + CRM->misc1_bit.hick_to_sclk = temp_sclk; + crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_div); } /** @@ -724,7 +798,7 @@ void crm_hick_divider_select(crm_hick_div_6_type value) */ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value) { - __IO uint8_t temp_reg = CRM->misc2_bit.hick_to_sclk_div; + __IO uint8_t temp_div = CRM->misc2_bit.hick_to_sclk_div; crm_hick_sclk_div_set(CRM_HICK_SCLK_DIV_16); /* delay */ @@ -736,9 +810,9 @@ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value) } CRM->misc1_bit.hick_to_sclk = TRUE; - crm_hick_divider_select(CRM_HICK48_NODIV); + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; CRM->misc1_bit.hick_to_sclk = value; - crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_reg); + crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_div); } /** @@ -849,7 +923,7 @@ crm_sclk_type crm_sysclk_switch_status_get(void) void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) { uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0; - uint32_t temp = 0, div_value = 0; + uint32_t temp = 0, div_value = 0, psc = 0; crm_sclk_type sclk_source; static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; @@ -867,9 +941,14 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) clocks_struct->sclk_freq = HICK_VALUE * 6; else clocks_struct->sclk_freq = HICK_VALUE; + + psc = CRM->misc2_bit.hick_to_sclk_div; + clocks_struct->sclk_freq = clocks_struct->sclk_freq >> psc; break; case CRM_SCLK_HEXT: clocks_struct->sclk_freq = HEXT_VALUE; + psc = CRM->misc2_bit.hext_to_sclk_div; + clocks_struct->sclk_freq = clocks_struct->sclk_freq >> psc; break; case CRM_SCLK_PLL: /* get pll clock source */ diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c index ca9fda4e3c..24bfb5e60e 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c @@ -414,6 +414,34 @@ flag_status dac_udr_flag_get(dac_select_type dac_select) return status; } +/** + * @brief get flag of the dac udr interrupt flag. + * @param dac_select + * this parameter can be one of the following values: + * - DAC1_SELECT + * - DAC2_SELECT + * @retval the new state of dac udr flag status(SET or RESET). + */ +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select) +{ + flag_status status = RESET; + + switch(dac_select) + { + case DAC1_SELECT: + if((DAC->sts_bit.d1dmaudrf && DAC->ctrl_bit.d1dmaudrien) != 0) + status = SET; + break; + case DAC2_SELECT: + if((DAC->sts_bit.d2dmaudrf && DAC->ctrl_bit.d2dmaudrien) != 0) + status = SET; + break; + default: + break; + } + return status; +} + /** * @brief clear the dac udr flag. * @param dac_select diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c index e0482717ed..b4d8c7c061 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c @@ -197,6 +197,48 @@ void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state dmax_channely->ctrl_bit.chen = new_state; } +/** + * @brief dma interrupt flag get. + * @param dma_flag + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag. + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if((temp & dmax_flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief dma flag get. * @param dma_flag @@ -600,6 +642,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux sync interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_SYNC_OV1_FLAG + * - DMAMUX_SYNC_OV2_FLAG + * - DMAMUX_SYNC_OV3_FLAG + * - DMAMUX_SYNC_OV4_FLAG + * - DMAMUX_SYNC_OV5_FLAG + * - DMAMUX_SYNC_OV6_FLAG + * - DMAMUX_SYNC_OV7_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + { + tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset)); + } + else + { + tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset)); + } + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + + if(dma_x == DMA1) + { + if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + /** * @brief dmamux sync flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. @@ -642,6 +756,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux request generator interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_GEN_TRIG_OV1_FLAG + * - DMAMUX_GEN_TRIG_OV2_FLAG + * - DMAMUX_GEN_TRIG_OV3_FLAG + * - DMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset)); + else + tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset)); + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + if(dma_x == DMA1) + { + if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + /** * @brief dmamux request generator flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c index 71aa4fb100..4dae593dd7 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c @@ -1402,6 +1402,55 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * - ERTC_TP2F_FLAG: tamper detection 2 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + case ERTC_TP2F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c index e3be6dd1a7..76947dcdb4 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c @@ -163,6 +163,40 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_18 + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * - EXINT_LINE_23 + * - EXINT_LINE_25 + * - EXINT_LINE_26 + * - EXINT_LINE_28 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c index 299fc41d94..14200f6860 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c @@ -43,7 +43,7 @@ * @brief reset the gpio register * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @retval none */ void gpio_reset(gpio_type *gpio_x) @@ -84,7 +84,7 @@ void gpio_reset(gpio_type *gpio_x) * @brief initialize the gpio peripheral. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param gpio_init_struct: pointer to gpio init structure. * @retval none */ @@ -134,7 +134,7 @@ void gpio_default_para_init(gpio_init_type *gpio_init_struct) * @brief read the specified input port pin. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * this parameter can be one of the following values: * - GPIO_PINS_0 @@ -175,7 +175,7 @@ flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins) * @brief read the specified gpio input data port. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @retval gpio input data port value. */ uint16_t gpio_input_data_read(gpio_type *gpio_x) @@ -187,7 +187,7 @@ uint16_t gpio_input_data_read(gpio_type *gpio_x) * @brief read the specified output port pin. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * this parameter can be one of the following values: * - GPIO_PINS_0 @@ -228,7 +228,7 @@ flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins) * @brief read the specified gpio ouput data port. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @retval gpio input data port value. */ uint16_t gpio_output_data_read(gpio_type *gpio_x) @@ -240,7 +240,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x) * @brief set the selected data port bits. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -271,7 +271,7 @@ void gpio_bits_set(gpio_type *gpio_x, uint16_t pins) * @brief clear the selected data port bits. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -302,7 +302,7 @@ void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins) * @brief toggle the selected data port bits. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -333,7 +333,7 @@ void gpio_bits_toggle(gpio_type *gpio_x, uint16_t pins) * @brief set or clear the selected data port bit. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -372,7 +372,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @brief write data to the specified gpio data port. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param port_value: specifies the value to be written to the port output data register. * @retval none */ @@ -385,7 +385,7 @@ void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) * @brief write protect gpio pins configuration registers. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * this parameter can be any combination of the following: * - GPIO_PINS_0 @@ -428,7 +428,7 @@ void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins) * @brief enable or disable gpio pins huge driven. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -468,7 +468,7 @@ void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_stat * @brief configure the pin's muxing function. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param gpio_pin_source: specifies the pin for the muxing function. * this parameter can be one of the following values: * - GPIO_PINS_SOURCE0 diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c index 22fac2df2a..c9dbebe563 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c @@ -120,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -708,6 +708,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c index d485a17c39..c3e278403c 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE @@ -77,9 +75,13 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola * - SCFG_MEM_MAP_BOOT_MEMORY * - SCFG_MEM_MAP_INTERNAL_SRAM */ -uint8_t scfg_mem_map_get(void) +scfg_mem_map_type scfg_mem_map_get(void) { - return (uint8_t)SCFG->cfg1_bit.mem_map_sel; + if(SCFG->cfg1_bit.mem_map_sel & 0x1) + { + return (scfg_mem_map_type)SCFG->cfg1_bit.mem_map_sel; + } + return SCFG_MEM_MAP_MAIN_MEMORY; } /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c index 0794c3eeb1..9ae28ac20c 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c @@ -587,6 +587,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c index 75f7f7f27e..72bba081ce 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c @@ -242,7 +242,8 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 - * @param tmr_rpr_value (0x0000~0xFFFF) + * @param tmr_rpr_value for TMR1(0x0000~0xFFFF) + * for TMR9, TMR10, TMR11, TMR12, TMR13, TMR14(0x00~0xFF) * @retval none */ void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value) @@ -286,8 +287,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -1383,6 +1383,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1642,7 +1676,7 @@ void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divide * @brief config tmr encoder mode * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR4 + * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12 * @param encoder_mode * this parameter can be one of the following values: * - TMR_ENCODER_MODE_A @@ -1776,7 +1810,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 @@ -1795,6 +1829,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) tmr_x->brk_bit.wpc = brkdt_struct->wp_level; } +/** + * @brief set tmr break input filter value + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 + * @param filter_value (0x0~0xf) + * @retval none + */ +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value) +{ + tmr_x->brk_bit.bkf = filter_value; +} + /** * @brief set tmr14 input channel remap * @param tmr_x: select the tmr peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c index dc3378dfd9..9e77885821 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c @@ -84,8 +84,7 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_USART7_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART7_PERIPH_RESET, FALSE); } -#if defined (AT32F423Kx) || defined (AT32F423Tx) || defined (AT32F423Cx) || \ - defined (AT32F423Rx) || defined (AT32F423Vx) +#if defined (AT32F423Rx) || defined (AT32F423Vx) else if(usart_x == USART8) { crm_periph_reset(CRM_USART8_PERIPH_RESET, TRUE); @@ -105,6 +104,9 @@ void usart_reset(usart_type* usart_x) * - USART_DATA_7BITS * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -139,6 +141,10 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type else { apb_clock = HICK_VALUE; + if(CRM->misc1_bit.hickdiv == CRM_HICK48_NODIV) + { + apb_clock = apb_clock * 6; + } } } else if(usart_x == USART2) @@ -159,6 +165,10 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type else { apb_clock = HICK_VALUE; + if(CRM->misc1_bit.hickdiv == CRM_HICK48_NODIV) + { + apb_clock = apb_clock * 6; + } } } else if(usart_x == USART3) @@ -179,6 +189,10 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type else { apb_clock = HICK_VALUE; + if(CRM->misc1_bit.hickdiv == CRM_HICK48_NODIV) + { + apb_clock = apb_clock * 6; + } } } else if(usart_x == USART6) @@ -292,10 +306,9 @@ void usart_receiver_enable(usart_type* usart_x, confirm_state new_state) /** * @brief usart clock config. - * @note clock config are not available for USART4, USART5, USART7 and USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4 ,USART5, USART6, USART7 or USART8. * @param clk_pol: polarity of the clock output on the ck pin. * this parameter can be one of the following values: * - USART_CLOCK_POLARITY_LOW @@ -319,10 +332,9 @@ void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, /** * @brief usart enable the ck pin. - * @note clock enable are not available for USART4, USART5, USART7 and USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4 ,USART5, USART6, USART7 or USART8. * @param new_state: TRUE or FALSE * @retval none */ @@ -507,10 +519,9 @@ void usart_break_send(usart_type* usart_x) /** * @brief config the specified usart smartcard guard time. - * @note The guard time bits are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param guard_time_val: specifies the guard time (0x00~0xFF). * @retval none */ @@ -521,10 +532,9 @@ void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val) /** * @brief config the irda/smartcard division. - * @note the division are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param div_val: specifies the division. * @retval none */ @@ -535,10 +545,9 @@ void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val) /** * @brief enable or disable the usart smart card mode. - * @note the smart card mode are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param new_state: new state of the smart card mode. * this parameter can be: TRUE or FALSE. * @retval none @@ -550,10 +559,9 @@ void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state) /** * @brief enable or disable nack transmission in smartcard mode. - * @note the smart card nack are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param new_state: new state of the nack transmission. * this parameter can be: TRUE or FALSE. * @retval none @@ -609,7 +617,7 @@ void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state) * @brief configure the usart's hardware flow control. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param flow_state: specifies the hardware flow control. * this parameter can be one of the following values: * - USART_HARDWARE_FLOW_NONE @@ -679,6 +687,91 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_RTODF_FLAG: receiver time out detection flag + * - USART_CMDF_FLAG: character match detection flag + * - USART_LPWUF_FLAG: low power wake up flag + * - USART_CTSCF_FLAG: cts change flag + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + case USART_RTODF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.retodie; + break; + case USART_CMDF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.cmdie; + break; + case USART_LPWUF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.lpwufie; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -737,7 +830,7 @@ void usart_flag_clear(usart_type* usart_x, uint32_t flag) * @brief configure the usart's rs485 transmit delay time. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param start_delay_time: transmit start delay time. * @param complete_delay_time: transmit complete delay time. * @retval none diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c index 651134c6ee..86774b5658 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c index 2cf073e0cd..5d8626dfa5 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c @@ -222,7 +222,7 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne * @param r2r_timing :read timing * @retval none */ -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) { XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8; XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h index ada93a9153..321ba563d2 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h @@ -179,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h index fbca4102dc..e983e51b22 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h @@ -630,6 +630,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h index 47a2c17017..0d35df2bb3 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h @@ -961,6 +961,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h index 9bcb925e14..f792ed3e70 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h @@ -66,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -105,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -129,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h index b5fc424abb..ff85abd775 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h @@ -133,7 +133,7 @@ typedef enum CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 27), /*!< acc periph clock */ - CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ + CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */ } crm_periph_clock_type; @@ -176,7 +176,7 @@ typedef enum CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x10, 27), /*!< acc periph reset */ - CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ + CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */ } crm_periph_reset_type; @@ -270,7 +270,7 @@ typedef enum CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */ CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */ CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */ - CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ + CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ } crm_pll_fref_type; /** @@ -862,6 +862,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h index 07fa1714da..2f8531756b 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h @@ -128,6 +128,26 @@ typedef struct } ctrl_bit; }; + /** + * @brief debug reserved1 register, offset:0x08~0x1C + */ + __IO uint32_t reserved1[6]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h index 192ca907d3..b5a0328793 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h @@ -457,6 +457,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state); void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type* dma_init_struct); void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h index 619e0f59f3..786782e016 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h @@ -84,10 +84,6 @@ extern "C" { #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */ #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */ -/** - * @} - */ - /** * @brief compatible with older versions */ @@ -923,6 +919,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h index fe4379d21f..347bca09fb 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h @@ -208,6 +208,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h index 47b046e41d..c2670deab9 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h @@ -190,13 +190,13 @@ typedef struct struct { __IO uint32_t wtcyc : 3; /* [2:0] */ - __IO uint32_t hfcyc_en : 1; /* [3] */ + __IO uint32_t reserved1 : 1; /* [3] */ __IO uint32_t pft_en : 1; /* [4] */ __IO uint32_t pft_enf : 1; /* [5] */ __IO uint32_t pft_en2 : 1; /* [6] */ __IO uint32_t pft_enf2 : 1; /* [7] */ __IO uint32_t pft_lat_dis : 1; /* [8] */ - __IO uint32_t reserved1 : 23;/* [31:9] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ } psr_bit; }; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h index 09f535c4eb..55166087fe 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h @@ -155,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -455,6 +455,7 @@ void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h index daef96b898..907a0acc51 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h @@ -58,12 +58,12 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ -#define PWC_WAKEUP_PIN_4 ((uint32_t)0x00000800) /*!< standby wake-up pin4 */ -#define PWC_WAKEUP_PIN_5 ((uint32_t)0x00001000) /*!< standby wake-up pin5 */ -#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6 */ -#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ +#define PWC_WAKEUP_PIN_4 ((uint32_t)0x00000800) /*!< standby wake-up pin4(pa2) */ +#define PWC_WAKEUP_PIN_5 ((uint32_t)0x00001000) /*!< standby wake-up pin5(pc5) */ +#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */ +#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h index e1afb481f8..fc124fce2d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h @@ -65,9 +65,7 @@ typedef enum */ typedef enum { - SCFG_IR_SOURCE_TMR16 = 0x00, /* infrared signal source select tmr16 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR16 = 0x00 /* infrared signal source select tmr16 */ } scfg_ir_source_type; /** @@ -268,7 +266,7 @@ typedef struct void scfg_reset(void); void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity); -uint8_t scfg_mem_map_get(void); +scfg_mem_map_type scfg_mem_map_get(void); void scfg_pa11pa12_pin_remap(scfg_pa11pa12_remap_type pin_remap); void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source); void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h index a10911ef6e..6249f428e1 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h @@ -482,6 +482,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h index ec919c283a..68dd04f89d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h @@ -236,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -801,7 +801,8 @@ typedef struct __IO uint32_t brkv : 1; /* [13] */ __IO uint32_t aoen : 1; /* [14] */ __IO uint32_t oen : 1; /* [15] */ - __IO uint32_t reserved1 : 16; /* [31:16] */ + __IO uint32_t bkf : 4; /* [19:16] */ + __IO uint32_t reserved1 : 12;/* [31:20] */ } brk_bit; }; /** @@ -917,6 +918,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); @@ -938,6 +940,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \ tmr_dma_address_type dma_base_address); void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct); +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value); void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h index f0457e9c1c..dc0bac389d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h @@ -380,6 +380,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h index ff37f876a8..b6e5d2c9eb 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h @@ -705,6 +705,7 @@ typedef struct __IO uint32_t nptxfspcavail : 16; /* [15:0] */ __IO uint32_t nptxqspcavail : 8; /* [23:16] */ __IO uint32_t nptxqtop : 7; /* [30:24] */ + __IO uint32_t reserved1 : 1; /* [31] */ } gnptxsts_bit; }; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h index 8c6429233e..3b8364e53d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c index b583b88f26..afdd42b1bd 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c @@ -188,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c index 9baceedbc3..c9306dadab 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c @@ -82,7 +82,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -108,7 +108,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -312,117 +312,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -470,66 +395,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -803,10 +685,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -861,6 +743,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c index baa4e2b62a..bfcaf305d0 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c @@ -923,6 +923,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c index 9b702d4f34..7072f52a83 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c @@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c index c278da1a18..104eea43d1 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c @@ -134,6 +134,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c index 5d63d5f69b..6345c012a1 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c @@ -259,6 +259,38 @@ flag_status dma_flag_get(uint32_t dmax_flag) return status; } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + temp = DMA1->sts; + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief clear dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c index 96b533438a..176c41d763 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c @@ -316,7 +316,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -391,8 +391,6 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - UNUSED(ERTC->sts); - reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -1298,6 +1296,49 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1339,13 +1380,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c index e271211918..c5f013d240 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c @@ -151,6 +151,34 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_20 + * @retval state of exint flag + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag =0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c index 5425c073d3..739999ad71 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c @@ -634,7 +634,7 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ flash_status_type status = FLASH_OPERATE_DONE; /*check range param limits*/ - if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \ + if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \ (inst_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c index e25e8026dd..9b2376b94b 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c @@ -115,12 +115,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -703,6 +703,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c index ddee3898ae..8ec4982927 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c @@ -218,17 +218,17 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) { switch(pwc_regulator) { - case 0: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 0; + case PWC_REGULATOR_ON: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = FALSE; break; - case 1: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = TRUE; break; - case 2: - PWC->ctrl2_bit.vrexlpen = 1; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_EXTRA_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = TRUE; + PWC->ctrl_bit.vrsel = TRUE; break; default: break; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c index 42d1ad76fa..26a3b3858b 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE @@ -77,9 +75,13 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola * - SCFG_MEM_MAP_BOOT_MEMORY * - SCFG_MEM_MAP_INTERNAL_SRAM */ -uint8_t scfg_mem_map_get(void) +scfg_mem_map_type scfg_mem_map_get(void) { - return (uint8_t)SCFG->cfg1_bit.mem_map_sel ; + if(SCFG->cfg1_bit.mem_map_sel & 0x1) + { + return (scfg_mem_map_type)SCFG->cfg1_bit.mem_map_sel; + } + return SCFG_MEM_MAP_MAIN_MEMORY; } /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c index 880ccbe3b3..b1323e277c 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c @@ -588,6 +588,77 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c index 471ecdf035..68b860e7bf 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c @@ -775,7 +775,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: - tmr_x->cctrl_bit.c1en = FALSE; + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -785,7 +785,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: - tmr_x->cctrl_bit.c2en = FALSE; + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -795,7 +795,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: - tmr_x->cctrl_bit.c3en = FALSE; + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -805,7 +805,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: - tmr_x->cctrl_bit.c4en = FALSE; + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1277,11 +1277,46 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, TMR16, TMR17 + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 * @param tmr_flag * this parameter can be one of the following values: * - TMR_OVF_FLAG @@ -1317,7 +1352,9 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) /** * @brief clear tmr flag * @param tmr_x: select the tmr peripheral. - * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, TMR16, TMR17 + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 * @param tmr_flag * this parameter can be any combination of the following values: * - TMR_OVF_FLAG @@ -1343,7 +1380,8 @@ void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag) * @brief generate tmr event * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, TMR16, TMR17 + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 * @param tmr_event * this parameter can be one of the following values: * - TMR_OVERFLOW_SWTRIG @@ -1656,7 +1694,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR15, TMR16, TMR17 @@ -1675,6 +1713,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) tmr_x->brk_bit.wpc = brkdt_struct->wp_level; } +/** + * @brief set tmr break input filter value + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR15, TMR16, TMR17 + * @param filter_value (0x0~0xf) + * @retval none + */ +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value) +{ + tmr_x->brk_bit.bkf = filter_value; +} + /** * @brief set tmr14 input channel remap * @param tmr_x: select the tmr peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c index f4c2521fad..ddd04a0a49 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c @@ -82,6 +82,9 @@ void usart_reset(usart_type* usart_x) * - USART_DATA_7BITS * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -579,6 +582,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3 or USART4. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c index b9e8033e8a..c87a7b8a84 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c @@ -97,7 +97,7 @@ void usb_global_init(otg_global_type *usbx) */ otg_global_type *usb_global_select_core(uint8_t usb_id) { - /* use otg1 */ + UNUSED(usb_id); return OTG1_GLOBAL; } @@ -438,6 +438,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin uint32_t n_index; uint32_t nhbytes = (nbytes + 3) / 4; uint32_t *pbuf = (uint32_t *)pusr_buf; + UNUSED(num); for(n_index = 0; n_index < nhbytes; n_index ++) { #if defined (__ICCARM__) && (__VER__ < 7000000) diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c index a3842fad3b..c1d824a43a 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c index 70070c7796..4b5e42178d 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f435_437.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer @@ -37,7 +35,7 @@ /** @addtogroup AT32F435_437_system_private_defines * @{ */ -#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x400. */ /** * @} */ @@ -81,12 +79,12 @@ void SystemInit (void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); - /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ - CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ + CRM->cfg = 0; + /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h index 1365c30f43..9bff3b94fb 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f435_437.h - * @version v2.0.8 - * @date 2022-04-25 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -39,6 +37,12 @@ extern "C" { * @{ */ +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} + /** @defgroup AT32F435_437_system_exported_variables * @{ */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h index 50eac602f0..91c0d91c58 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_acc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 acc header file ************************************************************************** * Copyright notice & Disclaimer @@ -184,6 +182,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h index 9f390c9ee8..80a7069b46 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_adc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -912,6 +910,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint32_t adc_combine_ordinary_conversion_data_get(void); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h index 9fcb209d15..3dd9011386 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_can.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -1020,6 +1018,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h index 484f3abfbb..a0ff483263 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h index 5358d720d3..4e24d97e19 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crm.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -398,13 +396,12 @@ typedef enum CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */ + CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */ + CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */ + CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */ - CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */ - CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */ - CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */ - CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */ /* ahb periph2 */ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */ @@ -470,9 +467,16 @@ typedef enum CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */ + CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */ + CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */ + CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */ + CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */ + CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */ + CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */ + CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */ /* ahb periph2 */ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */ @@ -1115,9 +1119,11 @@ typedef struct __IO uint32_t reserved3 : 1; /* [23] */ __IO uint32_t dma2en : 1; /* [24] */ __IO uint32_t emacen : 1; /* [25] */ - __IO uint32_t reserved4 : 3; /* [28:26] */ + __IO uint32_t emactxen : 1; /* [26] */ + __IO uint32_t emacrxen : 1; /* [27] */ + __IO uint32_t emacptpen : 1; /* [28] */ __IO uint32_t otgfs2en : 1; /* [29] */ - __IO uint32_t reserved5 : 2; /* [31:30] */ + __IO uint32_t reserved4 : 2; /* [31:30] */ } ahben1_bit; #endif }; @@ -1287,9 +1293,11 @@ typedef struct __IO uint32_t reserved3 : 1; /* [23] */ __IO uint32_t dma2lpen : 1; /* [24] */ __IO uint32_t emaclpen : 1; /* [25] */ - __IO uint32_t reserved4 : 3; /* [28:26] */ + __IO uint32_t emactxlpen : 1; /* [26] */ + __IO uint32_t emacrxlpen : 1; /* [27] */ + __IO uint32_t emacptplpen : 1; /* [28] */ __IO uint32_t otgfs2lpen : 1; /* [29] */ - __IO uint32_t reserved5 : 2; /* [31:30] */ + __IO uint32_t reserved4 : 2; /* [31:30] */ } ahblpen1_bit; #endif }; @@ -1513,6 +1521,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h index 01cb78b8aa..a09aac8512 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dac.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 dac header file ************************************************************************** * Copyright notice & Disclaimer @@ -373,6 +371,7 @@ void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data); void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2); void dac_udr_enable(dac_select_type dac_select, confirm_state new_state); flag_status dac_udr_flag_get(dac_select_type dac_select); +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select); void dac_udr_flag_clear(dac_select_type dac_select); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h index 80adf93513..8e6ccd2846 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_mcudbg.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 mcudbg header file ************************************************************************** * Copyright notice & Disclaimer @@ -120,6 +118,7 @@ typedef struct __IO uint32_t reserved1 : 29;/* [31:3] */ } ctrl_bit; }; + /** * @brief debug apb1 frz register, offset:0x08 */ @@ -152,8 +151,9 @@ typedef struct __IO uint32_t reserved4 : 3;/* [31:29] */ } apb1_frz_bit; }; + /** - * @brief debug apb2 frz register, offset:0x0c + * @brief debug apb2 frz register, offset:0x0C */ union { @@ -172,6 +172,26 @@ typedef struct } apb2_frz_bit; }; + /** + * @brief debug reserved1 register, offset:0x10~0x1C + */ + __IO uint32_t reserved1[4]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h index 285988cd42..c6bb77604f 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_def.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h index ce8adb3d7c..974cb96a7f 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dma.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -747,6 +745,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely); void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type *dma_init_struct); void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct); @@ -762,8 +761,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state); void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state); flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag); flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h index 3169c63fa2..65d1bc5c87 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dvp.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 dvp header file ************************************************************************** * Copyright notice & Disclaimer @@ -204,17 +202,17 @@ typedef enum { DVP_STATUS_HSYN = 0x00, DVP_STATUS_VSYN = 0x01, - DVP_STATUS_OFS = 0x02 + DVP_STATUS_OFNE = 0x02 } dvp_status_basic_type; /** - * @brief dvp pcdse type + * @brief dvp pcdes type */ typedef enum { - DVP_PCDSE_CAP_FIRST = 0x00, - DVP_PCDSE_DROP_FIRST = 0x01 -} dvp_pcdse_type; + DVP_PCDES_CAP_FIRST = 0x00, + DVP_PCDES_DROP_FIRST = 0x01 +} dvp_pcdes_type; /** * @brief dvp efdf type @@ -224,18 +222,18 @@ typedef enum DVP_EFDF_BYPASS = 0x00, DVP_EFDF_YUV422_UYVY = 0x04, DVP_EFDF_YUV422_YUYV = 0x05, - DVP_EFDF_YUV444 = 0x06, + DVP_EFDF_RGB565_555 = 0x06, DVP_EFDF_Y8 = 0x07 } dvp_efdf_type; /** - * @brief dvp iduc type + * @brief dvp idus type */ typedef enum { - DVP_IDUC_MSB = 0x00, - DVP_IDUC_LSB = 0x01 -} dvp_iduc_type; + DVP_IDUS_MSB = 0x00, + DVP_IDUS_LSB = 0x01 +} dvp_idus_type; /** * @brief dvp dmabt type @@ -247,22 +245,22 @@ typedef enum } dvp_dmabt_type; /** - * @brief dvp hseis type + * @brief dvp hseid type */ typedef enum { - DVP_HSEIS_LINE_END = 0x00, - DVP_HSEIS_LINE_START = 0x01 -} dvp_hseis_type; + DVP_HSEID_LINE_END = 0x00, + DVP_HSEID_LINE_START = 0x01 +} dvp_hseid_type; /** - * @brief dvp vseis type + * @brief dvp vseid type */ typedef enum { - DVP_VSEIS_FRAME_END = 0x00, - DVP_VSEIS_FRMAE_START = 0x01 -} dvp_vseis_type; + DVP_VSEID_FRAME_END = 0x00, + DVP_VSEID_FRMAE_START = 0x01 +} dvp_vseid_type; /** * @brief dvp idun type */ @@ -301,7 +299,7 @@ typedef struct __IO uint32_t pcds : 1; /* [18] */ __IO uint32_t lcdc : 1; /* [19] */ __IO uint32_t lcds : 1; /* [20] */ - __IO uint32_t : 11;/* [31:21] */ + __IO uint32_t reserved3 : 11;/* [31:21] */ } ctrl_bit; }; @@ -315,7 +313,7 @@ typedef struct { __IO uint32_t hsyn : 1; /* [0] */ __IO uint32_t vsyn : 1; /* [1] */ - __IO uint32_t ofs : 1; /* [2] */ + __IO uint32_t ofne : 1; /* [2] */ __IO uint32_t reserved1 : 29;/* [31:3] */ } sts_bit; }; @@ -479,18 +477,18 @@ typedef struct __IO uint32_t eisre : 1; /* [0] */ __IO uint32_t efrce : 1; /* [1] */ __IO uint32_t mibe : 1; /* [2] */ - __IO uint32_t pcdse : 1; /* [3] */ + __IO uint32_t pcdes : 1; /* [3] */ __IO uint32_t efdf : 3; /* [6:4] */ __IO uint32_t reserved1 : 1; /* [7] */ __IO uint32_t idun : 2; /* [9:8] */ - __IO uint32_t iduc : 1; /* [10] */ + __IO uint32_t idus : 1; /* [10] */ __IO uint32_t reserved2 : 1; /* [11] */ __IO uint32_t dmabt : 1; /* [12] */ __IO uint32_t reserved3 : 1; /* [13] */ __IO uint32_t reserved4 : 1; /* [14] */ __IO uint32_t reserved5 : 1; /* [15] */ - __IO uint32_t hseis : 1; /* [16] */ - __IO uint32_t vseis : 1; /* [17] */ + __IO uint32_t hseid : 1; /* [16] */ + __IO uint32_t vseid : 1; /* [17] */ __IO uint32_t reserved6 : 1; /* [18] */ __IO uint32_t reserved7 : 2; /* [20:19] */ __IO uint32_t reserved8 : 11;/* [31:21] */ @@ -540,9 +538,9 @@ typedef struct __IO uint32_t frf; struct { - __IO uint32_t efrcfm : 5; /* [4:0] */ + __IO uint32_t efrcsf : 5; /* [4:0] */ __IO uint32_t reserved1 : 3; /* [7:5] */ - __IO uint32_t efrcfn : 5; /* [12:8] */ + __IO uint32_t efrctf : 5; /* [12:8] */ __IO uint32_t reserved2 : 19;/* [31:13] */ } frf_bit; }; @@ -572,10 +570,12 @@ typedef struct * @{ */ +void dvp_reset(void); +void dvp_capture_enable(confirm_state new_state); void dvp_capture_enable(confirm_state new_state); void dvp_capture_mode_set(dvp_cfm_type cap_mode); void dvp_window_crop_enable(confirm_state new_state); -void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h); +void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes); void dvp_jpeg_enable(confirm_state new_state); void dvp_sync_mode_set(dvp_sm_type sync_mode); void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec); @@ -586,20 +586,21 @@ void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol); void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc); void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl); void dvp_enable(confirm_state new_state); -void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse); +void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes); void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds); flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic); void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state); +flag_status dvp_interrupt_flag_get(uint32_t flag); flag_status dvp_flag_get(uint32_t flag); void dvp_flag_clear(uint32_t flag); void dvp_enhanced_scaling_resize_enable(confirm_state new_state); void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h); -void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state); +void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state); void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state); void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf); -void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun); +void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun); void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt); -void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis); +void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid); /** * @} diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h index 9d0d408d6c..68286e90be 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_edma.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 edma header file ************************************************************************** * Copyright notice & Disclaimer @@ -49,10 +47,10 @@ extern "C" { * @{ */ -#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error intterrupt */ -#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error intterrupt */ -#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer intterrupt */ -#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer intterrupt */ +#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error interrupt */ +#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error interrupt */ +#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer interrupt */ +#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer interrupt */ #define EDMA_FERR_INT ((uint32_t)0x00000080) /* edma fifo error interrupt */ /** @@ -1021,6 +1019,7 @@ edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx); flag_status edma_stream_status_get(edma_stream_type *edma_streamx); uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx); flag_status edma_flag_get(uint32_t edma_flag); +flag_status edma_interrupt_flag_get(uint32_t edma_flag); void edma_flag_clear(uint32_t edma_flag); /* edma 2d controller function */ @@ -1041,8 +1040,10 @@ void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state); void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state); flag_status edmamux_sync_flag_get(uint32_t flag); +flag_status edmamux_sync_interrupt_flag_get(uint32_t flag); void edmamux_sync_flag_clear(uint32_t flag); flag_status edmamux_generator_flag_get(uint32_t flag); +flag_status edmamux_generator_interrupt_flag_get(uint32_t flag); void edmamux_generator_flag_clear(uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h index 85c04805b6..12a5c338d0 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_emac.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 eth header file ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,7 @@ extern "C" { */ #define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */ +#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR /** @defgroup EMAC_smi_clock_border_definition * @brief emac smi clock border @@ -271,6 +270,15 @@ extern "C" { #define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */ #define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */ +/** + * @brief emac ptp time sign + */ +#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */ +#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */ + +#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */ +#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */ +#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */ /** @defgroup EMAC_exported_types * @{ */ @@ -346,9 +354,10 @@ typedef enum */ typedef enum { - EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ - EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ - EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ + EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ + EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */ + EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ + EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ } emac_control_frames_filter_type; /** @@ -634,6 +643,10 @@ typedef struct { uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */ uint32_t buf1addr; /*!< buffer1 address pointer */ uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */ + uint32_t extendedstatus; + uint32_t reserved1; + uint32_t timestamp_l; + uint32_t timestamp_h; } emac_dma_desc_type; /** @@ -892,7 +905,7 @@ typedef struct __IO uint32_t reserved1 : 8; /* [16:23] */ __IO uint32_t mbc : 6; /* [24:29] */ __IO uint32_t sa : 1; /* [30] */ - __IO uint32_t ae : 1; /* [31] */ + __IO uint32_t ae : 1; /* [31] */ } a1h_bit; }; @@ -1329,7 +1342,7 @@ typedef struct __IO uint32_t swr : 1; /* [0] */ __IO uint32_t da : 1; /* [1] */ __IO uint32_t dsl : 5; /* [2:6] */ - __IO uint32_t reserved1 : 1; /* [7] */ + __IO uint32_t atds : 1; /* [7] */ __IO uint32_t pbl : 6; /* [8:13] */ __IO uint32_t pr : 2; /* [14:15] */ __IO uint32_t fb : 1; /* [16] */ @@ -1337,7 +1350,7 @@ typedef struct __IO uint32_t usp : 1; /* [23] */ __IO uint32_t pblx8 : 1; /* [24] */ __IO uint32_t aab : 1; /* [25] */ - __IO uint32_t reserved2 : 6; /* [26:31] */ + __IO uint32_t reserved : 6; /* [26:31] */ } bm_bit; }; @@ -1629,6 +1642,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil uint32_t emac_received_packet_size_get(void); uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc); void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count); +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count); uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type); void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state); void emac_dma_para_init(emac_dma_config_type *control_para); @@ -1651,6 +1665,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void); uint16_t emac_dma_application_missing_frame_get(void); uint8_t emac_dma_fifo_overflow_bit_get(void); uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type); +void emac_dma_alternate_desc_size(confirm_state new_state); void emac_mmc_counter_reset(void); void emac_mmc_rollover_stop(confirm_state new_state); void emac_mmc_reset_on_read_enable(confirm_state new_state); @@ -1677,19 +1692,19 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state); void emac_ptp_snapshot_master_event_enable(confirm_state new_state); void emac_ptp_clock_node_set(emac_ptp_clock_node_type node); void emac_ptp_mac_address_filter_enable(confirm_state new_state); +flag_status emac_ptp_flag_get(uint32_t flag); void emac_ptp_subsecond_increment_set(uint8_t value); uint32_t emac_ptp_system_second_get(void); uint32_t emac_ptp_system_subsecond_get(void); confirm_state emac_ptp_system_time_sign_get(void); -void emac_ptp_system_second_set(uint32_t second); -void emac_ptp_system_subsecond_set(uint32_t subsecond); -void emac_ptp_system_time_sign_set(confirm_state sign); +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond); void emac_ptp_timestamp_addend_set(uint32_t value); void emac_ptp_target_second_set(uint32_t value); void emac_ptp_target_nanosecond_set(uint32_t value); confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status); void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq); flag_status emac_dma_flag_get(uint32_t dma_flag); +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag); void emac_dma_flag_clear(uint32_t dma_flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h index a13eafd19c..ec65ad1384 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_ertc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 ertc header file ************************************************************************** * Copyright notice & Disclaimer @@ -90,6 +88,12 @@ extern "C" { #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */ #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */ +/** + * @brief compatible with older versions + */ +#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS +#define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS + /** * @} */ @@ -167,8 +171,8 @@ typedef enum ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01, /*!< the wake up timer clock is ERTC_CLK / 8 */ ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02, /*!< the wake up timer clock is ERTC_CLK / 4 */ ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03, /*!< the wake up timer clock is ERTC_CLK / 2 */ - ERTC_WAT_CLK_CK_A_16BITS = 0x04, /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT */ - ERTC_WAT_CLK_CK_A_17BITS = 0x06 /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT + 65535 */ + ERTC_WAT_CLK_CK_B_16BITS = 0x04, /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT */ + ERTC_WAT_CLK_CK_B_17BITS = 0x06 /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT + 65535 */ } ertc_wakeup_clock_type; /** @@ -1176,6 +1180,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h index fe25afa692..ec3b73399a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_exint.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -211,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h index 19cf2d83f7..7b3e7f3df5 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_flash.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 flash header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h index c6b487d505..0e8d91a702 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_gpio.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -541,7 +539,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state); void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h index cdab00e6fe..0d2e3ba653 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_i2c.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -157,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -176,14 +174,14 @@ typedef enum } i2c_reload_stop_mode_type; /** - * @brief i2c start stop mode + * @brief i2c start mode */ typedef enum { I2C_WITHOUT_START = 0x00000000, /*!< transfer data without start condition */ I2C_GEN_START_READ = 0x00002400, /*!< read data and generate start */ I2C_GEN_START_WRITE = 0x00002000 /*!< send data and generate start */ -} i2c_start_stop_mode_type; +} i2c_start_mode_type; /** * @brief type define i2c register all @@ -452,12 +450,13 @@ void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state); void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state); flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source); void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state); -void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop); +void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start); void i2c_start_generate(i2c_type *i2c_x); void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h index 9d14517952..6189983be7 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_misc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h index 0d302a43a6..c9e731cb36 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_pwc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 pwr header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,17 +58,19 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ /** * @brief select ldo output voltage. * @param val: set the ldo output voltage. * this parameter can be one of the following values: - * - PWC_LDO_OUTPUT_1V2 - * - PWC_LDO_OUTPUT_1V3 - * - PWC_LDO_OUTPUT_1V1 - * - PWC_LDO_OUTPUT_1V0 + * - PWC_LDO_OUTPUT_1V3: system clock up to 288MHz. + * - PWC_LDO_OUTPUT_1V2: system clock up to 240MHz. + * - PWC_LDO_OUTPUT_1V1: system clock up to 192MHz. + * - PWC_LDO_OUTPUT_1V0: system clock up to 144MHz. + * @note useage limited. + * PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V. */ #define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val) @@ -97,8 +97,8 @@ typedef enum */ typedef enum { - PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */ PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */ + PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */ PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */ PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */ } pwc_ldo_output_voltage_type; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h index 4cd235ec1c..02df07778b 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_qspi.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 qspi header file ************************************************************************** * Copyright notice & Disclaimer @@ -123,11 +121,11 @@ typedef enum typedef enum { QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */ + QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */ + QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */ - QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ - QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */ } qspi_clk_div_type; @@ -179,7 +177,7 @@ typedef enum { QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */ - QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */ + QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */ } qspi_dma_fifo_thod_type; /** @@ -187,7 +185,7 @@ typedef enum */ typedef struct { - confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */ + confirm_state pe_mode_enable; /*!< performance enhance mode enable */ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */ uint8_t instruction_code; /*!< instruction code */ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */ @@ -314,17 +312,9 @@ typedef struct }; /** - * @brief qspi actr register, offset:0x14 + * @brief qspi register, offset:0x14 */ - union - { - __IO uint32_t actr; - struct - { - __IO uint32_t csdly : 4; /* [3:0] */ - __IO uint32_t reserved1 : 28;/* [31:4] */ - } actr_bit; - }; + __IO uint32_t reserved0; /** * @brief qspi fifosts register, offset:0x18 @@ -441,12 +431,12 @@ typedef struct __IO uint32_t xip_cmd_w2; struct { - __IO uint32_t xipr_dcnt : 6; /* [5:0] */ - __IO uint32_t reserved1 : 2; /* [7:6] */ + __IO uint32_t xipr_dcnt : 5; /* [4:0] */ + __IO uint32_t reserved1 : 3; /* [7:5] */ __IO uint32_t xipr_tcnt : 7; /* [14:8] */ __IO uint32_t xipr_sel : 1; /* [15] */ - __IO uint32_t xipw_dcnt : 6; /* [21:16] */ - __IO uint32_t reserved2 : 2; /* [23:22] */ + __IO uint32_t xipw_dcnt : 5; /* [20:16] */ + __IO uint32_t reserved2 : 3; /* [23:21] */ __IO uint32_t xipw_tcnt : 7; /* [30:24] */ __IO uint32_t xipw_sel : 1; /* [31] */ } xip_cmd_w2_bit; @@ -468,9 +458,24 @@ typedef struct }; /** - * @brief qspi reserved register, offset:0x40~4C + * @brief qspi ctrl3 register, offset:0x40 */ - __IO uint32_t reserved2[4]; + union + { + __IO uint32_t ctrl3; + struct + { + __IO uint32_t ispd : 6; /* [5:0] */ + __IO uint32_t reserved1 : 2; /* [7:6] */ + __IO uint32_t ispc : 1; /* [8] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ + } ctrl3_bit; + }; + + /** + * @brief qspi reserved register, offset:0x44~4C + */ + __IO uint32_t reserved2[3]; /** * @brief qspi rev register, offset:0x50 @@ -516,13 +521,15 @@ typedef struct * @{ */ +void qspi_reset(qspi_type* qspi_x); void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state); -void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode); +void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode); void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv); void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state); void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state); flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag); -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag); +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag); +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag); void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state); @@ -536,6 +543,7 @@ uint32_t qspi_word_read(qspi_type* qspi_x); void qspi_word_write(qspi_type* qspi_x, uint32_t value); void qspi_half_word_write(qspi_type* qspi_x, uint16_t value); void qspi_byte_write(qspi_type* qspi_x, uint8_t value); +void qspi_auto_ispc_enable(qspi_type* qspi_x); /** * @} */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h index 0c221880ca..1e11bf36dc 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_scfg.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 system config header file ************************************************************************** * Copyright notice & Disclaimer @@ -57,9 +55,9 @@ extern "C" { typedef enum { SCFG_XMC_SWAP_NONE = 0x00, /* no swap */ - SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram nor psram sram nand2 swap */ - SCFG_XMC_SWAP_MODE2 = 0x02, /* nand3 qspi2 swap */ - SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram nor psram sram nand2 nand3 qspi2 swap */ + SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */ + SCFG_XMC_SWAP_MODE2 = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */ + SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */ } scfg_xmc_swap_type; /** @@ -67,9 +65,7 @@ typedef enum */ typedef enum { - SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR10 = 0x00 /* infrared signal source select tmr10 */ } scfg_ir_source_type; /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h index 33d5ca76f5..c78803e777 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_sdio.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -578,7 +576,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -588,6 +586,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h index d28b3d90d6..ae99b541bd 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_spi.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -484,6 +482,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h index de800e971a..488dba8d5a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_tmr.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -54,6 +52,7 @@ extern "C" { #define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */ #define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */ #define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */ +#define TMR_C5_FLAG ((uint32_t)0x010000) /*!< tmr flag channel 5 */ #define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */ #define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */ #define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */ @@ -239,7 +238,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -291,17 +290,6 @@ typedef enum TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */ }tmr_event_trigger_type; -/** - * @brief tmr channel output fast type - */ -typedef enum -{ - TMR_CHANNEL1_OUTPUT_FAST = MAKE_VALUE(0x18, 2), /*!< tmr channel 1 output fast mode */ - TMR_CHANNEL2_OUTPUT_FAST = MAKE_VALUE(0x18, 10), /*!< tmr channel 2 output fast mode */ - TMR_CHANNEL3_OUTPUT_FAST = MAKE_VALUE(0x1c, 2), /*!< tmr channel 3 output fast mode */ - TMR_CHANNEL4_OUTPUT_FAST = MAKE_VALUE(0x1c, 10) /*!< tmr channel 4 output fast mode */ -}tmr_channel_output_fast_type; - /** * @brief tmr polarity active type */ @@ -930,7 +918,7 @@ void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct); void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div); void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div); void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir); -void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value); +void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value); void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value); uint32_t tmr_counter_value_get(tmr_type *tmr_x); void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value); @@ -962,7 +950,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -975,12 +963,12 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state); void tmr_internal_clock_set(tmr_type *tmr_x); -void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast); void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_polarity_active_type oc_polarity); void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h index 4416c3a61d..9ac1bb87db 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usart.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,10 @@ typedef struct #define UART5 ((usart_type *) UART5_BASE) #define USART6 ((usart_type *) USART6_BASE) #define UART7 ((usart_type *) UART7_BASE) +#if defined (AT32F435Zx) || defined (AT32F435Vx) || defined (AT32F435Rx) || \ + defined (AT32F437Zx) || defined (AT32F437Vx) || defined (AT32F437Rx) #define UART8 ((usart_type *) UART8_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -386,6 +387,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h index 9e41b14cb9..2e5c0b0d40 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usb.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -707,6 +705,7 @@ typedef struct __IO uint32_t nptxfspcavail : 16; /* [15:0] */ __IO uint32_t nptxqspcavail : 8; /* [23:16] */ __IO uint32_t nptxqtop : 7; /* [30:24] */ + __IO uint32_t reserved1 : 1; /* [31] */ } gnptxsts_bit; }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h index 2b823eee1b..5cc24927e8 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wdt.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h index d8a572372e..f73217702e 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wwdt.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h index 7d3b9e68dc..398ddb2893 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_xmc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 xmc header file ************************************************************************** * Copyright notice & Disclaimer @@ -605,7 +603,7 @@ typedef struct xmc_bank1_tmgwr_reg_type tmgwr_group[4]; /** - * @brief xmc bank1 reserved register, offset:0x120~0x21C + * @brief xmc bank1 reserved register, offset:0x120~0x220 */ __IO uint32_t reserved2[63]; @@ -1024,7 +1022,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct, xmc_norsram_timing_init_type* xmc_w_timing_struct); void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state); -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); void xmc_nand_reset(xmc_class_bank_type xmc_bank); void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct); void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct, @@ -1037,6 +1035,7 @@ void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state); uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank); void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state); flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); void xmc_pccard_reset(void); void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c index 69a3ae74ee..7c1cdcedfb 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_acc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the acc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -203,6 +201,23 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c index 5ca6d054bc..53eb738e11 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_adc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -78,7 +76,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -104,7 +102,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -471,120 +469,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - case ADC_CHANNEL_18: - adc_x->spt1_bit.cspt18 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -632,69 +552,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - case ADC_CHANNEL_18: - adc_x->spt1_bit.cspt18 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -978,6 +852,7 @@ flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x) void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state) { adc_x->ctrl2_bit.pcswtrg = new_state; + adc_x->ctrl2_bit.pcswtrg = FALSE; } /** @@ -1087,6 +962,54 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * - ADC1, ADC2, ADC3. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_OCCE_FLAG + * - ADC_PCCE_FLAG + * - ADC_OCCO_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_OCCE_FLAG: + if(adc_x->sts_bit.occe && adc_x->ctrl1_bit.occeien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + case ADC_OCCO_FLAG: + if(adc_x->sts_bit.occo && adc_x->ctrl1_bit.occoien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c index e4df40f222..e1aa2d9021 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_can.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -933,6 +931,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c index 3d225cabea..1dd90c8358 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c index 378aa9443a..de1eabb9fd 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crm.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,12 +59,12 @@ void crm_reset(void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); - /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ - CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ + CRM->cfg = 0; + /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; @@ -135,6 +133,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -282,6 +338,7 @@ void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state) * - CRM_USART6_PERIPH_LOWPOWER - CRM_ADC1_PERIPH_LOWPOWER - CRM_ADC2_PERIPH_LOWPOWER - CRM_ADC3_PERIPH_LOWPOWER * - CRM_SPI1_PERIPH_LOWPOWER - CRM_SPI4_PERIPH_LOWPOWER - CRM_SCFG_PERIPH_LOWPOWER - CRM_TMR9_PERIPH_LOWPOWER * - CRM_TMR10_PERIPH_LOWPOWER - CRM_TMR11_PERIPH_LOWPOWER - CRM_TMR20_PERIPH_LOWPOWER - CRM_ACC_PERIPH_LOWPOWER + * - CRM_FLASH_PERIPH_LOWPOWER - CRM_SRAM1_PERIPH_LOWPOWER - CRM_SRAM2_PERIPH_LOWPOWER * @param new_state (TRUE or FALSE) * @retval none */ @@ -367,6 +424,7 @@ void crm_flag_clear(uint32_t flag) case CRM_LOWPOWER_RESET_FLAG: case CRM_ALL_RESET_FLAG: CRM->ctrlsts_bit.rstfc = TRUE; + while(CRM->ctrlsts_bit.rstfc == TRUE); break; case CRM_LICK_READY_INT_FLAG: CRM->clkint_bit.lickstblfc = TRUE; @@ -468,6 +526,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 144 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -484,6 +543,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 144 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -623,7 +683,7 @@ void crm_clkout_to_tmr10_enable(confirm_state new_state) * pll_ms * * pll_rcs_freq * pll_ns - * 500mhz <= -------------------------------- <= 1000mhz + * 500mhz <= -------------------------------- <= 1200mhz * pll_ms * @param clock_source * this parameter can be one of the following values: @@ -645,6 +705,10 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ uint16_t pll_ms, crm_pll_fr_type pll_fr) { /* config pll clock source */ + if(clock_source == CRM_PLL_SOURCE_HICK) + { + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; + } CRM->pllcfg_bit.pllrcs = clock_source; /* config pll multiplication factor */ @@ -665,6 +729,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** @@ -888,7 +953,7 @@ void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state) * pll_ms * * pll_rcs_freq * pll_ns - * 500mhz <= -------------------------------- <= 1000mhz + * 500mhz <= -------------------------------- <= 1200mhz * pll_ms * @param pll_rcs * this parameter can be one of the following values: @@ -903,9 +968,10 @@ void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state) error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr) { - uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fr = 0; - uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF; - uint32_t result = 0, absolute_value = 0; + uint32_t error_min = 0xFFFFFFFF; + uint32_t pll_rcs_freq = 0, result = 0, absolute_value = 0; + uint16_t ns = 0, ms = 0, ms_min = 0, ms_max = 0; + int16_t fr = 0; /* reduce calculate accuracy, target_sclk_freq accuracy with khz */ target_sclk_freq = target_sclk_freq / 1000; @@ -932,13 +998,13 @@ error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint /* polling pll parameters */ for(ms = ms_min; ms <= ms_max; ms ++) { - for(fr = 0; fr <= 5; fr ++) + for(fr = 5; fr >= 0; fr --) { for(ns = 31; ns <= 500; ns ++) { result = (pll_rcs_freq * ns) / (ms); /* check vco frequency range, accuracy with khz */ - if((result < 500000U) || (result > 1000000U)) + if((result < 500000U) || (result > 1200000U)) { continue; } @@ -949,7 +1015,7 @@ error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint { *ret_ms = ms; *ret_ns = ns; - *ret_fr = fr; + *ret_fr = (uint16_t)fr; /* the pll parameters that is equal to target_sclk_freq */ return SUCCESS; } @@ -960,7 +1026,7 @@ error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint error_min = absolute_value; *ret_ms = ms; *ret_ns = ns; - *ret_fr = fr; + *ret_fr = (uint16_t)fr; } } } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c index daa9a528f6..eab69e080c 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dac.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the dac firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -416,6 +414,34 @@ flag_status dac_udr_flag_get(dac_select_type dac_select) return status; } +/** + * @brief get flag of the dac udr interrupt flag. + * @param dac_select + * this parameter can be one of the following values: + * - DAC1_SELECT + * - DAC2_SELECT + * @retval the new state of dac udr flag status(SET or RESET). + */ +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select) +{ + flag_status status = RESET; + + switch(dac_select) + { + case DAC1_SELECT: + if((DAC->sts_bit.d1dmaudrf && DAC->ctrl_bit.d1dmaudrien) != 0) + status = SET; + break; + case DAC2_SELECT: + if((DAC->sts_bit.d2dmaudrf && DAC->ctrl_bit.d2dmaudrien) != 0) + status = SET; + break; + default: + break; + } + return status; +} + /** * @brief clear the dac udr flag. * @param dac_select diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c index 86d07cdbac..dcad0d7de1 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_mcudbg.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the mcudbg firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c index 24dce61dc4..0c15f350f1 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dma.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -241,6 +239,48 @@ flag_status dma_flag_get(uint32_t dmax_flag) } } +/** + * @brief dma interrupt flag get. + * @param dma_flag + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag. + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if((temp & dmax_flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief dma flag clear. * @param dma_flag @@ -363,9 +403,9 @@ void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct) * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1 * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3 - * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM + * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_HALL * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4 - * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1 + * - DMAMUX_DMAREQ_ID_TMR8_OVERFLOW- DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_HALL - DMAMUX_DMAREQ_ID_TMR2_CH1 * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3 * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1 @@ -426,9 +466,9 @@ void dmamux_enable(dma_type *dma_x, confirm_state new_state) * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1 * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3 - * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM + * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_HALL * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4 - * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1 + * - DMAMUX_DMAREQ_ID_TMR8_OVERFLOW- DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_HALL - DMAMUX_DMAREQ_ID_TMR2_CH1 * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3 * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1 @@ -483,7 +523,7 @@ void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_t { dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel; dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity; - dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number; + dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number - 1; dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable; dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable; } @@ -520,7 +560,7 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini { dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel; dmamux_gen_x->gctrl_bit.gpol = dmamux_gen_init_struct->gen_polarity; - dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number; + dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number - 1; dmamux_gen_x->gctrl_bit.gen = dmamux_gen_init_struct->gen_enable; } @@ -610,6 +650,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux sync interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_SYNC_OV1_FLAG + * - DMAMUX_SYNC_OV2_FLAG + * - DMAMUX_SYNC_OV3_FLAG + * - DMAMUX_SYNC_OV4_FLAG + * - DMAMUX_SYNC_OV5_FLAG + * - DMAMUX_SYNC_OV6_FLAG + * - DMAMUX_SYNC_OV7_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + { + tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset)); + } + else + { + tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset)); + } + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + + if(dma_x == DMA1) + { + if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + /** * @brief dmamux sync flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. @@ -652,6 +764,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux request generator interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_GEN_TRIG_OV1_FLAG + * - DMAMUX_GEN_TRIG_OV2_FLAG + * - DMAMUX_GEN_TRIG_OV3_FLAG + * - DMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset)); + else + tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset)); + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + if(dma_x == DMA1) + { + if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + /** * @brief dmamux request generator flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c index f8de9ada7d..9688236b12 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dvp.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the dvp firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -41,6 +39,17 @@ * @{ */ +/** + * @brief reset the dvp register + * @param none + * @retval none + */ +void dvp_reset(void) +{ + crm_periph_reset(CRM_DVP_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_DVP_PERIPH_RESET, FALSE); +} + /** * @brief enable or disable dvp capture * @param new_state (TRUE or FALSE) @@ -76,16 +85,18 @@ void dvp_window_crop_enable(confirm_state new_state) /** * @brief set dvp cropping window configuration - * @param crop_x(0x0000~0x3FFF): cropping window horizontal start pixel - * @param crop_y(0x0000~0x1FFF): cropping window vertical start pixel - * @param crop_w(0x0001~0x3FFF): cropping window horizontal pixel number - * @param crop_h(0x0001~0x3FFF): cropping window vertical pixel number + * @param crop_x: cropping window horizontal start pixel + * @param crop_y: cropping window vertical start line + * @param crop_w: cropping window horizontal pixel number + * @param crop_h: cropping window vertical line number + * @param bytes: the number of bytes corresponding to one pixel + * eg. y8:bytes = 1, rgb565:bytes = 2 * @retval none */ -void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h) +void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes) { - DVP->cwst = ((crop_x * 2) | (crop_y << 16)); - DVP->cwsz = ((crop_w * 2 - 1) | ((crop_h - 1) << 16)); + DVP->cwst = ((crop_x * bytes) | (crop_y << 16)); + DVP->cwsz = ((crop_w * bytes - 1) | ((crop_h - 1) << 16)); } /** @@ -218,15 +229,15 @@ void dvp_enable(confirm_state new_state) /** * @brief set dvp zoomout select - * @param dvp_pcdse: pixel capture/drop selection extension (Only work when pcdc = 2) + * @param dvp_pcdes: pixel capture/drop selection extension (Only work when pcdc = 2) * this parameter can be one of the following values: - * - DVP_PCDSE_CAP_FIRST - * - DVP_PCDSE_DROP_FIRST + * - DVP_PCDES_CAP_FIRST + * - DVP_PCDES_DROP_FIRST * @retval none */ -void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse) +void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes) { - DVP->actrl_bit.pcdse = dvp_pcdse; + DVP->actrl_bit.pcdes = dvp_pcdes; } /** @@ -265,7 +276,7 @@ void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_ty * this parameter can be one of the following values: * - DVP_STATUS_HSYN * - DVP_STATUS_VSYN - * - DVP_STATUS_OFS + * - DVP_STATUS_OFNE * @retval flag_status (SET or RESET) */ flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic) @@ -309,16 +320,9 @@ void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state) } /** - * @brief get dvp event/interrupt flag status + * @brief get dvp interrupt flag status * @param flag * this parameter can be one of the following values: - * event flag: - * - DVP_CFD_EVT_FLAG - * - DVP_OVR_EVT_FLAG - * - DVP_ESE_EVT_FLAG - * - DVP_VS_EVT_FLAG - * - DVP_HS_EVT_FLAG - * interrupt flag: * - DVP_CFD_INT_FLAG * - DVP_OVR_INT_FLAG * - DVP_ESE_INT_FLAG @@ -326,31 +330,47 @@ void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state) * - DVP_HS_INT_FLAG * @retval flag_status (SET or RESET) */ -flag_status dvp_flag_get(uint32_t flag) +flag_status dvp_interrupt_flag_get(uint32_t flag) { flag_status status = RESET; - if(flag & 0x80000000) + + if((DVP->ists & flag) != RESET) { - if((DVP->ists & flag) != RESET) - { - status = SET; - } - else - { - status = RESET; - } + status = SET; } else { - if((DVP->ests & flag) != RESET) - { - status = SET; - } - else - { - status = RESET; - } + status = RESET; } + + return status; +} + +/** + * @brief get dvp event flag status + * @param flag + * this parameter can be one of the following values: + * - DVP_CFD_EVT_FLAG + * - DVP_OVR_EVT_FLAG + * - DVP_ESE_EVT_FLAG + * - DVP_VS_EVT_FLAG + * - DVP_HS_EVT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status dvp_flag_get(uint32_t flag) +{ + flag_status status = RESET; + flag &= ~0x80000000; + + if((DVP->ests & flag) != RESET) + { + status = SET; + } + else + { + status = RESET; + } + return status; } @@ -406,16 +426,16 @@ void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t sr /** * @brief set enhanced frame rate control configuration - * @param efrcfm(0x00~0x1F): original frame rate contorl factor - * @param efrcfn(0x00~0x1F): enhanced frame rate contorl factor + * @param efrcsf(0x00~0x1F): original frame rate contorl factor + * @param efrctf(0x00~0x1F): enhanced frame rate contorl factor * @param new_state (TRUE or FALSE) * @retval none */ -void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state) +void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state) { - if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrcfn <= efrcfm)) + if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrctf <= efrcsf)) { - DVP->frf = (efrcfm | (efrcfn << 8)); + DVP->frf = (efrcsf | (efrctf << 8)); } DVP->actrl_bit.efrce = new_state; @@ -440,7 +460,7 @@ void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_sta * - DVP_EFDF_BYPASS * - DVP_EFDF_YUV422_UYVY * - DVP_EFDF_YUV422_YUYV - * - DVP_EFDF_YUV444 + * - DVP_EFDF_RGB565_555 * - DVP_EFDF_Y8 * @retval none */ @@ -451,10 +471,10 @@ void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf) /** * @brief set dvp input data un-used condition/number configuration - * @param dvp_iduc: input data un-used condition + * @param dvp_idus: input data un-used condition * this parameter can be one of the following values: - * - DVP_IDUC_MSB - * - DVP_IDUC_LSB + * - DVP_IDUS_MSB + * - DVP_IDUS_LSB * @param dvp_idun: input data un-used number * this parameter can be one of the following values: * - DVP_IDUN_0 @@ -463,9 +483,9 @@ void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf) * - DVP_IDUN_6 * @retval none */ -void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun) +void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun) { - DVP->actrl_bit.iduc = dvp_iduc; + DVP->actrl_bit.idus = dvp_idus; DVP->actrl_bit.idun = dvp_idun; } @@ -484,20 +504,20 @@ void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt) /** * @brief set dvp hsync/vsync event interrupt strategy configuration - * @param dvp_hseis: hsync event interrupt strategy + * @param dvp_hseid: hsync event interrupt strategy * this parameter can be one of the following values: - * - DVP_HSEIS_LINE_END - * - DVP_HSEIS_LINE_START - * @param dvp_vseis: vsync event interrupt strategy + * - DVP_HSEID_LINE_END + * - DVP_HSEID_LINE_START + * @param dvp_vseid: vsync event interrupt strategy * this parameter can be one of the following values: - * - DVP_VSEIS_FRAME_END - * - DVP_VSEIS_FRMAE_START + * - DVP_VSEID_FRAME_END + * - DVP_VSEID_FRMAE_START * @retval none */ -void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis) +void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid) { - DVP->actrl_bit.hseis = dvp_hseis; - DVP->actrl_bit.vseis = dvp_vseis; + DVP->actrl_bit.hseid = dvp_hseid; + DVP->actrl_bit.vseid = dvp_vseid; } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c index 42cc0a28dd..ca6e9b8709 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_edma.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the edma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -532,6 +530,43 @@ flag_status edma_flag_get(uint32_t edma_flag) } } +/** + * @brief get the edma interrupt flag. + * @param edma_flag: + * this parameter can be one of the following values: + * - EDMA_FERR1_FLAG - EDMA_DMERR1_FLAG - EDMA_DTERR1_FLAG - EDMA_HDT1_FLAG - EDMA_FDT1_FLAG + * - EDMA_FERR2_FLAG - EDMA_DMERR2_FLAG - EDMA_DTERR2_FLAG - EDMA_HDT2_FLAG - EDMA_FDT2_FLAG + * - EDMA_FERR3_FLAG - EDMA_DMERR3_FLAG - EDMA_DTERR3_FLAG - EDMA_HDT3_FLAG - EDMA_FDT3_FLAG + * - EDMA_FERR4_FLAG - EDMA_DMERR4_FLAG - EDMA_DTERR4_FLAG - EDMA_HDT4_FLAG - EDMA_FDT4_FLAG + * - EDMA_FERR5_FLAG - EDMA_DMERR5_FLAG - EDMA_DTERR5_FLAG - EDMA_HDT5_FLAG - EDMA_FDT5_FLAG + * - EDMA_FERR6_FLAG - EDMA_DMERR6_FLAG - EDMA_DTERR6_FLAG - EDMA_HDT6_FLAG - EDMA_FDT6_FLAG + * - EDMA_FERR7_FLAG - EDMA_DMERR7_FLAG - EDMA_DTERR7_FLAG - EDMA_HDT7_FLAG - EDMA_FDT7_FLAG + * - EDMA_FERR8_FLAG - EDMA_DMERR8_FLAG - EDMA_DTERR8_FLAG - EDMA_HDT8_FLAG - EDMA_FDT8_FLAG + * @retval the new state of edma flag (SET or RESET). + */ +flag_status edma_interrupt_flag_get(uint32_t edma_flag) +{ + uint32_t status; + + if(edma_flag > ((uint32_t)0x20000000)) + { + status = EDMA->sts2; + } + else + { + status = EDMA->sts1; + } + + if((status & edma_flag) != ((uint32_t)RESET)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the edma flag. * @param edma_flag: @@ -753,7 +788,7 @@ void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_in { edmamux_channelx->muxctrl_bit.syncsel = edmamux_sync_init_struct->sync_signal_sel; edmamux_channelx->muxctrl_bit.syncpol = edmamux_sync_init_struct->sync_polarity; - edmamux_channelx->muxctrl_bit.reqcnt = edmamux_sync_init_struct->sync_request_number; + edmamux_channelx->muxctrl_bit.reqcnt = edmamux_sync_init_struct->sync_request_number - 1; edmamux_channelx->muxctrl_bit.evtgen = edmamux_sync_init_struct->sync_event_enable; edmamux_channelx->muxctrl_bit.syncen = edmamux_sync_init_struct->sync_enable; } @@ -780,7 +815,7 @@ void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen { edmamux_gen_x->gctrl_bit.sigsel = edmamux_gen_init_struct->gen_signal_sel; edmamux_gen_x->gctrl_bit.gpol = edmamux_gen_init_struct->gen_polarity; - edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number; + edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number - 1; edmamux_gen_x->gctrl_bit.gen = edmamux_gen_init_struct->gen_enable; } @@ -860,6 +895,63 @@ flag_status edmamux_sync_flag_get(uint32_t flag) } } +/** + * @brief edmamux sync interrupt flag get. + * @param flag + * this parameter can be any combination of the following values: + * - EDMAMUX_SYNC_OV1_FLAG + * - EDMAMUX_SYNC_OV2_FLAG + * - EDMAMUX_SYNC_OV3_FLAG + * - EDMAMUX_SYNC_OV4_FLAG + * - EDMAMUX_SYNC_OV5_FLAG + * - EDMAMUX_SYNC_OV6_FLAG + * - EDMAMUX_SYNC_OV7_FLAG + * - EDMAMUX_SYNC_OV8_FLAG + * @retval state of edmamux sync flag. + */ +flag_status edmamux_sync_interrupt_flag_get(uint32_t flag) +{ + uint32_t int_stat = 0; + + if(flag == EDMAMUX_SYNC_OV1_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL1->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV2_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL2->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV3_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL3->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV4_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL4->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV5_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL5->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV6_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL6->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV7_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL7->muxctrl_bit.syncovien; + } + else + { + int_stat = (uint32_t)EDMAMUX_CHANNEL8->muxctrl_bit.syncovien; + } + + if((int_stat != RESET) && ((EDMA->muxsyncsts & flag) != RESET)) + return SET; + else + return RESET; +} + /** * @brief edmamux sync flag clear. * @param flag @@ -901,6 +993,43 @@ flag_status edmamux_generator_flag_get(uint32_t flag) } } +/** + * @brief edmamux request generator interrupt flag get. + * @param flag + * this parameter can be any combination of the following values: + * - EDMAMUX_GEN_TRIG_OV1_FLAG + * - EDMAMUX_GEN_TRIG_OV2_FLAG + * - EDMAMUX_GEN_TRIG_OV3_FLAG + * - EDMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of edmamux sync flag. + */ +flag_status edmamux_generator_interrupt_flag_get(uint32_t flag) +{ + uint32_t int_stat = 0; + + if(flag == EDMAMUX_GEN_TRIG_OV1_FLAG) + { + int_stat = EDMAMUX_GENERATOR1->gctrl_bit.trgovien; + } + else if(flag == EDMAMUX_GEN_TRIG_OV2_FLAG) + { + int_stat = EDMAMUX_GENERATOR2->gctrl_bit.trgovien; + } + else if(flag == EDMAMUX_GEN_TRIG_OV3_FLAG) + { + int_stat = EDMAMUX_GENERATOR3->gctrl_bit.trgovien; + } + else + { + int_stat = EDMAMUX_GENERATOR4->gctrl_bit.trgovien; + } + + if((int_stat != RESET) && ((EDMA->muxgsts & flag) != RESET)) + return SET; + else + return RESET; +} + /** * @brief edmamux request generator flag clear. * @param flag diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c index 749766eeb5..a90ff38b36 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_emac.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the emac firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -45,8 +43,10 @@ /** * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors */ -emac_dma_desc_type *dma_tx_desc_to_set; -emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *dma_tx_desc_to_set; +__IO emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *ptp_dma_tx_desc_to_set; +__IO emac_dma_desc_type *ptp_dma_rx_desc_to_get; /* emac private function */ static void emac_delay(uint32_t delay); @@ -221,7 +221,6 @@ void emac_stop(void) emac_trasmitter_enable(FALSE); } - /** * @brief write phy data. * @param address: phy address. @@ -530,6 +529,7 @@ void emac_broadcast_frames_disable(confirm_state new_state) * @param condition: set what control frame can pass filter. * this parameter can be one of the following values: * - EMAC_CONTROL_FRAME_PASSING_NO + * - EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE * - EMAC_CONTROL_FRAME_PASSING_ALL * - EMAC_CONTROL_FRAME_PASSING_MATCH * @retval none @@ -989,6 +989,90 @@ void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, ema } } +/** + * @brief set transmit/receive descriptor list address + * @param transfer_type: it will be transmit or receive + * this parameter can be one of the following values: + * - EMAC_DMA_TRANSMIT + * - EMAC_DMA_RECEIVE + * @param dma_desc_tab: pointer on the first tx desc list + * @param buff: pointer on the first tx/rx buffer list + * @param buffer_count: number of the used Tx desc in the list + * @retval none + */ +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count) +{ + uint32_t i = 0; + emac_dma_desc_type *dma_descriptor; + + switch(transfer_type) + { + case EMAC_DMA_TRANSMIT: + { + dma_tx_desc_to_set = dma_desc_tab; + ptp_dma_tx_desc_to_set = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMATXDESC_TCH | EMAC_DMATXDESC_TTSE; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab; + break; + } + case EMAC_DMA_RECEIVE: + { + dma_rx_desc_to_get = dma_desc_tab; + ptp_dma_rx_desc_to_get = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMARXDESC_OWN; + + dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab; + break; + } + } +} /** * @brief enable or disable the specified dma rx descriptor receive interrupt * @param dma_rx_desc: pointer on a rx desc. @@ -1049,7 +1133,7 @@ uint32_t emac_received_packet_size_get(void) ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) && ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET)) { - frame_length = emac_dmarxdesc_frame_length_get(dma_rx_desc_to_get); + frame_length = emac_dmarxdesc_frame_length_get((emac_dma_desc_type*) dma_rx_desc_to_get); } return frame_length; @@ -1660,6 +1744,16 @@ uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_ty return address; } +/** + * @brief alternate dma descriptor size + * @param new_state: TRUE or FALSE + * @retval none + */ +void emac_dma_alternate_desc_size(confirm_state new_state) +{ + EMAC_DMA->bm_bit.atds = new_state; +} + /** * @brief reset all counter * @param none @@ -2039,6 +2133,27 @@ void emac_ptp_mac_address_filter_enable(confirm_state new_state) EMAC_PTP->tsctrl_bit.emafpff = new_state; } +/** + * @brief check whether the specified emac ptp flag is set or not. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - EMAC_PTP_TI_FLAG: time stamp initialized flag + * - EMAC_PTP_TU_FLAG: time stamp updtated flag + * - EMAC_PTP_ARU_FLAG: transmit data buffer empty flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status emac_ptp_flag_get(uint32_t flag) +{ + if(EMAC_PTP->tsctrl & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief set subsecond increment value * @param value: add to subsecond value for every update @@ -2089,42 +2204,19 @@ confirm_state emac_ptp_system_time_sign_get(void) } /** - * @brief set system time second + * @brief set system time + * @param sign: plus or minus * @param second: system time second - * @retval none - */ -void emac_ptp_system_second_set(uint32_t second) -{ - EMAC_PTP->tshud_bit.ts = second; -} - -/** - * @brief set system time subsecond * @param subsecond: system time subsecond * @retval none */ -void emac_ptp_system_subsecond_set(uint32_t subsecond) +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond) { + EMAC_PTP->tslud_bit.ast = sign ? 1 : 0; + EMAC_PTP->tshud_bit.ts = second; EMAC_PTP->tslud_bit.tss = subsecond; } -/** - * @brief set system time sign - * @param sign: TRUE or FALSE. - * @retval none - */ -void emac_ptp_system_time_sign_set(confirm_state sign) -{ - if(sign) - { - EMAC_PTP->tslud_bit.ast = 1; - } - else - { - EMAC_PTP->tslud_bit.ast = 0; - } -} - /** * @brief set time stamp addend * @param value: to achieve time synchronization @@ -2266,6 +2358,62 @@ flag_status emac_dma_flag_get(uint32_t dma_flag) return status; } +/** + * @brief check whether the specified emac dma interrupt flag is set or not. + * @param dma_flag: specifies the emac dma flag to check. + * this parameter can be one of emac dma flag status: + * - EMAC_DMA_TI_FLAG + * - EMAC_DMA_TPS_FLAG + * - EMAC_DMA_TBU_FLAG + * - EMAC_DMA_TJT_FLAG + * - EMAC_DMA_OVF_FLAG + * - EMAC_DMA_UNF_FLAG + * - EMAC_DMA_RI_FLAG + * - EMAC_DMA_RBU_FLAG + * - EMAC_DMA_RPS_FLAG + * - EMAC_DMA_RWT_FLAG + * - EMAC_DMA_ETI_FLAG + * - EMAC_DMA_FBEI_FLAG + * - EMAC_DMA_ERI_FLAG + * - EMAC_DMA_AIS_FLAG + * - EMAC_DMA_NIS_FLAG + * @retval the new state of dma_flag (SET or RESET). + */ +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag) +{ + flag_status status = RESET; + switch(dma_flag) + { + case EMAC_DMA_TI_FLAG: + case EMAC_DMA_TBU_FLAG: + case EMAC_DMA_RI_FLAG: + case EMAC_DMA_ERI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_NIS_FLAG)) + status = SET; + break; + case EMAC_DMA_TPS_FLAG: + case EMAC_DMA_TJT_FLAG: + case EMAC_DMA_OVF_FLAG: + case EMAC_DMA_UNF_FLAG: + case EMAC_DMA_RBU_FLAG: + case EMAC_DMA_RPS_FLAG: + case EMAC_DMA_RWT_FLAG: + case EMAC_DMA_ETI_FLAG: + case EMAC_DMA_FBEI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_AIS_FLAG)) + status = SET; + break; + default: + break; + } + /* return the new state (SET or RESET) */ + return status; +} + /** * @brief clear the emac dma flag. * @param dma_flag: specifies the emac dma flags to clear. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c index ab5aaed58f..ed60bac123 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_ertc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the ertc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -98,15 +96,9 @@ error_status ertc_wait_update(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - /* clear updf flag */ ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7); - /* enable write protection */ - ertc_write_protect_enable(); - while(ERTC->sts_bit.updf == 0) { if(timeout == 0) @@ -164,9 +156,6 @@ error_status ertc_init_mode_enter(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - if(ERTC->sts_bit.imf == 0) { /* enter init mode */ @@ -331,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -406,8 +395,6 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - (void) (ERTC->sts); - reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -724,8 +711,8 @@ uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x) * - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8. * - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4. * - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2. - * - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT - * - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535. + * - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT + * - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535. * @retval none. */ void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock) @@ -1483,6 +1470,55 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * - ERTC_TP2F_FLAG: tamper detection 2 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + case ERTC_TP2F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1527,13 +1563,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c index bade7c89b7..3269d3badb 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_exint.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -155,6 +153,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c index 1003400d75..a49140e67c 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_flash.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -359,41 +357,27 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type status = FLASH_OPERATE_DONE; if((sector_address >= FLASH_BANK1_START_ADDR) && (sector_address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; } else if((sector_address >= FLASH_BANK2_START_ADDR) && (sector_address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.secers = TRUE; + FLASH->addr2 = sector_address; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl2_bit.secers = TRUE; - FLASH->addr2 = sector_address; - FLASH->ctrl2_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl2_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl2_bit.secers = FALSE; } /* return the erase status */ @@ -411,41 +395,27 @@ flash_status_type flash_block_erase(uint32_t block_address) flash_status_type status = FLASH_OPERATE_DONE; if((block_address >= FLASH_BANK1_START_ADDR) && (block_address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.blkers = TRUE; + FLASH->addr = block_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the blkers */ - FLASH->ctrl_bit.blkers = TRUE; - FLASH->addr = block_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the blkers bit */ - FLASH->ctrl_bit.blkers = FALSE; - } + /* disable the blkers bit */ + FLASH->ctrl_bit.blkers = FALSE; } else if((block_address >= FLASH_BANK2_START_ADDR) && (block_address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.blkers = TRUE; + FLASH->addr2 = block_address; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the blkers */ - FLASH->ctrl2_bit.blkers = TRUE; - FLASH->addr2 = block_address; - FLASH->ctrl2_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the blkers bit */ - FLASH->ctrl2_bit.blkers = FALSE; - } + /* disable the blkers bit */ + FLASH->ctrl2_bit.blkers = FALSE; } /* return the erase status */ @@ -461,21 +431,16 @@ flash_status_type flash_block_erase(uint32_t block_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } if(status == FLASH_OPERATE_DONE) { /* if the previous operation is completed, continue to erase bank2 */ @@ -501,21 +466,16 @@ flash_status_type flash_internal_all_erase(void) flash_status_type flash_bank1_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -529,21 +489,16 @@ flash_status_type flash_bank1_erase(void) flash_status_type flash_bank2_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl2_bit.bankers = TRUE; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank2 */ - FLASH->ctrl2_bit.bankers = TRUE; - FLASH->ctrl2_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl2_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl2_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -566,41 +521,36 @@ flash_status_type flash_user_system_data_erase(void) fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the status */ return status; } @@ -625,28 +575,23 @@ flash_status_type flash_eopb0_config(flash_usd_eopb0_type data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; + /* restore the default eopb0 value */ + USD->eopb0 = (uint16_t)data; - /* restore the default eopb0 value */ - USD->eopb0 = (uint16_t)data; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the status */ return status; } @@ -663,35 +608,23 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ @@ -710,35 +643,23 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ @@ -758,35 +679,23 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -802,24 +711,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + if(address == USD_BASE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; + if(data != 0xA5) + return FLASH_OPERATE_DONE; } + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the user system data program status */ return status; } @@ -842,73 +755,69 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - - sector_bits[1] = (uint32_t)(~sector_bits[1]); - epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF); - epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF); - epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF); - epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF); - if(status == FLASH_OPERATE_DONE) - { - USD->epp4 = epp_data[0]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp5 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp6 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp7 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + + sector_bits[1] = (uint32_t)(~sector_bits[1]); + epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF); + epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF); + epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF); + epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF); + if(status == FLASH_OPERATE_DONE) + { + USD->epp4 = epp_data[0]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp5 = epp_data[1]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp6 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp7 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -937,43 +846,41 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ + /* restore the default eopb0 value */ + USD->eopb0 = (uint16_t)0x0002; + + /* Wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the default eopb0 value */ - USD->eopb0 = (uint16_t)0x0002; - + USD->fap = FAP_RELIEVE_KEY; /* Wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - - if(new_state == FALSE) - { - USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the flash access protection operation status */ return status; } @@ -1022,26 +929,22 @@ flag_status flash_fap_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -1097,30 +1000,32 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ - if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \ + if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \ (inst_start_sector != 0xFFFF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); slib_range = ((uint32_t)(end_sector << 16) & FLASH_SLIB_END_SECTOR) | (start_sector & FLASH_SLIB_START_SECTOR); FLASH->slib_set_range0 = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000; - FLASH->slib_set_range1 = slib_range; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + if(status == FLASH_OPERATE_DONE) + { + slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000; + FLASH->slib_set_range1 = slib_range; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } } + return status; } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c index e6af8067db..1250c81d8d 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_gpio.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -357,7 +355,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c index 5bf12026e3..6b3de028ff 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_i2c.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -122,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -271,11 +269,13 @@ void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction) } /** - * @brief get the i2c slave received direction. + * @brief slave get the i2c transfer direction. * @param i2c_x: to select the i2c peripheral. * this parameter can be one of the following values: * I2C1, I2C2, I2C3. - * @retval the value of the received direction. + * @retval the value of the slave direction + * - I2C_DIR_TRANSMIT: master request a write transfer, slave enters receiver mode. + * - I2C_DIR_RECEIVE: master request a read transfer, slave enters transmitter mode. */ i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x) { @@ -595,14 +595,14 @@ void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state * - I2C_AUTO_STOP_MODE: auto generate stop mode. * - I2C_SOFT_STOP_MODE: soft generate stop mode. * - I2C_RELOAD_MODE: reload mode. - * @param start_stop: config gen start condition mode. + * @param start: config gen start condition mode. * this parameter can be one of the following values: * - I2C_WITHOUT_START: transfer data without start condition. * - I2C_GEN_START_READ: read data and generate start. * - I2C_GEN_START_WRITE: send data and generate start. * @retval none */ -void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop) +void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start) { uint32_t temp; @@ -613,7 +613,7 @@ void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload temp &= ~0x03FF67FF; /* transfer mode and address set */ - temp |= address | rld_stop | start_stop; + temp |= address | rld_stop | start; /* transfer counter set */ temp |= (uint32_t)cnt << 16; @@ -708,6 +708,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c index c94394eca8..3fd5305895 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_misc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c index 0ea1c278d5..5c106ddaea 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_pwc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -226,10 +224,13 @@ void pwc_standby_mode_enter(void) PWC->ctrl_bit.clswef = TRUE; PWC->ctrl_bit.lpsel = TRUE; SCB->SCR |= 0x04; -#if defined (__CC_ARM) +#if defined (__ARMCC_VERSION) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c index e46c06506a..7ee585c1d3 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_qspi.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contain all the functions for qspi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -41,6 +39,27 @@ * @{ */ +/** + * @brief deinitialize the qspi peripheral registers to their default reset values. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1,QSPI2. + * @retval none + */ +void qspi_reset(qspi_type* qspi_x) +{ + if(qspi_x == QSPI1) + { + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE); + } + else if(qspi_x == QSPI2) + { + crm_periph_reset(CRM_QSPI2_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_QSPI2_PERIPH_RESET, FALSE); + } +} + /** * @brief enable/disable encryption for qspi. * @note the function must be configured only when qspi in command-port mode!!! @@ -67,7 +86,7 @@ void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state) * - QSPI_SCK_MODE_3 * @retval none */ -void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode) +void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode) { qspi_x->ctrl_bit.sckmode = new_mode; } @@ -102,6 +121,8 @@ void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv) * this parameter can be one of the following values: * QSPI1,QSPI2. * @param new_state (TRUE or FALSE) + * TRUE: disable cache + * FALSE: enable cache * @retval none */ void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state) @@ -133,7 +154,7 @@ void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state) * - QSPI_RXFIFORDY_FLAG * - QSPI_TXFIFORDY_FLAG * - QSPI_CMDSTS_FLAG - * @retval the new state of usart_flag (SET or RESET). + * @retval the new state of the flag (SET or RESET). */ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) { @@ -155,6 +176,24 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) return bit_status; } +/** + * @brief get interrupt flags. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1,QSPI2. + * @param flag: only QSPI_CMDSTS_FLAG valid. + * @retval the new state of the flag (SET or RESET). + */ +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag) +{ + if(QSPI_CMDSTS_FLAG != flag) + return RESET; + if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie) + return SET; + else + return RESET; +} + /** * @brief clear flags * @param qspi_x: select the qspi peripheral. @@ -165,7 +204,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) * - QSPI_CMDSTS_FLAG * @retval none */ -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag) { qspi_x->cmdsts = QSPI_CMDSTS_FLAG; } @@ -180,7 +219,7 @@ void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -198,7 +237,7 @@ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_th * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -253,21 +292,35 @@ void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos) */ void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state) { + register uint16_t dly=0; /* skip if state is no change */ if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel)) { return; } - /* wait until tx fifo emoty*/ + /* wait until tx fifo is empty*/ while(qspi_x->fifosts_bit.txfifordy == 0); + /* make sure IO is transmitted */ + dly = 64; + while(dly--) + { + __NOP(); + } + /* flush and reset qspi state */ qspi_x->ctrl_bit.xiprcmdf = 1; /* wait until action is finished */ while(qspi_x->ctrl_bit.abort); + /* make sure IO is transmitted */ + dly = 64; + while(dly--) + { + __NOP(); + } /* set xip mode to new state */ qspi_x->ctrl_bit.xipsel = new_state; @@ -414,6 +467,20 @@ void qspi_word_write(qspi_type* qspi_x, uint32_t value) qspi_x->dt = value; } +/** + * @brief enable auto input sampling phase correction + * @param qspi_x: select the qspi peripheral. + * @retval none. + */ +void qspi_auto_ispc_enable(qspi_type* qspi_x) +{ + qspi_x->ctrl3_bit.ispc = TRUE; + if(qspi_x == QSPI1) + qspi_x->ctrl3_bit.ispd = 56; + else if(qspi_x == QSPI2) + qspi_x->ctrl3_bit.ispd = 50; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c index 3d31f26f2f..9ad6c0093c 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_scfg.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the system config firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -72,8 +70,6 @@ void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c index f5b53efa38..a22a280798 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_sdio.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1, SDIO2. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1, SDIO2. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c index abc26cd272..e759e32b61 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_spi.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -594,6 +592,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. @@ -615,25 +683,23 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_CSPAS_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c index cc62736683..063f0563db 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_tmr.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -262,14 +260,10 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) * @param tmr_rpr_value (0x0000~0xFFFF) * @retval none */ -void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) +void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value) { /* set the repetition counter value */ - if((tmr_x == TMR1) || (tmr_x == TMR8)) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -307,8 +301,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -350,23 +343,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -398,38 +391,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -880,6 +873,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -889,6 +883,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -898,6 +893,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -907,6 +903,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1141,15 +1138,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1398,6 +1395,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1411,6 +1442,7 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state * - TMR_C2_FLAG * - TMR_C3_FLAG * - TMR_C4_FLAG + * - TMR_C5_FLAG * - TMR_HALL_FLAG * - TMR_TRIGGER_FLAG * - TMR_BRK_FLAG @@ -1449,6 +1481,7 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) * - TMR_C2_FLAG * - TMR_C3_FLAG * - TMR_C4_FLAG + * - TMR_C5_FLAG * - TMR_HALL_FLAG * - TMR_TRIGGER_FLAG * - TMR_BRK_FLAG @@ -1511,25 +1544,6 @@ void tmr_internal_clock_set(tmr_type *tmr_x) tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE; } -/** - * @brief set tmr output channel fast - * @param tmr_x: select the tmr peripheral. - * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10, - * TMR11, TMR12, TMR13, TMR14, TMR20 - * @param oc_fast - * this parameter can be one of the following values: - * - TMR_CHANNEL1_OUTPUT_FAST - * - TMR_CHANNEL2_OUTPUT_FAST - * - TMR_CHANNEL3_OUTPUT_FAST - * - TMR_CHANNEL4_OUTPUT_FAST - * @retval none - */ -void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast) -{ - PERIPH_REG((uint32_t)(tmr_x), oc_fast) |= PERIPH_REG_BIT(oc_fast); -} - /** * @brief set tmr output channel polarity * @param tmr_x: select the tmr peripheral. @@ -1807,7 +1821,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR8, TMR20 diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c index 58803c89ba..acf8702c56 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usart.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -86,11 +84,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE); } +#if defined (AT32F435Zx) || defined (AT32F435Vx) || defined (AT32F435Rx) || \ + defined (AT32F437Zx) || defined (AT32F437Vx) || defined (AT32F437Rx) else if(usart_x == UART8) { crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE); } +#endif } /** @@ -104,6 +105,9 @@ void usart_reset(usart_type* usart_x) * - USART_DATA_7BITS * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -607,6 +611,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -618,6 +695,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -630,7 +712,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c index 8f63015236..15d42075d9 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usb.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -447,6 +445,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin uint32_t n_index; uint32_t nhbytes = (nbytes + 3) / 4; uint32_t *pbuf = (uint32_t *)pusr_buf; + UNUSED(num); for(n_index = 0; n_index < nhbytes; n_index ++) { #if defined (__ICCARM__) && (__VER__ < 7000000) @@ -1020,11 +1019,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE) { usb_chh->hcchar_bit.chdis = TRUE; - if((usbx->gnptxsts & 0xFFFF) == 0) + if((usbx->gnptxsts_bit.nptxqspcavail) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) @@ -1039,11 +1037,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) else { usb_chh->hcchar_bit.chdis = TRUE; - if((usb_host->hptxsts & 0xFFFF) == 0) + if((usb_host->hptxsts_bit.ptxqspcavil) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c index a93eec352a..5e9e54ce4a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wdt.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c index 967af61a40..1b338f47bf 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wwdt.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c index ac6df0b167..7ef0c11a2e 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_xmc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the xmc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -224,9 +222,9 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne * @param r2r_timing :read timing * @retval none */ -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) { - XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8; + XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing; XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing; } @@ -726,6 +724,97 @@ flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag return status; } +/** + * @brief check whether the specified xmc interrupt flag is set or not. + * @param xmc_bank: specifies the xmc bank to be used + * this parameter can be one of the following values: + * - XMC_BANK2_NAND + * - XMC_BANK3_NAND + * - XMC_BANK4_PCCARD + * @param xmc_flag: specifies the flag to check. + * this parameter can be any combination of the following values: + * - XMC_RISINGEDGE_FLAG + * - XMC_LEVEL_FLAG + * - XMC_FALLINGEDGE_FLAG + * @retval none + */ +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag) +{ + flag_status status = RESET; + + if(xmc_bank == XMC_BANK2_NAND) + { + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls) + status = SET; + break; + + default: + break; + } + } + else if(xmc_bank == XMC_BANK3_NAND) + { + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK3->bk3is_bit.reien && XMC_BANK3->bk3is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK3->bk3is_bit.feien && XMC_BANK3->bk3is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK3->bk3is_bit.hlien && XMC_BANK3->bk3is_bit.hls) + status = SET; + break; + + default: + break; + } + } + else if(xmc_bank == XMC_BANK4_PCCARD) + { + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK4->bk4is_bit.reien && XMC_BANK4->bk4is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK4->bk4is_bit.feien && XMC_BANK4->bk4is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK4->bk4is_bit.hlien && XMC_BANK4->bk4is_bit.hls) + status = SET; + break; + + default: + break; + } + } + /* return the flag status */ + return status; +} + /** * @brief clear the xmc's pending flags. * @param xmc_bank: specifies the xmc bank to be used diff --git a/bsp/at32/libraries/rt_drivers/SConscript b/bsp/at32/libraries/rt_drivers/SConscript index 7589393620..051e02dd33 100644 --- a/bsp/at32/libraries/rt_drivers/SConscript +++ b/bsp/at32/libraries/rt_drivers/SConscript @@ -44,6 +44,9 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): src += ['drv_soft_i2c.c'] +if GetDepend(['BSP_USING_HARD_I2C']): + src += Glob('drv_hard_i2c.c') + if GetDepend(['BSP_USING_ADC']): src += Glob('drv_adc.c') diff --git a/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h b/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h index 51d1869d68..bc9577a313 100644 --- a/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h @@ -29,6 +29,11 @@ extern "C" { #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL2 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C3_TX_DMA_IRQ DMA1_Channel2_IRQn #endif /* DMA1 channel3 */ @@ -42,6 +47,11 @@ extern "C" { #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL3 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn #endif /* DMA1 channel4 */ @@ -55,6 +65,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -63,12 +78,16 @@ extern "C" { #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn - #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -77,6 +96,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -85,6 +109,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel1 */ diff --git a/bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h new file mode 100644 index 0000000000..ed6b1e920c --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 100000, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h b/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h index d913f31059..131284103b 100644 --- a/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ @@ -162,7 +204,7 @@ extern "C" { /* DMA2 channel4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler -#define UART6_RX_DMA_CLOCK CRM_DMA4_PERIPH_CLOCK +#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 diff --git a/bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h new file mode 100644 index 0000000000..6bc2a184ef --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h index 1dcb38d41f..c379be4185 100644 --- a/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ @@ -162,7 +204,7 @@ extern "C" { /* DMA2 channel4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler -#define UART6_RX_DMA_CLOCK CRM_DMA4_PERIPH_CLOCK +#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 diff --git a/bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h new file mode 100644 index 0000000000..1700059a8a --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x90F02F2F, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x90F02F2F, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0x90F02F2F, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h index cbbda889da..1ade3b7db4 100644 --- a/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h @@ -29,6 +29,11 @@ extern "C" { #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL2 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C3_TX_DMA_IRQ DMA1_Channel2_IRQn #endif /* DMA1 channel3 */ @@ -42,6 +47,11 @@ extern "C" { #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL3 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn #endif /* DMA1 channel4 */ @@ -55,6 +65,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -63,12 +78,16 @@ extern "C" { #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn - #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -77,6 +96,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -85,6 +109,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel1 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h new file mode 100644 index 0000000000..ed6b1e920c --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 100000, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h index 5dd80c2422..89c3f242cd 100644 --- a/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h @@ -55,6 +55,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -63,12 +68,16 @@ extern "C" { #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn - #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -77,6 +86,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -85,6 +99,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel3 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h new file mode 100644 index 0000000000..fe34d4bb32 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h index baf1d36c5d..89c3f242cd 100644 --- a/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h @@ -55,6 +55,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -68,6 +73,11 @@ extern "C" { #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -76,6 +86,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -84,6 +99,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel3 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h new file mode 100644 index 0000000000..fe34d4bb32 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h index cb92ac4807..e68ca7a62e 100644 --- a/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h @@ -29,6 +29,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL2 #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel3_2_IRQn #endif /* DMA1 channel3 */ @@ -42,6 +47,11 @@ extern "C" { #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL3 #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C1_RX_DMA_IRQ DMA1_Channel3_2_IRQn #endif /* DMA1 channel4 */ @@ -55,6 +65,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART2_TX_DMA_IRQ DMA1_Channel5_4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel5_4_IRQn #endif /* DMA1 channel5 */ @@ -68,6 +83,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART2_RX_DMA_IRQ DMA1_Channel5_4_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_4_IRQn #endif #ifdef __cplusplus diff --git a/bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h new file mode 100644 index 0000000000..fe34d4bb32 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h index be8118cf93..0777309a41 100644 --- a/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ @@ -162,7 +204,7 @@ extern "C" { /* DMA2 channel4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler -#define UART6_RX_DMA_CLOCK CRM_DMA4_PERIPH_CLOCK +#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 diff --git a/bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h new file mode 100644 index 0000000000..6bc2a184ef --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h index 1577a135f2..69119922b6 100644 --- a/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h @@ -33,6 +33,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn #define UART1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 #define UART1_RX_DMA_REQ_ID DMA_FLEXIBLE_UART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_RX_DMA_IRQ DMA1_Channel3_2_IRQn +#define I2C1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 +#define I2C1_RX_DMA_REQ_ID DMA_FLEXIBLE_I2C1_RX #endif /* DMA1 channel3 */ @@ -50,6 +57,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn #define UART1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 #define UART1_TX_DMA_REQ_ID DMA_FLEXIBLE_UART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C1_TX_DMA_IRQ DMA1_Channel3_2_IRQn +#define I2C1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 +#define I2C1_TX_DMA_REQ_ID DMA_FLEXIBLE_I2C1_TX #endif /* DMA1 channel4 */ @@ -67,6 +81,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel7_4_IRQn #define UART2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 #define UART2_RX_DMA_REQ_ID DMA_FLEXIBLE_UART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_RX_DMA_IRQ DMA1_Channel7_4_IRQn +#define I2C2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 +#define I2C2_RX_DMA_REQ_ID DMA_FLEXIBLE_I2C2_RX #endif /* DMA1 channel5 */ @@ -84,6 +105,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel7_4_IRQn #define UART2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 #define UART2_TX_DMA_REQ_ID DMA_FLEXIBLE_UART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_TX_DMA_IRQ DMA1_Channel7_4_IRQn +#define I2C2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 +#define I2C2_TX_DMA_REQ_ID DMA_FLEXIBLE_I2C2_TX #endif /* DMA1 channel6 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h new file mode 100644 index 0000000000..3674786c0b --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x80E02E2E, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .flex_channel = I2C1_RX_DMA_FLEX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .flex_channel = I2C1_TX_DMA_FLEX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x80E02E2E, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .flex_channel = I2C2_RX_DMA_FLEX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .flex_channel = I2C2_TX_DMA_FLEX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h index 2ef2f1cf29..8fbdc4dcd3 100644 --- a/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h new file mode 100644 index 0000000000..e4867c1336 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0xC0F03030, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0xC0F03030, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0xC0F03030, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/drv_config.h b/bsp/at32/libraries/rt_drivers/drv_config.h index 988b172f99..891271d2f3 100644 --- a/bsp/at32/libraries/rt_drivers/drv_config.h +++ b/bsp/at32/libraries/rt_drivers/drv_config.h @@ -10,6 +10,7 @@ * 2023-04-08 shelton add support f423 * 2023-10-18 shelton add support f402/f405 * 2024-04-12 shelton add support a403a and a423 + * 2024-07-31 shelton add support hwi2c driver */ #ifndef __DRV_CONFIG_H__ @@ -25,54 +26,64 @@ extern "C" { #if defined(SOC_SERIES_AT32A403A) #include "a403a/dma_config.h" #include "a403a/uart_config.h" +#include "a403a/i2c_config.h" #include "a403a/spi_config.h" #include "a403a/usb_config.h" #include "a403a/dac_config.h" #elif defined(SOC_SERIES_AT32A423) #include "a423/dma_config.h" #include "a423/uart_config.h" +#include "a423/i2c_config.h" #include "a423/spi_config.h" #include "a423/usb_config.h" #include "a423/dac_config.h" #elif defined(SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) #include "f402_405/dma_config.h" #include "f402_405/uart_config.h" +#include "f402_405/i2c_config.h" #include "f402_405/spi_config.h" #include "f402_405/usb_config.h" #elif defined(SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) #include "f403a_407/dma_config.h" #include "f403a_407/uart_config.h" +#include "f403a_407/i2c_config.h" #include "f403a_407/spi_config.h" #include "f403a_407/usb_config.h" #include "f403a_407/dac_config.h" #elif defined(SOC_SERIES_AT32F413) #include "f413/dma_config.h" #include "f413/uart_config.h" +#include "f413/i2c_config.h" #include "f413/spi_config.h" #include "f413/usb_config.h" #elif defined(SOC_SERIES_AT32F415) #include "f415/dma_config.h" #include "f415/uart_config.h" +#include "f415/i2c_config.h" #include "f415/spi_config.h" #include "f415/usb_config.h" #elif defined(SOC_SERIES_AT32F421) #include "f421/dma_config.h" #include "f421/uart_config.h" +#include "f421/i2c_config.h" #include "f421/spi_config.h" #elif defined(SOC_SERIES_AT32F423) #include "f423/dma_config.h" #include "f423/uart_config.h" +#include "f423/i2c_config.h" #include "f423/spi_config.h" #include "f423/usb_config.h" #include "f423/dac_config.h" #elif defined(SOC_SERIES_AT32F425) #include "f425/dma_config.h" #include "f425/uart_config.h" +#include "f425/i2c_config.h" #include "f425/spi_config.h" #include "f425/usb_config.h" #elif defined(SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) #include "f435_437/dma_config.h" #include "f435_437/uart_config.h" +#include "f435_437/i2c_config.h" #include "f435_437/spi_config.h" #include "f435_437/usb_config.h" #include "f435_437/dac_config.h" diff --git a/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c new file mode 100644 index 0000000000..b6f5202e5e --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c @@ -0,0 +1,1695 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#include "drv_common.h" +#include "drv_hard_i2c.h" +#include "drv_config.h" +#include + +#if defined(BSP_USING_HARD_I2C1) || defined(BSP_USING_HARD_I2C2) || \ + defined(BSP_USING_HARD_I2C3) + +//#define DRV_DEBUG +#define LOG_TAG "drv.hwi2c" +#include + +enum +{ +#ifdef BSP_USING_HARD_I2C1 + I2C1_INDEX, +#endif +#ifdef BSP_USING_HARD_I2C2 + I2C2_INDEX, +#endif +#ifdef BSP_USING_HARD_I2C3 + I2C3_INDEX, +#endif +}; + +static struct at32_i2c_handle i2c_handle[] = { +#ifdef BSP_USING_HARD_I2C1 + I2C1_CONFIG, +#endif + +#ifdef BSP_USING_HARD_I2C2 + I2C2_CONFIG, +#endif + +#ifdef BSP_USING_HARD_I2C3 + I2C3_CONFIG, +#endif +}; + +static struct at32_i2c i2cs[sizeof(i2c_handle) / sizeof(i2c_handle[0])] = {0}; + +/* private rt-thread i2c ops function */ +static rt_ssize_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); +static struct rt_i2c_bus_device_ops at32_i2c_ops = +{ + master_xfer, + RT_NULL, + RT_NULL +}; + +static rt_err_t at32_i2c_configure(struct rt_i2c_bus_device *bus) +{ + RT_ASSERT(RT_NULL != bus); + struct at32_i2c *instance = rt_container_of(bus, struct at32_i2c, i2c_bus); + + at32_msp_i2c_init(instance->handle->i2c_x); + +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + i2c_init(instance->handle->i2c_x, I2C_FSMODE_DUTY_2_1, instance->handle->timing); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + i2c_init(instance->handle->i2c_x, 0x0F, instance->handle->timing); +#endif + i2c_own_address1_set(instance->handle->i2c_x, I2C_ADDRESS_MODE_7BIT, HWI2C_OWN_ADDRESS); + + nvic_irq_enable(instance->handle->ev_irqn, 0, 0); + nvic_irq_enable(instance->handle->er_irqn, 0, 0); + + i2c_enable(instance->handle->i2c_x, TRUE); + + return RT_EOK; +} + +static void i2c_dma_config(struct at32_i2c_handle *handle, rt_uint8_t *buffer, rt_uint32_t size) +{ + struct dma_config *dma = RT_NULL; + + if(handle->comm.mode == I2C_DMA_MA_TX) + { + dma = handle->dma_tx; +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->dt); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->txdt); +#endif + } + else if(handle->comm.mode == I2C_DMA_MA_RX) + { + dma = handle->dma_rx; +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->dt); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->rxdt); +#endif + } + + dma->dma_channel->dtcnt = size; + dma->dma_channel->maddr = (rt_uint32_t)buffer; + + /* enable transmit complete interrupt */ + dma_interrupt_enable(dma->dma_channel, DMA_FDT_INT, TRUE); + + /* mark dma flag */ + dma->dma_done = RT_FALSE; + /* enable dma channel */ + dma_channel_enable(dma->dma_channel, TRUE); +} + +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) +void i2c_refresh_txdt_register(i2c_type *i2c_x) +{ + /* clear tdis flag */ + if (i2c_flag_get(i2c_x, I2C_TDIS_FLAG) != RESET) + { + i2c_x->txdt = 0x00; + } + /* refresh txdt register*/ + if (i2c_flag_get(i2c_x, I2C_TDBE_FLAG) == RESET) + { + i2c_x->sts_bit.tdbe = 1; + } +} + +void i2c_reset_ctrl2_register(i2c_type *i2c_x) +{ + i2c_x->ctrl2_bit.saddr = 0; + i2c_x->ctrl2_bit.readh10 = 0; + i2c_x->ctrl2_bit.cnt = 0; + i2c_x->ctrl2_bit.rlden = 0; + i2c_x->ctrl2_bit.dir = 0; +} +#endif + +i2c_status_type i2c_wait_end(struct at32_i2c_handle *handle, uint32_t timeout) +{ + while(handle->comm.status != I2C_END) + { + /* check timeout */ + if((timeout--) == 0) + { + return I2C_ERR_TIMEOUT; + } + } + + if(handle->comm.error_code != I2C_OK) + { + return handle->comm.error_code; + } + else + { + return I2C_OK; + } +} + +i2c_status_type i2c_wait_flag(struct at32_i2c_handle *handle, uint32_t flag, uint32_t event_check, uint32_t timeout) +{ + if(flag == I2C_BUSYF_FLAG) + { + while(i2c_flag_get(handle->i2c_x, flag) != RESET) + { + /* check timeout */ + if((timeout--) == 0) + { + handle->comm.error_code = I2C_ERR_TIMEOUT; + + return I2C_ERR_TIMEOUT; + } + } + } + else + { + while(i2c_flag_get(handle->i2c_x, flag) == RESET) + { + /* check the ack fail flag */ + if(event_check & I2C_EVENT_CHECK_ACKFAIL) + { + if(i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); +#endif + /* clear ack fail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + handle->comm.error_code = I2C_ERR_ACKFAIL; + + return I2C_ERR_ACKFAIL; + } + } + + /* check the stop flag */ + if(event_check & I2C_EVENT_CHECK_STOP) + { + if(i2c_flag_get(handle->i2c_x, I2C_STOPF_FLAG) != RESET) + { + /* clear stop flag */ + i2c_flag_clear(handle->i2c_x, I2C_STOPF_FLAG); +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + i2c_reset_ctrl2_register(handle->i2c_x); +#endif + handle->comm.error_code = I2C_ERR_STOP; + + return I2C_ERR_STOP; + } + } + + /* check timeout */ + if((timeout--) == 0) + { + handle->comm.error_code = I2C_ERR_TIMEOUT; + + return I2C_ERR_TIMEOUT; + } + } + } + + return I2C_OK; +} + +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) +i2c_status_type i2c_master_write_addr(struct at32_i2c_handle *handle, uint16_t address, uint32_t timeout) +{ + /* generate start condtion */ + i2c_start_generate(handle->i2c_x); + + /* wait for the start flag to be set */ + if(i2c_wait_flag(handle, I2C_STARTF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_START; + + return I2C_ERR_START; + } + + if(handle->i2c_x->oaddr1_bit.addr1mode == I2C_ADDRESS_MODE_7BIT) + { + /* send slave address */ + i2c_7bit_address_send(handle->i2c_x, address, I2C_DIRECTION_TRANSMIT); + } + else + { + /* send slave 10-bit address header */ + i2c_data_send(handle->i2c_x, (uint8_t)((address & 0x0300) >> 7) | 0xF0); + + /* wait for the addrh flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDRHF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR10; + + return I2C_ERR_ADDR10; + } + + /* send slave address */ + i2c_data_send(handle->i2c_x, (uint8_t)(address & 0x00FF)); + } + + /* wait for the addr7 flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDR7F_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR; + + return I2C_ERR_ADDR; + } + + return I2C_OK; +} + +i2c_status_type i2c_master_read_addr(struct at32_i2c_handle *handle, uint16_t address, uint32_t timeout) +{ + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* generate start condtion */ + i2c_start_generate(handle->i2c_x); + + /* wait for the start flag to be set */ + if(i2c_wait_flag(handle, I2C_STARTF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_START; + + return I2C_ERR_START; + } + + if(handle->i2c_x->oaddr1_bit.addr1mode == I2C_ADDRESS_MODE_7BIT) + { + /* send slave address */ + i2c_7bit_address_send(handle->i2c_x, address, I2C_DIRECTION_RECEIVE); + } + else + { + /* send slave 10-bit address header */ + i2c_data_send(handle->i2c_x, (uint8_t)((address & 0x0300) >> 7) | 0xF0); + + /* wait for the addrh flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDRHF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR10; + + return I2C_ERR_ADDR10; + } + + /* send slave address */ + i2c_data_send(handle->i2c_x, (uint8_t)(address & 0x00FF)); + + /* wait for the addr7 flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDR7F_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR; + + return I2C_ERR_ADDR; + } + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* generate restart condtion */ + i2c_start_generate(handle->i2c_x); + + /* wait for the start flag to be set */ + if(i2c_wait_flag(handle, I2C_STARTF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_START; + + return I2C_ERR_START; + } + + /* send slave 10-bit address header */ + i2c_data_send(handle->i2c_x, (uint8_t)((address & 0x0300) >> 7) | 0xF1); + } + + /* wait for the addr7 flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDR7F_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR; + + return I2C_ERR_ADDR; + } + + return I2C_OK; +} + +i2c_status_type i2c_master_transmit_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* send slave address */ + if(i2c_master_write_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* send slave address */ + if(i2c_master_read_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + if(handle->comm.pcount == 1) + { + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + } + else if(handle->comm.pcount == 2) + { + /* ack acts on the next byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_NEXT); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + } + else + { + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + } + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_transmit_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, FALSE); + + /* configure the dma channel */ + i2c_dma_config(handle, pdata, size); + + /* send slave address */ + if(i2c_master_write_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, FALSE); + + /* configure the dma channel */ + i2c_dma_config(handle, pdata, size); + + /* send slave address */ + if(i2c_master_read_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + if(size == 1) + { + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, TRUE); + } + else + { + /* enable dma end transfer */ + i2c_dma_end_transfer_set(handle->i2c_x, TRUE); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, TRUE); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + } + + return I2C_OK; +} + + +void i2c_master_tx_isr_int(struct at32_i2c_handle *handle) +{ + /* step 1: transfer data */ + if(i2c_flag_get(handle->i2c_x, I2C_TDBE_FLAG) != RESET) + { + if(handle->comm.pcount == 0) + { + rt_completion_done(&handle->completion); + + /* transfer complete */ + handle->comm.status = I2C_END; + + /* disable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, FALSE); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + } + else + { + /* write data */ + i2c_data_send(handle->i2c_x, *handle->comm.pbuff++); + handle->comm.pcount--; + } + } +} + +void i2c_master_rx_isr_int(struct at32_i2c_handle *handle) +{ + if(i2c_flag_get(handle->i2c_x, I2C_TDC_FLAG) != RESET) + { + if(handle->comm.pcount == 3) + { + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + } + else if(handle->comm.pcount == 2) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + + /* transfer complete */ + rt_completion_done(&handle->completion); + handle->comm.status = I2C_END; + + /* disable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, FALSE); + } + else + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + } + } + else if(i2c_flag_get(handle->i2c_x, I2C_RDBF_FLAG) != RESET) + { + if(handle->comm.pcount > 3) + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + } + else if((handle->comm.pcount == 3) || (handle->comm.pcount == 2)) + { + /* disable rdbf interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_DATA_INT, FALSE); + } + else + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + + /* transfer complete */ + rt_completion_done(&handle->completion); + handle->comm.status = I2C_END; + + /* disable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, FALSE); + } + } +} + +void i2c_master_tx_isr_dma(struct at32_i2c_handle *handle) +{ + /* tdc interrupt */ + if(i2c_flag_get(handle->i2c_x, I2C_TDC_FLAG) != RESET) + { + rt_completion_done(&handle->completion); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* disable evt interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + } +} + +void i2c_evt_isr(struct at32_i2c_handle *handle) +{ + switch(handle->comm.mode) + { + case I2C_INT_MA_TX: + i2c_master_tx_isr_int(handle); + break; + case I2C_INT_MA_RX: + i2c_master_rx_isr_int(handle); + break; + case I2C_DMA_MA_TX: + i2c_master_tx_isr_dma(handle); + break; + default: + break; + } +} +#endif + +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) +void i2c_start_transfer(struct at32_i2c_handle *handle, uint16_t address, i2c_start_mode_type start) +{ + if (handle->comm.pcount > MAX_TRANSFER_CNT) + { + handle->comm.psize = MAX_TRANSFER_CNT; + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_RELOAD_MODE, start); + } + else + { + handle->comm.psize = handle->comm.pcount; + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_AUTO_STOP_MODE, start); + } +} + +void i2c_start_transfer_dma(struct at32_i2c_handle *handle, uint16_t address, i2c_start_mode_type start) +{ + if (handle->comm.pcount > MAX_TRANSFER_CNT) + { + handle->comm.psize = MAX_TRANSFER_CNT; + + /* config dma */ + i2c_dma_config(handle, handle->comm.pbuff, handle->comm.psize); + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_RELOAD_MODE, start); + } + else + { + handle->comm.psize = handle->comm.pcount; + + /* config dma */ + i2c_dma_config(handle, handle->comm.pbuff, handle->comm.psize); + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_AUTO_STOP_MODE, start); + } +} + +i2c_status_type i2c_master_transmit_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if (i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* start transfer */ + i2c_start_transfer(handle, address, I2C_GEN_START_WRITE); + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if (i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* start transfer */ + i2c_start_transfer(handle, address, I2C_GEN_START_READ); + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_RD_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_transmit_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, FALSE); + + /* start transfer */ + i2c_start_transfer_dma(handle, address, I2C_GEN_START_WRITE); + + /* enable i2c interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, FALSE); + + /* start transfer */ + i2c_start_transfer_dma(handle, address, I2C_GEN_START_READ); + + /* enable i2c interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, TRUE); + + return I2C_OK; +} + +void i2c_master_isr_int(struct at32_i2c_handle *handle) +{ + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + /* refresh tx register */ + i2c_refresh_txdt_register(handle->i2c_x); + + if(handle->comm.pcount != 0) + { + handle->comm.error_code = I2C_ERR_ACKFAIL; + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_TDIS_FLAG) != RESET) + { + /* send data */ + i2c_data_send(handle->i2c_x, *handle->comm.pbuff++); + handle->comm.pcount--; + handle->comm.psize--; + } + else if (i2c_flag_get(handle->i2c_x, I2C_TCRLD_FLAG) != RESET) + { + if ((handle->comm.psize == 0) && (handle->comm.pcount != 0)) + { + /* continue transfer */ + i2c_start_transfer(handle, i2c_transfer_addr_get(handle->i2c_x), I2C_WITHOUT_START); + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_RDBF_FLAG) != RESET) + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + handle->comm.psize--; + } + else if (i2c_flag_get(handle->i2c_x, I2C_TDC_FLAG) != RESET) + { + if (handle->comm.pcount == 0) + { + if (handle->i2c_x->ctrl2_bit.astopen == 0) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + } + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_STOPF_FLAG) != RESET) + { + /* clear stop flag */ + i2c_flag_clear(handle->i2c_x, I2C_STOPF_FLAG); + + /* reset ctrl2 register */ + i2c_reset_ctrl2_register(handle->i2c_x); + + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + } + + /* refresh tx dt register */ + i2c_refresh_txdt_register(handle->i2c_x); + + /* disable interrupts */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT | I2C_RD_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + rt_completion_done(&handle->completion); + } +} + +void i2c_master_isr_dma(struct at32_i2c_handle *handle) +{ + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + /* enable stop interrupt to wait for stop generate stop */ + i2c_interrupt_enable(handle->i2c_x, I2C_STOP_INT, TRUE); + + /* refresh tx dt register */ + i2c_refresh_txdt_register(handle->i2c_x); + + if(handle->comm.pcount != 0) + { + handle->comm.error_code = I2C_ERR_ACKFAIL; + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_TCRLD_FLAG) != RESET) + { + /* disable tdc interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_TDC_INT, FALSE); + + if (handle->comm.pcount != 0) + { + /* continue transfer */ + i2c_start_transfer(handle, i2c_transfer_addr_get(handle->i2c_x), I2C_WITHOUT_START); + + /* enable dma request */ + if(handle->comm.mode == I2C_DMA_MA_TX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, TRUE); + else if(handle->comm.mode == I2C_DMA_MA_RX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, TRUE); + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_STOPF_FLAG) != RESET) + { + /* clear stop flag */ + i2c_flag_clear(handle->i2c_x, I2C_STOPF_FLAG); + + /* reset ctrl2 register */ + i2c_reset_ctrl2_register(handle->i2c_x); + + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + } + + /* refresh tx dt register */ + i2c_refresh_txdt_register(handle->i2c_x); + + /* disable interrupts */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT | I2C_RD_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + rt_completion_done(&handle->completion); + } +} + +void i2c_evt_isr(struct at32_i2c_handle *handle) +{ + switch(handle->comm.mode) + { + case I2C_INT_MA_TX: + case I2C_INT_MA_RX: + i2c_master_isr_int(handle); + break; + case I2C_DMA_MA_TX: + case I2C_DMA_MA_RX: + i2c_master_isr_dma(handle); + break; + default: + break; + } +} +#endif + +static rt_ssize_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + /* for dma may more stability */ +#define DMA_TRANS_MIN_LEN 2 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ +#define TRANS_TIMEOUT_PERSEC 8 /* per ms will trans nums bytes */ + + rt_int32_t i, ret; + struct rt_i2c_msg *msg = msgs; + struct rt_completion *completion; + rt_uint32_t timeout; + if (num == 0) + { + return 0; + } + RT_ASSERT((msgs != RT_NULL) && (bus != RT_NULL)); + struct at32_i2c *instance = rt_container_of(bus, struct at32_i2c, i2c_bus); + completion = &instance->handle->completion; + + LOG_D("xfer start %d mags", num); + for (i = 0; i < (num - 1); i++) + { + msg = &msgs[i]; + LOG_D("xfer msgs[%d] addr=0x%2x buf=0x%x len= 0x%x flags= 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); + timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; + + if (msg->flags & RT_I2C_RD) + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_receive_dma(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_receive_int(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_E("[%s:%d]i2c read error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("receive time out"); + goto out; + } + } + else + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_transmit_dma(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_transmit_int(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]i2c write error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("transmit time out"); + goto out; + } + } + } + /* last msg */ + msg = &msgs[i]; + timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; + + LOG_D("xfer last msgs[%d] addr=0x%2x buf= 0x%x len= 0x%x flags = 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); + if (msg->flags & RT_I2C_RD) + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_receive_dma(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_receive_int(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]i2c read error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("receive time out"); + goto out; + } + } + else + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_transmit_dma(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_transmit_int(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]i2c write error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("transmit time out"); + goto out; + } + } + ret = num; + LOG_D("xfer end %d mags\r\n", num); + return ret; + +out: + if(instance->handle->comm.error_code == I2C_ERR_ACKFAIL) + { + LOG_D("i2c nack error now stoped"); + } + if(instance->handle->comm.error_code == I2C_ERR_INTERRUPT) + { + LOG_D("i2c bus error now stoped"); + ret = i - 1; + } + /* generate stop */ + i2c_stop_generate(instance->handle->i2c_x); + return ret; +} + +static void _dma_base_channel_check(struct at32_i2c *instance) +{ + dma_channel_type *rx_channel = instance->handle->dma_rx->dma_channel; + dma_channel_type *tx_channel = instance->handle->dma_tx->dma_channel; + + if(instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + instance->handle->dma_rx->dma_done = RT_TRUE; + instance->handle->dma_rx->dma_x = (dma_type *)((rt_uint32_t)rx_channel & ~0xFF); + instance->handle->dma_rx->channel_index = ((((rt_uint32_t)rx_channel & 0xFF) - 8) / 0x14) + 1; + } + + if(instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + instance->handle->dma_tx->dma_done = RT_TRUE; + instance->handle->dma_tx->dma_x = (dma_type *)((rt_uint32_t)tx_channel & ~0xFF); + instance->handle->dma_tx->channel_index = ((((rt_uint32_t)tx_channel & 0xFF) - 8) / 0x14) + 1; + } +} + +static void at32_i2c_dma_init(struct at32_i2c *instance) +{ + dma_init_type dma_init_struct; + + /* search dma base and channel index */ + _dma_base_channel_check(instance); + + /* config dma channel */ + dma_default_para_init(&dma_init_struct); + dma_init_struct.peripheral_inc_enable = FALSE; + dma_init_struct.memory_inc_enable = TRUE; + dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE; + dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE; + dma_init_struct.priority = DMA_PRIORITY_MEDIUM; + dma_init_struct.loop_mode_enable = FALSE; + + if (instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + crm_periph_clock_enable(instance->handle->dma_rx->dma_clock, TRUE); + dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY; + + dma_reset(instance->handle->dma_rx->dma_channel); + dma_init(instance->handle->dma_rx->dma_channel, &dma_init_struct); +#if defined (SOC_SERIES_AT32F425) + dma_flexible_config(instance->handle->dma_rx->dma_x, instance->handle->dma_rx->flex_channel, \ + (dma_flexible_request_type)instance->handle->dma_rx->request_id); +#endif +#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \ + defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) + dmamux_enable(instance->handle->dma_rx->dma_x, TRUE); + dmamux_init(instance->handle->dma_rx->dmamux_channel, (dmamux_requst_id_sel_type)instance->handle->dma_rx->request_id); +#endif + /* dma irq should set in dma rx mode */ + nvic_irq_enable(instance->handle->dma_rx->dma_irqn, 0, 1); + } + + if (instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + crm_periph_clock_enable(instance->handle->dma_tx->dma_clock, TRUE); + dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL; + + dma_reset(instance->handle->dma_tx->dma_channel); + dma_init(instance->handle->dma_tx->dma_channel, &dma_init_struct); +#if defined (SOC_SERIES_AT32F425) + dma_flexible_config(instance->handle->dma_tx->dma_x, instance->handle->dma_tx->flex_channel, \ + (dma_flexible_request_type)instance->handle->dma_tx->request_id); +#endif +#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \ + defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) + dmamux_enable(instance->handle->dma_tx->dma_x, TRUE); + dmamux_init(instance->handle->dma_tx->dmamux_channel, (dmamux_requst_id_sel_type)instance->handle->dma_tx->request_id); +#endif + /* dma irq should set in dma tx mode */ + nvic_irq_enable(instance->handle->dma_tx->dma_irqn, 0, 1); + } +} + +void i2c_err_isr(struct at32_i2c_handle *handle) +{ + /* buserr */ + if(i2c_flag_get(handle->i2c_x, I2C_BUSERR_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_BUSERR_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* arlost */ + if(i2c_flag_get(handle->i2c_x, I2C_ARLOST_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_ARLOST_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + /* ackfail */ + if(i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + switch(handle->comm.mode) + { + case I2C_DMA_SLA_TX: + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* disable evt interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + break; + default: + handle->comm.error_code = I2C_ERR_INTERRUPT; + break; + } + } +#endif + + /* ouf */ + if(i2c_flag_get(handle->i2c_x, I2C_OUF_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_OUF_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* pecerr */ + if(i2c_flag_get(handle->i2c_x, I2C_PECERR_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_PECERR_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* tmout */ + if(i2c_flag_get(handle->i2c_x, I2C_TMOUT_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_TMOUT_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* alertf */ + if(i2c_flag_get(handle->i2c_x, I2C_ALERTF_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_ALERTF_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* disable all interrupts */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT, FALSE); +} + +void dma_isr(struct at32_i2c_handle *handle) +{ + volatile rt_uint32_t reg_sts = 0, index = 0; + struct dma_config *dma = RT_NULL; + + if(handle->comm.mode == I2C_DMA_MA_TX) + { + dma = handle->dma_tx; + } + else if(handle->comm.mode == I2C_DMA_MA_RX) + { + dma = handle->dma_rx; + } + + reg_sts = dma->dma_x->sts; + index = dma->channel_index; + + /* transfer complete */ + if((reg_sts & (DMA_FDT_FLAG << (4 * (index - 1)))) != RESET) + { + /* clear dma flag */ + dma->dma_x->clr |= (rt_uint32_t)((DMA_FDT_FLAG << (4 * (index - 1))) | \ + (DMA_HDT_FLAG << (4 * (index - 1)))); + /* disable the transfer complete interrupt */ + dma_interrupt_enable(dma->dma_channel, DMA_FDT_INT, FALSE); + /* mark done */ + dma->dma_done = RT_TRUE; +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, FALSE); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + /* disable dma request */ + if(handle->comm.mode == I2C_DMA_MA_TX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, FALSE); + else if(handle->comm.mode == I2C_DMA_MA_RX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, FALSE); +#endif + /* disable dma channel */ + dma_channel_enable(dma->dma_channel, FALSE); + + switch(handle->comm.mode) + { +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + case I2C_DMA_MA_TX: + /* enable tdc interrupt, generate stop condition in tdc interrupt */ + handle->comm.pcount = 0; + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT, TRUE); + break; + case I2C_DMA_MA_RX: + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + handle->comm.pcount = 0; + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* transfer complete */ + rt_completion_done(&handle->completion); + handle->comm.status = I2C_END; + break; + default: + break; +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + case I2C_DMA_MA_TX: + case I2C_DMA_MA_RX: + { + /* update the number of transfers */ + handle->comm.pcount -= handle->comm.psize; + + /* transfer complete */ + if (handle->comm.pcount == 0) + { + /* enable stop interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_STOP_INT, TRUE); + } + /* the transfer has not been completed */ + else + { + /* update the buffer pointer of transfers */ + handle->comm.pbuff += handle->comm.psize; + + /* set the number to be transferred */ + if (handle->comm.pcount > MAX_TRANSFER_CNT) + { + handle->comm.psize = MAX_TRANSFER_CNT; + } + else + { + handle->comm.psize = handle->comm.pcount; + } + + /* config dma channel, continue to transfer data */ + i2c_dma_config(handle, handle->comm.pbuff, handle->comm.psize); + + /* enable tdc interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_TDC_INT, TRUE); + } + } + break; + default: + break; +#endif + } + } +} + +#ifdef BSP_USING_HARD_I2C1 +void I2C1_EVT_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_evt_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void I2C1_ERR_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_err_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C1_RX_USING_DMA) +void I2C1_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C1_RX_USING_DMA) */ +#if defined(BSP_I2C1_TX_USING_DMA) +void I2C1_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C1_TX_USING_DMA) */ +#endif +#ifdef BSP_USING_HARD_I2C2 +void I2C2_EVT_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_evt_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void I2C2_ERR_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_err_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C2_RX_USING_DMA) +void I2C2_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C2_RX_USING_DMA) */ +#if defined(BSP_I2C2_TX_USING_DMA) +void I2C2_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C2_TX_USING_DMA) */ +#endif +#ifdef BSP_USING_HARD_I2C3 +void I2C3_EVT_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_evt_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void I2C3_ERR_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_err_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C3_RX_USING_DMA) +void I2C3_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C3_RX_USING_DMA) */ +#if defined(BSP_I2C3_TX_USING_DMA) +void I2C3_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C3_TX_USING_DMA) */ +#endif + +#if defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) +void I2C1_TX_RX_DMA_IRQHandler(void) +{ +#if defined(BSP_USING_HARD_I2C1) && defined(BSP_I2C1_TX_USING_DMA) + I2C1_TX_DMA_IRQHandler(); +#endif + +#if defined(BSP_USING_HARD_I2C1) && defined(BSP_I2C1_RX_USING_DMA) + I2C1_RX_DMA_IRQHandler(); +#endif +} + +void I2C2_TX_RX_DMA_IRQHandler(void) +{ +#if defined(BSP_USING_HARD_I2C2) && defined(BSP_I2C2_TX_USING_DMA) + I2C2_TX_DMA_IRQHandler(); +#endif + +#if defined(BSP_USING_HARD_I2C2) && defined(BSP_I2C2_RX_USING_DMA) + I2C2_RX_DMA_IRQHandler(); +#endif +} +#endif + +static void at32_i2c_get_dma_config(void) +{ +#ifdef BSP_USING_HARD_I2C1 + i2c_handle[I2C1_INDEX].i2c_dma_flag = 0; +#ifdef BSP_I2C1_RX_USING_DMA + i2c_handle[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config i2c1_dma_rx = I2C1_RX_DMA_CONFIG; + i2c_handle[I2C1_INDEX].dma_rx = &i2c1_dma_rx; +#endif +#ifdef BSP_I2C1_TX_USING_DMA + i2c_handle[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config i2c1_dma_tx = I2C1_TX_DMA_CONFIG; + i2c_handle[I2C1_INDEX].dma_tx = &i2c1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_HARD_I2C2 + i2c_handle[I2C2_INDEX].i2c_dma_flag = 0; +#ifdef BSP_I2C2_RX_USING_DMA + i2c_handle[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config i2c2_dma_rx = I2C2_RX_DMA_CONFIG; + i2c_handle[I2C2_INDEX].dma_rx = &i2c2_dma_rx; +#endif +#ifdef BSP_I2C2_TX_USING_DMA + i2c_handle[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config i2c2_dma_tx = I2C2_TX_DMA_CONFIG; + i2c_handle[I2C2_INDEX].dma_tx = &i2c2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_HARD_I2C3 + i2c_handle[I2C3_INDEX].i2c_dma_flag = 0; +#ifdef BSP_I2C3_RX_USING_DMA + i2c_handle[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config i2c3_dma_rx = I2C3_RX_DMA_CONFIG; + i2c_handle[I2C3_INDEX].dma_rx = &i2c3_dma_rx; +#endif +#ifdef BSP_I2C3_TX_USING_DMA + i2c_handle[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config i2c3_dma_tx = I2C3_TX_DMA_CONFIG; + i2c_handle[I2C3_INDEX].dma_tx = &i2c3_dma_tx; +#endif +#endif +} + +int rt_hw_hwi2c_init(void) +{ + int i; + rt_err_t result; + rt_size_t obj_num = sizeof(i2c_handle) / sizeof(i2c_handle[0]); + + at32_i2c_get_dma_config(); + + for (i = 0; i < obj_num; i++) + { + i2cs[i].handle = &i2c_handle[i]; + i2cs[i].i2c_bus.ops = &at32_i2c_ops; + + if(i2cs[i].handle->i2c_dma_flag & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) + { + at32_i2c_dma_init(&i2cs[i]); + } + rt_completion_init(&i2cs[i].handle->completion); + at32_i2c_configure(&(i2cs[i].i2c_bus)); + result = rt_i2c_bus_device_register(&(i2cs[i].i2c_bus), i2cs[i].handle->i2c_name); + } + + return result; +} + +INIT_BOARD_EXPORT(rt_hw_hwi2c_init); + +#endif diff --git a/bsp/at32/libraries/rt_drivers/drv_hard_i2c.h b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.h new file mode 100644 index 0000000000..bc34abf1c9 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __DRV_HARD_I2C_H__ +#define __DRV_HARD_I2C_H__ + +#include +#include +#include "drv_common.h" +#include "drv_dma.h" + +#define I2C_START 0 +#define I2C_END 1 + +#define I2C_EVENT_CHECK_NONE ((uint32_t)0x00000000) +#define I2C_EVENT_CHECK_ACKFAIL ((uint32_t)0x00000001) +#define I2C_EVENT_CHECK_STOP ((uint32_t)0x00000002) + +typedef enum +{ + I2C_INT_MA_TX = 0, + I2C_INT_MA_RX, + I2C_INT_SLA_TX, + I2C_INT_SLA_RX, + I2C_DMA_MA_TX, + I2C_DMA_MA_RX, + I2C_DMA_SLA_TX, + I2C_DMA_SLA_RX, +} i2c_mode_type; + +typedef enum +{ + I2C_OK = 0, + I2C_ERR_STEP_1, + I2C_ERR_STEP_2, + I2C_ERR_STEP_3, + I2C_ERR_STEP_4, + I2C_ERR_STEP_5, + I2C_ERR_STEP_6, + I2C_ERR_STEP_7, + I2C_ERR_STEP_8, + I2C_ERR_STEP_9, + I2C_ERR_STEP_10, + I2C_ERR_STEP_11, + I2C_ERR_STEP_12, + I2C_ERR_START, + I2C_ERR_ADDR10, + I2C_ERR_TCRLD, + I2C_ERR_TDC, + I2C_ERR_ADDR, + I2C_ERR_STOP, + I2C_ERR_ACKFAIL, + I2C_ERR_TIMEOUT, + I2C_ERR_INTERRUPT, +} i2c_status_type; + +struct i2c_comm_type +{ + rt_uint8_t *pbuff; + rt_uint16_t psize; + rt_uint16_t pcount; + i2c_mode_type mode; + rt_uint32_t timeout; + rt_uint32_t status; + i2c_status_type error_code; +}; + +struct at32_i2c_handle +{ + i2c_type *i2c_x; + const char *i2c_name; + rt_uint32_t timing; + IRQn_Type ev_irqn; + IRQn_Type er_irqn; + struct dma_config *dma_rx; + struct dma_config *dma_tx; + struct i2c_comm_type comm; + rt_uint16_t i2c_dma_flag; + struct rt_completion completion; +}; + +struct at32_i2c +{ + struct at32_i2c_handle *handle; + struct rt_i2c_bus_device i2c_bus; +}; + +#endif