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[bsp][stm32] update f7-hal library

This commit is contained in:
SummerGift 2018-12-26 10:30:22 +08:00
parent ea9958a506
commit d193dbbda3
58 changed files with 3735 additions and 3475 deletions
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14
bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h
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@ -74,7 +74,9 @@
*/ */
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ #if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
!defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \
!defined (STM32F750xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */ STM32F756NG Devices */
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
@ -93,6 +95,8 @@
/* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
/* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
/* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
/* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */
/* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -109,11 +113,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V1.2.2 * @brief CMSIS Device version number V1.2.3
*/ */
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F7_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ #define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
@ -150,6 +154,10 @@
#include "stm32f777xx.h" #include "stm32f777xx.h"
#elif defined(STM32F779xx) #elif defined(STM32F779xx)
#include "stm32f779xx.h" #include "stm32f779xx.h"
#elif defined(STM32F730xx)
#include "stm32f730xx.h"
#elif defined(STM32F750xx)
#include "stm32f750xx.h"
#else #else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif #endif

27
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

@ -381,7 +381,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{ * @{
*/ */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -431,12 +431,12 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@ -564,7 +564,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -2120,20 +2120,6 @@
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
#if defined(STM32WB)
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
#define QSPI_IRQHandler QUADSPI_IRQHandler
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@ -2804,7 +2790,6 @@
#if defined(STM32L4) #if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0)
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif #endif
@ -2932,10 +2917,8 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32G0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT

8
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h
View File

@ -93,7 +93,7 @@ typedef enum
#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/
@ -103,7 +103,7 @@ typedef enum
#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/
#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
/** /**
* @} * @}
@ -143,7 +143,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
*/ */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
((CHANNEL) == DMA_CHANNEL_1) || \ ((CHANNEL) == DMA_CHANNEL_1) || \
((CHANNEL) == DMA_CHANNEL_2) || \ ((CHANNEL) == DMA_CHANNEL_2) || \
@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
((CHANNEL) == DMA_CHANNEL_6) || \ ((CHANNEL) == DMA_CHANNEL_6) || \
((CHANNEL) == DMA_CHANNEL_7)) ((CHANNEL) == DMA_CHANNEL_7))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/
/** /**
* @} * @}
*/ */

10
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h
View File

@ -185,6 +185,15 @@ typedef struct
/** @defgroup FLASH_Sectors FLASH Sectors /** @defgroup FLASH_Sectors FLASH Sectors
* @{ * @{
*/ */
#if (FLASH_SECTOR_TOTAL == 2)
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
#elif (FLASH_SECTOR_TOTAL == 4)
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
#else
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ #define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ #define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ #define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
@ -193,6 +202,7 @@ typedef struct
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ #define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ #define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ #define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
#endif /* FLASH_SECTOR_TOTAL */
/** /**
* @} * @}
*/ */

55
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h
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@ -440,7 +440,34 @@ typedef struct
*/ */
#endif /* FLASH_SECTOR_TOTAL == 8 */ #endif /* FLASH_SECTOR_TOTAL == 8 */
#if (FLASH_SECTOR_TOTAL == 4)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */
/**
* @}
*/
#endif /* FLASH_SECTOR_TOTAL == 4 */
#if (FLASH_SECTOR_TOTAL == 2)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */
/**
* @}
*/
#endif /* FLASH_SECTOR_TOTAL == 2 */
#if defined (FLASH_OPTCR2_PCROP) #if defined (FLASH_OPTCR2_PCROP)
#if (FLASH_SECTOR_TOTAL == 8)
/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors /** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
* @{ * @{
*/ */
@ -456,6 +483,21 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif /* FLASH_SECTOR_TOTAL == 8 */
#if (FLASH_SECTOR_TOTAL == 4)
/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
* @{
*/
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */
#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */
/**
* @}
*/
#endif /* FLASH_SECTOR_TOTAL == 4 */
/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit /** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit
* @{ * @{
@ -607,6 +649,19 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 24 */ #endif /* FLASH_SECTOR_TOTAL == 24 */
#if (FLASH_SECTOR_TOTAL == 4)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 4 */
#if (FLASH_SECTOR_TOTAL == 2)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 2 */
#if defined (FLASH_OPTCR_nDBANK) #if defined (FLASH_OPTCR_nDBANK)
#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ #define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
((VALUE) == OB_NDBANK_DUAL_BANK)) ((VALUE) == OB_NDBANK_DUAL_BANK))

33
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h
View File

@ -64,7 +64,7 @@
*/ */
/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ /*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/** /**
* @brief AF 0 selection * @brief AF 0 selection
*/ */
@ -173,12 +173,12 @@
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ #define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) #if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ #define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) #if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ #define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @brief AF 10 selection * @brief AF 10 selection
*/ */
@ -220,14 +220,14 @@
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ #define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) #if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ #define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */
/** /**
* @brief AF 14 selection * @brief AF 14 selection
*/ */
#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ #define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @brief AF 15 selection * @brief AF 15 selection
*/ */
@ -236,7 +236,7 @@
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ /*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/
#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx)
/** /**
* @brief AF 0 selection * @brief AF 0 selection
*/ */
@ -348,7 +348,7 @@
* @brief AF 15 selection * @brief AF 15 selection
*/ */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/** /**
@ -410,7 +410,8 @@
* @{ * @{
*/ */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOC))? 2U :\
@ -421,9 +422,9 @@
((__GPIOx__) == (GPIOH))? 7U :\ ((__GPIOx__) == (GPIOH))? 7U :\
((__GPIOx__) == (GPIOI))? 8U :\ ((__GPIOx__) == (GPIOI))? 8U :\
((__GPIOx__) == (GPIOJ))? 9U : 10U) ((__GPIOx__) == (GPIOJ))? 9U : 10U)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOC))? 2U :\
@ -432,7 +433,7 @@
((__GPIOx__) == (GPIOF))? 5U :\ ((__GPIOx__) == (GPIOF))? 5U :\
((__GPIOx__) == (GPIOG))? 6U :\ ((__GPIOx__) == (GPIOG))? 6U :\
((__GPIOx__) == (GPIOH))? 7U : 8U) ((__GPIOx__) == (GPIOH))? 7U : 8U)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
/** /**
* @} * @}
*/ */
@ -452,7 +453,7 @@
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
* @{ * @{
*/ */
#if defined(STM32F756xx) || defined(STM32F746xx) #if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
@ -611,7 +612,7 @@
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
((AF) == GPIO_AF10_OTG_FS)) ((AF) == GPIO_AF10_OTG_FS))
#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
@ -638,7 +639,7 @@
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
((AF) == GPIO_AF10_OTG_FS)) ((AF) == GPIO_AF10_OTG_FS))
#endif /* STM32F756xx || STM32F746xx */ #endif /* STM32F756xx || STM32F746xx || STM32F750xx */
/** /**
* @} * @}
*/ */

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h
View File

@ -41,7 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h" #include "stm32f7xx_hal_def.h"
@ -433,7 +433,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/** /**
* @} * @}
*/ */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}
*/ */

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h
View File

@ -41,7 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h" #include "stm32f7xx_hal_def.h"
@ -183,7 +183,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
/** /**
* @} * @}
*/ */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}
*/ */

27
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h
View File

@ -48,8 +48,7 @@
* @{ * @{
*/ */
/** @defgroup HCD HCD /** @addtogroup HCD
* @brief HCD HAL module driver
* @{ * @{
*/ */
@ -63,11 +62,11 @@
*/ */
typedef enum typedef enum
{ {
HAL_HCD_STATE_RESET = 0x00U, HAL_HCD_STATE_RESET = 0x00,
HAL_HCD_STATE_READY = 0x01U, HAL_HCD_STATE_READY = 0x01,
HAL_HCD_STATE_ERROR = 0x02U, HAL_HCD_STATE_ERROR = 0x02,
HAL_HCD_STATE_BUSY = 0x03U, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04U HAL_HCD_STATE_TIMEOUT = 0x04
} HCD_StateTypeDef; } HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
@ -86,7 +85,7 @@ typedef struct
{ {
HCD_TypeDef *Instance; /*!< Register base address */ HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO HCD_StateTypeDef State; /*!< HCD communication state */
void *pData; /*!< Pointer Stack Handler */ void *pData; /*!< Pointer Stack Handler */
@ -132,8 +131,8 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations * @brief macros to handle interrupts and specific clock configurations
* @{ * @{
*/ */
#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
@ -233,14 +232,6 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/** @defgroup HCD_Private_Macros HCD Private Macros /** @defgroup HCD_Private_Macros HCD Private Macros
* @{ * @{
*/ */
/** @defgroup HCD_Instance_definition HCD Instance definition
* @{
*/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
((INSTANCE) == USB_OTG_HS))
/**
* @}
*/
/** /**
* @} * @}

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h
View File

@ -41,7 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h" #include "stm32f7xx_hal_def.h"
@ -646,7 +646,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/** /**
* @} * @}
*/ */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}
*/ */

132
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h
View File

@ -62,25 +62,29 @@
*/ */
typedef enum typedef enum
{ {
HAL_PCD_STATE_RESET = 0x00U, HAL_PCD_STATE_RESET = 0x00,
HAL_PCD_STATE_READY = 0x01U, HAL_PCD_STATE_READY = 0x01,
HAL_PCD_STATE_ERROR = 0x02U, HAL_PCD_STATE_ERROR = 0x02,
HAL_PCD_STATE_BUSY = 0x03U, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04U HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef; } PCD_StateTypeDef;
/* Device LPM suspend state */ /* Device LPM suspend state */
typedef enum typedef enum
{ {
LPM_L0 = 0x00U, /* on */ LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01U, /* LPM L1 sleep */ LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02U, /* suspend */ LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03U, /* off */ LPM_L3 = 0x03, /* off */
}PCD_LPM_StateTypeDef; }PCD_LPM_StateTypeDef;
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
typedef USB_OTG_EPTypeDef PCD_EPTypeDef; typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
#endif /* USB_OTG_FS || USB_OTG_HS */
/** /**
* @brief PCD Handle Structure definition * @brief PCD Handle Structure definition
@ -89,6 +93,7 @@ typedef struct
{ {
PCD_TypeDef *Instance; /*!< Register base address */ PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */ PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
@ -96,10 +101,8 @@ typedef struct
uint32_t Setup[12]; /*!< Setup packet buffer */ uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL; uint32_t BESL;
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
This parameter can be set to ENABLE or DISABLE */
uint32_t battery_charging_active; /*!< Enable or disable Battery charging. uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
This parameter can be set to ENABLE or DISABLE */ This parameter can be set to ENABLE or DISABLE */
void *pData; /*!< Pointer to upper stack Handler */ void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef; } PCD_HandleTypeDef;
@ -108,7 +111,7 @@ typedef struct
* @} * @}
*/ */
/* Include PCD HAL Extension module */ /* Include PCD HAL Extended module */
#include "stm32f7xx_hal_pcd_ex.h" #include "stm32f7xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
@ -119,8 +122,10 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed /** @defgroup PCD_Speed PCD Speed
* @{ * @{
*/ */
#if defined (USB_OTG_HS)
#define PCD_SPEED_HIGH 0U #define PCD_SPEED_HIGH 0U
#define PCD_SPEED_HIGH_IN_FULL 1U #define PCD_SPEED_HIGH_IN_FULL 1U
#endif
#define PCD_SPEED_FULL 2U #define PCD_SPEED_FULL 2U
/** /**
* @} * @}
@ -145,7 +150,6 @@ typedef struct
#ifndef USBD_FS_TRDT_VALUE #ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U #define USBD_FS_TRDT_VALUE 5U
#endif /* USBD_HS_TRDT_VALUE */ #endif /* USBD_HS_TRDT_VALUE */
/** /**
* @} * @}
*/ */
@ -159,12 +163,13 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations * @brief macros to handle interrupts and specific clock configurations
* @{ * @{
*/ */
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
@ -172,60 +177,31 @@ typedef struct
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ do { \
}while(0)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
}while(0)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ } while(0U)
}while(0)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ do { \
}while(0)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
}while(0)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ } while(0U)
}while(0) #endif /* USB_OTG_FS || USB_OTG_HS */
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/** /**
* @} * @}
*/ */
@ -297,6 +273,43 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
* @{ * @{
*/ */
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCD_Private_Constants PCD Private Constants
* @{
*/
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#ifndef LL_EXTI_LINE_18
#define LL_EXTI_LINE_18 0x00040000U
#endif
#ifndef LL_EXTI_LINE_20
#define LL_EXTI_LINE_20 0x00100000U
#endif
#define USB_OTG_FS_WAKEUP_EXTI_LINE LL_EXTI_LINE_18 /*!< External interrupt line 17 Connected to the USB EXTI Line */
#define USB_OTG_HS_WAKEUP_EXTI_LINE LL_EXTI_LINE_20 /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#endif /* USB_OTG_FS || USB_OTG_HS */
/** /**
* @} * @}
*/ */
@ -309,14 +322,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/** @defgroup PCD_Private_Macros PCD Private Macros /** @defgroup PCD_Private_Macros PCD Private Macros
* @{ * @{
*/ */
/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
((INSTANCE) == USB_OTG_HS))
/**
* @}
*/
/** /**
* @} * @}
@ -334,7 +339,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} }
#endif #endif
#endif /* __STM32F7xx_HAL_PCD_H */ #endif /* __STM32F7xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h
View File

@ -2,7 +2,7 @@
****************************************************************************** ******************************************************************************
* @file stm32f7xx_hal_pcd_ex.h * @file stm32f7xx_hal_pcd_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of PCD HAL module. * @brief Header file of PCD HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
@ -54,8 +54,8 @@
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
typedef enum typedef enum
{ {
PCD_LPM_L0_ACTIVE = 0x00U, /* on */ PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef; }PCD_LPM_MsgTypeDef;
typedef enum typedef enum
@ -78,13 +78,14 @@ typedef enum
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{ * @{
*/ */
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* USB_OTG_FS || USB_OTG_HS */
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);

332
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h
View File

@ -104,11 +104,11 @@ typedef struct
This parameter will be used only when PLLI2S is selected as Clock Source SAI */ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
}RCC_PLLI2SInitTypeDef; }RCC_PLLI2SInitTypeDef;
/** /**
@ -125,11 +125,11 @@ typedef struct
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
@ -225,10 +225,10 @@ typedef struct
This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
@ -251,9 +251,9 @@ typedef struct
* @{ * @{
*/ */
#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
@ -277,9 +277,9 @@ typedef struct
#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
@ -290,7 +290,7 @@ typedef struct
*/ */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
* @{ * @{
*/ */
@ -301,7 +301,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
* @{ * @{
@ -335,7 +335,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
* @{ * @{
*/ */
@ -540,7 +539,7 @@ typedef struct
*/ */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
* @{ * @{
*/ */
@ -549,7 +548,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
@ -716,7 +715,8 @@ typedef struct
} while(0) } while(0)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
@ -740,7 +740,7 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
@ -757,14 +757,16 @@ typedef struct
#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
/** /**
* @brief Enable ETHERNET clock. * @brief Enable ETHERNET clock.
*/ */
@ -817,7 +819,7 @@ typedef struct
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
__HAL_RCC_ETHMAC_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
} while(0) } while(0)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Enable or disable the AHB2 peripheral clock. /** @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access) * @note After reset, the peripheral clock (used for registers read/write access)
@ -825,7 +827,8 @@ typedef struct
* using it. * using it.
*/ */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
@ -834,7 +837,7 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ #define __HAL_RCC_JPEG_CLK_ENABLE() do { \
@ -867,7 +870,7 @@ typedef struct
#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
@ -886,9 +889,9 @@ typedef struct
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
#endif /* STM32F756x || STM32F777xx || STM32F779xx */ #endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F732xx) || defined (STM32F733xx) #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_AES_CLK_ENABLE() do { \ #define __HAL_RCC_AES_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
@ -898,7 +901,7 @@ typedef struct
} while(0) } while(0)
#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
#endif /* STM32F732xx || STM32F733xx */ #endif /* STM32F732xx || STM32F733xx || STM32F730xx */
/** @brief Enables or disables the AHB3 peripheral clock. /** @brief Enables or disables the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access) * @note After reset, the peripheral clock (used for registers read/write access)
@ -1011,7 +1014,7 @@ typedef struct
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_RTC_CLK_ENABLE() do { \ #define __HAL_RCC_RTC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
@ -1020,7 +1023,7 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
@ -1137,7 +1140,8 @@ typedef struct
} while(0) } while(0)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
@ -1169,7 +1173,7 @@ typedef struct
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
@ -1183,10 +1187,10 @@ typedef struct
#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
@ -1204,12 +1208,13 @@ typedef struct
#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */
/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access) * @note After reset, the peripheral clock (used for registers read/write access)
@ -1249,7 +1254,7 @@ typedef struct
} while(0) } while(0)
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
@ -1257,7 +1262,7 @@ typedef struct
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
@ -1363,7 +1368,7 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
@ -1371,7 +1376,7 @@ typedef struct
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_CLK_ENABLE() do { \ #define __HAL_RCC_DSI_CLK_ENABLE() do { \
@ -1400,7 +1405,7 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F723xx) || defined (STM32F733xx) #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
@ -1408,16 +1413,16 @@ typedef struct
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif /* STM32F723xx || STM32F733xx */ #endif /* STM32F723xx || STM32F733xx || STM32F730xx */
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
@ -1431,9 +1436,9 @@ typedef struct
#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
#endif /* STM32F769xx || STM32F779xx */ #endif /* STM32F769xx || STM32F779xx */
@ -1441,15 +1446,14 @@ typedef struct
#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F723xx) || defined (STM32F733xx) #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN))
#endif /* STM32F723xx || STM32F733xx */ #endif /* STM32F723xx || STM32F733xx || STM32F730xx */
/** /**
* @} * @}
*/ */
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the AHB/APB peripheral clock. * @brief Get the enable or disable status of the AHB/APB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access) * @note After reset, the peripheral clock (used for registers read/write access)
@ -1478,11 +1482,12 @@ typedef struct
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
@ -1499,14 +1504,16 @@ typedef struct
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
/** /**
* @brief Enable ETHERNET clock. * @brief Enable ETHERNET clock.
*/ */
@ -1528,7 +1535,7 @@ typedef struct
#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
__HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Get the enable or disable status of the AHB2 peripheral clock. /** @brief Get the enable or disable status of the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access) * @note After reset, the peripheral clock (used for registers read/write access)
@ -1541,23 +1548,24 @@ typedef struct
#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F732xx) || defined (STM32F733xx) #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
#endif /* STM32F732xx || STM32F733xx */ #endif /* STM32F732xx || STM32F733xx || STM32F730xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
@ -1634,7 +1642,8 @@ typedef struct
#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
@ -1644,15 +1653,15 @@ typedef struct
#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
/** @brief Get the enable or disable status of the APB2 peripheral clock. /** @brief Get the enable or disable status of the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access) * @note After reset, the peripheral clock (used for registers read/write access)
@ -1676,23 +1685,23 @@ typedef struct
#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
#endif /* STM32F769xx || STM32F779xx */ #endif /* STM32F769xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F723xx) || defined (STM32F733xx) #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET)
#endif /* STM32F723xx || STM32F733xx */ #endif /* STM32F723xx || STM32F733xx || STM32F730xx */
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
@ -1711,23 +1720,23 @@ typedef struct
#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
#endif /* STM32F769xx || STM32F779xx */ #endif /* STM32F769xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F723xx) || defined (STM32F733xx) #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET)
#endif /* STM32F723xx || STM32F733xx */ #endif /* STM32F723xx || STM32F733xx || STM32F730xx */
/** /**
* @} * @}
@ -1765,7 +1774,8 @@ typedef struct
#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
@ -1775,7 +1785,7 @@ typedef struct
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Force or release AHB2 peripheral reset. /** @brief Force or release AHB2 peripheral reset.
*/ */
@ -1792,23 +1802,24 @@ typedef struct
#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F732xx) || defined (STM32F733xx) #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
#endif /* STM32F732xx || STM32F733xx */ #endif /* STM32F732xx || STM32F733xx || STM32F730xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Force or release AHB3 peripheral reset /** @brief Force or release AHB3 peripheral reset
*/ */
@ -1877,7 +1888,8 @@ typedef struct
#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
@ -1887,7 +1899,7 @@ typedef struct
#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Force or release APB2 peripheral reset. /** @brief Force or release APB2 peripheral reset.
*/ */
@ -1906,12 +1918,12 @@ typedef struct
#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F723xx) || defined (STM32F733xx) #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST))
#endif /* STM32F723xx || STM32F733xx */ #endif /* STM32F723xx || STM32F733xx || STM32F730xx */
#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
@ -1928,12 +1940,12 @@ typedef struct
#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F723xx) || defined (STM32F733xx) #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST))
#endif /* STM32F723xx || STM32F733xx */ #endif /* STM32F723xx || STM32F733xx || STM32F730xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
@ -1941,10 +1953,10 @@ typedef struct
#endif /* STM32F769xx || STM32F779xx */ #endif /* STM32F769xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
@ -2006,7 +2018,8 @@ typedef struct
#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
@ -2022,7 +2035,7 @@ typedef struct
#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce * @note Peripheral clock gating in SLEEP mode can be used to further reduce
@ -2031,10 +2044,11 @@ typedef struct
* @note By default, all peripheral clocks are enabled during SLEEP mode. * @note By default, all peripheral clocks are enabled during SLEEP mode.
*/ */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
@ -2047,18 +2061,18 @@ typedef struct
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F732xx) || defined (STM32F733xx) #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
#endif /* STM32F732xx || STM32F733xx */ #endif /* STM32F732xx || STM32F733xx || STM32F730xx */
/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce * @note Peripheral clock gating in SLEEP mode can be used to further reduce
@ -2134,14 +2148,15 @@ typedef struct
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
@ -2151,7 +2166,7 @@ typedef struct
#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce * @note Peripheral clock gating in SLEEP mode can be used to further reduce
@ -2175,9 +2190,9 @@ typedef struct
#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
@ -2195,9 +2210,9 @@ typedef struct
#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx)
#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
@ -2209,16 +2224,17 @@ typedef struct
#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}
*/ */
@ -2277,7 +2293,8 @@ typedef struct
#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
@ -2293,7 +2310,7 @@ typedef struct
#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce * @note Peripheral clock gating in SLEEP mode can be used to further reduce
@ -2302,10 +2319,11 @@ typedef struct
* @note By default, all peripheral clocks are enabled during SLEEP mode. * @note By default, all peripheral clocks are enabled during SLEEP mode.
*/ */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
@ -2318,18 +2336,18 @@ typedef struct
#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined(STM32F732xx) || defined (STM32F733xx) #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET)
#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET)
#endif /* STM32F732xx || STM32F733xx */ #endif /* STM32F732xx || STM32F733xx || STM32F730xx */
/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce * @note Peripheral clock gating in SLEEP mode can be used to further reduce
@ -2361,10 +2379,10 @@ typedef struct
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
@ -2394,10 +2412,10 @@ typedef struct
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx) defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
@ -2416,7 +2434,8 @@ typedef struct
#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
@ -2426,7 +2445,7 @@ typedef struct
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce * @note Peripheral clock gating in SLEEP mode can be used to further reduce
@ -2450,16 +2469,16 @@ typedef struct
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
#endif /* STM32F769xx || STM32F779xx */ #endif /* STM32F769xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
@ -2481,26 +2500,27 @@ typedef struct
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F769xx) || defined (STM32F779xx) #if defined (STM32F769xx) || defined (STM32F779xx)
#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
#endif /* STM32F769xx || STM32F779xx */ #endif /* STM32F769xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}
*/ */
@ -2600,7 +2620,7 @@ typedef struct
#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
/** @brief Macro to configure the PLLSAI clock multiplication and division factors. /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
* @note This function must be used only when the PLLSAI is disabled. * @note This function must be used only when the PLLSAI is disabled.
* @note PLLSAI clock source is common with the main PLL (configured in * @note PLLSAI clock source is common with the main PLL (configured in
@ -2682,7 +2702,7 @@ typedef struct
((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
* @note This function must be called before enabling the PLLI2S. * @note This function must be called before enabling the PLLI2S.
@ -2701,7 +2721,8 @@ typedef struct
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
defined (STM32F750xx)
/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
* @note This function must be called before enabling the PLLSAI. * @note This function must be called before enabling the PLLSAI.
* @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
@ -2710,7 +2731,7 @@ typedef struct
*/ */
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** @brief Macro to configure SAI1 clock source selection. /** @brief Macro to configure SAI1 clock source selection.
* @note This function must be called before enabling PLLSAI, PLLI2S and * @note This function must be called before enabling PLLSAI, PLLI2S and
@ -2744,7 +2765,6 @@ typedef struct
*/ */
#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
/** @brief Macro to configure SAI2 clock source selection. /** @brief Macro to configure SAI2 clock source selection.
* @note This function must be called before enabling PLLSAI, PLLI2S and * @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock. * the SAI clock.
@ -3125,7 +3145,7 @@ typedef struct
#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
* @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@ -3141,7 +3161,7 @@ typedef struct
* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
*/ */
#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @brief Macro to configure the DFSDM1 clock /** @brief Macro to configure the DFSDM1 clock
@ -3218,7 +3238,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
* @{ * @{
*/ */
#if defined(STM32F756xx) || defined(STM32F746xx) #if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) \ #define IS_RCC_PERIPHCLOCK(SELECTION) \
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
@ -3322,7 +3342,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) \ #define IS_RCC_PERIPHCLOCK(SELECTION) \
((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
@ -3344,15 +3364,15 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#endif /* STM32F746xx || STM32F756xx */ #endif /* STM32F746xx || STM32F756xx || STM32F750xx */
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
((VALUE) == RCC_PLLI2SP_DIV4) ||\ ((VALUE) == RCC_PLLI2SP_DIV4) ||\
((VALUE) == RCC_PLLI2SP_DIV6) ||\ ((VALUE) == RCC_PLLI2SP_DIV6) ||\
((VALUE) == RCC_PLLI2SP_DIV8)) ((VALUE) == RCC_PLLI2SP_DIV8))
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
@ -3456,14 +3476,14 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
((VALUE) == RCC_TIMPRES_ACTIVATED)) ((VALUE) == RCC_TIMPRES_ACTIVATED))
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\
defined (STM32F746xx) || defined (STM32F756xx) defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx)
#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
@ -3486,10 +3506,10 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\

102
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h
View File

@ -2,7 +2,7 @@
****************************************************************************** ******************************************************************************
* @file stm32f7xx_ll_usb.h * @file stm32f7xx_ll_usb.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of USB Core HAL module. * @brief Header file of USB Low Layer HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
@ -44,11 +44,11 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h" #include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL /** @addtogroup STM32F7xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup USB_Core /** @addtogroup USB_LL
* @{ * @{
*/ */
@ -59,30 +59,29 @@
*/ */
typedef enum typedef enum
{ {
USB_OTG_DEVICE_MODE = 0U, USB_DEVICE_MODE = 0,
USB_OTG_HOST_MODE = 1U, USB_HOST_MODE = 1,
USB_OTG_DRD_MODE = 2U USB_DRD_MODE = 2
}USB_OTG_ModeTypeDef; }USB_OTG_ModeTypeDef;
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** /**
* @brief URB States definition * @brief URB States definition
*/ */
typedef enum { typedef enum {
URB_IDLE = 0U, URB_IDLE = 0,
URB_DONE, URB_DONE,
URB_NOTREADY, URB_NOTREADY,
URB_NYET, URB_NYET,
URB_ERROR, URB_ERROR,
URB_STALL URB_STALL
}USB_OTG_URBStateTypeDef; }USB_OTG_URBStateTypeDef;
/** /**
* @brief Host channel States definition * @brief Host channel States definition
*/ */
typedef enum { typedef enum {
HC_IDLE = 0U, HC_IDLE = 0,
HC_XFRC, HC_XFRC,
HC_HALTED, HC_HALTED,
HC_NAK, HC_NAK,
@ -91,11 +90,10 @@ typedef enum {
HC_XACTERR, HC_XACTERR,
HC_BBLERR, HC_BBLERR,
HC_DATATGLERR HC_DATATGLERR
}USB_OTG_HCStateTypeDef; }USB_OTG_HCStateTypeDef;
/** /**
* @brief PCD Initialization Structure definition * @brief USB OTG Initialization Structure definition
*/ */
typedef struct typedef struct
{ {
@ -110,7 +108,7 @@ typedef struct
uint32_t speed; /*!< USB Core speed. uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed_ */ This parameter can be any value of @ref USB_Core_Speed_ */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
This parameter can be any value of @ref USB_EP0_MPS_ */ This parameter can be any value of @ref USB_EP0_MPS_ */
@ -131,7 +129,6 @@ typedef struct
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
}USB_OTG_CfgTypeDef; }USB_OTG_CfgTypeDef;
typedef struct typedef struct
@ -167,7 +164,6 @@ typedef struct
uint32_t xfer_len; /*!< Current transfer length */ uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
}USB_OTG_EPTypeDef; }USB_OTG_EPTypeDef;
typedef struct typedef struct
@ -221,8 +217,9 @@ typedef struct
USB_OTG_HCStateTypeDef state; /*!< Host Channel state. USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
}USB_OTG_HCTypeDef; }USB_OTG_HCTypeDef;
#endif /* defined USB_OTG_FS || USB_OTG_HS */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
@ -230,6 +227,7 @@ typedef struct
* @{ * @{
*/ */
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @defgroup USB_Core_Mode_ USB Core Mode /** @defgroup USB_Core_Mode_ USB Core Mode
* @{ * @{
*/ */
@ -240,7 +238,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_Core_Speed_ USB Core Speed /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{ * @{
*/ */
#define USB_OTG_SPEED_HIGH 0U #define USB_OTG_SPEED_HIGH 0U
@ -251,7 +249,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_Core_PHY_ USB Core PHY /** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{ * @{
*/ */
#define USB_OTG_ULPI_PHY 1U #define USB_OTG_ULPI_PHY 1U
@ -261,12 +259,11 @@ typedef struct
#if !defined (USB_HS_PHYC_TUNE_VALUE) #if !defined (USB_HS_PHYC_TUNE_VALUE)
#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ #define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
#endif /* USB_HS_PHYC_TUNE_VALUE */ #endif /* USB_HS_PHYC_TUNE_VALUE */
/** /**
* @} * @}
*/ */
/** @defgroup USB_Core_MPS_ USB Core MPS /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{ * @{
*/ */
#define USB_OTG_HS_MAX_PACKET_SIZE 512U #define USB_OTG_HS_MAX_PACKET_SIZE 512U
@ -276,18 +273,18 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
* @{ * @{
*/ */
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) #define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/** /**
* @} * @}
*/ */
/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval /** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{ * @{
*/ */
#define DCFG_FRAME_INTERVAL_80 0U #define DCFG_FRAME_INTERVAL_80 0U
@ -298,7 +295,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_EP0_MPS_ USB EP0 MPS /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{ * @{
*/ */
#define DEP0CTL_MPS_64 0U #define DEP0CTL_MPS_64 0U
@ -309,7 +306,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_EP_Speed_ USB EP Speed /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{ * @{
*/ */
#define EP_SPEED_LOW 0U #define EP_SPEED_LOW 0U
@ -319,7 +316,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_EP_Type_ USB EP Type /** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{ * @{
*/ */
#define EP_TYPE_CTRL 0U #define EP_TYPE_CTRL 0U
@ -331,7 +328,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup USB_STS_Defines_ USB STS Defines /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{ * @{
*/ */
#define STS_GOUT_NAK 1U #define STS_GOUT_NAK 1U
@ -343,7 +340,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines /** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{ * @{
*/ */
#define HCFG_30_60_MHZ 0U #define HCFG_30_60_MHZ 0U
@ -353,7 +350,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{ * @{
*/ */
#define HPRT0_PRTSPD_HIGH_SPEED 0U #define HPRT0_PRTSPD_HIGH_SPEED 0U
@ -378,30 +375,43 @@ typedef struct
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U #define GRXSTS_PKTSTS_CH_HALTED 7U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) #define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) #define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) #define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
#endif /* USB_OTG_FS || USB_OTG_HS */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) #define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
#endif /* USB_OTG_FS || USB_OTG_HS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
@ -453,6 +463,16 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
#endif /* USB_OTG_FS || USB_OTG_HS */
/**
* @}
*/
/**
* @}
*/
/** /**
* @} * @}

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
View File

@ -66,11 +66,11 @@
* @{ * @{
*/ */
/** /**
* @brief STM32F7xx HAL Driver version number V1.2.5 * @brief STM32F7xx HAL Driver version number V1.2.6
*/ */
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c
View File

@ -100,7 +100,7 @@
* @{ * @{
*/ */
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/** @defgroup HASH HASH /** @defgroup HASH HASH
* @brief HASH HAL module driver. * @brief HASH HAL module driver.
@ -1867,7 +1867,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
/** /**
* @} * @}
*/ */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c
View File

@ -96,7 +96,7 @@
/** @addtogroup STM32F7xx_HAL_Driver /** @addtogroup STM32F7xx_HAL_Driver
* @{ * @{
*/ */
#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) #if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined (STM32F750xx)
/** @defgroup HASHEx HASHEx /** @defgroup HASHEx HASHEx
* @brief HASH Extension HAL module driver. * @brief HASH Extension HAL module driver.
@ -1625,7 +1625,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/** /**
* @} * @}
*/ */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}

608
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c
View File

@ -87,7 +87,7 @@
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/** @defgroup HCD_Private_Functions HCD Private Functions /** @defgroup HCD_Private_Functions HCD Private Functions
* @{ * @{
*/ */
@ -133,22 +133,28 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
hhcd->State = HAL_HCD_STATE_BUSY; if(hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhcd->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd); HAL_HCD_MspInit(hhcd);
}
hhcd->State = HAL_HCD_STATE_BUSY;
/* Disable the Interrupts */ /* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd); __HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */ /* Init the Core (common init.) */
USB_CoreInit(hhcd->Instance, hhcd->Init); (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
/* Force Host Mode*/ /* Force Host Mode*/
USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE); (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
/* Init Host */ /* Init Host */
USB_HostInit(hhcd->Instance, hhcd->Init); (void)USB_HostInit(hhcd->Instance, hhcd->Init);
hhcd->State= HAL_HCD_STATE_READY; hhcd->State= HAL_HCD_STATE_READY;
@ -187,16 +193,25 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ep_type, uint8_t ep_type,
uint16_t mps) uint16_t mps)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status;
__HAL_LOCK(hhcd); __HAL_LOCK(hhcd);
hhcd->hc[ch_num].do_ping = 0; hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].dev_addr = dev_address; hhcd->hc[ch_num].dev_addr = dev_address;
hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type; hhcd->hc[ch_num].ep_type = ep_type;
hhcd->hc[ch_num].ep_num = epnum & 0x7F; hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
if ((epnum & 0x80U) == 0x80U)
{
hhcd->hc[ch_num].ep_is_in = 1U;
}
else
{
hhcd->hc[ch_num].ep_is_in = 0U;
}
hhcd->hc[ch_num].speed = speed; hhcd->hc[ch_num].speed = speed;
status = USB_HC_Init(hhcd->Instance, status = USB_HC_Init(hhcd->Instance,
@ -223,7 +238,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(hhcd); __HAL_LOCK(hhcd);
USB_HC_Halt(hhcd->Instance, ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_UNLOCK(hhcd); __HAL_UNLOCK(hhcd);
return status; return status;
@ -264,7 +279,7 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_MspInit could be implemented in the user file the HAL_HCD_MspInit could be implemented in the user file
*/ */
} }
@ -279,7 +294,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_MspDeInit could be implemented in the user file the HAL_HCD_MspDeInit could be implemented in the user file
*/ */
} }
@ -335,10 +350,12 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint16_t length, uint16_t length,
uint8_t do_ping) uint8_t do_ping)
{ {
UNUSED(do_ping);
hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type; hhcd->hc[ch_num].ep_type = ep_type;
if(token == 0) if(token == 0U)
{ {
hhcd->hc[ch_num].data_pid = HC_PID_SETUP; hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
} }
@ -351,15 +368,15 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
switch(ep_type) switch(ep_type)
{ {
case EP_TYPE_CTRL: case EP_TYPE_CTRL:
if((token == 1) && (direction == 0)) /*send data */ if((token == 1U) && (direction == 0U)) /*send data */
{ {
if ( length == 0 ) if (length == 0U)
{ /* For Status OUT stage, Length==0, Status Out PID = 1 */ { /* For Status OUT stage, Length==0, Status Out PID = 1 */
hhcd->hc[ch_num].toggle_out = 1; hhcd->hc[ch_num].toggle_out = 1U;
} }
/* Set the Data Toggle bit as per the Flag */ /* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0) if (hhcd->hc[ch_num].toggle_out == 0U)
{ /* Put the PID 0 */ { /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0; hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
} }
@ -371,10 +388,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
break; break;
case EP_TYPE_BULK: case EP_TYPE_BULK:
if(direction == 0) if(direction == 0U)
{ {
/* Set the Data Toggle bit as per the Flag */ /* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0) if ( hhcd->hc[ch_num].toggle_out == 0U)
{ /* Put the PID 0 */ { /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0; hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
} }
@ -385,7 +402,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
} }
else else
{ {
if( hhcd->hc[ch_num].toggle_in == 0) if( hhcd->hc[ch_num].toggle_in == 0U)
{ {
hhcd->hc[ch_num].data_pid = HC_PID_DATA0; hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
} }
@ -397,10 +414,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
break; break;
case EP_TYPE_INTR: case EP_TYPE_INTR:
if(direction == 0) if(direction == 0U)
{ {
/* Set the Data Toggle bit as per the Flag */ /* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0) if ( hhcd->hc[ch_num].toggle_out == 0U)
{ /* Put the PID 0 */ { /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0; hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
} }
@ -411,7 +428,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
} }
else else
{ {
if( hhcd->hc[ch_num].toggle_in == 0) if( hhcd->hc[ch_num].toggle_in == 0U)
{ {
hhcd->hc[ch_num].data_pid = HC_PID_DATA0; hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
} }
@ -425,16 +442,19 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
case EP_TYPE_ISOC: case EP_TYPE_ISOC:
hhcd->hc[ch_num].data_pid = HC_PID_DATA0; hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
break; break;
default:
break;
} }
hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length; hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE; hhcd->hc[ch_num].urb_state = URB_IDLE;
hhcd->hc[ch_num].xfer_count = 0 ; hhcd->hc[ch_num].xfer_count = 0U;
hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE; hhcd->hc[ch_num].state = HC_IDLE;
return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
} }
/** /**
@ -445,12 +465,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{ {
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t i = 0 , interrupt = 0; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i, interrupt;
/* ensure that we are in device mode */ /* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{ {
/* avoid spurious interrupt */ /* Avoid spurious interrupt */
if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{ {
return; return;
@ -458,25 +479,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{ {
/* incorrect mode, acknowledge the interrupt */ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
} }
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{ {
/* incorrect mode, acknowledge the interrupt */ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
} }
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{ {
/* incorrect mode, acknowledge the interrupt */ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
} }
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{ {
/* incorrect mode, acknowledge the interrupt */ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
} }
@ -490,7 +511,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
/* Handle Host Port Interrupts */ /* Handle Host Port Interrupts */
HAL_HCD_Disconnect_Callback(hhcd); HAL_HCD_Disconnect_Callback(hhcd);
USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
} }
@ -511,17 +532,17 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{ {
interrupt = USB_HC_ReadInterrupt(hhcd->Instance); interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
for (i = 0; i < hhcd->Init.Host_channels ; i++) for (i = 0U; i < hhcd->Init.Host_channels; i++)
{ {
if (interrupt & (1 << i)) if ((interrupt & (1UL << (i & 0xFU))) != 0U)
{ {
if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR) if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
{ {
HCD_HC_IN_IRQHandler (hhcd, i); HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
} }
else else
{ {
HCD_HC_OUT_IRQHandler (hhcd, i); HCD_HC_OUT_IRQHandler (hhcd, (uint8_t)i);
} }
} }
} }
@ -529,7 +550,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
} }
/* Handle Rx Queue Level Interrupts */ /* Handle Rx Queue Level Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) if((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{ {
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
@ -550,7 +571,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_SOF_Callback could be implemented in the user file the HAL_HCD_SOF_Callback could be implemented in the user file
*/ */
} }
@ -565,7 +586,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Connect_Callback could be implemented in the user file the HAL_HCD_Connect_Callback could be implemented in the user file
*/ */
} }
@ -580,35 +601,37 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/ */
} }
/** /**
* @brief Port Enabled Event callback. * @brief Port Enabled Event callback.
* @param hhcd: HCD handle * @param hhcd HCD handle
* @retval None * @retval None
*/ */
__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) __weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/ */
} }
/** /**
* @brief Port Disabled Event callback. * @brief Port Disabled Event callback.
* @param hhcd: HCD handle * @param hhcd HCD handle
* @retval None * @retval None
*/ */
__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) __weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/ */
} }
@ -632,8 +655,10 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hhcd); UNUSED(hhcd);
UNUSED(chnum);
UNUSED(urb_state);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/ */
} }
@ -666,7 +691,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{ {
__HAL_LOCK(hhcd); __HAL_LOCK(hhcd);
__HAL_HCD_ENABLE(hhcd); __HAL_HCD_ENABLE(hhcd);
USB_DriveVbus(hhcd->Instance, 1); (void)USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd); __HAL_UNLOCK(hhcd);
return HAL_OK; return HAL_OK;
} }
@ -680,7 +705,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
{ {
__HAL_LOCK(hhcd); __HAL_LOCK(hhcd);
USB_StopHost(hhcd->Instance); (void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd); __HAL_UNLOCK(hhcd);
return HAL_OK; return HAL_OK;
} }
@ -819,147 +844,163 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{ {
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t tmpreg = 0; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) uint32_t tmpreg;
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{ {
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
} }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{ {
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
} }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
{ {
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
hhcd->hc[chnum].state = HC_STALL; hhcd->hc[ch_num].state = HC_STALL;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
USB_HC_Halt(hhcd->Instance, chnum); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
} }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{ {
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
USB_HC_Halt(hhcd->Instance, chnum); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
hhcd->hc[chnum].state = HC_DATATGLERR; hhcd->hc[ch_num].state = HC_DATATGLERR;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
}
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
{
if (hhcd->Init.dma_enable)
{
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
(USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[chnum].state = HC_XFRC;
hhcd->hc[chnum].ErrCnt = 0;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[chnum].urb_state = URB_DONE;
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
}
hhcd->hc[chnum].toggle_in ^= 1;
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
{
__HAL_HCD_MASK_HALT_HC_INT(chnum);
if(hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[chnum].urb_state = URB_DONE;
}
else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].urb_state = URB_STALL;
}
else if((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
if(hhcd->hc[chnum].ErrCnt++ > 3)
{
hhcd->hc[chnum].ErrCnt = 0;
hhcd->hc[chnum].urb_state = URB_ERROR;
} }
else else
{ {
hhcd->hc[chnum].urb_state = URB_NOTREADY; /* ... */
}
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
if (hhcd->Init.dma_enable != 0U)
{
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
(USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[ch_num].state = HC_XFRC;
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
else if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
}
else
{
/* ... */
}
hhcd->hc[ch_num].toggle_in ^= 1U;
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
__HAL_HCD_MASK_HALT_HC_INT(ch_num);
if(hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
}
else if (hhcd->hc[ch_num].state == HC_STALL)
{
hhcd->hc[ch_num].urb_state = URB_STALL;
}
else if((hhcd->hc[ch_num].state == HC_XACTERR) ||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
if(hhcd->hc[ch_num].ErrCnt > 3U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
} }
/* re-activate the channel */ /* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA; tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg; USBx_HC(ch_num)->HCCHAR = tmpreg;
} }
else if (hhcd->hc[chnum].state == HC_NAK) else if (hhcd->hc[ch_num].state == HC_NAK)
{ {
hhcd->hc[chnum].urb_state = URB_NOTREADY; hhcd->hc[ch_num].urb_state = URB_NOTREADY;
/* re-activate the channel */ /* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA; tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg; USBx_HC(ch_num)->HCCHAR = tmpreg;
} }
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
{ {
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); /* ... */
hhcd->hc[chnum].ErrCnt++;
hhcd->hc[chnum].state = HC_XACTERR;
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
} }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
{ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
hhcd->hc[chnum].ErrCnt = 0;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
} }
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{ {
hhcd->hc[chnum].ErrCnt = 0; __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
if (!hhcd->Init.dma_enable) hhcd->hc[ch_num].ErrCnt++;
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{ {
hhcd->hc[chnum].state = HC_NAK; if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); {
USB_HC_Halt(hhcd->Instance, chnum); hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
hhcd->hc[ch_num].ErrCnt = 0U;
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_NAK;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
} }
} }
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); else
{
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
else
{
/* ... */
} }
} }
@ -973,144 +1014,144 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{ {
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t tmpreg = 0; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
uint32_t tmpreg;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{ {
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
} }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{ {
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
if( hhcd->hc[chnum].do_ping == 1)
if( hhcd->hc[ch_num].do_ping == 1U)
{ {
hhcd->hc[chnum].do_ping = 0; hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[chnum].urb_state = URB_NOTREADY; hhcd->hc[ch_num].urb_state = URB_NOTREADY;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
USB_HC_Halt(hhcd->Instance, chnum); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
hhcd->hc[ch_num].state = HC_NYET;
hhcd->hc[ch_num].do_ping = 1U;
hhcd->hc[ch_num].ErrCnt= 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[ch_num].state = HC_XFRC;
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[ch_num].state = HC_STALL;
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].state = HC_NAK;
if (hhcd->hc[ch_num].do_ping == 0U)
{
if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
{
hhcd->hc[ch_num].do_ping = 1U;
} }
} }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
{ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[chnum].state = HC_NYET; __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
hhcd->hc[chnum].do_ping = 1;
hhcd->hc[chnum].ErrCnt= 0;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
} }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
{ {
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
USB_HC_Halt(hhcd->Instance, chnum); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); hhcd->hc[ch_num].state = HC_XACTERR;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
} }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
{ {
hhcd->hc[chnum].ErrCnt = 0; __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
hhcd->hc[chnum].state = HC_XFRC; hhcd->hc[ch_num].state = HC_DATATGLERR;
} }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
__HAL_HCD_MASK_HALT_HC_INT(ch_num);
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) if (hhcd->hc[ch_num].state == HC_XFRC)
{ {
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); hhcd->hc[ch_num].urb_state = URB_DONE;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)
USB_HC_Halt(hhcd->Instance, chnum);
hhcd->hc[chnum].state = HC_STALL;
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
{ {
hhcd->hc[chnum].ErrCnt = 0; hhcd->hc[ch_num].toggle_out ^= 1U;
hhcd->hc[chnum].state = HC_NAK;
if ( hhcd->hc[chnum].do_ping == 0)
{
if (hhcd->hc[chnum].speed == HCD_SPEED_HIGH)
{
hhcd->hc[chnum].do_ping = 1;
} }
} }
else if (hhcd->hc[ch_num].state == HC_NAK)
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); {
USB_HC_Halt(hhcd->Instance, chnum); hhcd->hc[ch_num].urb_state = URB_NOTREADY;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
} }
else if (hhcd->hc[ch_num].state == HC_NYET)
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
{ {
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); hhcd->hc[ch_num].urb_state = URB_NOTREADY;
USB_HC_Halt(hhcd->Instance, chnum);
hhcd->hc[chnum].state = HC_XACTERR;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
} }
else if (hhcd->hc[ch_num].state == HC_STALL)
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
{ {
__HAL_HCD_UNMASK_HALT_HC_INT(chnum); hhcd->hc[ch_num].urb_state = URB_STALL;
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
hhcd->hc[chnum].state = HC_DATATGLERR;
} }
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) (hhcd->hc[ch_num].state == HC_DATATGLERR))
{ {
__HAL_HCD_MASK_HALT_HC_INT(chnum); hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 3U)
if(hhcd->hc[chnum].state == HC_XFRC)
{ {
hhcd->hc[chnum].urb_state = URB_DONE; hhcd->hc[ch_num].ErrCnt = 0U;
if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) hhcd->hc[ch_num].urb_state = URB_ERROR;
{
hhcd->hc[chnum].toggle_out ^= 1;
}
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].urb_state = URB_STALL;
}
else if((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
if(hhcd->hc[chnum].ErrCnt++ > 3)
{
hhcd->hc[chnum].ErrCnt = 0;
hhcd->hc[chnum].urb_state = URB_ERROR;
} }
else else
{ {
hhcd->hc[chnum].urb_state = URB_NOTREADY; hhcd->hc[ch_num].urb_state = URB_NOTREADY;
} }
/* re-activate the channel */ /* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA; tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg; USBx_HC(ch_num)->HCCHAR = tmpreg;
}
else
{
/* ... */
} }
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
}
else
{
/* ... */
} }
} }
@ -1122,14 +1163,15 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
{ {
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint8_t channelnum =0; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts; uint32_t pktsts;
uint32_t pktcnt; uint32_t pktcnt;
uint32_t temp = 0; uint32_t temp;
uint32_t tmpreg = 0; uint32_t tmpreg;
uint32_t ch_num;
temp = hhcd->Instance->GRXSTSP; temp = hhcd->Instance->GRXSTSP;
channelnum = temp & USB_OTG_GRXSTSP_EPNUM; ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
@ -1137,29 +1179,29 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
{ {
case GRXSTS_PKTSTS_IN: case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */ /* Read the data into the host buffer. */
if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
{ {
(void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
/*manage multiple Xfer */ /*manage multiple Xfer */
hhcd->hc[channelnum].xfer_buff += pktcnt; hhcd->hc[ch_num].xfer_buff += pktcnt;
hhcd->hc[channelnum].xfer_count += pktcnt; hhcd->hc[ch_num].xfer_count += pktcnt;
if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) if((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
{ {
/* re-activate the channel when more packets are expected */ /* re-activate the channel when more packets are expected */
tmpreg = USBx_HC(channelnum)->HCCHAR; tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA; tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(channelnum)->HCCHAR = tmpreg; USBx_HC(ch_num)->HCCHAR = tmpreg;
hhcd->hc[channelnum].toggle_in ^= 1; hhcd->hc[ch_num].toggle_in ^= 1U;
} }
} }
break; break;
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
break; break;
case GRXSTS_PKTSTS_IN_XFER_COMP: case GRXSTS_PKTSTS_IN_XFER_COMP:
case GRXSTS_PKTSTS_CH_HALTED: case GRXSTS_PKTSTS_CH_HALTED:
default: default:
@ -1175,6 +1217,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{ {
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0, hprt0_dup; __IO uint32_t hprt0, hprt0_dup;
/* Handle Host Port Interrupts */ /* Handle Host Port Interrupts */
@ -1193,7 +1236,6 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
HAL_HCD_Connect_Callback(hhcd); HAL_HCD_Connect_Callback(hhcd);
} }
hprt0_dup |= USB_OTG_HPRT_PCDET; hprt0_dup |= USB_OTG_HPRT_PCDET;
} }
/* Check whether Port Enable Changed */ /* Check whether Port Enable Changed */
@ -1207,28 +1249,28 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{ {
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
{ {
USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
} }
else else
{ {
USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
} }
} }
else else
{ {
if(hhcd->Init.speed == HCD_SPEED_FULL) if(hhcd->Init.speed == HCD_SPEED_FULL)
{ {
USBx_HOST->HFIR = (uint32_t)60000; USBx_HOST->HFIR = 60000U;
} }
} }
HAL_HCD_PortEnabled_Callback(hhcd); HAL_HCD_PortEnabled_Callback(hhcd);
HAL_HCD_Connect_Callback(hhcd); HAL_HCD_Connect_Callback(hhcd);
} }
else else
{ {
HAL_HCD_PortDisabled_Callback(hhcd); HAL_HCD_PortDisabled_Callback(hhcd);
/* Cleanup HPRT */ /* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
@ -1237,7 +1279,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
} }
} }
/* Check For an overcurrent */ /* Check for an overcurrent */
if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{ {
hprt0_dup |= USB_OTG_HPRT_POCCHNG; hprt0_dup |= USB_OTG_HPRT_POCCHNG;

4
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c
View File

@ -113,7 +113,7 @@
/** @addtogroup STM32F7xx_HAL_Driver /** @addtogroup STM32F7xx_HAL_Driver
* @{ * @{
*/ */
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/** @defgroup LTDC LTDC /** @defgroup LTDC LTDC
* @brief LTDC HAL module driver * @brief LTDC HAL module driver
@ -1904,7 +1904,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/** /**
* @} * @}
*/ */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/** /**
* @} * @}

490
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c
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File diff suppressed because it is too large Load Diff

144
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c
View File

@ -2,7 +2,7 @@
****************************************************************************** ******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c * @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team * @author MCD Application Team
* @brief PCD HAL module driver. * @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller: * functionalities of the USB Peripheral Controller:
* + Extended features functions * + Extended features functions
@ -48,6 +48,7 @@
* @brief PCD Extended HAL module driver * @brief PCD Extended HAL module driver
* @{ * @{
*/ */
#ifdef HAL_PCD_MODULE_ENABLED #ifdef HAL_PCD_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
@ -74,7 +75,7 @@
@endverbatim @endverbatim
* @{ * @{
*/ */
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** /**
* @brief Set Tx FIFO * @brief Set Tx FIFO
* @param hpcd PCD handle * @param hpcd PCD handle
@ -84,8 +85,8 @@
*/ */
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{ {
uint8_t i = 0; uint8_t i;
uint32_t Tx_Offset = 0; uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index) /* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows: When a TxFIFO is not used, the Configuration should be as follows:
@ -99,20 +100,20 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
Tx_Offset = hpcd->Instance->GRXFSIZ; Tx_Offset = hpcd->Instance->GRXFSIZ;
if(fifo == 0) if(fifo == 0U)
{ {
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
} }
else else
{ {
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0; i < (fifo - 1); i++) for (i = 0U; i < (fifo - 1U); i++)
{ {
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
} }
/* Multiply Tx_Size by 2 to get higher performance */ /* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
} }
return HAL_OK; return HAL_OK;
@ -132,7 +133,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
} }
/** /**
* @brief Activate LPM Feature * @brief Activate LPM feature.
* @param hpcd PCD handle * @param hpcd PCD handle
* @retval HAL status * @retval HAL status
*/ */
@ -140,7 +141,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{ {
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = ENABLE; hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0; hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
@ -149,7 +150,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
} }
/** /**
* @brief DeActivate LPM feature. * @brief Deactivate LPM feature.
* @param hpcd PCD handle * @param hpcd PCD handle
* @retval HAL status * @retval HAL status
*/ */
@ -157,114 +158,32 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{ {
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = DISABLE; hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK; return HAL_OK;
} }
#endif /* USB_OTG_FS || USB_OTG_HS */
#if defined (USB_OTG_GCCFG_BCDEN)
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Start BCD When device is connected */
if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
{
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > 1000)
{
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
return;
}
}
/* Right response got */
HAL_Delay(100);
/* Check Detect flag*/
if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
{
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
}
/*Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(100);
if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
{
/* Case of Standard Downstream Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(100);
if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
}
else
{
/* case Charging Downstream Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
}
}
/* Battery Charging capability discovery finished */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
}
}
/** /**
* @brief Activate BatteryCharging feature. * @brief Send LPM message to user layer callback.
* @param hpcd PCD handle * @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{ {
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; /* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
hpcd->battery_charging_active = ENABLE; /* NOTE : This function should not be modified, when the callback is needed,
USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); the HAL_PCDEx_LPM_Callback could be implemented in the user file
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/ */
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = DISABLE;
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
return HAL_OK;
} }
/** /**
* @brief Send BatteryCharging message to user layer callback. * @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle * @param hpcd PCD handle
@ -282,24 +201,6 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
*/ */
} }
#endif /* USB_OTG_GCCFG_BCDEN */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/** /**
* @} * @}
*/ */
@ -309,6 +210,7 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m
*/ */
#endif /* HAL_PCD_MODULE_ENABLED */ #endif /* HAL_PCD_MODULE_ENABLED */
/** /**
* @} * @}
*/ */

25
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
View File

@ -104,7 +104,8 @@
* @{ * @{
*/ */
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \
defined (STM32F750xx)
/** /**
* @brief Initializes the RCC extended peripherals clocks according to the specified * @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef. * parameters in the RCC_PeriphCLKInitTypeDef.
@ -408,12 +409,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
} }
/*-------------------------------------- LTDC Configuration -----------------------------------*/ /*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
{ {
pllsaiused = 1; pllsaiused = 1;
} }
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
@ -633,7 +634,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
} }
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/ /*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{ {
@ -652,7 +653,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
} }
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */ /* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE(); __HAL_RCC_PLLSAI_ENABLE();
@ -810,9 +811,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
} }
} }
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
/** /**
* @brief Initializes the RCC extended peripherals clocks according to the specified * @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef. * parameters in the RCC_PeriphCLKInitTypeDef.
@ -1386,7 +1387,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
} }
} }
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
/** /**
* @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
@ -1627,7 +1628,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
} }
/* Configure the PLLI2S division factors */ /* Configure the PLLI2S division factors */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
/* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
/* I2SRCLK = PLLI2S_VCO / PLLI2SR */ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
@ -1638,7 +1639,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
/* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
/* I2SRCLK = PLLI2S_VCO / PLLI2SR */ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
/* Enable the PLLI2S */ /* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE(); __HAL_RCC_PLLI2S_ENABLE();
@ -1715,7 +1716,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
} }
/* Configure the PLLSAI division factors */ /* Configure the PLLSAI division factors */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
/* SAIPCLK = PLLSAI_VCO / PLLSAIP */ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
/* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
@ -1727,7 +1728,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
/* SAIRCLK = PLLSAI_VCO / PLLSAIR */ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
/* Enable the PLLSAI */ /* Enable the PLLSAI */
__HAL_RCC_PLLSAI_ENABLE(); __HAL_RCC_PLLSAI_ENABLE();

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bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c
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