diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h index 569dbe3ce9..2275870a4b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h @@ -9,8 +9,8 @@ * - Configuration section that allows to select: * - The STM32F7xx device used in the target application * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * ****************************************************************************** @@ -74,7 +74,9 @@ */ #if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \ - !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) + !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \ + !defined (STM32F750xx) + /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG Devices */ /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, @@ -93,6 +95,8 @@ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */ + /* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */ + /* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -109,11 +113,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.2.2 + * @brief CMSIS Device version number V1.2.3 */ #define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ @@ -150,6 +154,10 @@ #include "stm32f777xx.h" #elif defined(STM32F779xx) #include "stm32f779xx.h" +#elif defined(STM32F730xx) + #include "stm32f730xx.h" +#elif defined(STM32F750xx) + #include "stm32f750xx.h" #else #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" #endif diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf index 58ee4473d2..eaaa38acce 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf index 991b88d912..85101464bf 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf index 58ee4473d2..eaaa38acce 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf index 991b88d912..85101464bf 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_sram.icf index 140eb6e4ad..4c4ae82501 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f723xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf index 58ee4473d2..eaaa38acce 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf index 991b88d912..85101464bf 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_sram.icf index 140eb6e4ad..4c4ae82501 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f732xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf index 58ee4473d2..eaaa38acce 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0027FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf index 991b88d912..85101464bf 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_sram.icf index 140eb6e4ad..4c4ae82501 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f733xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf index dd85d484b7..7dfaf768a2 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf index 663a68fd1b..a321e0e888 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_sram.icf index d55c0c25d4..3e3947d8b6 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f745xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf index dd85d484b7..7dfaf768a2 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf index 663a68fd1b..a321e0e888 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_sram.icf index d55c0c25d4..3e3947d8b6 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f746xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf index dd85d484b7..7dfaf768a2 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf index 663a68fd1b..a321e0e888 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_sram.icf index d55c0c25d4..3e3947d8b6 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f756xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20030000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf index f58304c60f..8d3b21a1c3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf index d519df8549..ceb5a7b0c5 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_sram.icf index f3db1bb369..ea05b7fae4 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f765xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf index f58304c60f..8d3b21a1c3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf index d519df8549..ceb5a7b0c5 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_sram.icf index f3db1bb369..ea05b7fae4 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f767xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf index f58304c60f..8d3b21a1c3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf index d519df8549..ceb5a7b0c5 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_sram.icf index f3db1bb369..ea05b7fae4 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f769xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf index f58304c60f..8d3b21a1c3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf index d519df8549..ceb5a7b0c5 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_sram.icf index f3db1bb369..ea05b7fae4 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f777xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf index f58304c60f..8d3b21a1c3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_ITCM_flash.icf @@ -1,35 +1,35 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00200000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; -define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00200000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; place in ITCMRAM_region { }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf index d519df8549..ceb5a7b0c5 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_flash.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_sram.icf b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_sram.icf index f3db1bb369..ea05b7fae4 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_sram.icf +++ b/bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f779xx_sram.icf @@ -1,34 +1,34 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20050000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index d42722a286..5aa10ce346 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -381,7 +381,7 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -431,12 +431,12 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -564,7 +564,7 @@ #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -2120,20 +2120,6 @@ #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2804,7 +2790,6 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -2932,10 +2917,8 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) -#else + #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h index f4ad27c69a..a3fab0158d 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h @@ -93,7 +93,7 @@ typedef enum #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ @@ -103,7 +103,7 @@ typedef enum #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ /** * @} @@ -143,7 +143,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ ((CHANNEL) == DMA_CHANNEL_1) || \ ((CHANNEL) == DMA_CHANNEL_2) || \ @@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre ((CHANNEL) == DMA_CHANNEL_6) || \ ((CHANNEL) == DMA_CHANNEL_7)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/ /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h index 4f4ea73207..0fba4c21ee 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_FLASH_H @@ -50,40 +50,40 @@ /** @addtogroup FLASH * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ - + /** * @brief FLASH Procedure structure definition */ -typedef enum +typedef enum { - FLASH_PROC_NONE = 0U, + FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM } FLASH_ProcedureTypeDef; -/** - * @brief FLASH handle Structure definition +/** + * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - + __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ - + __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ - + __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ __IO uint32_t Address; /* Internal variable to save address selected for program */ - + HAL_LockTypeDef Lock; /* FLASH locking object */ __IO uint32_t ErrorCode; /* FLASH error code */ @@ -97,12 +97,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ - */ + */ /** @defgroup FLASH_Error_Code FLASH Error Code - * @brief FLASH Error Code + * @brief FLASH Error Code * @{ - */ + */ #define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ #define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ @@ -113,10 +113,10 @@ typedef struct /** * @} */ - + /** @defgroup FLASH_Type_Program FLASH Type Program * @{ - */ + */ #define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ #define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ #define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ @@ -128,7 +128,7 @@ typedef struct /** @defgroup FLASH_Flag_definition FLASH Flag definition * @brief Flag definition * @{ - */ + */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ @@ -169,11 +169,11 @@ typedef struct #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) /** * @} - */ + */ /** @defgroup FLASH_Keys FLASH Keys * @{ - */ + */ #define FLASH_KEY1 ((uint32_t)0x45670123U) #define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) @@ -185,6 +185,15 @@ typedef struct /** @defgroup FLASH_Sectors FLASH Sectors * @{ */ +#if (FLASH_SECTOR_TOTAL == 2) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#elif (FLASH_SECTOR_TOTAL == 4) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#else #define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ #define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ #define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ @@ -193,21 +202,22 @@ typedef struct #define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ #define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ #define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#endif /* FLASH_SECTOR_TOTAL */ /** * @} - */ + */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @{ */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ @@ -216,74 +226,74 @@ typedef struct /** * @brief Get the FLASH Latency. - * @retval FLASH Latency + * @retval FLASH Latency * The value of this parameter depend on device used within the same series - */ + */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** * @brief Enable the FLASH prefetch buffer. * @retval none - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) /** * @brief Disable the FLASH prefetch buffer. * @retval none - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) /** * @brief Enable the FLASH Adaptive Real-Time memory accelerator. * @note The ART accelerator is available only for flash access on ITCM interface. * @retval none - */ + */ #define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) /** * @brief Disable the FLASH Adaptive Real-Time memory accelerator. * @retval none - */ + */ #define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) /** * @brief Resets the FLASH Adaptive Real-Time memory accelerator. * @note This function must be used only when the Adaptive Real-Time memory accelerator - * is disabled. + * is disabled. * @retval None */ #define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt + * @arg FLASH_IT_ERR: Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt + * @arg FLASH_IT_ERR: Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) /** - * @brief Get the specified FLASH flag status. + * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag * @arg FLASH_FLAG_BSY : FLASH Busy flag * @retval The new state of __FLAG__ (SET or RESET). */ @@ -293,12 +303,12 @@ typedef struct * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) @@ -321,7 +331,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** @@ -369,9 +379,9 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); * @{ */ -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) /** @@ -389,7 +399,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) /** * @} */ @@ -409,7 +419,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} - */ + */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h index a2bbd5b462..2205595b08 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h @@ -52,7 +52,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASH Exported Types * @{ */ @@ -65,11 +65,11 @@ typedef struct uint32_t TypeErase; /*!< Mass erase or sector Erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ -#if defined (FLASH_OPTCR_nDBANK) +#if defined (FLASH_OPTCR_nDBANK) uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. This parameter must be a value of @ref FLASHEx_Banks */ -#endif /* FLASH_OPTCR_nDBANK */ - +#endif /* FLASH_OPTCR_nDBANK */ + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of @ref FLASHEx_Sectors */ @@ -101,10 +101,10 @@ typedef struct uint32_t BORLevel; /*!< Set the BOR Level. This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ - uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ - + uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. This parameter can be a value of @ref FLASHEx_Boot_Address */ @@ -116,7 +116,7 @@ typedef struct This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ #endif /* FLASH_OPTCR2_PCROP */ } FLASH_OBProgramInitTypeDef; @@ -132,16 +132,16 @@ typedef struct /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ - */ + */ #define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ /** * @} */ - + /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range * @{ - */ + */ #define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ #define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ #define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ @@ -149,19 +149,19 @@ typedef struct /** * @} */ - + /** @defgroup FLASHEx_WRP_State FLASH WRP State * @{ - */ + */ #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ /** * @} */ - + /** @defgroup FLASHEx_Option_Type FLASH Option Type * @{ - */ + */ #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ @@ -175,49 +175,49 @@ typedef struct /** * @} */ - + /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection * @{ */ #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) #define OB_RDP_LEVEL_1 ((uint8_t)0x55U) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0 */ /** * @} - */ - + */ + /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog * @{ - */ + */ #define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ #define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ /** * @} - */ - + */ + /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog * @{ - */ + */ #define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ /** * @} - */ + */ /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP * @{ - */ + */ #define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ /** * @} - */ + */ /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY * @{ - */ + */ #define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ /** @@ -256,13 +256,13 @@ typedef struct #if defined (FLASH_OPTCR_nDBOOT) /** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT * @{ - */ + */ #define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ -#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash (Dual bank Boot mode), or RAM if Boot address option in RAM */ /** * @} - */ + */ #endif /* FLASH_OPTCR_nDBOOT */ #if defined (FLASH_OPTCR_nDBANK) @@ -293,7 +293,7 @@ typedef struct /** * @} */ - + /** @defgroup FLASH_Latency FLASH Latency * @{ */ @@ -364,14 +364,14 @@ typedef struct #endif /* FLASH_SECTOR_TOTAL == 24 */ /** * @} - */ + */ #if (FLASH_SECTOR_TOTAL == 24) /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, - * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. * @{ @@ -388,7 +388,7 @@ typedef struct #define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ #define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ #define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ -#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ #define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ /* Dual Bank Sectors */ @@ -403,7 +403,7 @@ typedef struct #define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ #define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ #define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ -#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ #define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ #define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ #define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ @@ -421,7 +421,7 @@ typedef struct * @} */ #endif /* FLASH_SECTOR_TOTAL == 24 */ - + #if (FLASH_SECTOR_TOTAL == 8) /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ @@ -440,7 +440,34 @@ typedef struct */ #endif /* FLASH_SECTOR_TOTAL == 8 */ +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 2 */ + #if defined (FLASH_OPTCR2_PCROP) +#if (FLASH_SECTOR_TOTAL == 8) /** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors * @{ */ @@ -456,6 +483,21 @@ typedef struct /** * @} */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ /** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit * @{ @@ -469,8 +511,8 @@ typedef struct /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @{ @@ -485,7 +527,7 @@ typedef struct /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ @@ -520,15 +562,15 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); */ #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_4)) + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) + ((VALUE) == OB_WRPSTATE_ENABLE)) #if defined (FLASH_OPTCR2_PCROP) #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ @@ -607,6 +649,19 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) #endif /* FLASH_SECTOR_TOTAL == 24 */ +#if (FLASH_SECTOR_TOTAL == 4) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 2 */ + #if defined (FLASH_OPTCR_nDBANK) #define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ ((VALUE) == OB_NDBANK_DUAL_BANK)) @@ -642,11 +697,11 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h index e1f6e21ff2..10722cf70b 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h @@ -64,7 +64,7 @@ */ /*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** * @brief AF 0 selection */ @@ -173,12 +173,12 @@ #define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) #define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) #define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @brief AF 10 selection */ @@ -220,14 +220,14 @@ #if defined (STM32F769xx) || defined (STM32F779xx) #define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) #define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @brief AF 15 selection */ @@ -236,7 +236,7 @@ /*----------------------------------------------------------------------------*/ /*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ -#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx) /** * @brief AF 0 selection */ @@ -348,7 +348,7 @@ * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /*----------------------------------------------------------------------------*/ /** @@ -410,7 +410,8 @@ * @{ */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -421,9 +422,9 @@ ((__GPIOx__) == (GPIOH))? 7U :\ ((__GPIOx__) == (GPIOI))? 8U :\ ((__GPIOx__) == (GPIOJ))? 9U : 10U) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -432,7 +433,7 @@ ((__GPIOx__) == (GPIOF))? 5U :\ ((__GPIOx__) == (GPIOG))? 6U :\ ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /** * @} */ @@ -452,7 +453,7 @@ /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ @@ -611,7 +612,7 @@ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ ((AF) == GPIO_AF10_OTG_FS)) -#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ @@ -638,7 +639,7 @@ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ ((AF) == GPIO_AF10_OTG_FS)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F756xx || STM32F746xx || STM32F750xx */ /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h index ebc6d2b38b..7a25b806a3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -433,7 +433,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h index 904c2b08eb..56839594e0 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -183,7 +183,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h index 655356b9d0..7d1859e0ad 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h @@ -48,8 +48,7 @@ * @{ */ -/** @defgroup HCD HCD - * @brief HCD HAL module driver +/** @addtogroup HCD * @{ */ @@ -63,18 +62,18 @@ */ typedef enum { - HAL_HCD_STATE_RESET = 0x00U, - HAL_HCD_STATE_READY = 0x01U, - HAL_HCD_STATE_ERROR = 0x02U, - HAL_HCD_STATE_BUSY = 0x03U, - HAL_HCD_STATE_TIMEOUT = 0x04U + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; -typedef USB_OTG_HCTypeDef HCD_HCTypeDef ; -typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ; -typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; /** * @} */ @@ -86,7 +85,7 @@ typedef struct { HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ - HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ void *pData; /*!< Pointer Stack Handler */ @@ -132,8 +131,8 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ -#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) @@ -166,9 +165,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); /** * @} */ @@ -233,14 +232,6 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ -/** @defgroup HCD_Instance_definition HCD Instance definition - * @{ - */ -#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ - ((INSTANCE) == USB_OTG_HS)) -/** - * @} - */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h index f9fac3c1a8..f4f343169d 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -646,7 +646,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** * @} */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h index a1eccd3181..984eeedd16 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_PCD_H @@ -43,72 +43,75 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_ll_usb.h" - + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ /** @addtogroup PCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PCD_Exported_Types PCD Exported Types * @{ */ - + /** * @brief PCD State structure definition - */ -typedef enum + */ +typedef enum { - HAL_PCD_STATE_RESET = 0x00U, - HAL_PCD_STATE_READY = 0x01U, - HAL_PCD_STATE_ERROR = 0x02U, - HAL_PCD_STATE_BUSY = 0x03U, - HAL_PCD_STATE_TIMEOUT = 0x04U + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 } PCD_StateTypeDef; /* Device LPM suspend state */ -typedef enum +typedef enum { - LPM_L0 = 0x00U, /* on */ - LPM_L1 = 0x01U, /* LPM L1 sleep */ - LPM_L2 = 0x02U, /* suspend */ - LPM_L3 = 0x03U, /* off */ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ }PCD_LPM_StateTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; -typedef USB_OTG_EPTypeDef PCD_EPTypeDef ; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* USB_OTG_FS || USB_OTG_HS */ -/** - * @brief PCD Handle Structure definition - */ + +/** + * @brief PCD Handle Structure definition + */ typedef struct { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ } PCD_HandleTypeDef; /** * @} */ - -/* Include PCD HAL Extension module */ + +/* Include PCD HAL Extended module */ #include "stm32f7xx_hal_pcd_ex.h" /* Exported constants --------------------------------------------------------*/ @@ -119,13 +122,15 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ +#if defined (USB_OTG_HS) #define PCD_SPEED_HIGH 0U #define PCD_SPEED_HIGH_IN_FULL 1U +#endif #define PCD_SPEED_FULL 2U /** * @} */ - + /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ @@ -145,87 +150,58 @@ typedef struct #ifndef USBD_FS_TRDT_VALUE #define USBD_FS_TRDT_VALUE 5U #endif /* USBD_HS_TRDT_VALUE */ - /** * @} */ /** * @} - */ - + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) + ~(USB_OTG_PCGCCTL_STOPCLK) #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) - -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) - -#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - }while(0) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - }while(0) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - }while(0) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) - +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - }while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - }while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - }while(0) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* USB_OTG_FS || USB_OTG_HS */ -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) /** * @} */ @@ -240,7 +216,7 @@ typedef struct * @{ */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); /** @@ -299,42 +275,70 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @} - */ + */ /** * @} - */ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U + +#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U + +#ifndef LL_EXTI_LINE_18 +#define LL_EXTI_LINE_18 0x00040000U +#endif + +#ifndef LL_EXTI_LINE_20 +#define LL_EXTI_LINE_20 0x00100000U +#endif + +#define USB_OTG_FS_WAKEUP_EXTI_LINE LL_EXTI_LINE_18 /*!< External interrupt line 17 Connected to the USB EXTI Line */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE LL_EXTI_LINE_20 /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + + +/** + * @} + */ + +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ -/** @defgroup PCD_Instance_definition PCD Instance definition - * @{ + +/** + * @} */ -#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ - ((INSTANCE) == USB_OTG_HS)) -/** - * @} - */ /** * @} - */ + */ /** * @} - */ - -/** - * @} - */ + */ #ifdef __cplusplus } #endif - #endif /* __STM32F7xx_HAL_PCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h index e97d42e9ce..ede43f0600 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @brief Header file of PCD HAL module. + * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention * @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_PCD_EX_H @@ -43,7 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" - + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -52,21 +52,21 @@ * @{ */ /* Exported types ------------------------------------------------------------*/ -typedef enum +typedef enum { - PCD_LPM_L0_ACTIVE = 0x00U, /* on */ - PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ }PCD_LPM_MsgTypeDef; -typedef enum +typedef enum { - PCD_BCD_ERROR = 0xFF, + PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00, - + }PCD_BCD_MsgTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -78,27 +78,28 @@ typedef enum /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* USB_OTG_FS || USB_OTG_HS */ + HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h index 3e76778ebe..d43c6bfc76 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h - * @author MCD Application Team + * @author MCD Application Team * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_RCC_EX_H @@ -50,15 +50,15 @@ /** @addtogroup RCCEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ - -/** - * @brief RCC PLL configuration structure definition + +/** + * @brief RCC PLL configuration structure definition */ typedef struct { @@ -66,10 +66,10 @@ typedef struct This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ @@ -82,12 +82,12 @@ typedef struct #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -}RCC_PLLInitTypeDef; +}RCC_PLLInitTypeDef; -/** - * @brief PLLI2S Clock structure definition +/** + * @brief PLLI2S Clock structure definition */ typedef struct { @@ -96,58 +96,58 @@ typedef struct This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLI2S is selected as Clock Source SAI */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ }RCC_PLLI2SInitTypeDef; -/** - * @brief PLLSAI Clock structure definition +/** + * @brief PLLSAI Clock structure definition */ typedef struct { uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - + #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider This parameter will be used only when PLLSAI is disabled */ }RCC_PLLSAIInitTypeDef; -/** - * @brief RCC extended clocks structure definition +/** + * @brief RCC extended clocks structure definition */ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. @@ -161,82 +161,82 @@ typedef struct uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ - uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. + uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. + + uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ - uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ - + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source + + uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source + + uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - uint32_t Usart3ClockSelection; /*!< USART3 clock source - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t Uart4ClockSelection; /*!< UART4 clock source + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - - uint32_t Uart5ClockSelection; /*!< UART5 clock source + + uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - - uint32_t Usart6ClockSelection; /*!< USART6 clock source + + uint32_t Usart6ClockSelection; /*!< USART6 clock source This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ - - uint32_t Uart7ClockSelection; /*!< UART7 clock source + + uint32_t Uart7ClockSelection; /*!< UART7 clock source This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ - - uint32_t Uart8ClockSelection; /*!< UART8 clock source + + uint32_t Uart8ClockSelection; /*!< UART8 clock source This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - uint32_t I2c2ClockSelection; /*!< I2C2 clock source + uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - uint32_t I2c3ClockSelection; /*!< I2C3 clock source + uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - - uint32_t I2c4ClockSelection; /*!< I2C4 clock source + + uint32_t I2c4ClockSelection; /*!< I2C4 clock source This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t CecClockSelection; /*!< CEC clock source + + uint32_t CecClockSelection; /*!< CEC clock source This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - + uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source + + uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ - + #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ - - uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PeriphCLKInitTypeDef; /** * @} @@ -251,9 +251,9 @@ typedef struct * @{ */ #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) @@ -277,20 +277,20 @@ typedef struct #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) -#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /** * @} */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider * @{ */ @@ -301,8 +301,8 @@ typedef struct /** * @} */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider * @{ */ @@ -333,9 +333,8 @@ typedef struct /** * @} - */ - - + */ + /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source * @{ */ @@ -347,7 +346,7 @@ typedef struct #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source * @{ @@ -360,7 +359,7 @@ typedef struct #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ @@ -540,7 +539,7 @@ typedef struct */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source * @{ */ @@ -549,9 +548,9 @@ typedef struct /** * @} */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source * @{ */ @@ -576,16 +575,16 @@ typedef struct * @{ */ #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) -#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) /** * @} - */ + */ #endif /* STM32F769xx || STM32F779xx */ /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ @@ -593,14 +592,14 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable * @brief Enables or disables the AHB/APB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ - + /** @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. */ #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ @@ -610,7 +609,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ @@ -618,7 +617,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ @@ -716,7 +715,8 @@ typedef struct } while(0) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ @@ -732,7 +732,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ @@ -740,7 +740,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) @@ -757,14 +757,16 @@ typedef struct #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) /** * @brief Enable ETHERNET clock. */ @@ -799,7 +801,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_ETH_CLK_ENABLE() do { \ __HAL_RCC_ETHMAC_CLK_ENABLE(); \ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ @@ -817,15 +819,16 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ @@ -834,9 +837,9 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ @@ -844,8 +847,8 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -862,12 +865,12 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ UNUSED(tmpreg); \ __HAL_RCC_SYSCFG_CLK_ENABLE();\ - } while(0) + } while(0) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -883,12 +886,12 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) -#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ @@ -896,14 +899,14 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ UNUSED(tmpreg); \ } while(0) - -#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) -#endif /* STM32F732xx || STM32F733xx */ - + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. */ #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -926,8 +929,8 @@ typedef struct /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1011,7 +1014,7 @@ typedef struct #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ @@ -1020,7 +1023,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ @@ -1031,7 +1034,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ @@ -1103,7 +1106,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ @@ -1135,9 +1138,10 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ UNUSED(tmpreg); \ } while(0) - + #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ @@ -1169,7 +1173,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) @@ -1183,13 +1187,13 @@ typedef struct #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) @@ -1204,16 +1208,17 @@ typedef struct #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. */ #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ @@ -1249,7 +1254,7 @@ typedef struct } while(0) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ @@ -1257,7 +1262,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1363,7 +1368,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ @@ -1371,26 +1376,26 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* STM32F769xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0) #define __HAL_RCC_MDIO_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1400,7 +1405,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ @@ -1408,16 +1413,16 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F723xx || STM32F733xx */ - +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) @@ -1431,25 +1436,24 @@ typedef struct #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) -#endif /* STM32F723xx || STM32F733xx */ - +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + /** * @} */ - /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB/APB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1457,15 +1461,15 @@ typedef struct * using it. * @{ */ - + /** @brief Get the enable or disable status of the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. + * using it. */ #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) @@ -1478,11 +1482,12 @@ typedef struct #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) @@ -1499,14 +1504,16 @@ typedef struct #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) /** * @brief Enable ETHERNET clock. */ @@ -1528,36 +1535,37 @@ typedef struct #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. + * using it. */ #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) - -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined(STM32F732xx) || defined (STM32F733xx) +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) @@ -1568,7 +1576,7 @@ typedef struct * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. - */ + */ #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) @@ -1634,7 +1642,8 @@ typedef struct #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) @@ -1644,15 +1653,15 @@ typedef struct #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1676,23 +1685,23 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) @@ -1711,35 +1720,35 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ /** * @} - */ + */ /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset * @brief Forces or releases AHB/APB peripheral reset. * @{ */ - + /** @brief Force or release AHB1 peripheral reset. - */ + */ #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) @@ -1765,7 +1774,8 @@ typedef struct #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) @@ -1775,11 +1785,11 @@ typedef struct #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release AHB2 peripheral reset. */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) @@ -1792,36 +1802,37 @@ typedef struct #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release AHB3 peripheral reset - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) - + /** @brief Force or release APB1 peripheral reset. - */ + */ #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -1877,17 +1888,18 @@ typedef struct #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) - + #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release APB2 peripheral reset. */ @@ -1906,12 +1918,12 @@ typedef struct #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1928,12 +1940,12 @@ typedef struct #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) @@ -1941,10 +1953,10 @@ typedef struct #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) @@ -1954,7 +1966,7 @@ typedef struct #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. @@ -1963,10 +1975,10 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ - */ - + */ + /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - */ + */ #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) @@ -2006,7 +2018,8 @@ typedef struct #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) @@ -2022,7 +2035,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2031,10 +2044,11 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) @@ -2047,18 +2061,18 @@ typedef struct #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) - + #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2077,7 +2091,7 @@ typedef struct * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) @@ -2134,14 +2148,15 @@ typedef struct #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) @@ -2150,15 +2165,15 @@ typedef struct #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) @@ -2175,9 +2190,9 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -2195,9 +2210,9 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) @@ -2209,16 +2224,17 @@ typedef struct #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ @@ -2231,12 +2247,12 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ - + /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) @@ -2277,7 +2293,8 @@ typedef struct #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) @@ -2293,7 +2310,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2302,34 +2319,35 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) - + #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2348,7 +2366,7 @@ typedef struct * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) @@ -2361,10 +2379,10 @@ typedef struct #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -2394,10 +2412,10 @@ typedef struct #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -2416,24 +2434,25 @@ typedef struct #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) - + #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) @@ -2450,16 +2469,16 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) @@ -2481,26 +2500,27 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ @@ -2513,7 +2533,7 @@ typedef struct * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input @@ -2549,7 +2569,7 @@ typedef struct * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input @@ -2575,45 +2595,45 @@ typedef struct ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*---------------------------------------------------------------------------------------------*/ -/** @brief Macro to configure the Timers clocks prescalers +/** @brief Macro to configure the Timers clocks prescalers * @param __PRESC__ specifies the Timers clocks prescalers selection * This parameter can be one of the following values: - * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding * to division by 8 or more. - */ + */ #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ RCC->DCKCFGR1 |= (__PRESC__); \ }while(0) -/** @brief Macros to Enable or Disable the PLLISAI. - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in + * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - */ + */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ @@ -2621,18 +2641,18 @@ typedef struct /** @brief Macro to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLI2SQ__ specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. + * on the I2S clock frequency. */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ @@ -2641,20 +2661,20 @@ typedef struct #else /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in + * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ @@ -2662,33 +2682,33 @@ typedef struct /** @brief Macro to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. - * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. * @param __PLLI2SQ__ specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. + * on the I2S clock frequency. */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. + * @note This function must be called before enabling the PLLI2S. * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ */ #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) @@ -2696,69 +2716,69 @@ typedef struct * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between Min_Data = 1 and Max_Data = 32. - * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. - * @note This function must be called before enabling the PLLSAI. + * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. - * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ - */ + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Macro to configure SAI1 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__ specifies the SAI1 clock source. * This parameter can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) - /** @brief Macro to configure SAI2 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__ specifies the SAI2 clock source. * This parameter can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) @@ -2766,15 +2786,15 @@ typedef struct /** @brief Macro to get the SAI2 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) @@ -2803,7 +2823,7 @@ typedef struct /** @brief Macro to Get I2S clock source selection. * @retval The clock source can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source */ #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) @@ -3125,7 +3145,7 @@ typedef struct #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. * This parameter can be one of the following values: @@ -3141,8 +3161,8 @@ typedef struct * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock */ #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the DFSDM1 clock * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. @@ -3174,25 +3194,25 @@ typedef struct * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F769xx) || defined (STM32F779xx) /** @brief Macro to configure the DSI clock. * @param __DSI_CLKSOURCE__ specifies the DSI clock source. * This parameter can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. */ #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) /** @brief Macro to Get the DSI clock. * @retval The clock source can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) -#endif /* STM32F769xx || STM32F779xx */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ /** * @} */ @@ -3210,7 +3230,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros * @{ @@ -3218,7 +3238,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ @@ -3294,7 +3314,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined (STM32F765xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ @@ -3321,8 +3341,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ @@ -3343,16 +3363,16 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F746xx || STM32F756xx */ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ ((VALUE) == RCC_PLLI2SP_DIV4) ||\ ((VALUE) == RCC_PLLI2SP_DIV6) ||\ ((VALUE) == RCC_PLLI2SP_DIV8)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -3362,7 +3382,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); ((VALUE) == RCC_PLLSAIP_DIV6) ||\ ((VALUE) == RCC_PLLSAIP_DIV8)) #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) @@ -3456,18 +3476,18 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); ((VALUE) == RCC_TIMPRES_ACTIVATED)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ - defined (STM32F746xx) || defined (STM32F756xx) + defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */ - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ + #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - + #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ @@ -3486,19 +3506,15 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ /** * @} @@ -3506,11 +3522,15 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** * @} - */ + */ /** * @} - */ + */ + +/** + * @} + */ #ifdef __cplusplus } #endif diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h index b3a0cf3ea0..94c13802b6 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @brief Header file of USB Core HAL module. + * @brief Header file of USB Low Layer HAL module. ****************************************************************************** * @attention * @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_LL_USB_H @@ -44,192 +44,190 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" -/** @addtogroup STM32F7xx_HAL +/** @addtogroup STM32F7xx_HAL_Driver * @{ */ -/** @addtogroup USB_Core +/** @addtogroup USB_LL * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ -/** - * @brief USB Mode definition - */ -typedef enum +/** + * @brief USB Mode definition + */ +typedef enum { - USB_OTG_DEVICE_MODE = 0U, - USB_OTG_HOST_MODE = 1U, - USB_OTG_DRD_MODE = 2U - + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 }USB_OTG_ModeTypeDef; -/** - * @brief URB States definition - */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief URB States definition + */ typedef enum { - URB_IDLE = 0U, + URB_IDLE = 0, URB_DONE, URB_NOTREADY, URB_NYET, URB_ERROR, URB_STALL - }USB_OTG_URBStateTypeDef; -/** - * @brief Host channel States definition - */ +/** + * @brief Host channel States definition + */ typedef enum { - HC_IDLE = 0U, + HC_IDLE = 0, HC_XFRC, HC_HALTED, HC_NAK, HC_NYET, HC_STALL, - HC_XACTERR, - HC_BBLERR, + HC_XACTERR, + HC_BBLERR, HC_DATATGLERR - }USB_OTG_HCStateTypeDef; -/** - * @brief PCD Initialization Structure definition +/** + * @brief USB OTG Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref USB_EP0_MPS_ */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS_ */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + This parameter can be any value of @ref USB_Core_PHY_ */ - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ }USB_OTG_CfgTypeDef; typedef struct { uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ - + This parameter can be any value of @ref USB_EP_Type_ */ + uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ }USB_OTG_EPTypeDef; typedef struct { uint8_t dev_addr ; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t speed; /*!< USB Host speed. This parameter can be any value of @ref USB_Core_Speed_ */ - + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_EP_Type_ */ - + uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t data_pid; /*!< Initial data PID. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - + uint32_t xfer_len; /*!< Current transfer length. */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - + uint8_t toggle_in; /*!< IN transfer current toggle flag. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - + uint32_t ErrCnt; /*!< Host channel error count.*/ - - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ - + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ }USB_OTG_HCTypeDef; - +#endif /* defined USB_OTG_FS || USB_OTG_HS */ + + /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_Core_Mode_ USB Core Mode * @{ */ @@ -240,56 +238,55 @@ typedef struct * @} */ -/** @defgroup USB_Core_Speed_ USB Core Speed +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ - */ + */ #define USB_OTG_SPEED_HIGH 0U #define USB_OTG_SPEED_HIGH_IN_FULL 1U -#define USB_OTG_SPEED_LOW 2U +#define USB_OTG_SPEED_LOW 2U #define USB_OTG_SPEED_FULL 3U /** * @} */ - -/** @defgroup USB_Core_PHY_ USB Core PHY + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY * @{ - */ + */ #define USB_OTG_ULPI_PHY 1U #define USB_OTG_EMBEDDED_PHY 2U #define USB_OTG_HS_EMBEDDED_PHY 3U -#if !defined (USB_HS_PHYC_TUNE_VALUE) +#if !defined (USB_HS_PHYC_TUNE_VALUE) #define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ #endif /* USB_HS_PHYC_TUNE_VALUE */ - -/** - * @} - */ - -/** @defgroup USB_Core_MPS_ USB Core MPS - * @{ - */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ -/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ - -/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency * @{ - */ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ #define DCFG_FRAME_INTERVAL_80 0U #define DCFG_FRAME_INTERVAL_85 1U #define DCFG_FRAME_INTERVAL_90 2U @@ -298,7 +295,7 @@ typedef struct * @} */ -/** @defgroup USB_EP0_MPS_ USB EP0 MPS +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ #define DEP0CTL_MPS_64 0U @@ -309,7 +306,7 @@ typedef struct * @} */ -/** @defgroup USB_EP_Speed_ USB EP Speed +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed * @{ */ #define EP_SPEED_LOW 0U @@ -319,7 +316,7 @@ typedef struct * @} */ -/** @defgroup USB_EP_Type_ USB EP Type +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ */ #define EP_TYPE_CTRL 0U @@ -331,7 +328,7 @@ typedef struct * @} */ -/** @defgroup USB_STS_Defines_ USB STS Defines +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ #define STS_GOUT_NAK 1U @@ -343,31 +340,31 @@ typedef struct * @} */ -/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines * @{ - */ + */ #define HCFG_30_60_MHZ 0U #define HCFG_48_MHZ 1U #define HCFG_6_MHZ 2U /** * @} */ - -/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ - */ + */ #define HPRT0_PRTSPD_HIGH_SPEED 0U #define HPRT0_PRTSPD_FULL_SPEED 1U #define HPRT0_PRTSPD_LOW_SPEED 2U /** * @} - */ - + */ + #define HCCHAR_CTRL 0U #define HCCHAR_ISOC 1U #define HCCHAR_BULK 2U #define HCCHAR_INTR 3U - + #define HC_PID_DATA0 0U #define HC_PID_DATA2 1U #define HC_PID_DATA1 2U @@ -377,31 +374,44 @@ typedef struct #define GRXSTS_PKTSTS_IN_XFER_COMP 3U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) +#endif /* USB_OTG_FS || USB_OTG_HS */ -#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) -#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) - - /** * @} */ + /* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - + #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* USB_OTG_FS || USB_OTG_HS */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); @@ -409,7 +419,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode); HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ); +HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); @@ -441,27 +451,37 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); - -/** - * @} - */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +#endif /* USB_OTG_FS || USB_OTG_HS */ /** * @} */ - +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c index c280e15447..ac33986156 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -66,11 +66,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.2.5 + * @brief STM32F7xx HAL Driver version number V1.2.6 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c index 980b7b8332..9ec93117bf 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c @@ -100,7 +100,7 @@ * @{ */ -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup HASH HASH * @brief HASH HAL module driver. @@ -1867,7 +1867,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c index 11975a1549..de9c9967f6 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c @@ -96,7 +96,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined (STM32F750xx) /** @defgroup HASHEx HASHEx * @brief HASH Extension HAL module driver. @@ -1625,7 +1625,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c index 3b7becede7..690c4e0b02 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c @@ -87,7 +87,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private function ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ /** @defgroup HCD_Private_Functions HCD Private Functions * @{ */ @@ -133,26 +133,32 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + if(hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); + } + hhcd->State = HAL_HCD_STATE_BUSY; - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_HCD_MspInit(hhcd); - /* Disable the Interrupts */ - __HAL_HCD_DISABLE(hhcd); + __HAL_HCD_DISABLE(hhcd); - /*Init the Core (common init.) */ - USB_CoreInit(hhcd->Instance, hhcd->Init); + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); - /* Force Host Mode*/ - USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE); + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); - /* Init Host */ - USB_HostInit(hhcd->Instance, hhcd->Init); + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); - hhcd->State= HAL_HCD_STATE_READY; + hhcd->State= HAL_HCD_STATE_READY; - return HAL_OK; + return HAL_OK; } /** @@ -162,7 +168,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 1 to 15 * @param epnum Endpoint number. * This parameter can be a value from 1 to 15 - * @param dev_address Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 * @param speed Current device speed. * This parameter can be one of these values: @@ -187,16 +193,25 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ep_type, uint16_t mps) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; __HAL_LOCK(hhcd); - hhcd->hc[ch_num].do_ping = 0; + hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7F; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + hhcd->hc[ch_num].speed = speed; status = USB_HC_Init(hhcd->Instance, @@ -223,7 +238,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HAL_StatusTypeDef status = HAL_OK; __HAL_LOCK(hhcd); - USB_HC_Halt(hhcd->Instance, ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_UNLOCK(hhcd); return status; @@ -247,7 +262,7 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) /* DeInit the low level hardware */ HAL_HCD_MspDeInit(hhcd); - __HAL_HCD_DISABLE(hhcd); + __HAL_HCD_DISABLE(hhcd); hhcd->State = HAL_HCD_STATE_RESET; @@ -264,7 +279,7 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_MspInit could be implemented in the user file */ } @@ -279,7 +294,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_MspDeInit could be implemented in the user file */ } @@ -327,18 +342,20 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, - uint16_t length, - uint8_t do_ping) + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t* pbuff, + uint16_t length, + uint8_t do_ping) { + UNUSED(do_ping); + hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; - if(token == 0) + if(token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; } @@ -351,15 +368,15 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, switch(ep_type) { case EP_TYPE_CTRL: - if((token == 1) && (direction == 0)) /*send data */ + if((token == 1U) && (direction == 0U)) /*send data */ { - if ( length == 0 ) + if (length == 0U) { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1; + hhcd->hc[ch_num].toggle_out = 1U; } /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if (hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -371,10 +388,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, break; case EP_TYPE_BULK: - if(direction == 0) + if(direction == 0U) { /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -385,7 +402,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, } else { - if( hhcd->hc[ch_num].toggle_in == 0) + if( hhcd->hc[ch_num].toggle_in == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -397,21 +414,21 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, break; case EP_TYPE_INTR: - if(direction == 0) + if(direction == 0U) { /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } else { - if( hhcd->hc[ch_num].toggle_in == 0) + if( hhcd->hc[ch_num].toggle_in == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -425,16 +442,19 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, case EP_TYPE_ISOC: hhcd->hc[ch_num].data_pid = HC_PID_DATA0; break; + + default: + break; } hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0 ; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].state = HC_IDLE; - return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); } /** @@ -445,12 +465,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t i = 0 , interrupt = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, interrupt; - /* ensure that we are in device mode */ + /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) { - /* avoid spurious interrupt */ + /* Avoid spurious interrupt */ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) { return; @@ -458,25 +479,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); } @@ -490,7 +511,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Handle Host Port Interrupts */ HAL_HCD_Disconnect_Callback(hhcd); - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); } @@ -511,25 +532,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (i = 0; i < hhcd->Init.Host_channels ; i++) + for (i = 0U; i < hhcd->Init.Host_channels; i++) { - if (interrupt & (1 << i)) + if ((interrupt & (1UL << (i & 0xFU))) != 0U) { - if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR) + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) { - HCD_HC_IN_IRQHandler (hhcd, i); + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); } else { - HCD_HC_OUT_IRQHandler (hhcd, i); + HCD_HC_OUT_IRQHandler (hhcd, (uint8_t)i); } } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } - /* Handle Rx Queue Level Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) + /* Handle Rx Queue Level Interrupts */ + if((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); @@ -550,7 +571,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_SOF_Callback could be implemented in the user file */ } @@ -565,7 +586,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Connect_Callback could be implemented in the user file */ } @@ -580,35 +601,37 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ } /** * @brief Port Enabled Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ } /** * @brief Port Disabled Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ } @@ -632,8 +655,10 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file */ } @@ -666,7 +691,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); + (void)USB_DriveVbus(hhcd->Instance, 1U); __HAL_UNLOCK(hhcd); return HAL_OK; } @@ -680,7 +705,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); - USB_StopHost(hhcd->Instance); + (void)USB_StopHost(hhcd->Instance); __HAL_UNLOCK(hhcd); return HAL_OK; } @@ -816,150 +841,166 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + } + else + { + /* ... */ } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - hhcd->hc[chnum].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - } - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) - { - - if (hhcd->Init.dma_enable) + if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \ - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)|| + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + else if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[ch_num].urb_state = URB_DONE; + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } - hhcd->hc[chnum].toggle_in ^= 1; + else + { + /* ... */ + } + hhcd->hc[ch_num].toggle_in ^= 1U; } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); + __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if(hhcd->hc[chnum].state == HC_XFRC) + if(hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; + hhcd->hc[ch_num].urb_state = URB_DONE; } - - else if (hhcd->hc[chnum].state == HC_STALL) + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; + hhcd->hc[ch_num].urb_state = URB_STALL; } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + else if((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) + hhcd->hc[ch_num].ErrCnt++; + if(hhcd->hc[ch_num].ErrCnt > 3U) { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[ch_num].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].ErrCnt++; - hhcd->hc[chnum].state = HC_XACTERR; - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + else { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + /* ... */ } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - hhcd->hc[chnum].ErrCnt = 0; - if (!hhcd->Init.dma_enable) + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)|| + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[ch_num].ErrCnt = 0U; + if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[ch_num].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ } } @@ -970,147 +1011,147 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + uint32_t tmpreg; - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - if( hhcd->hc[chnum].do_ping == 1) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + + if( hhcd->hc[ch_num].do_ping == 1U) { - hhcd->hc[chnum].do_ping = 0; - hhcd->hc[chnum].urb_state = URB_NOTREADY; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { - hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].do_ping = 1; - hhcd->hc[chnum].ErrCnt= 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt= 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - hhcd->hc[chnum].state = HC_XFRC; - + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_STALL; } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].state = HC_NAK; + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; - if ( hhcd->hc[chnum].do_ping == 0) + if (hhcd->hc[ch_num].do_ping == 0U) { - if (hhcd->hc[chnum].speed == HCD_SPEED_HIGH) + if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) { - hhcd->hc[chnum].do_ping = 1; + hhcd->hc[ch_num].do_ping = 1U; } } - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_XACTERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - hhcd->hc[chnum].state = HC_DATATGLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); + __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if(hhcd->hc[chnum].state == HC_XFRC) + if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; - if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) + hhcd->hc[ch_num].urb_state = URB_DONE; + if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) { - hhcd->hc[chnum].toggle_out ^= 1; + hhcd->hc[ch_num].toggle_out ^= 1U; } } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[ch_num].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - - else if (hhcd->hc[chnum].state == HC_NYET) + else if (hhcd->hc[ch_num].state == HC_NYET) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - - else if (hhcd->hc[chnum].state == HC_STALL) + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; + hhcd->hc[ch_num].urb_state = URB_STALL; } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else + { + /* ... */ } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else + { + /* ... */ } } @@ -1119,47 +1160,48 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) * @param hhcd HCD handle * @retval none */ -static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; - uint32_t pktsts; - uint32_t pktcnt; - uint32_t temp = 0; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; - temp = hhcd->Instance->GRXSTSP ; - channelnum = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + temp = hhcd->Instance->GRXSTSP; + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; switch (pktsts) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) { - - USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); /*manage multiple Xfer */ - hhcd->hc[channelnum].xfer_buff += pktcnt; - hhcd->hc[channelnum].xfer_count += pktcnt; + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; - if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) + if((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) { /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(channelnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(channelnum)->HCCHAR = tmpreg; - hhcd->hc[channelnum].toggle_in ^= 1; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; } } break; case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: break; + case GRXSTS_PKTSTS_IN_XFER_COMP: case GRXSTS_PKTSTS_CH_HALTED: default: @@ -1172,9 +1214,10 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) * @param hhcd HCD handle * @retval None */ -static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0, hprt0_dup; /* Handle Host Port Interrupts */ @@ -1182,7 +1225,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) hprt0_dup = USBx_HPRT0; hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); /* Check whether Port Connect detected */ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) @@ -1193,7 +1236,6 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) HAL_HCD_Connect_Callback(hhcd); } hprt0_dup |= USB_OTG_HPRT_PCDET; - } /* Check whether Port Enable Changed */ @@ -1207,28 +1249,28 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); } else { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } else { if(hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = (uint32_t)60000; + USBx_HOST->HFIR = 60000U; } } HAL_HCD_PortEnabled_Callback(hhcd); HAL_HCD_Connect_Callback(hhcd); - } else { HAL_HCD_PortDisabled_Callback(hhcd); + /* Cleanup HPRT */ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); @@ -1237,7 +1279,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) } } - /* Check For an overcurrent */ + /* Check for an overcurrent */ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { hprt0_dup |= USB_OTG_HPRT_POCCHNG; diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c index fe4791e068..af7be5026c 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c @@ -113,7 +113,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup LTDC LTDC * @brief LTDC HAL module driver @@ -1904,7 +1904,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /** * @} */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c index 441815a543..b9f0df14c3 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c @@ -77,7 +77,7 @@ * @{ */ -/** @defgroup PCD PCD +/** @defgroup PCD * @brief PCD HAL module driver * @{ */ @@ -87,6 +87,14 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * USB_OTG_CORE VERSION ID + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +#define USB_OTG_CORE_ID_320A 0x4F54320AU +#endif /* USB_OTG_FS || USB_OTG_HS */ /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ @@ -101,7 +109,9 @@ /** @defgroup PCD_Private_Functions PCD Private Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* USB_OTG_FS || USB_OTG_HS */ /** * @} */ @@ -126,13 +136,13 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t /** * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and create the associated handle. + * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t i = 0; + uint8_t i; /* Check the PCD handle allocation */ if(hpcd == NULL) @@ -143,68 +153,66 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + if(hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + } + hpcd->State = HAL_PCD_STATE_BUSY; - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); - /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); + __HAL_PCD_DISABLE(hpcd); - /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); + /*Init the Core (common init.) */ + (void)USB_CoreInit(hpcd->Instance, hpcd->Init); - /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE); + /* Force Device Mode*/ + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); - /* Init endpoints structures */ - for (i = 0; i < 15 ; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1; - hpcd->IN_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->IN_ep[i].type = EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0; - hpcd->IN_ep[i].xfer_buff = 0; - hpcd->IN_ep[i].xfer_len = 0; - } + /* Init endpoints structures */ + for (i = 0U; i < 15U; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } - for (i = 0; i < 15 ; i++) - { - hpcd->OUT_ep[i].is_in = 0; - hpcd->OUT_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0; - hpcd->OUT_ep[i].xfer_buff = 0; - hpcd->OUT_ep[i].xfer_len = 0; + for (i = 0U; i < 15U; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } - hpcd->Instance->DIEPTXF[i] = 0; - } + /* Init Device */ + (void)USB_DevInit(hpcd->Instance, hpcd->Init); - /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; - hpcd->State= HAL_PCD_STATE_READY; + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } - /* Activate LPM */ - if (hpcd->Init.lpm_enable ==1) - { - HAL_PCDEx_ActivateLPM(hpcd); - } -#if defined (USB_OTG_GCCFG_BCDEN) - /* Activate Battery charging */ - if (hpcd->Init.battery_charging_enable ==1) - { - HAL_PCDEx_ActivateBCD(hpcd); - } -#endif /* USB_OTG_GCCFG_BCDEN */ + (void)USB_DevDisconnect (hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); - return HAL_OK; + return HAL_OK; } /** @@ -223,7 +231,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - HAL_PCD_Stop(hpcd); + (void)HAL_PCD_Stop(hpcd); /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); @@ -243,7 +251,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_MspInit could be implemented in the user file */ } @@ -258,7 +266,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_MspDeInit could be implemented in the user file */ } @@ -267,7 +275,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @} */ -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * @verbatim @@ -283,21 +291,21 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) */ /** - * @brief Start The USB OTG Device. + * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); + (void)USB_DevConnect (hpcd->Instance); __HAL_PCD_ENABLE(hpcd); __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Stop The USB OTG Device. + * @brief Stop the USB device. * @param hpcd PCD handle * @retval HAL status */ @@ -305,24 +313,27 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); + (void)USB_StopDevice(hpcd->Instance); + (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** - * @brief Handle PCD interrupt request. + * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0; - uint32_t fifoemptymsk = 0, temp = 0; - USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 200000000; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t TempReg = USBx_BASE + 0x40U; + uint32_t gSNPSiD = *(uint32_t *) TempReg; + uint32_t i, ep_intr, epint, epnum = 0U; + uint32_t fifoemptymsk, temp; + USB_OTG_EPTypeDef *ep; + uint32_t hclk; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -335,61 +346,90 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { - epnum = 0; + epnum = 0U; /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - while ( ep_intr ) + while (ep_intr != 0U) { - if (ep_intr & 0x1) + if ((ep_intr & 0x1U) != 0U) { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); - if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - /* setup/out transaction management for Core ID >= 310A */ - if (hpcd->Init.dma_enable == 1) + if (gSNPSiD > USB_OTG_CORE_ID_300A) { - if (USBx_OUTEP(0)->DOEPINT & (1 << 15)) + /* setup/out transaction management for Core ID >= 310A */ + if (hpcd->Init.dma_enable == 1U) { - CLEAR_OUT_EP_INTR(epnum, (1 << 15)); + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } } } - if(hpcd->Init.dma_enable == 1) + if(hpcd->Init.dma_enable == 1U) { hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; } - HAL_PCD_DataOutStageCallback(hpcd, epnum); - if(hpcd->Init.dma_enable == 1) + if (gSNPSiD == USB_OTG_CORE_ID_310A) { - if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0)) + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } + else + { + HAL_PCD_DataOutStageCallback(hpcd, epnum); + } + } + else + { + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); + } + + if(hpcd->Init.dma_enable == 1U) + { + if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) { /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } } - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { - /* setup/out transaction management for Core ID >= 310A */ - if (hpcd->Init.dma_enable == 1) + if (gSNPSiD == USB_OTG_CORE_ID_310A) { - if (USBx_OUTEP(0)->DOEPINT & (1 << 15)) + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) { - CLEAR_OUT_EP_INTR(epnum, (1 << 15)); + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } + } + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + /* setup/out transaction management for Core ID >= 310A */ + if (hpcd->Init.dma_enable == 1U) + { + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } } } @@ -402,14 +442,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + +#ifdef USB_OTG_DOEPINT_OTEPSPR /* Clear Status Phase Received interrupt */ if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } +#endif /* USB_OTG_DOEPINT_OTEPSPR */ } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } @@ -418,61 +461,61 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - epnum = 0; + epnum = 0U; - while ( ep_intr ) + while (ep_intr != 0U) { - if (ep_intr & 0x1) /* In ITR */ + if ((ep_intr & 0x1U) != 0U) /* In ITR */ { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = (uint32_t)(0x1UL << (epnum & 0xFU)); USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; } - HAL_PCD_DataInStageCallback(hpcd, epnum); + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) { /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { - PCD_WriteEmptyTxFifo(hpcd , epnum); + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } @@ -491,6 +534,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { HAL_PCD_ResumeCallback(hpcd); } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } @@ -512,7 +556,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if( hpcd->LPM_State == LPM_L0) { hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); } else @@ -525,26 +569,29 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance, 0x10); + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { - USBx_INEP(i)->DIEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; + USBx_DEVICE->DAINTMSK |= 0x10001U; - if(hpcd->Init.use_dedicated_ep1) + if (hpcd->Init.use_dedicated_ep1 != 0U) { USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } else { +#ifdef USB_OTG_DOEPINT_OTEPSPR USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); +#else + USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); +#endif /* USB_OTG_DOEPINT_OTEPSPR */ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } @@ -552,7 +599,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } @@ -560,19 +607,19 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Enumeration done Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { - USB_ActivateSetup(hpcd->Instance); + (void)USB_ActivateSetup(hpcd->Instance); hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH) { hpcd->Init.speed = USB_OTG_SPEED_HIGH; - hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE; + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT); } else { hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; + hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE; /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response @@ -582,64 +629,64 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); - if((hclk >= 14200000)&&(hclk < 15000000)) + if((hclk >= 14200000U) && (hclk < 15000000U)) { /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 15000000)&&(hclk < 16000000)) + else if((hclk >= 15000000U) && (hclk < 16000000U)) { /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 16000000)&&(hclk < 17200000)) + else if((hclk >= 16000000U) && (hclk < 17200000U)) { /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 17200000)&&(hclk < 18500000)) + else if((hclk >= 17200000U) && (hclk < 18500000U)) { /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 18500000)&&(hclk < 20000000)) + else if((hclk >= 18500000U) && (hclk < 20000000U)) { /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 20000000)&&(hclk < 21800000)) + else if((hclk >= 20000000U) && (hclk < 21800000U)) { /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 21800000)&&(hclk < 24000000)) + else if((hclk >= 21800000U) && (hclk < 24000000U)) { /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 24000000)&&(hclk < 27700000)) + else if((hclk >= 24000000U) && (hclk < 27700000U)) { /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 27700000)&&(hclk < 32000000)) + else if((hclk >= 27700000U) && (hclk < 32000000U)) { /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10) & USB_OTG_GUSBCFG_TRDT); } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10) & USB_OTG_GUSBCFG_TRDT); } } @@ -652,23 +699,29 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + temp = USBx->GRXSTSP; + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) + if((temp & USB_OTG_GRXSTSP_BCNT) != 0U) { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); + (void)USB_ReadPacket(USBx, ep->xfer_buff, (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; } + else + { + /* ... */ + } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -682,14 +735,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO IN Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } /* Handle Incomplete ISO OUT Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } @@ -713,6 +766,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } } +#endif /* USB_OTG_FS || USB_OTG_HS */ + /** * @brief Data OUT stage callback. @@ -720,42 +775,44 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataOutStageCallback could be implemented in the user file */ } /** - * @brief Data IN stage callback. + * @brief Data IN stage callback * @param hpcd PCD handle * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataInStageCallback could be implemented in the user file */ } /** - * @brief Setup stage callback. + * @brief Setup stage callback * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SetupStageCallback could be implemented in the user file */ } @@ -765,12 +822,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SOFCallback could be implemented in the user file */ } @@ -780,12 +837,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResetCallback could be implemented in the user file */ } @@ -795,12 +852,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SuspendCallback could be implemented in the user file */ } @@ -810,12 +867,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResumeCallback could be implemented in the user file */ } @@ -826,28 +883,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file */ } /** - * @brief Incomplete ISO IN callback. + * @brief Incomplete ISO IN callback. * @param hpcd PCD handle * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file */ } @@ -857,12 +916,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ConnectCallback could be implemented in the user file */ } @@ -872,12 +931,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DisconnectCallback could be implemented in the user file */ } @@ -902,14 +961,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) */ /** - * @brief Connect the USB device. + * @brief Connect the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -922,7 +981,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); + (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -936,7 +995,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { __HAL_LOCK(hpcd); - USB_SetDevAddress(hpcd->Instance, address); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -951,39 +1011,41 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - ep->is_in = (0x80 & ep_addr) != 0; + ep->num = ep_addr & 0xFU; ep->maxpacket = ep_mps; ep->type = ep_type; - if (ep->is_in) + + if (ep->is_in != 0U) { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } /* Set initial data PID. */ - if (ep_type == EP_TYPE_BULK ) + if (ep_type == EP_TYPE_BULK) { - ep->data_pid_start = 0; + ep->data_pid_start = 0U; } __HAL_LOCK(hpcd); - USB_ActivateEndpoint(hpcd->Instance , ep); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); __HAL_UNLOCK(hpcd); + return ret; } - /** * @brief Deactivate an endpoint. * @param hpcd PCD handle @@ -992,22 +1054,22 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; + ep->num = ep_addr & 0xFU; __HAL_LOCK(hpcd); - USB_DeactivateEndpoint(hpcd->Instance , ep); + (void)USB_DeactivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -1023,46 +1085,46 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0xFU; - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & 0x7F) == 0) + if ((ep_addr & 0xFU) == 0U) { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } return HAL_OK; } /** - * @brief Get Received Data Size. + * @brief Get Received Data Size * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0xF].xfer_count; + return (uint16_t)hpcd->OUT_ep[ep_addr & 0xFU].xfer_count; } /** - * @brief Send an amount of data. + * @brief Send an amount of data * @param hpcd PCD handle * @param ep_addr endpoint address * @param pBuf pointer to the transmission buffer @@ -1071,68 +1133,69 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0xFU; - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & 0x7F) == 0) + if ((ep_addr & 0xFU) == 0U) { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } return HAL_OK; } /** - * @brief Set a STALL condition over an endpoint. + * @brief Set a STALL condition over an endpoint * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints) + if (((uint32_t)ep_addr & 0xFU) > hpcd->Init.dev_endpoints) { return HAL_ERROR; } - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; } - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - + ep->is_stall = 1U; + ep->num = ep_addr & 0xFU; __HAL_LOCK(hpcd); - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) + + (void)USB_EPSetStall(hpcd->Instance, ep); + if((ep_addr & 0xFU) == 0U) { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } __HAL_UNLOCK(hpcd); @@ -1140,42 +1203,43 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief Clear a STALL condition over in an endpoint. + * @brief Clear a STALL condition over in an endpoint * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints) + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) { return HAL_ERROR; } - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr]; + ep = &hpcd->OUT_ep[ep_addr &0xFU]; + ep->is_in = 0U; } - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 0U; + ep->num = ep_addr & 0xFU; __HAL_LOCK(hpcd); - USB_EPClearStall(hpcd->Instance , ep); + (void)USB_EPClearStall(hpcd->Instance, ep); __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Flush an endpoint. + * @brief Flush an endpoint * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status @@ -1184,13 +1248,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { __HAL_LOCK(hpcd); - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & 0xFU); } else { - USB_FlushRxFifo(hpcd->Instance); + (void)USB_FlushRxFifo(hpcd->Instance); } __HAL_UNLOCK(hpcd); @@ -1199,20 +1263,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief Activate remote wakeup signalling. + * @brief Activate remote wakeup signalling * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* Activate Remote wakeup signaling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - return HAL_OK; + return(USB_ActivateRemoteWakeup(hpcd->Instance)); } /** @@ -1222,12 +1279,9 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - /* De-activate Remote wakeup signaling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - return HAL_OK; + return(USB_DeActivateRemoteWakeup(hpcd->Instance)); } + /** * @} */ @@ -1256,6 +1310,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) { return hpcd->State; } + /** * @} */ @@ -1268,20 +1323,21 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) /** @addtogroup PCD_Private_Functions * @{ */ - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Check FIFO for the next packet to be loaded. * @param hpcd PCD handle - * @param epnum endpoint number + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; USB_OTG_EPTypeDef *ep; - int32_t len = 0; + uint32_t len; uint32_t len32b; - uint32_t fifoemptymsk = 0; + uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; len = ep->xfer_len - ep->xfer_count; @@ -1291,12 +1347,10 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t len = ep->maxpacket; } + len32b = (len + 3U) / 4U; - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; @@ -1305,29 +1359,31 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t { len = ep->maxpacket; } - len32b = (len + 3) / 4; + len32b = (len + 3U) / 4U; - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, (uint8_t)hpcd->Init.dma_enable); ep->xfer_buff += len; ep->xfer_count += len; } - if(len <= 0) + if(len <= 0U) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = (uint32_t)(0x1UL << epnum); USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - } return HAL_OK; } +#endif /* USB_OTG_FS || USB_OTG_HS */ + /** * @} */ #endif /* HAL_PCD_MODULE_ENABLED */ + /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c index 1e00bba36b..cee1bb0583 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Extended features functions * @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -48,6 +48,7 @@ * @brief PCD Extended HAL module driver * @{ */ + #ifdef HAL_PCD_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ @@ -62,19 +63,19 @@ */ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions + * @brief PCDEx control functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Update FIFO configuration @endverbatim * @{ */ - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Set Tx FIFO * @param hpcd PCD handle @@ -84,37 +85,37 @@ */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { - uint8_t i = 0; - uint32_t Tx_Offset = 0; + uint8_t i; + uint32_t Tx_Offset; /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: + When a TxFIFO is not used, the Configuration should be as follows: case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) --> Txm can use the space allocated for Txn. case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top + The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - + Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) + + if(fifo == 0U) { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (i = 0; i < (fifo - 1); i++) + for (i = 0U; i < (fifo - 1U); i++) { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); } - + /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; } - + return HAL_OK; } @@ -127,144 +128,62 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { hpcd->Instance->GRXFSIZ = size; - + return HAL_OK; } /** - * @brief Activate LPM Feature + * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; hpcd->LPM_State = LPM_L0; USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; + + return HAL_OK; } /** - * @brief DeActivate LPM feature. + * @brief Deactivate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} -#if defined (USB_OTG_GCCFG_BCDEN) -/** - * @brief Handle BatteryCharging Process. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Start BCD When device is connected */ - if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) - { - /* Enable DCD : Data Contact Detect */ - USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } - } - - /* Right response got */ - HAL_Delay(100); - - /* Check Detect flag*/ - if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - - /*Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(100); - - if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) - { - /* Case of Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } - else - { - /* start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(100); - - if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) - { - /* case Dedicated Charging Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* case Charging Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - } - } - /* Battery Charging capability discovery finished */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); - } + return HAL_OK; } +#endif /* USB_OTG_FS || USB_OTG_HS */ + /** - * @brief Activate BatteryCharging feature. + * @brief Send LPM message to user layer callback. * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); - hpcd->battery_charging_active = ENABLE; - USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); - - return HAL_OK; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ } -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); - return HAL_OK; -} - - /** * @brief Send BatteryCharging message to user layer callback. * @param hpcd PCD handle @@ -279,25 +198,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ -} - -#endif /* USB_OTG_GCCFG_BCDEN */ -/** - * @brief Send LPM message to user layer callback. - * @param hpcd PCD handle - * @param msg LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ + */ } /** @@ -309,6 +210,7 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m */ #endif /* HAL_PCD_MODULE_ENABLED */ + /** * @} */ diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c index 407609bd9c..6b7a153e56 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c @@ -3,10 +3,10 @@ * @file stm32f7xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -84,37 +84,38 @@ * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - [..] + [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register will be set to their reset values. - + @endverbatim * @{ */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \ + defined (STM32F750xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * * @retval HAL status @@ -126,88 +127,88 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t tmpreg1 = 0; uint32_t plli2sused = 0; uint32_t pllsaiused = 0; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - + /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } } - + /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - + /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - + /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - plli2sused = 1; - } - + { + plli2sused = 1; + } + /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) { @@ -237,8 +238,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -256,47 +257,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - + /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } - + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - + /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } - + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - + /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } - + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - + /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } - + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - + /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); } @@ -306,7 +307,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - + /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } @@ -316,7 +317,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - + /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } @@ -326,7 +327,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - + /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } @@ -336,7 +337,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - + /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } @@ -346,7 +347,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - + /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } @@ -356,7 +357,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - + /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); } @@ -366,7 +367,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - + /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); } @@ -376,76 +377,76 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - + /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); } - + /*--------------------------------------- CEC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - + /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } - + /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) { - pllsaiused = 1; + pllsaiused = 1; } } /*-------------------------------------- LTDC Configuration -----------------------------------*/ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { - pllsaiused = 1; + pllsaiused = 1; } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } - + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - + /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); } - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - + /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); } - + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) { @@ -455,7 +456,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); } - + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) { @@ -464,38 +465,38 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the DFSDM interface clock source */ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } + } #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - + __HAL_RCC_PLLI2S_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); @@ -504,35 +505,35 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); @@ -540,9 +541,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ @@ -554,11 +555,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -567,19 +568,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - } - + } + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) { /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - + __HAL_RCC_PLLSAI_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -587,16 +588,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } - + } + /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -604,7 +605,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); @@ -612,13 +613,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) { /* check for Parameters */ @@ -626,37 +627,37 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - + /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); - } + } -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); - - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -664,8 +665,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } @@ -682,9 +683,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg = 0; - + /* Set all possible values for the extended clock type parameter------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ @@ -697,7 +698,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; -#else +#else PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ @@ -709,20 +710,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48; -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); @@ -730,76 +731,76 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the SAI1 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - + /* Get the SAI2 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - + /* Get the I2S clock configuration ------------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - + /* Get the I2C1 clock configuration ------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - + /* Get the I2C2 clock configuration ------------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - + /* Get the I2C3 clock configuration ------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - + /* Get the I2C4 clock configuration ------------------------------------------*/ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); - + /* Get the USART1 clock configuration ------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - + /* Get the USART2 clock configuration ------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - + /* Get the USART3 clock configuration ------------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - + /* Get the UART4 clock configuration ------------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - + /* Get the UART5 clock configuration ------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - + /* Get the USART6 clock configuration ------------------------------------------*/ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - + /* Get the UART7 clock configuration ------------------------------------------*/ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - + /* Get the UART8 clock configuration ------------------------------------------*/ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - + /* Get the LPTIM1 clock configuration ------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - + /* Get the CEC clock configuration -----------------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - + /* Get the CK48 clock configuration -----------------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); /* Get the SDMMC1 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /* Get the SDMMC2 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - + /* Get the DFSDM clock configuration -----------------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the TIM Prescaler configuration --------------------------------------------*/ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) { @@ -810,19 +811,19 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } } -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * * @retval HAL status @@ -833,82 +834,82 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t tmpreg0 = 0; uint32_t plli2sused = 0; uint32_t pllsaiused = 0; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - + /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } } - + /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - + /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - + /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) { @@ -938,8 +939,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -957,37 +958,37 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - + /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } - + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - + /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } - + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - + /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } - + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - + /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } @@ -997,7 +998,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - + /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } @@ -1007,7 +1008,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - + /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } @@ -1017,7 +1018,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - + /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } @@ -1027,7 +1028,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - + /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } @@ -1037,7 +1038,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - + /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } @@ -1047,7 +1048,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - + /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); } @@ -1057,7 +1058,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - + /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); } @@ -1067,86 +1068,86 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - + /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); } - + /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } - + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - + /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); } - + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - + /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); } - + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - + __HAL_RCC_PLLI2S_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Configure the PLLI2S division factors */ @@ -1154,29 +1155,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ @@ -1186,11 +1187,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -1199,19 +1200,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - } - + } + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) { /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - + __HAL_RCC_PLLSAI_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -1219,16 +1220,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } - + } + /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -1236,27 +1237,27 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - + /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ @@ -1265,7 +1266,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -1273,8 +1274,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } @@ -1291,7 +1292,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg = 0; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ @@ -1303,79 +1304,79 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; - + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); /* Get the SAI1 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - + /* Get the SAI2 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - + /* Get the I2S clock configuration ------------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - + /* Get the I2C1 clock configuration ------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - + /* Get the I2C2 clock configuration ------------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - + /* Get the I2C3 clock configuration ------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - + /* Get the USART1 clock configuration ------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - + /* Get the USART2 clock configuration ------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - + /* Get the USART3 clock configuration ------------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - + /* Get the UART4 clock configuration ------------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - + /* Get the UART5 clock configuration ------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - + /* Get the USART6 clock configuration ------------------------------------------*/ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - + /* Get the UART7 clock configuration ------------------------------------------*/ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - + /* Get the UART8 clock configuration ------------------------------------------*/ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - + /* Get the LPTIM1 clock configuration ------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - + /* Get the CK48 clock configuration -----------------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); /* Get the SDMMC1 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - + /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the TIM Prescaler configuration --------------------------------------------*/ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) { @@ -1386,10 +1387,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } } -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: @@ -1406,17 +1407,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) uint32_t vcoinput = 0; /* This variable is used to store the SAI clock source */ uint32_t saiclocksource = 0; - + if (PeriphClk == RCC_PERIPHCLK_SAI1) { - saiclocksource = RCC->DCKCFGR1; + saiclocksource = RCC->DCKCFGR1; saiclocksource &= RCC_DCKCFGR1_SAI1SEL; switch (saiclocksource) { - case 0: /* PLLSAI is the clock source for SAI1 */ + case 0: /* PLLSAI is the clock source for SAI1 */ { /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1426,21 +1427,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } + } /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; + frequency = frequency/(tmpreg); + break; } case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ - { + { /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1451,23 +1452,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); frequency = frequency/(tmpreg); break; } case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; - break; + break; } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ { if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) @@ -1480,26 +1481,26 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the main PLL Source is HSE */ frequency = HSE_VALUE; } - break; + break; } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; } } } - + if (PeriphClk == RCC_PERIPHCLK_SAI2) { - saiclocksource = RCC->DCKCFGR1; + saiclocksource = RCC->DCKCFGR1; saiclocksource &= RCC_DCKCFGR1_SAI2SEL; switch (saiclocksource) { - case 0: /* PLLSAI is the clock source for SAI*/ + case 0: /* PLLSAI is the clock source for SAI*/ { /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1509,21 +1510,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } + } /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; + frequency = frequency/(tmpreg); + break; } case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ - { + { /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1534,21 +1535,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); frequency = frequency/(tmpreg); break; } case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ { frequency = EXTERNAL_CLOCK_VALUE; - break; + break; } #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ @@ -1563,16 +1564,16 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the main PLL Source is HSE */ frequency = HSE_VALUE; } - break; + break; } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; } } } - + return frequency; } @@ -1583,12 +1584,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * -@verbatim +@verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the + This subsection provides a set of functions allowing to control the activation or deactivation of PLLI2S, PLLSAI. @endverbatim * @{ @@ -1627,7 +1628,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) } /* Configure the PLLI2S division factors */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ @@ -1638,7 +1639,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); @@ -1715,7 +1716,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) } /* Configure the PLLSAI division factors */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ @@ -1727,7 +1728,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /* Enable the PLLSAI */ __HAL_RCC_PLLSAI_ENABLE(); diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c index 87bd84a4b9..b75c656a23 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c +++ b/bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c @@ -68,6 +68,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); #ifdef USB_HS_PHYC @@ -75,18 +76,17 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); #endif /* Exported functions --------------------------------------------------------*/ -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions * @{ */ -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== - ##### Initialization/de-initialization functions ##### + ##### Initialization/de-initialization functions ##### =============================================================================== - [..] This section provides functions allowing to: @endverbatim * @{ @@ -95,7 +95,7 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); /** * @brief Initializes the USB Core * @param USBx USB Instance - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -103,7 +103,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { if (cfg.phy_itface == USB_OTG_ULPI_PHY) { - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); /* Init The ULPI Interface */ @@ -111,15 +110,14 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); - if(cfg.use_external_vbus == 1) + if(cfg.use_external_vbus == 1U) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; } /* Reset after a PHY select */ - USB_CoreReset(USBx); + (void)USB_CoreReset(USBx); } #ifdef USB_HS_PHYC - else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -152,13 +150,13 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); + (void)USB_CoreReset(USBx); /* Deactivate the power down*/ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; } - if(cfg.dma_enable == ENABLE) + if(cfg.dma_enable == 1U) { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; @@ -179,7 +177,6 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) return HAL_OK; } - /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg @@ -197,24 +194,28 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @param mode current core mode * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_HOST_MODE: Host mode + * @arg USB_DRD_MODE: Dual Role Device mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode) { USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - if ( mode == USB_OTG_HOST_MODE) + if (mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; } - else if ( mode == USB_OTG_DEVICE_MODE) + else if (mode == USB_DEVICE_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } - HAL_Delay(50); + else + { + return HAL_ERROR; + } + HAL_Delay(50U); return HAL_OK; } @@ -229,15 +230,21 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT */ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - uint32_t i = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } /*Activate VBUS Sensing B */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - if (cfg.vbus_sensing_enable == 0) + if (cfg.vbus_sensing_enable == 0U) { /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; /* B-peripheral session valid override enable*/ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; @@ -245,120 +252,133 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; + USBx_PCGCCTL = 0U; /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - if(cfg.phy_itface == USB_OTG_ULPI_PHY) + if(cfg.phy_itface == USB_OTG_ULPI_PHY) { if(cfg.speed == USB_OTG_SPEED_HIGH) { /* Set High speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH); } else { /* set High speed phy in Full speed mode */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL); } } - - else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { if(cfg.speed == USB_OTG_SPEED_HIGH) { /* Set High speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH); } else { /* set High speed phy in Full speed mode */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL); } } - else { /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_FULL); } /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; - for (i = 0; i < cfg.dev_endpoints; i++) + for (i = 0U; i < cfg.dev_endpoints; i++) { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) { - USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } } else { - USBx_INEP(i)->DIEPCTL = 0; + USBx_INEP(i)->DIEPCTL = 0U; } - USBx_INEP(i)->DIEPTSIZ = 0; - USBx_INEP(i)->DIEPINT = 0xFF; + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; } - for (i = 0; i < cfg.dev_endpoints; i++) + for (i = 0U; i < cfg.dev_endpoints; i++) { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) { - USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } } else { - USBx_OUTEP(i)->DOEPCTL = 0; + USBx_OUTEP(i)->DOEPCTL = 0U; } - USBx_OUTEP(i)->DOEPTSIZ = 0; - USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - if (cfg.dma_enable == 1) + if (cfg.dma_enable == 1U) { /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); + USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 | + USB_OTG_DTHRCTL_RXTHRLEN_6; - i= USBx_DEVICE->DTHRCTL; + USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN | + USB_OTG_DTHRCTL_ISOTHREN | + USB_OTG_DTHRCTL_NONISOTHREN; } /* Disable all interrupts. */ - USBx->GINTMSK = 0; + USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; + USBx->GINTSTS = 0xBFFFFFFFU; /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) + if (cfg.dma_enable == 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; } /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM| + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; - if(cfg.Sof_enable) + if(cfg.Sof_enable != 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - if (cfg.vbus_sensing_enable == ENABLE) + if (cfg.vbus_sensing_enable == 1U) { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); } @@ -366,7 +386,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c return HAL_OK; } - /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO * @param USBx Selected device @@ -375,15 +394,15 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) +HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0; + uint32_t count = 0U; - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } @@ -393,7 +412,6 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) return HAL_OK; } - /** * @brief USB_FlushRxFifo : Flush Rx FIFO * @param USBx Selected device @@ -407,7 +425,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } @@ -431,6 +449,8 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_DEVICE->DCFG |= speed; return HAL_OK; } @@ -446,21 +466,27 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { - uint8_t speed = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + if(DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { speed = USB_OTG_SPEED_HIGH; } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USB_OTG_SPEED_FULL; } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + else if (DevEnumSpeed == DSTS_ENUMSPD_LS_PHY_6MHZ) { speed = USB_OTG_SPEED_LOW; } + else + { + speed = 0U; + } return speed; } @@ -473,29 +499,36 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)); - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; } - } else { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16); - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; } + /** * @brief Activate and configure a dedicated endpoint * @param USBx Selected device @@ -504,41 +537,37 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - static __IO uint32_t debug = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; } - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)); } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; } - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16); } return HAL_OK; } + /** * @brief De-activate and de-initialize an endpoint * @param USBx Selected device @@ -547,19 +576,30 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); } else { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); } + return HAL_OK; } @@ -571,17 +611,21 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); } + return HAL_OK; } @@ -597,17 +641,19 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) { - uint16_t pktcnt = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -616,52 +662,52 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); if (ep->type == EP_TYPE_ISOC) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); } } - if (dma == 1) + if (dma == 1U) { - USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); } else { if (ep->type != EP_TYPE_ISOC) { /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) + if (ep->xfer_len > 0U) { - USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU); } } } if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } else { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } } /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); if (ep->type == EP_TYPE_ISOC) { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); } } else /* OUT endpoint */ @@ -670,40 +716,41 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); } - if (dma == 1) + if (dma == 1U) { - USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff; + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)ep->xfer_buff; } if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; } else { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; } } /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } @@ -719,15 +766,18 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe */ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -736,33 +786,32 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); if(ep->xfer_len > ep->maxpacket) { ep->xfer_len = ep->maxpacket; } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); } - if (dma == 1) + if (dma == 1U) { - USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); } else { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) { - USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num); + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU); } } /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -770,26 +819,26 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len > 0) + if (ep->xfer_len > 0U) { ep->xfer_len = ep->maxpacket; } - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - - if (dma == 1) + if (dma == 1U) { - USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff); + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); } /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } @@ -808,16 +857,20 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD */ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { - uint32_t count32b= 0 , i= 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; - if (dma == 0) + if (dma == 0U) { - count32b = (len + 3) / 4; - for (i = 0; i < count32b; i++, src += 4) + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); + USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc); + pSrc++; } } + return HAL_OK; } @@ -825,8 +878,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx Selected device - * @param src source pointer - * @param ch_ep_num endpoint or host channel number + * @param dest source pointer * @param len Number of bytes to read * @param dma USB dma enabled or disabled * This parameter can be one of these values: @@ -836,15 +888,18 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; - for ( i = 0; i < count32b; i++, dest += 4 ) + for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - + *(__packed uint32_t *)pDest = USBx_DFIFO(0U); + pDest++; } - return ((void *)dest); + + return ((void *)pDest); } /** @@ -855,26 +910,29 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; } + return HAL_OK; } - /** * @brief USB_EPClearStall : Clear a stall condition over an EP * @param USBx Selected device @@ -883,20 +941,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ } } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ } } return HAL_OK; @@ -909,24 +970,24 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; /* Clear Pending interrupt */ - for (i = 0; i < 15 ; i++) + for (i = 0U; i < 15U; i++) { - USBx_INEP(i)->DIEPINT = 0xFF; - USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); + (void)USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx , 0x10U); return HAL_OK; } @@ -940,8 +1001,10 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; return HAL_OK; } @@ -953,8 +1016,10 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre */ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + HAL_Delay(3U); return HAL_OK; } @@ -966,8 +1031,10 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + HAL_Delay(3U); return HAL_OK; } @@ -979,11 +1046,12 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) { - uint32_t v = 0; + uint32_t tmpreg; - v = USBx->GINTSTS; - v &= USBx->GINTMSK; - return v; + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; } /** @@ -993,10 +1061,13 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) { - uint32_t v; - v = USBx_DEVICE->DAINT; - v &= USBx_DEVICE->DAINTMSK; - return ((v & 0xffff0000) >> 16); + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); } /** @@ -1006,10 +1077,13 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) { - uint32_t v; - v = USBx_DEVICE->DAINT; - v &= USBx_DEVICE->DAINTMSK; - return ((v & 0xFFFF)); + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); } /** @@ -1021,10 +1095,13 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { - uint32_t v; - v = USBx_OUTEP(epnum)->DOEPINT; - v &= USBx_DEVICE->DOEPMSK; - return v; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; } /** @@ -1036,13 +1113,15 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) */ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { - uint32_t v, msk, emp; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - v = USBx_INEP(epnum)->DIEPINT & msk; - return v; + msk |= ((emp >> (epnum & 0xFU)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; } /** @@ -1066,10 +1145,9 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { - return ((USBx->GINTSTS ) & 0x1); + return ((USBx->GINTSTS ) & 0x1U); } - /** * @brief Activate EP0 for Setup transactions * @param USBx Selected device @@ -1077,19 +1155,20 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) { - USBx_INEP(0)->DIEPCTL |= 3; + USBx_INEP(0U)->DIEPCTL |= 3U; } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; } - /** * @brief Prepare the EP0 to start the first control setup * @param USBx Selected device @@ -1102,22 +1181,23 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) { - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + uint32_t USBx_BASE = (uint32_t)USBx; - if (dma == 1) + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) { - USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup; + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; /* EP enable */ - USBx_OUTEP(0)->DOEPCTL = 0x80008000; + USBx_OUTEP(0U)->DOEPCTL = 0x80008000U; } return HAL_OK; } - /** * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device @@ -1125,25 +1205,25 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Core Soft Reset */ - count = 0; + count = 0U; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } @@ -1162,7 +1242,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) */ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + uint32_t count = 0U; /* Enable LDO */ USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; @@ -1170,37 +1250,36 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) /* wait for LDO Ready */ while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET) { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } /* Controls PHY frequency operation selection */ - if (HSE_VALUE == 12000000) /* HSE = 12MHz */ + if (HSE_VALUE == 12000000U) /* HSE = 12MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x0 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); } - else if (HSE_VALUE == 12500000) /* HSE = 12.5MHz */ + else if (HSE_VALUE == 12500000U) /* HSE = 12.5MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x2 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); } - else if (HSE_VALUE == 16000000) /* HSE = 16MHz */ + else if (HSE_VALUE == 16000000U) /* HSE = 16MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x3 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); } - - else if (HSE_VALUE == 24000000) /* HSE = 24MHz */ + else if (HSE_VALUE == 24000000U) /* HSE = 24MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x4 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); } - else if (HSE_VALUE == 25000000) /* HSE = 25MHz */ + else if (HSE_VALUE == 25000000U) /* HSE = 25MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x5 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); } - else if (HSE_VALUE == 32000000) /* HSE = 32MHz */ + else if (HSE_VALUE == 32000000U) /* HSE = 32MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x7 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); } /* Control the tuning interface of the High Speed PHY */ @@ -1226,17 +1305,17 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; + USBx_PCGCCTL = 0U; - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) + if ((cfg.speed == USB_OTG_SPEED_FULL) && (USBx != USB_OTG_FS)) { USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; } @@ -1246,51 +1325,51 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef } /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); /* Clear all pending HC Interrupts */ - for (i = 0; i < cfg.Host_channels; i++) + for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(i)->HCINT = 0xFFFFFFFF; - USBx_HC(i)->HCINTMSK = 0; + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; } /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); + (void)USB_DriveVbus(USBx, 1U); - HAL_Delay(200); + HAL_Delay(200U); /* Disable all interrupts. */ - USBx->GINTMSK = 0; + USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; + USBx->GINTSTS = 0xFFFFFFFFU; if(USBx == USB_OTG_FS) { /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); } else { /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x200; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200); - USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300); + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) + if (cfg.dma_enable == 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; } /* Enable interrupts matching to the Host mode ONLY */ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT|\ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); return HAL_OK; @@ -1308,17 +1387,24 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef */ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); + uint32_t USBx_BASE = (uint32_t)USBx; - if (freq == HCFG_48_MHZ) + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) { - USBx_HOST->HFIR = (uint32_t)48000; + USBx_HOST->HFIR = 48000U; } - else if (freq == HCFG_6_MHZ) + else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = (uint32_t)6000; + USBx_HOST->HFIR = 6000U; } + else + { + /* ... */ + } + return HAL_OK; } @@ -1326,12 +1412,14 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq * @brief USB_OTG_ResetPort : Reset Host Port * @param USBx Selected device * @retval HAL status - * @note : (1)The application must wait at least 10 ms + * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0; + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; hprt0 = USBx_HPRT0; @@ -1339,9 +1427,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (100); /* See Note #1 */ + HAL_Delay (100U); /* See Note #1 */ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - HAL_Delay (10); + HAL_Delay (10U); return HAL_OK; } @@ -1356,18 +1444,19 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) { - __IO uint32_t hprt0; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; hprt0 = USBx_HPRT0; hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) { USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) { USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); } @@ -1385,7 +1474,8 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) */ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); @@ -1398,6 +1488,8 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } @@ -1433,86 +1525,107 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ep_type, uint16_t mps) { + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; /* Enable channel interrupts required for this transfer. */ switch (ep_type) { case EP_TYPE_CTRL: case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) + if ((epnum & 0x80U) == 0x80U) { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } else { if(USBx != USB_OTG_FS) { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); } } break; case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + if ((epnum & 0x80U) == 0x80U) { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } break; + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + if ((epnum & 0x80U) == 0x80U) { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); } break; + + default: + ret = HAL_ERROR; + break; } /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); /* Make sure host channel interrupts are enabled. */ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); + if((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if(speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; if (ep_type == EP_TYPE_INTR) { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; } - return HAL_OK; + return ret; } /** @@ -1527,67 +1640,73 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, */ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) { - static __IO uint32_t tmpreg = 0; - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH)) { - if((dma == 0) && (hc->do_ping == 1)) + if((dma == 0U) && (hc->do_ping == 1U)) { - USB_DoPing(USBx, hc->ch_num); + (void)USB_DoPing(USBx, hc->ch_num); return HAL_OK; } - else if(dma == 1) + else if(dma == 1U) { - USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); - hc->do_ping = 0; + USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + hc->do_ping = 0U; + } + else + { + /* ... */ } } /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) + if (hc->xfer_len > 0U) { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } } else { - num_packets = 1; + num_packets = 1U; } - if (hc->ep_is_in) + if (hc->ep_is_in != 0U) { - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); - if (dma) + if (dma != 0U) { /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; } - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; /* make sure to set the correct ep direction */ - if (hc->ep_is_in) + if (hc->ep_is_in != 0U) { tmpreg |= USB_OTG_HCCHAR_EPDIR; } @@ -1596,11 +1715,11 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe tmpreg &= ~USB_OTG_HCCHAR_EPDIR; } tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; - if (dma == 0) /* Slave mode */ + if (dma == 0U) /* Slave mode */ { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) + if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) { switch(hc->ep_type) { @@ -1608,21 +1727,22 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe case EP_TYPE_CTRL: case EP_TYPE_BULK: - len_words = (hc->xfer_len + 3) / 4; + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) + if(len_words > (USBx->HNPTXSTS & 0xFFFFU)) { /* need to process data in nptxfempty interrupt */ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; } break; + /* Periodic transfer */ case EP_TYPE_INTR: case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ + if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ { /* need to process data in ptxfempty interrupt */ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; @@ -1634,7 +1754,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe } /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); } } @@ -1648,7 +1768,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe */ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) { - return ((USBx_HOST->HAINT) & 0xFFFF); + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); } /** @@ -1660,54 +1782,56 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { - uint32_t count = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; /* Check for space in the request queue to issue the halt. */ - if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || - (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK))) + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx->HNPTXSTS & 0xFFFF) == 0) + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000) + if (++count > 1000U) { break; } } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000) + if (++count > 1000U) { break; } } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } @@ -1723,17 +1847,19 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) */ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) { - uint8_t num_packets = 1; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; return HAL_OK; } @@ -1745,21 +1871,22 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { - uint8_t i; - uint32_t count = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; uint32_t value; + uint32_t i; - USB_DisableGlobalInt(USBx); + + (void)USB_DisableGlobalInt(USBx); /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); /* Flush out any leftover queued requests. */ - for (i = 0; i <= 15; i++) + for (i = 0U; i <= 15U; i++) { - - value = USBx_HC(i)->HCCHAR ; + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; value &= ~USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; @@ -1767,18 +1894,17 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Halt all channels to put them into a known state. */ - for (i = 0; i <= 15; i++) + for (i = 0U; i <= 15U; i++) { - value = USBx_HC(i)->HCCHAR ; - + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; value |= USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; + do { - if (++count > 1000) + if (++count > 1000U) { break; } @@ -1787,11 +1913,51 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); + return HAL_OK; } + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined USB_OTG_FS || defined USB_OTG_HS */ + + +/** + * @} + */ /** * @} */