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rt-thread-official
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use rt_memcpy/rt_memset to replace memcpy/memset

This commit is contained in:
Meco Man 2022-11-17 12:07:20 -05:00 committed by Man, Jianting (Meco)
parent b9a9225c84
commit cf66a5bc63
5 changed files with 10 additions and 10 deletions
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4
bsp/imxrt/libraries/drivers/drv_can.c
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@ -181,12 +181,12 @@ static rt_err_t can_cfg(struct rt_can_device *can_dev, struct can_configure *cfg
#ifdef SOC_IMXRT1170_SERIES
flexcan_timing_config_t timing_config;
memset(&timing_config, 0, sizeof(flexcan_timing_config_t));
rt_memset(&timing_config, 0, sizeof(flexcan_timing_config_t));
if(FLEXCAN_CalculateImprovedTimingValues(can->base, config.baudRate, GetCanSrcFreq(can->base), &timing_config))
{
/* Update the improved timing configuration*/
memcpy(&(config.timingConfig), &timing_config, sizeof(flexcan_timing_config_t));
rt_memcpy(&(config.timingConfig), &timing_config, sizeof(flexcan_timing_config_t));
}
else
{

8
bsp/imxrt/libraries/drivers/drv_eth.c
View File

@ -703,7 +703,7 @@ static status_t _ENET_SendFrame(ENET_Type *base,
if (sizeleft > handle->txBuffSizeAlign[ringId])
{
/* Data copy. */
(void)memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src,
(void)rt_memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src,
handle->txBuffSizeAlign[ringId]);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
if (handle->txMaintainEnable[ringId])
@ -733,7 +733,7 @@ static status_t _ENET_SendFrame(ENET_Type *base,
}
else
{
(void)memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src, sizeleft);
(void)rt_memcpy((void *)(uint32_t *)address, (void *)(uint32_t *)src, sizeleft);
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
if (handle->txMaintainEnable[ringId])
{
@ -893,7 +893,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
rt_memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
/* Data length update. */
curBuffDescrip->length = handle->txBuffSizeAlign[0];
len += handle->txBuffSizeAlign[0];
@ -910,7 +910,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui
#else
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data + len, sizeleft);
rt_memcpy((void *)address, data + len, sizeleft);
curBuffDescrip->length = sizeleft;
/* Set Last buffer wrap flag. */
curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;

2
bsp/imxrt/libraries/drivers/drv_flexspi.c
View File

@ -124,7 +124,7 @@ static void flexspi_test(void)
*(flexspi + 3) = send_buf[0];
LOG_D("FLEXSPI Memory 32 bit Write End\n");
memset(recv_buf, 0, sizeof(recv_buf));
rt_memset(recv_buf, 0, sizeof(recv_buf));
LOG_D("FLEXSPI Memory 32 bit Read Start\n");
recv_buf[2] = *(flexspi + 11);

2
bsp/imxrt/libraries/drivers/drv_sdio.c
View File

@ -174,7 +174,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
data = cmd->data;
memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
rt_memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
/* config adma */
dmaConfig.dmaMode = USDHC_DMA_MODE;
#if !(defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)

4
bsp/imxrt/libraries/drivers/drv_sdram.c
View File

@ -34,8 +34,8 @@ int rt_hw_sdram_init(void)
#endif
/* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t));
memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
rt_memset(&config, 0, sizeof(semc_config_t));
rt_memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
/* Initialize SEMC. */
SEMC_GetDefaultConfig(&config);