[bsp] code cleanup.
This commit is contained in:
parent
a9f03fb446
commit
cc3c4fe621
|
@ -11,8 +11,8 @@
|
|||
* Date Author Notes
|
||||
* 2009-01-05 Bernard the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
#include <shell.h>
|
||||
|
@ -23,11 +23,11 @@ extern int demo_init(void);
|
|||
|
||||
void rt_init_thread_entry(void* parameter)
|
||||
{
|
||||
/* initialization finsh shell Component */
|
||||
/* initialization finsh shell Component */
|
||||
finsh_system_init();
|
||||
|
||||
demo_init();
|
||||
|
||||
demo_init();
|
||||
|
||||
}
|
||||
|
||||
int rt_application_init()
|
||||
|
@ -39,7 +39,6 @@ int rt_application_init()
|
|||
2048, RT_THREAD_PRIORITY_MAX/3, 20);
|
||||
if (tid != RT_NULL)
|
||||
rt_thread_startup(tid);
|
||||
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -24,8 +24,6 @@
|
|||
#include <components.h>
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
|
@ -41,9 +39,6 @@ void SysTick_Handler(void)
|
|||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* This function will initial LPC54xx board.
|
||||
*/
|
||||
|
@ -58,7 +53,7 @@ void rt_hw_board_init()
|
|||
/* Set the Vector Table base location at 0x00000000 */
|
||||
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
SystemCoreClockUpdate();
|
||||
/* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
/* set pend exception priority */
|
||||
|
@ -68,29 +63,17 @@ void rt_hw_board_init()
|
|||
rt_hw_uart_init();
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
|
||||
#if LPC_EXT_SDRAM == 1
|
||||
lpc_sdram_hw_init();
|
||||
mpu_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
/* initialization board with RT-Thread Components */
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* initialization for system heap */
|
||||
int rt_hw_board_heap_init(void)
|
||||
{
|
||||
#ifdef RT_USING_HEAP
|
||||
#if LPC_EXT_SDRAM
|
||||
#include "drv_sram.h"
|
||||
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
|
||||
sram_init();
|
||||
#else
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -25,50 +25,50 @@ extern int rt_application_init(void);
|
|||
*/
|
||||
void rtthread_startup(void)
|
||||
{
|
||||
/* initialize board */
|
||||
rt_hw_board_init();
|
||||
/* initialize board */
|
||||
rt_hw_board_init();
|
||||
|
||||
/* show version */
|
||||
rt_show_version();
|
||||
/* show version */
|
||||
rt_show_version();
|
||||
|
||||
/* initialize tick */
|
||||
rt_system_tick_init();
|
||||
/* initialize tick */
|
||||
rt_system_tick_init();
|
||||
|
||||
/* initialize kernel object */
|
||||
rt_system_object_init();
|
||||
/* initialize kernel object */
|
||||
rt_system_object_init();
|
||||
|
||||
/* initialize timer system */
|
||||
rt_system_timer_init();
|
||||
/* initialize timer system */
|
||||
rt_system_timer_init();
|
||||
|
||||
/* initialize system heap */
|
||||
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
|
||||
|
||||
/* initialize scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
/* initialize scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
|
||||
/* initialize application */
|
||||
rt_application_init();
|
||||
/* initialize application */
|
||||
rt_application_init();
|
||||
|
||||
/* initialize timer thread */
|
||||
rt_system_timer_thread_init();
|
||||
|
||||
/* initialize idle thread */
|
||||
rt_thread_idle_init();
|
||||
/* initialize idle thread */
|
||||
rt_thread_idle_init();
|
||||
|
||||
/* start scheduler */
|
||||
rt_system_scheduler_start();
|
||||
/* start scheduler */
|
||||
rt_system_scheduler_start();
|
||||
|
||||
/* never reach here */
|
||||
return ;
|
||||
/* never reach here */
|
||||
return ;
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* disable interrupt first */
|
||||
rt_hw_interrupt_disable();
|
||||
/* disable interrupt first */
|
||||
rt_hw_interrupt_disable();
|
||||
|
||||
/* startup RT-Thread RTOS */
|
||||
rtthread_startup();
|
||||
/* startup RT-Thread RTOS */
|
||||
rtthread_startup();
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -5,42 +5,42 @@
|
|||
|
||||
struct led_ctrl
|
||||
{
|
||||
uint32_t num;
|
||||
uint32_t port;
|
||||
uint32_t num;
|
||||
uint32_t port;
|
||||
};
|
||||
|
||||
struct lpc_led
|
||||
{
|
||||
/* inherit from rt_device */
|
||||
struct rt_device parent;
|
||||
struct led_ctrl ctrl[LED_NUM];
|
||||
/* inherit from rt_device */
|
||||
struct rt_device parent;
|
||||
struct led_ctrl ctrl[LED_NUM];
|
||||
};
|
||||
|
||||
static struct lpc_led led;
|
||||
|
||||
static rt_err_t rt_led_init(rt_device_t dev)
|
||||
{
|
||||
/*led2 Blue:P0.31 ,led1 Green:P0.30 ,led0 Red:P0_29 P38,P32*/
|
||||
LPC_SYSCON->AHBCLKCTRLSET[0] = (1UL << 14); /* enable GPIO0 clock*/
|
||||
|
||||
LPC_SYSCON->PRESETCTRLSET[0] = (1UL << 14); /* Resets a GPIO0 peripheral */
|
||||
LPC_SYSCON->PRESETCTRLCLR[0] = (1UL << 14);
|
||||
|
||||
/* set P0.31, P0.30, P0.29 output. */
|
||||
LPC_GPIO->DIR[0] |= 0x07UL << 29;
|
||||
|
||||
/* turn off all the led */
|
||||
LPC_GPIO->SET[0] = 0x07UL << 29;
|
||||
|
||||
led.ctrl[0].num = 29;
|
||||
led.ctrl[0].port = 0;
|
||||
led.ctrl[1].num = 30;
|
||||
led.ctrl[1].port = 0;
|
||||
led.ctrl[2].num = 31;
|
||||
led.ctrl[2].port = 0;
|
||||
/*led2 Blue:P0.31 ,led1 Green:P0.30 ,led0 Red:P0_29 P38,P32*/
|
||||
LPC_SYSCON->AHBCLKCTRLSET[0] = (1UL << 14); /* enable GPIO0 clock*/
|
||||
|
||||
LPC_SYSCON->PRESETCTRLSET[0] = (1UL << 14); /* Resets a GPIO0 peripheral */
|
||||
LPC_SYSCON->PRESETCTRLCLR[0] = (1UL << 14);
|
||||
|
||||
/* set P0.31, P0.30, P0.29 output. */
|
||||
LPC_GPIO->DIR[0] |= 0x07UL << 29;
|
||||
|
||||
/* turn off all the led */
|
||||
LPC_GPIO->SET[0] = 0x07UL << 29;
|
||||
|
||||
led.ctrl[0].num = 29;
|
||||
led.ctrl[0].port = 0;
|
||||
led.ctrl[1].num = 30;
|
||||
led.ctrl[1].port = 0;
|
||||
led.ctrl[2].num = 31;
|
||||
led.ctrl[2].port = 0;
|
||||
|
||||
return RT_EOK;
|
||||
|
||||
return RT_EOK;
|
||||
|
||||
}
|
||||
|
||||
static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
|
@ -53,7 +53,6 @@ static rt_err_t rt_led_close(rt_device_t dev)
|
|||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
|
||||
rt_size_t size)
|
||||
{
|
||||
|
@ -66,22 +65,19 @@ static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
|
|||
|
||||
for (index = 0; index < nr; index++)
|
||||
{
|
||||
//if ((LPC_GPIO->PIN[led.ctrl[pos + index].port]) & 1 << led.ctrl[pos + index].num)
|
||||
if ((LPC_GPIO->B[0][led.ctrl[pos + index].num]))
|
||||
{
|
||||
*value = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
*value = 1;
|
||||
}
|
||||
value++;
|
||||
if ((LPC_GPIO->B[0][led.ctrl[pos + index].num]))
|
||||
{
|
||||
*value = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
*value = 1;
|
||||
}
|
||||
value++;
|
||||
}
|
||||
return index;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
|
||||
const void *buffer, rt_size_t size)
|
||||
{
|
||||
|
@ -93,21 +89,20 @@ static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
|
|||
RT_ASSERT((pos + size) <= LED_NUM);
|
||||
for (index = 0; index < nw; index++)
|
||||
{
|
||||
if (*value > 0)
|
||||
{
|
||||
//LPC_GPIO->CLR[led.ctrl[pos + index].port] |= (1 << led.ctrl[pos + index].num);
|
||||
LPC_GPIO->CLR[0] |= (1 << led.ctrl[pos + index].num);
|
||||
}
|
||||
else
|
||||
{
|
||||
//LPC_GPIO->SET[led.ctrl[pos + index].port] |= (1 << led.ctrl[pos + index].num);
|
||||
LPC_GPIO->SET[0] |= (1 << led.ctrl[pos + index].num);
|
||||
}
|
||||
}
|
||||
|
||||
return index;
|
||||
}
|
||||
if (*value > 0)
|
||||
{
|
||||
//LPC_GPIO->CLR[led.ctrl[pos + index].port] |= (1 << led.ctrl[pos + index].num);
|
||||
LPC_GPIO->CLR[0] |= (1 << led.ctrl[pos + index].num);
|
||||
}
|
||||
else
|
||||
{
|
||||
//LPC_GPIO->SET[led.ctrl[pos + index].port] |= (1 << led.ctrl[pos + index].num);
|
||||
LPC_GPIO->SET[0] |= (1 << led.ctrl[pos + index].num);
|
||||
}
|
||||
}
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static rt_err_t rt_led_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
|
@ -134,8 +129,6 @@ int rt_led_hw_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void Led_Control(rt_uint32_t Set_led, rt_uint32_t value)
|
||||
{
|
||||
if ( Set_led == 0 )
|
||||
|
@ -144,11 +137,11 @@ void Led_Control(rt_uint32_t Set_led, rt_uint32_t value)
|
|||
switch (value)
|
||||
{
|
||||
case 0:
|
||||
/* Light off */
|
||||
/* Light off */
|
||||
LPC_GPIO->B[0][led.ctrl[Set_led].num] = 1UL;
|
||||
break;
|
||||
case 1:
|
||||
/* Lights on */
|
||||
/* Lights on */
|
||||
LPC_GPIO->B[0][led.ctrl[Set_led].num] = 0UL;
|
||||
break;
|
||||
default:
|
||||
|
@ -162,28 +155,28 @@ void Led_Control(rt_uint32_t Set_led, rt_uint32_t value)
|
|||
switch (value)
|
||||
{
|
||||
case 0:
|
||||
/* Light off */
|
||||
/* Light off */
|
||||
LPC_GPIO->B[0][led.ctrl[Set_led].num] = 1UL;
|
||||
break;
|
||||
case 1:
|
||||
/* Lights on */
|
||||
/* Lights on */
|
||||
LPC_GPIO->B[0][led.ctrl[Set_led].num] = 0UL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ( Set_led == 2 )
|
||||
if ( Set_led == 2 )
|
||||
{
|
||||
/* set led status */
|
||||
switch (value)
|
||||
{
|
||||
case 0:
|
||||
/* Lights off */
|
||||
/* Lights off */
|
||||
LPC_GPIO->B[0][led.ctrl[Set_led].num] = 1UL;
|
||||
break;
|
||||
case 1:
|
||||
/* Lights on */
|
||||
/* Lights on */
|
||||
LPC_GPIO->B[0][led.ctrl[Set_led].num] = 0UL;
|
||||
break;
|
||||
default:
|
||||
|
@ -191,10 +184,8 @@ void Led_Control(rt_uint32_t Set_led, rt_uint32_t value)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
INIT_DEVICE_EXPORT(rt_led_hw_init);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
void led_test(rt_uint32_t led_num, rt_uint32_t value)
|
||||
|
@ -204,7 +195,3 @@ void led_test(rt_uint32_t led_num, rt_uint32_t value)
|
|||
}
|
||||
FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 100).)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -25,7 +25,6 @@ static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict);
|
|||
static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev);
|
||||
static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub);
|
||||
static void _UART_CalcMul(UART_BAUD_T *ub);
|
||||
|
||||
|
||||
struct lpc_uart
|
||||
{
|
||||
|
@ -33,16 +32,13 @@ struct lpc_uart
|
|||
IRQn_Type UART_IRQn;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct lpc_uart *uart;
|
||||
|
||||
UART_BAUD_T baud;
|
||||
UART_CFG_T UART_cfg;
|
||||
|
||||
|
||||
UART_BAUD_T baud;
|
||||
UART_CFG_T UART_cfg;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct lpc_uart *)serial->parent.user_data;
|
||||
|
||||
|
@ -52,38 +48,36 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
|
|||
* 1 Stop bit
|
||||
* None parity
|
||||
*/
|
||||
|
||||
/* Set up baudrate parameters */
|
||||
baud.clk = Chip_Clock_GetAsyncSyscon_ClockRate(); /* Clock frequency */
|
||||
baud.baud = cfg->baud_rate; /* Required baud rate */
|
||||
baud.ovr = 0; /* Set the oversampling to the recommended rate */
|
||||
baud.mul = baud.div = 0;
|
||||
|
||||
if(!baud.mul)
|
||||
{
|
||||
_UART_CalcMul(&baud);
|
||||
}
|
||||
_UART_CalcDiv(&baud);
|
||||
|
||||
/* Set fractional control register */
|
||||
LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) baud.mul << 8) | 0xFF;
|
||||
|
||||
/* Configure the UART */
|
||||
UART_cfg.cfg = UART_CFG_8BIT;
|
||||
UART_cfg.div = baud.div; /* Use the calculated div value */
|
||||
UART_cfg.ovr = baud.ovr; /* Use oversampling rate from baud */
|
||||
UART_cfg.res = UART_BIT_DLY(cfg->baud_rate);
|
||||
|
||||
/* P254,255,246 */
|
||||
uart->UART->OSR = (UART_cfg.ovr - 1) & 0x0F;
|
||||
uart->UART->BRG = (UART_cfg.div - 1) & 0xFFFF;
|
||||
uart->UART->CFG = UART_CFG_ENABLE | (UART_cfg.cfg & ~UART_CFG_RES);
|
||||
|
||||
/* Set up baudrate parameters */
|
||||
baud.clk = Chip_Clock_GetAsyncSyscon_ClockRate(); /* Clock frequency */
|
||||
baud.baud = cfg->baud_rate; /* Required baud rate */
|
||||
baud.ovr = 0; /* Set the oversampling to the recommended rate */
|
||||
baud.mul = baud.div = 0;
|
||||
|
||||
if(!baud.mul)
|
||||
{
|
||||
_UART_CalcMul(&baud);
|
||||
}
|
||||
_UART_CalcDiv(&baud);
|
||||
|
||||
/* Set fractional control register */
|
||||
LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) baud.mul << 8) | 0xFF;
|
||||
|
||||
/* Configure the UART */
|
||||
UART_cfg.cfg = UART_CFG_8BIT;
|
||||
UART_cfg.div = baud.div; /* Use the calculated div value */
|
||||
UART_cfg.ovr = baud.ovr; /* Use oversampling rate from baud */
|
||||
UART_cfg.res = UART_BIT_DLY(cfg->baud_rate);
|
||||
|
||||
/* P254,255,246 */
|
||||
uart->UART->OSR = (UART_cfg.ovr - 1) & 0x0F;
|
||||
uart->UART->BRG = (UART_cfg.div - 1) & 0xFFFF;
|
||||
uart->UART->CFG = UART_CFG_ENABLE | (UART_cfg.cfg & ~UART_CFG_RES);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct lpc_uart *uart;
|
||||
|
@ -95,7 +89,7 @@ static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
|
|||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
uart->UART->INTENCLR &= ~0x01;
|
||||
uart->UART->INTENCLR &= ~0x01;
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
|
@ -106,16 +100,15 @@ static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
|
|||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static int lpc_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct lpc_uart *uart;
|
||||
|
||||
uart = (struct lpc_uart *)serial->parent.user_data;
|
||||
while(!(uart->UART->STAT & (0x01<<2)));
|
||||
|
||||
uart->UART->TXDAT = c ;
|
||||
|
||||
while(!(uart->UART->STAT & (0x01<<2)));
|
||||
|
||||
uart->UART->TXDAT = c ;
|
||||
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
@ -157,9 +150,9 @@ void UART0_IRQHandler(void)
|
|||
volatile uint32_t INTSTAT, tmp;
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
INTSTAT = LPC_USART0->INTSTAT;
|
||||
|
||||
|
||||
INTSTAT = LPC_USART0->INTSTAT;
|
||||
|
||||
INTSTAT &= 0x01;
|
||||
switch (INTSTAT)
|
||||
{
|
||||
|
@ -174,48 +167,42 @@ void UART0_IRQHandler(void)
|
|||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct lpc_uart *uart;
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
|
||||
uart = &uart0;
|
||||
|
||||
uart = &uart0;
|
||||
|
||||
serial0.ops = &lpc_uart_ops;
|
||||
serial0.config = config;
|
||||
serial0.parent.user_data = uart;
|
||||
|
||||
/* Enable IOCON clock Then your cfg will effective P38 */
|
||||
LPC_SYSCON->AHBCLKCTRLSET[0] = (1UL << 13);
|
||||
|
||||
/* Setup UART TX,RX Pin configuration cfg Pin as Tx, Rx */
|
||||
/* P63,P77
|
||||
Selects pin function 1 IOCON_FUNC1
|
||||
No addition pin function IOCON_MODE_INACT
|
||||
Enables digital function by setting 1 to bit 7(default) IOCON_DIGITAL_EN
|
||||
*/
|
||||
LPC_IOCON->PIO[0][0] = (0x1 | (0x0 << 3) | (0x1 << 7));
|
||||
LPC_IOCON->PIO[0][1] = (0x1 | (0x0 << 3) | (0x1 << 7));
|
||||
|
||||
|
||||
/* Enable asynchronous APB bridge and subsystem P30 */
|
||||
LPC_SYSCON->ASYNCAPBCTRL = 0x01;
|
||||
|
||||
/* The UART clock rate is the main system clock divided by this value P59 */
|
||||
LPC_ASYNC_SYSCON->ASYNCCLKDIV = 1; /* Set Async clock divider to 1 */
|
||||
|
||||
/* Enable peripheral clock(asynchronous APB) to UART0 P57*/
|
||||
LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << 0x01);
|
||||
|
||||
/* Controls the clock for the Fractional Rate Generator used with the USARTs P57*/
|
||||
LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << 0x0F); /* Enable clock to Fractional divider */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Enable IOCON clock Then your cfg will effective P38 */
|
||||
LPC_SYSCON->AHBCLKCTRLSET[0] = (1UL << 13);
|
||||
|
||||
/* Setup UART TX,RX Pin configuration cfg Pin as Tx, Rx */
|
||||
/* P63,P77
|
||||
Selects pin function 1 IOCON_FUNC1
|
||||
No addition pin function IOCON_MODE_INACT
|
||||
Enables digital function by setting 1 to bit 7(default) IOCON_DIGITAL_EN
|
||||
*/
|
||||
LPC_IOCON->PIO[0][0] = (0x1 | (0x0 << 3) | (0x1 << 7));
|
||||
LPC_IOCON->PIO[0][1] = (0x1 | (0x0 << 3) | (0x1 << 7));
|
||||
|
||||
|
||||
/* Enable asynchronous APB bridge and subsystem P30 */
|
||||
LPC_SYSCON->ASYNCAPBCTRL = 0x01;
|
||||
|
||||
/* The UART clock rate is the main system clock divided by this value P59 */
|
||||
LPC_ASYNC_SYSCON->ASYNCCLKDIV = 1; /* Set Async clock divider to 1 */
|
||||
|
||||
/* Enable peripheral clock(asynchronous APB) to UART0 P57*/
|
||||
LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << 0x01);
|
||||
|
||||
/* Controls the clock for the Fractional Rate Generator used with the USARTs P57*/
|
||||
LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << 0x0F); /* Enable clock to Fractional divider */
|
||||
|
||||
/* preemption = 1, sub-priority = 1 */
|
||||
NVIC_SetPriority(uart->UART_IRQn, ((0x01 << 3) | 0x01));
|
||||
|
||||
|
@ -232,102 +219,104 @@ void rt_hw_uart_init(void)
|
|||
/* PRIVATE: Division logic to divide without integer overflow */
|
||||
static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m)
|
||||
{
|
||||
uint32_t q, r, u = pclk >> 24, l = pclk << 8;
|
||||
m = m + 256;
|
||||
q = (1 << 24) / m;
|
||||
r = (1 << 24) - (q * m);
|
||||
return ((q * u) << 8) + (((r * u) << 8) + l) / m;
|
||||
uint32_t q, r, u = pclk >> 24, l = pclk << 8;
|
||||
m = m + 256;
|
||||
q = (1 << 24) / m;
|
||||
r = (1 << 24) - (q * m);
|
||||
return ((q * u) << 8) + (((r * u) << 8) + l) / m;
|
||||
}
|
||||
|
||||
/* PRIVATE: Get highest Over sampling value */
|
||||
static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict)
|
||||
{
|
||||
int32_t i, max = strict ? 16 : 5;
|
||||
for (i = 16; i >= max; i--) {
|
||||
if (!(val % i)) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
int32_t i, max = strict ? 16 : 5;
|
||||
for (i = 16; i >= max; i--)
|
||||
{
|
||||
if (!(val % i))
|
||||
{
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Calculate error difference */
|
||||
static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev)
|
||||
{
|
||||
uint32_t err = n - (n / d) * d;
|
||||
uint32_t herr = ((n / d) + 1) * d - n;
|
||||
if (herr < err) {
|
||||
err = herr;
|
||||
}
|
||||
uint32_t err = n - (n / d) * d;
|
||||
uint32_t herr = ((n / d) + 1) * d - n;
|
||||
if (herr < err) {
|
||||
err = herr;
|
||||
}
|
||||
|
||||
if (*prev <= err) {
|
||||
return 0;
|
||||
}
|
||||
*prev = err;
|
||||
return (herr == err) + 1;
|
||||
if (*prev <= err) {
|
||||
return 0;
|
||||
}
|
||||
*prev = err;
|
||||
return (herr == err) + 1;
|
||||
}
|
||||
|
||||
/* Calculate the base DIV value */
|
||||
static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub)
|
||||
{
|
||||
int32_t i = 0;
|
||||
uint32_t perr = ~0UL;
|
||||
int32_t i = 0;
|
||||
uint32_t perr = ~0UL;
|
||||
|
||||
if (!ub->div) {
|
||||
i = ub->ovr ? ub->ovr : 16;
|
||||
}
|
||||
if (!ub->div) {
|
||||
i = ub->ovr ? ub->ovr : 16;
|
||||
}
|
||||
|
||||
for (; i > 4; i--) {
|
||||
int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr);
|
||||
for (; i > 4; i--) {
|
||||
int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr);
|
||||
|
||||
/* Continue when no improvement seen in err value */
|
||||
if (!tmp) {
|
||||
continue;
|
||||
}
|
||||
/* Continue when no improvement seen in err value */
|
||||
if (!tmp) {
|
||||
continue;
|
||||
}
|
||||
|
||||
ub->div = tmp - 1;
|
||||
if (ub->ovr == i) {
|
||||
break;
|
||||
}
|
||||
ub->ovr = i;
|
||||
}
|
||||
ub->div = tmp - 1;
|
||||
if (ub->ovr == i) {
|
||||
break;
|
||||
}
|
||||
ub->ovr = i;
|
||||
}
|
||||
|
||||
if (!ub->ovr) {
|
||||
return ERR_UART_BAUDRATE;
|
||||
}
|
||||
if (!ub->ovr) {
|
||||
return ERR_UART_BAUDRATE;
|
||||
}
|
||||
|
||||
ub->div += ub->clk / (ub->baud * ub->ovr);
|
||||
if (!ub->div) {
|
||||
return ERR_UART_BAUDRATE;
|
||||
}
|
||||
ub->div += ub->clk / (ub->baud * ub->ovr);
|
||||
if (!ub->div) {
|
||||
return ERR_UART_BAUDRATE;
|
||||
}
|
||||
|
||||
ub->baud = ub->clk / (ub->div * ub->ovr);
|
||||
return LPC_OK;
|
||||
ub->baud = ub->clk / (ub->div * ub->ovr);
|
||||
return LPC_OK;
|
||||
}
|
||||
|
||||
/* Calculate the best MUL value */
|
||||
static void _UART_CalcMul(UART_BAUD_T *ub)
|
||||
{
|
||||
uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr;
|
||||
uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr;
|
||||
|
||||
/* If clock is UART's base clock calculate only the divider */
|
||||
for (m = 0; m < 256; m++) {
|
||||
uint32_t ov = ovr, x, v, tmp;
|
||||
/* If clock is UART's base clock calculate only the divider */
|
||||
for (m = 0; m < 256; m++) {
|
||||
uint32_t ov = ovr, x, v, tmp;
|
||||
|
||||
/* Get clock and calculate error */
|
||||
x = _UART_DivClk(pclk, m);
|
||||
tmp = _CalcErr(x, ub->baud, &perr);
|
||||
v = (x / ub->baud) + tmp - 1;
|
||||
/* Get clock and calculate error */
|
||||
x = _UART_DivClk(pclk, m);
|
||||
tmp = _CalcErr(x, ub->baud, &perr);
|
||||
v = (x / ub->baud) + tmp - 1;
|
||||
|
||||
/* Update if new error is better than previous best */
|
||||
if (!tmp || (ovr && (v % ovr)) ||
|
||||
(!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) {
|
||||
continue;
|
||||
}
|
||||
/* Update if new error is better than previous best */
|
||||
if (!tmp || (ovr && (v % ovr)) ||
|
||||
(!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) {
|
||||
continue;
|
||||
}
|
||||
|
||||
ub->ovr = ov;
|
||||
ub->mul = m;
|
||||
ub->clk = x;
|
||||
ub->div = tmp - 1;
|
||||
}
|
||||
ub->ovr = ov;
|
||||
ub->mul = m;
|
||||
ub->clk = x;
|
||||
ub->div = tmp - 1;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,10 +1,6 @@
|
|||
#ifndef __DRV_UART_H_
|
||||
#define __DRV_UART_H_
|
||||
|
||||
|
||||
|
||||
|
||||
void rt_hw_uart_init(void);
|
||||
|
||||
|
||||
#endif /* __BOARD_H_ */
|
||||
|
|
Loading…
Reference in New Issue