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Follow coding-style and formatting.

This commit is contained in:
Wayne Lin 2021-05-14 11:53:46 +08:00
parent 4ae3a3a7f0
commit cc32e7aa4d
39 changed files with 8912 additions and 8892 deletions
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9936
bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_math.h
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425
bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_compiler.h
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@ -31,21 +31,21 @@
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
#include "cmsis_gcc.h"
/*
@ -54,298 +54,313 @@
#elif defined ( __ICCARM__ )
#ifndef __ASM
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#endif
#include <cmsis_iar.h>
#include <cmsis_iar.h>
/* CMSIS compiler control architecture macros */
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
/* CMSIS compiler control architecture macros */
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
#ifndef __ARM_ARCH_6M__
#define __ARM_ARCH_6M__ 1
#define __ARM_ARCH_6M__ 1
#endif
#elif (__CORE__ == __ARM7M__)
#elif (__CORE__ == __ARM7M__)
#ifndef __ARM_ARCH_7M__
#define __ARM_ARCH_7M__ 1
#define __ARM_ARCH_7M__ 1
#endif
#elif (__CORE__ == __ARM7EM__)
#elif (__CORE__ == __ARM7EM__)
#ifndef __ARM_ARCH_7EM__
#define __ARM_ARCH_7EM__ 1
#define __ARM_ARCH_7EM__ 1
#endif
#endif
#endif
#ifndef __NO_RETURN
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
__packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
__packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
//#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#endif
#ifndef __RESTRICT
//#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
// Workaround for missing __CLZ intrinsic in
// various versions of the IAR compilers.
// __IAR_FEATURE_CLZ__ should be defined by
// the compiler that supports __CLZ internally.
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
// Workaround for missing __CLZ intrinsic in
// various versions of the IAR compilers.
// __IAR_FEATURE_CLZ__ should be defined by
// the compiler that supports __CLZ internally.
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
{
if (data == 0u)
{
return 32u;
}
uint32_t count = 0;
uint32_t mask = 0x80000000;
while ((data & mask) == 0)
{
if (data == 0u) { return 32u; }
uint32_t count = 0;
uint32_t mask = 0x80000000;
while ((data & mask) == 0)
{
count += 1u;
mask = mask >> 1u;
}
return (count);
}
#endif
return (count);
}
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#include <cmsis_ccs.h>
#ifndef __ASM
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#include <cmsis_csm.h>
#ifndef __ASM
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
#else
#error Unknown compiler.
#error Unknown compiler.
#endif

934
bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mbl.h
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1412
bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mml.h
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382
bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0.h
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@ -23,9 +23,9 @@
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
@ -34,7 +34,7 @@
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/**
@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@ -76,39 +76,39 @@
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
@ -127,25 +127,25 @@
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
@ -157,9 +157,9 @@
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
@ -198,15 +198,15 @@
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
@ -228,12 +228,12 @@ typedef union
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
@ -246,18 +246,18 @@ typedef union
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
@ -285,13 +285,13 @@ typedef union
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
@ -313,16 +313,16 @@ typedef union
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
@ -340,15 +340,15 @@ typedef struct
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
@ -447,10 +447,10 @@ typedef struct
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
@ -567,33 +567,33 @@ typedef struct
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
@ -614,10 +614,10 @@ typedef struct
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
@ -631,14 +631,14 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return (0U);
}
}
@ -650,12 +650,12 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
@ -669,14 +669,14 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return (0U);
}
}
@ -688,10 +688,10 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
@ -703,10 +703,10 @@ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
@ -721,16 +721,16 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
@ -746,14 +746,14 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
@ -768,8 +768,8 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
@ -783,8 +783,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
@ -794,16 +794,16 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
for (;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
@ -858,18 +858,18 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif

416
bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0plus.h
View File

@ -23,9 +23,9 @@
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
@ -34,7 +34,7 @@
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/**
@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@ -76,39 +76,39 @@
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
@ -127,35 +127,35 @@
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
@ -167,9 +167,9 @@
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
@ -209,15 +209,15 @@
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
@ -239,12 +239,12 @@ typedef union
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
@ -257,18 +257,18 @@ typedef union
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
@ -296,13 +296,13 @@ typedef union
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
struct
{
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
@ -327,16 +327,16 @@ typedef union
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
@ -354,19 +354,19 @@ typedef struct
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
@ -471,10 +471,10 @@ typedef struct
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
@ -523,11 +523,11 @@ typedef struct
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
@ -653,8 +653,8 @@ typedef struct
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
@ -683,33 +683,33 @@ typedef struct
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
@ -730,10 +730,10 @@ typedef struct
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
@ -747,14 +747,14 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return (0U);
}
}
@ -766,12 +766,12 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
@ -785,14 +785,14 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return (0U);
}
}
@ -804,10 +804,10 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
@ -819,10 +819,10 @@ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
@ -837,16 +837,16 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
@ -862,14 +862,14 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
@ -886,11 +886,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
@ -905,11 +905,11 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
uint32_t *vectors = (uint32_t *)0x0U;
#endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
@ -920,16 +920,16 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
*/
__STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
for (;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
@ -991,18 +991,18 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif

754
bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm3.h
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bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm33.h
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898
bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm4.h
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67
bsp/nuvoton/libraries/m2354/CMSIS/Include/mpu_armv7.h
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@ -21,7 +21,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
@ -54,7 +54,7 @@
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define ARM_MPU_AP_NONE 0u
#define ARM_MPU_AP_NONE 0u
#define ARM_MPU_AP_PRIV 1u
#define ARM_MPU_AP_URO 2u
#define ARM_MPU_AP_FULL 3u
@ -70,7 +70,7 @@
/**
* MPU Region Attribut and Size Register Value
*
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@ -79,7 +79,7 @@
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
@ -95,21 +95,22 @@
/**
* Struct for a single MPU Region
*/
typedef struct _ARM_MPU_Region_t {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
typedef struct _ARM_MPU_Region_t
{
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
@ -117,12 +118,12 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
*/
__STATIC_INLINE void ARM_MPU_Disable()
{
__DSB();
__ISB();
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
@ -130,30 +131,30 @@ __STATIC_INLINE void ARM_MPU_Disable()
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0u;
MPU->RNR = rnr;
MPU->RASR = 0u;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
@ -161,22 +162,22 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
__STATIC_INLINE void orderedCpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0u; i < len; ++i)
{
dst[i] = src[i];
}
uint32_t i;
for (i = 0u; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
{
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt * sizeof(ARM_MPU_Region_t) / 4u);
}
#endif

36
bsp/nuvoton/libraries/m2354/CMSIS/Include/tz_context.h
View File

@ -26,44 +26,44 @@
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
uint32_t TZ_InitContextSystem_S(void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

30
bsp/nuvoton/libraries/m2354/USBHostLib/inc/config.h
View File

@ -17,7 +17,7 @@
/*----------------------------------------------------------------------------------------*/
/* Hardware settings */
/*----------------------------------------------------------------------------------------*/
#define HCLK_MHZ 192 /* used for loop-delay. must be larger than
#define HCLK_MHZ 192 /* used for loop-delay. must be larger than
true HCLK clock MHz */
#define ENABLE_OHCI_IRQ() NVIC_EnableIRQ(USBH_IRQn)
@ -25,12 +25,12 @@
#define ENABLE_OHCI /* Enable OHCI host controller */
#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling
#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling
OHCI isochronous transfer */
#define MAX_DESC_BUFF_SIZE 512 /* To hold the configuration descriptor, USB
#define MAX_DESC_BUFF_SIZE 512 /* To hold the configuration descriptor, USB
core will allocate a buffer with this size
for each connected device. USB core does
for each connected device. USB core does
not release it until device disconnected. */
/*----------------------------------------------------------------------------------------*/
@ -57,7 +57,7 @@
/* Re-defined staff for various compiler */
/*----------------------------------------------------------------------------------------*/
#ifdef __ICCARM__
#define __inline inline
#define __inline inline
#endif
@ -70,21 +70,21 @@
//#define DUMP_DESCRIPTOR /* dump descriptors */
#ifdef ENABLE_ERROR_MSG
#define USB_error rt_kprintf
#define USB_error rt_kprintf
#else
#define USB_error(...)
#define USB_error(...)
#endif
#ifdef ENABLE_DEBUG_MSG
#define USB_debug rt_kprintf
#ifdef ENABLE_VERBOSE_DEBUG
#define USB_vdebug rt_kprintf
#define USB_debug rt_kprintf
#ifdef ENABLE_VERBOSE_DEBUG
#define USB_vdebug rt_kprintf
#else
#define USB_vdebug(...)
#endif
#else
#define USB_vdebug(...)
#endif
#else
#define USB_debug(...)
#define USB_vdebug(...)
#define USB_debug(...)
#define USB_vdebug(...)
#endif

10
bsp/nuvoton/libraries/m2354/USBHostLib/inc/usbh_lib.h
View File

@ -51,7 +51,7 @@ extern "C"
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
@ -145,7 +145,7 @@ extern int usbh_polling_root_hubs(void);
extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
extern void usbh_suspend(void);
extern void usbh_resume(void);
extern struct udev_t * usbh_find_device(char *hub_id, int port);
extern struct udev_t *usbh_find_device(char *hub_id, int port);
/**
* @brief A function return current tick count.
* @return Current tick.
@ -161,7 +161,7 @@ extern uint32_t usbh_tick_from_millisecond(uint32_t msec); /* This function mu
/* */
/*------------------------------------------------------------------*/
extern void usbh_cdc_init(void);
extern struct cdc_dev_t * usbh_cdc_get_device_list(void);
extern struct cdc_dev_t *usbh_cdc_get_device_list(void);
/// @cond HIDDEN_SYMBOLS
extern int32_t usbh_cdc_get_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
extern int32_t usbh_cdc_set_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
@ -178,7 +178,7 @@ extern int32_t usbh_cdc_send_data(struct cdc_dev_t *cdev, uint8_t *buff, int bu
/* */
/*------------------------------------------------------------------*/
extern void usbh_hid_init(void);
extern struct usbhid_dev * usbh_hid_get_device_list(void);
extern struct usbhid_dev *usbh_hid_get_device_list(void);
extern int32_t usbh_hid_get_report_descriptor(struct usbhid_dev *hdev, uint8_t *desc_buf, int buf_max_len);
extern int32_t usbh_hid_get_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
extern int32_t usbh_hid_set_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
@ -211,7 +211,7 @@ extern int usbh_umas_reset_disk(int drv_no);
/*------------------------------------------------------------------*/
extern void usbh_uac_init(void);
extern int usbh_uac_open(struct uac_dev_t *audev);
extern struct uac_dev_t * usbh_uac_get_device_list(void);
extern struct uac_dev_t *usbh_uac_get_device_list(void);
extern int usbh_uac_get_channel_number(struct uac_dev_t *audev, uint8_t target);
extern int usbh_uac_get_bit_resolution(struct uac_dev_t *audev, uint8_t target, uint8_t *byte_cnt);
extern int usbh_uac_get_sampling_rate(struct uac_dev_t *audev, uint8_t target, uint32_t *srate_list, int max_cnt, uint8_t *type);

16
bsp/nuvoton/libraries/m2354/USBHostLib/src/usb_core.c
View File

@ -22,7 +22,7 @@
USBH_T *_ohci;
static UDEV_DRV_T * _drivers[MAX_UDEV_DRIVER];
static UDEV_DRV_T *_drivers[MAX_UDEV_DRIVER];
static CONN_FUNC *g_conn_func, *g_disconn_func;
/// @endcond HIDDEN_SYMBOLS
@ -34,7 +34,7 @@ static CONN_FUNC *g_conn_func, *g_disconn_func;
*/
void usbh_core_init()
{
if((__PC() & NS_OFFSET) == NS_OFFSET)
if ((__PC() & NS_OFFSET) == NS_OFFSET)
{
_ohci = USBH_NS;
}
@ -50,7 +50,7 @@ void usbh_core_init()
g_conn_func = NULL;
g_disconn_func = NULL;
// usbh_hub_init();
// usbh_hub_init();
usbh_memory_init();
@ -111,7 +111,7 @@ int usbh_connect_device(UDEV_T *udev)
if (g_conn_func)
g_conn_func(udev, 0);
return 0;
}
@ -123,8 +123,8 @@ void usbh_disconnect_device(UDEV_T *udev)
if (g_disconn_func)
g_disconn_func(udev, 0);
#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application
#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application
usbh_quit_xfer(udev, &(udev->ep0)); /* Quit control transfer if hw_pipe is not NULL. */
/* remove device from global device list */
@ -153,7 +153,7 @@ int usbh_reset_port(UDEV_T *udev)
if (udev->parent == NULL)
{
if (udev->hc_driver)
return udev->hc_driver->rthub_port_reset(udev->port_num-1);
return udev->hc_driver->rthub_port_reset(udev->port_num - 1);
else
return USBH_ERR_NOT_FOUND;
}
@ -171,7 +171,7 @@ int usbh_reset_port(UDEV_T *udev)
*/
int usbh_quit_utr(UTR_T *utr)
{
if(!utr || !utr->udev)
if (!utr || !utr->udev)
return USBH_ERR_NOT_FOUND;
return utr->udev->hc_driver->quit_xfer(utr, NULL);

8
bsp/nuvoton/libraries/m480/CMSIS/Include/arm_common_tables.h
View File

@ -2,12 +2,12 @@
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*

62
bsp/nuvoton/libraries/m480/CMSIS/Include/arm_const_structs.h
View File

@ -2,12 +2,12 @@
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
@ -46,34 +46,34 @@
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

730
bsp/nuvoton/libraries/m480/CMSIS/Include/cmsis_armcc_V6.h
View File

File diff suppressed because it is too large Load Diff

6
bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/sys_reg.h
View File

@ -10,7 +10,7 @@
#define __SYS_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#pragma anon_unions
#endif
/**
@ -3339,7 +3339,7 @@ typedef struct
#define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */
#define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */
#define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */
#define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */
#define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */
#define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */
@ -3656,7 +3656,7 @@ typedef struct
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#pragma no_anon_unions
#endif
#endif /* __SYS_REG_H__ */

10
bsp/nuvoton/libraries/m480/StdDriver/inc/nu_clk.h
View File

@ -298,7 +298,7 @@ extern "C"
#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
//
//
#define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
#define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
@ -617,7 +617,7 @@ __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
{
}
@ -642,7 +642,7 @@ __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
do
{
if(us > delay)
if (us > delay)
{
us -= delay;
}
@ -657,13 +657,13 @@ __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
/* Disable SysTick counter */
SysTick->CTRL = 0UL;
}
while(us > 0UL);
while (us > 0UL);
}

4
bsp/nuvoton/libraries/m480/StdDriver/inc/nu_trng.h
View File

@ -32,8 +32,8 @@ extern "C"
/*----------------------------------------------------------------------------------------------*/
/**
* @brief Let TRNG engine know the currrent PCLK frequency. The CLKPSC is the peripheral
* clock frequency range for the selected value , the CLKPSC setting must be higher
* @brief Let TRNG engine know the currrent PCLK frequency. The CLKPSC is the peripheral
* clock frequency range for the selected value , the CLKPSC setting must be higher
* than or equal to the actual peripheral clock frequency (for correct random generation).
* @param clkpsc 0: PCLK is 80~100 MHz
* 1: PCLK is 60~80 MHz

46
bsp/nuvoton/libraries/m480/StdDriver/src/nu_crypto.c
View File

@ -16,9 +16,9 @@
#define ENABLE_DEBUG 0
#if ENABLE_DEBUG
#define CRPT_DBGMSG printf
#define CRPT_DBGMSG printf
#else
#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */
#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */
#endif
/** @endcond HIDDEN_SYMBOLS */
@ -75,8 +75,8 @@ void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32
crpt->PRNG_SEED = u32Seed;
}
crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
(u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
(u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
}
/**
@ -178,7 +178,7 @@ void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t
uint32_t i, wcnt, key_reg_addr;
key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL);
wcnt = 4UL + u32KeySize*2UL;
wcnt = 4UL + u32KeySize * 2UL;
for (i = 0U; i < wcnt; i++)
{
@ -379,9 +379,9 @@ void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t h
crpt->HMAC_KEYCNT = hmac_key_len;
if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0)
crpt->HMAC_CTL |= (1<<4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
crpt->HMAC_CTL |= (1 << 4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
else
crpt->HMAC_CTL |= (1<<11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
crpt->HMAC_CTL |= (1 << 11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
}
}
@ -447,7 +447,7 @@ void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[])
wcnt = 16UL;
}
reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]);
reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]);
for (i = 0UL; i < wcnt; i++)
{
u32Digest[i] = inpw(reg_addr);
@ -887,7 +887,7 @@ const ECC_CURVE _Curve[] =
static ECC_CURVE *pCurve;
static ECC_CURVE Curve_Copy;
static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);
static ECC_CURVE *get_curve(E_ECC_CURVE ecc_curve);
static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve);
static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);
@ -990,7 +990,7 @@ static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
*/
static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)
{
return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ];
return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ];
}
@ -1012,7 +1012,7 @@ static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])
}
}
static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
static ECC_CURVE *get_curve(E_ECC_CURVE ecc_curve)
{
uint32_t i;
ECC_CURVE *ret = NULL;
@ -1108,7 +1108,7 @@ static int ecc_strcmp(char *s1, char *s2)
while (*s1 == '0') s1++;
while (*s2 == '0') s2++;
for ( ; *s1 || *s2; s1++, s2++)
for (; *s1 || *s2; s1++, s2++)
{
if ((*s1 >= 'A') && (*s1 <= 'Z'))
c1 = *s1 + 32;
@ -1502,7 +1502,7 @@ int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *messag
Reg2Hex(pCurve->Echar, temp_result1, R);
/*
* 4. Compute s = k ? 1 ｝ (e + d ｝ r)(mod n). If s = 0, go to step 2
* 4. Compute s = k ? 1 ｝ (e + d ｝ r)(mod n). If s = 0, go to step 2
* (1) Write the curve order to N registers according
* (2) Write 0x1 to Y1 registers
* (3) Write the random integer k to X1 registers according
@ -1732,7 +1732,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
#endif
/*
* 4. Compute u1 = e ｝ w (mod n) and u2 = r ｝ w (mod n)
* 4. Compute u1 = e ｝ w (mod n) and u2 = r ｝ w (mod n)
* (1) Write the curve order and curve length to N ,M registers
* (2) Write e, w to X1, Y1 registers
* (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
@ -1814,7 +1814,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
#endif
/*
* 5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
* 5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
* (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
* (2) Write the point G(x, y) to X1, Y1 registers
* (3) Write u1 to K registers
@ -1833,17 +1833,17 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
* (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
* (17) Set START(CRPT_ECC_CTL[0]) to 1
* (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
* (19) Read X1, Y1 registers to get X・(x1・, y1・)
* (19) Read X1, Y1 registers to get X・(x1・, y1・)
* (20) Write the curve order and curve length to N ,M registers
* (21) Write x1・ to X1 registers
* (21) Write x1・ to X1 registers
* (22) Write 0x0 to Y1 registers
* (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
* (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
* (25) Set START(CRPT_ECC_CTL[0]) to 1
* (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
* (27) Read X1 registers to get x1・ (mod n)
* (27) Read X1 registers to get x1・ (mod n)
*
* 6. The signature is valid if x1・ = r, otherwise it is invalid
* 6. The signature is valid if x1・ = r, otherwise it is invalid
*/
/*
@ -1927,7 +1927,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
run_ecc_codec(crpt, ECCOP_POINT_ADD);
/* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
/* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
for (i = 0; i < 18; i++)
{
temp_x[i] = crpt->ECC_X1[i];
@ -1949,7 +1949,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
Hex2Reg(pCurve->Eorder, crpt->ECC_N);
/*
* (21) Write x1・ to X1 registers
* (21) Write x1・ to X1 registers
* (22) Write 0x0 to Y1 registers
*/
for (i = 0; i < 18; i++)
@ -1967,11 +1967,11 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
/* (27) Read X1 registers to get x1・ (mod n) */
/* (27) Read X1 registers to get x1・ (mod n) */
Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
/* 6. The signature is valid if x1・ = r, otherwise it is invalid */
/* 6. The signature is valid if x1・ = r, otherwise it is invalid */
/* Compare with test pattern to check if r is correct or not */
if (ecc_strcmp(temp_hex_str, R) != 0)

36
bsp/nuvoton/libraries/m480/USBHostLib/inc/config.h
View File

@ -18,7 +18,7 @@
/*----------------------------------------------------------------------------------------*/
/* Hardware settings */
/*----------------------------------------------------------------------------------------*/
#define HCLK_MHZ 192 /* used for loop-delay. must be larger than
#define HCLK_MHZ 192 /* used for loop-delay. must be larger than
true HCLK clock MHz */
#define ENABLE_OHCI_IRQ() NVIC_EnableIRQ(USBH_IRQn)
@ -29,26 +29,26 @@
#define ENABLE_OHCI /* Enable OHCI host controller */
#if defined(BSP_USING_HSUSBH)
#define ENABLE_EHCI /* Enable EHCI host controller */
#define ENABLE_EHCI /* Enable EHCI host controller */
#endif
#define EHCI_PORT_CNT 1 /* Number of EHCI roothub ports */
#define OHCI_PORT_CNT 2 /* Number of OHCI roothub ports */
#define OHCI_PER_PORT_POWER /* OHCI root hub per port powered */
#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling
#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling
OHCI isochronous transfer */
#define EHCI_ISO_DELAY 2 /* preserved number of frames while
#define EHCI_ISO_DELAY 2 /* preserved number of frames while
scheduling EHCI isochronous transfer */
#define EHCI_ISO_RCLM_RANGE 32 /* When inspecting activated iTD/siTD,
#define EHCI_ISO_RCLM_RANGE 32 /* When inspecting activated iTD/siTD,
unconditionally reclaim iTD/isTD scheduled
in just elapsed EHCI_ISO_RCLM_RANGE ms. */
#define MAX_DESC_BUFF_SIZE 512 /* To hold the configuration descriptor, USB
#define MAX_DESC_BUFF_SIZE 512 /* To hold the configuration descriptor, USB
core will allocate a buffer with this size
for each connected device. USB core does
for each connected device. USB core does
not release it until device disconnected. */
/*----------------------------------------------------------------------------------------*/
@ -75,7 +75,7 @@
/* Re-defined staff for various compiler */
/*----------------------------------------------------------------------------------------*/
#ifdef __ICCARM__
#define __inline inline
#define __inline inline
#endif
@ -88,21 +88,21 @@
//#define DUMP_DESCRIPTOR /* dump descriptors */
#ifdef ENABLE_ERROR_MSG
#define USB_error rt_kprintf
#define USB_error rt_kprintf
#else
#define USB_error(...)
#define USB_error(...)
#endif
#ifdef ENABLE_DEBUG_MSG
#define USB_debug rt_kprintf
#ifdef ENABLE_VERBOSE_DEBUG
#define USB_vdebug rt_kprintf
#define USB_debug rt_kprintf
#ifdef ENABLE_VERBOSE_DEBUG
#define USB_vdebug rt_kprintf
#else
#define USB_vdebug(...)
#endif
#else
#define USB_vdebug(...)
#endif
#else
#define USB_debug(...)
#define USB_vdebug(...)
#define USB_debug(...)
#define USB_vdebug(...)
#endif

4
bsp/nuvoton/libraries/m480/USBHostLib/inc/usbh_lib.h
View File

@ -51,7 +51,7 @@ extern "C"
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
@ -145,7 +145,7 @@ extern int usbh_polling_root_hubs(void);
extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
extern void usbh_suspend(void);
extern void usbh_resume(void);
extern struct udev_t * usbh_find_device(char *hub_id, int port);
extern struct udev_t *usbh_find_device(char *hub_id, int port);
/**
* @brief A function return current tick count.

50
bsp/nuvoton/libraries/m480/USBHostLib/src/ehci.c
View File

@ -29,13 +29,13 @@ extern int ehci_iso_xfer(UTR_T *utr); /* EHCI isochronous transfer functio
extern int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep);
#ifdef __ICCARM__
#pragma data_alignment=4096
uint32_t _PFList[FL_SIZE]; /* Periodic frame list (IAR) */
#pragma data_alignment=4096
uint32_t _PFList[FL_SIZE]; /* Periodic frame list (IAR) */
#else
uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
#endif
QH_T * _Iqh[NUM_IQH];
QH_T *_Iqh[NUM_IQH];
#ifdef ENABLE_ERROR_MSG
@ -65,7 +65,7 @@ void dump_ehci_qtd(qTD_T *qtd)
USB_debug(" [qTD] - 0x%08x\n", (int)qtd);
USB_debug(" 0x%08x (Next qtd Pointer)\n", qtd->Next_qTD);
USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qtd->Alt_Next_qTD);
USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token>>8)&0x3)==0) ? "OUT" : ((((qtd->Token>>8)&0x3)==1) ? "IN" : "SETUP"), (qtd->Token>>16)&0x7FFF, (qtd->Token>>15)&0x1);
USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token >> 8) & 0x3) == 0) ? "OUT" : ((((qtd->Token >> 8) & 0x3) == 1) ? "IN" : "SETUP"), (qtd->Token >> 16) & 0x7FFF, (qtd->Token >> 15) & 0x1);
USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qtd->Bptr[0]);
//USB_debug(" 0x%08x (Buffer Pointer (page 1))\n", qtd->Bptr[1]);
//USB_debug(" 0x%08x (Buffer Pointer (page 2))\n", qtd->Bptr[2]);
@ -84,7 +84,7 @@ void dump_ehci_asynclist(void)
{
USB_debug("[QH] - 0x%08x\n", (int)qh);
USB_debug(" 0x%08x (Queue Head Horizontal Link Pointer, Queue Head DWord 0)\n", qh->HLink);
USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst&0x7F, (qh->Chrst>>8)&0xF, (qh->Chrst>>16)&0x7FF, ((qh->Chrst>>12)&0x3 == 0) ? "Full" : (((qh->Chrst>>12)&0x3 == 1) ? "Low" : "High"));
USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst & 0x7F, (qh->Chrst >> 8) & 0xF, (qh->Chrst >> 16) & 0x7FF, ((qh->Chrst >> 12) & 0x3 == 0) ? "Full" : (((qh->Chrst >> 12) & 0x3 == 1) ? "Low" : "High"));
USB_debug(" 0x%08x (Endpoint Capabilities: Queue Head DWord 2)\n", qh->Cap);
USB_debug(" 0x%08x (Current qtd Pointer)\n", qh->Curr_qTD);
USB_debug(" --- Overlay Area ---\n");
@ -122,7 +122,7 @@ void dump_ehci_asynclist_simple(void)
void dump_ehci_period_frame_list_simple(void)
{
QH_T *qh = _Iqh[NUM_IQH-1];
QH_T *qh = _Iqh[NUM_IQH - 1];
USB_debug(">>> EHCI period frame list simple <<<\n");
USB_debug("[FList] => ");
@ -165,7 +165,7 @@ static void init_periodic_frame_list()
iso_ep_list = NULL;
for (i = NUM_IQH-1; i >= 0; i--) /* interval = i^2 */
for (i = NUM_IQH - 1; i >= 0; i--) /* interval = i^2 */
{
_Iqh[i] = alloc_ehci_QH();
@ -204,19 +204,19 @@ static void init_periodic_frame_list()
}
}
static QH_T * get_int_tree_head_node(int interval)
static QH_T *get_int_tree_head_node(int interval)
{
int i;
interval /= 8; /* each frame list entry for 8 micro-frame */
for (i = 0; i < NUM_IQH-1; i++)
for (i = 0; i < NUM_IQH - 1; i++)
{
interval >>= 1;
if (interval == 0)
return _Iqh[i];
}
return _Iqh[NUM_IQH-1];
return _Iqh[NUM_IQH - 1];
}
static int make_int_s_mask(int bInterval)
@ -245,7 +245,7 @@ static int make_int_s_mask(int bInterval)
static int ehci_init(void)
{
int timeout = 250*1000; /* EHCI reset time-out 250 ms */
int timeout = 250 * 1000; /* EHCI reset time-out 250 ms */
/*------------------------------------------------------------------------------------*/
/* Reset EHCI host controller */
@ -283,11 +283,11 @@ static int ehci_init(void)
/* Initialize periodic list */
/*------------------------------------------------------------------------------------*/
if (FL_SIZE == 256)
_ehci->UCMDR |= (0x2<<HSUSBH_UCMDR_FLSZ_Pos);
_ehci->UCMDR |= (0x2 << HSUSBH_UCMDR_FLSZ_Pos);
else if (FL_SIZE == 512)
_ehci->UCMDR |= (0x1<<HSUSBH_UCMDR_FLSZ_Pos);
_ehci->UCMDR |= (0x1 << HSUSBH_UCMDR_FLSZ_Pos);
else if (FL_SIZE == 1024)
_ehci->UCMDR |= (0x0<<HSUSBH_UCMDR_FLSZ_Pos);
_ehci->UCMDR |= (0x0 << HSUSBH_UCMDR_FLSZ_Pos);
else
return USBH_ERR_EHCI_INIT; /* Invalid FL_SIZE setting! */
@ -371,7 +371,7 @@ static void move_qh_to_remove_list(QH_T *qh)
/*------------------------------------------------------------------------------------*/
/* Search periodic frame list and remove qh if found in list. */
/*------------------------------------------------------------------------------------*/
q = _Iqh[NUM_IQH-1];
q = _Iqh[NUM_IQH - 1];
while (q->HLink != QH_HLNK_END)
{
if (QH_PTR(q->HLink) == qh)
@ -508,7 +508,7 @@ static int ehci_ctrl_xfer(UTR_T *utr)
if (utr->data_len > 0)
{
if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF)+0x5000))
if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF) + 0x5000))
return USBH_ERR_BUFF_OVERRUN;
}
@ -918,7 +918,7 @@ static int visit_qtd(qTD_T *qtd)
static void scan_asynchronous_list()
{
QH_T *qh, *qh_tmp;
qTD_T *q_pre=NULL, *qtd, *qtd_tmp;
qTD_T *q_pre = NULL, *qtd, *qtd_tmp;
UTR_T *utr;
qh = QH_PTR(_H_qh->HLink);
@ -982,7 +982,7 @@ static void scan_periodic_frame_list()
/*------------------------------------------------------------------------------------*/
/* Scan interrupt frame list */
/*------------------------------------------------------------------------------------*/
qh = _Iqh[NUM_IQH-1];
qh = _Iqh[NUM_IQH - 1];
while (qh != NULL)
{
qtd = qh->qtd_list;
@ -1095,7 +1095,7 @@ void iaad_remove_qh()
/*------------------------------------------------------------------------------------*/
/* Free all qTD in done_list of each QH of periodic frame list */
/*------------------------------------------------------------------------------------*/
qh = _Iqh[NUM_IQH-1];
qh = _Iqh[NUM_IQH - 1];
while (qh != NULL)
{
while (qh->done_list) /* we can free the qTDs now */
@ -1138,7 +1138,7 @@ void EHCI_IRQHandler(void)
}
}
static UDEV_T * ehci_find_device_by_port(int port)
static UDEV_T *ehci_find_device_by_port(int port)
{
UDEV_T *udev;
@ -1165,12 +1165,12 @@ static int ehci_rh_port_reset(int port)
_ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time)+1) ; /* wait at least 50 ms */
while (usbh_get_ticks() - t0 < (reset_time) + 1) ; /* wait at least 50 ms */
_ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time)+1)
while (usbh_get_ticks() - t0 < (reset_time) + 1)
{
if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) ||
((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)))
@ -1179,7 +1179,7 @@ static int ehci_rh_port_reset(int port)
reset_time += PORT_RESET_RETRY_INC_MS;
}
USB_debug("EHCI port %d - port reset failed!\n", port+1);
USB_debug("EHCI port %d - port reset failed!\n", port + 1);
return USBH_ERR_PORT_RESET;
port_reset_done:
@ -1222,7 +1222,7 @@ static int ehci_rh_polling(void)
/* Port de-bounce */
/*--------------------------------------------------------------------------------*/
t0 = usbh_get_ticks();
debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
connect_status = _ehci->UPSCR[0] & HSUSBH_UPSCR_CCS_Msk;
while (usbh_get_ticks() - t0 < debounce_tick)
{

10
bsp/nuvoton/libraries/m480/USBHostLib/src/usb_core.c
View File

@ -22,7 +22,7 @@
USBH_T *_ohci;
HSUSBH_T *_ehci;
static UDEV_DRV_T * _drivers[MAX_UDEV_DRIVER];
static UDEV_DRV_T *_drivers[MAX_UDEV_DRIVER];
static CONN_FUNC *g_conn_func, *g_disconn_func;
/**
@ -130,7 +130,7 @@ int usbh_connect_device(UDEV_T *udev)
if (g_conn_func)
g_conn_func(udev, 0);
return 0;
}
@ -142,8 +142,8 @@ void usbh_disconnect_device(UDEV_T *udev)
if (g_disconn_func)
g_disconn_func(udev, 0);
#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application
#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application
usbh_quit_xfer(udev, &(udev->ep0)); /* Quit control transfer if hw_pipe is not NULL. */
/* remove device from global device list */
@ -172,7 +172,7 @@ int usbh_reset_port(UDEV_T *udev)
if (udev->parent == NULL)
{
if (udev->hc_driver)
return udev->hc_driver->rthub_port_reset(udev->port_num-1);
return udev->hc_driver->rthub_port_reset(udev->port_num - 1);
else
return USBH_ERR_NOT_FOUND;
}

2
bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
View File

@ -484,7 +484,7 @@ int nu_epwm_capture_device_init(void)
}
}
#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
for (int i = 0; i < EPWM_CHANNEL_NUM; i++)
{

2
bsp/nuvoton/libraries/n9h30/Driver/Source/nu_cap.c
View File

@ -267,7 +267,7 @@ void CAP_Close(void)
{
// 1. Disable IP's interrupt
sysDisableInterrupt(CAP_IRQn);
// 2. Disable IP’s clock
// 2. Disable IP's clock
outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(0x1 << 25));
CAP_Reset();
outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(0x1 << 26));

2
bsp/nuvoton/libraries/n9h30/UsbHostLib/inc/usbh_lib.h
View File

@ -53,7 +53,7 @@ extern "C"
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */

2
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_pwm.h
View File

@ -46,7 +46,7 @@ extern "C"
#define PWM1_TIMER3 7 ///< PWM1 channel 3
//ioctl command
#define START_PWMTIMER 0 ///< Start PWM ioctl command
#define START_PWMTIMER 0 ///< Start PWM ioctl command
#define STOP_PWMTIMER 1 ///< Stop PWM ioctl command
#define SET_CSR 2 ///< Set CSR ioctl command
#define SET_CP 3 ///< Set CP ioctl command

34
bsp/nuvoton/libraries/nuc980/Driver/Include/nu_wwdt.h
View File

@ -25,24 +25,24 @@ extern "C"
/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
@{
*/
#define WWDT_PRESCALER_1 (0UL << 8) ///< WWDT setting prescaler to 1 \hideinitializer
#define WWDT_PRESCALER_2 (1UL << 8) ///< WWDT setting prescaler to 2 \hideinitializer
#define WWDT_PRESCALER_4 (2UL << 8) ///< WWDT setting prescaler to 4 \hideinitializer
#define WWDT_PRESCALER_8 (3UL << 8) ///< WWDT setting prescaler to 8 \hideinitializer
#define WWDT_PRESCALER_16 (4UL << 8) ///< WWDT setting prescaler to 16 \hideinitializer
#define WWDT_PRESCALER_32 (5UL << 8) ///< WWDT setting prescaler to 32 \hideinitializer
#define WWDT_PRESCALER_64 (6UL << 8) ///< WWDT setting prescaler to 64 \hideinitializer
#define WWDT_PRESCALER_128 (7UL << 8) ///< WWDT setting prescaler to 128 \hideinitializer
#define WWDT_PRESCALER_192 (8UL << 8) ///< WWDT setting prescaler to 192 \hideinitializer
#define WWDT_PRESCALER_256 (9UL << 8) ///< WWDT setting prescaler to 256 \hideinitializer
#define WWDT_PRESCALER_384 (0xAUL << 8) ///< WWDT setting prescaler to 384 \hideinitializer
#define WWDT_PRESCALER_512 (0xBUL << 8) ///< WWDT setting prescaler to 512 \hideinitializer
#define WWDT_PRESCALER_768 (0xCUL << 8) ///< WWDT setting prescaler to 768 \hideinitializer
#define WWDT_PRESCALER_1024 (0xDUL << 8) ///< WWDT setting prescaler to 1024 \hideinitializer
#define WWDT_PRESCALER_1536 (0xEUL << 8) ///< WWDT setting prescaler to 1536 \hideinitializer
#define WWDT_PRESCALER_2048 (0xFUL << 8) ///< WWDT setting prescaler to 2048 \hideinitializer
#define WWDT_PRESCALER_1 (0UL << 8) ///< WWDT setting prescaler to 1 \hideinitializer
#define WWDT_PRESCALER_2 (1UL << 8) ///< WWDT setting prescaler to 2 \hideinitializer
#define WWDT_PRESCALER_4 (2UL << 8) ///< WWDT setting prescaler to 4 \hideinitializer
#define WWDT_PRESCALER_8 (3UL << 8) ///< WWDT setting prescaler to 8 \hideinitializer
#define WWDT_PRESCALER_16 (4UL << 8) ///< WWDT setting prescaler to 16 \hideinitializer
#define WWDT_PRESCALER_32 (5UL << 8) ///< WWDT setting prescaler to 32 \hideinitializer
#define WWDT_PRESCALER_64 (6UL << 8) ///< WWDT setting prescaler to 64 \hideinitializer
#define WWDT_PRESCALER_128 (7UL << 8) ///< WWDT setting prescaler to 128 \hideinitializer
#define WWDT_PRESCALER_192 (8UL << 8) ///< WWDT setting prescaler to 192 \hideinitializer
#define WWDT_PRESCALER_256 (9UL << 8) ///< WWDT setting prescaler to 256 \hideinitializer
#define WWDT_PRESCALER_384 (0xAUL << 8) ///< WWDT setting prescaler to 384 \hideinitializer
#define WWDT_PRESCALER_512 (0xBUL << 8) ///< WWDT setting prescaler to 512 \hideinitializer
#define WWDT_PRESCALER_768 (0xCUL << 8) ///< WWDT setting prescaler to 768 \hideinitializer
#define WWDT_PRESCALER_1024 (0xDUL << 8) ///< WWDT setting prescaler to 1024 \hideinitializer
#define WWDT_PRESCALER_1536 (0xEUL << 8) ///< WWDT setting prescaler to 1536 \hideinitializer
#define WWDT_PRESCALER_2048 (0xFUL << 8) ///< WWDT setting prescaler to 2048 \hideinitializer
#define WWDT_RELOAD_WORD (0x00005AA5) ///< Fill this value to RLD register to reload WWDT counter \hideinitializer
#define WWDT_RELOAD_WORD (0x00005AA5) ///< Fill this value to RLD register to reload WWDT counter \hideinitializer
/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */

22
bsp/nuvoton/libraries/nuc980/Driver/Source/nu_crypto.c
View File

@ -1372,7 +1372,7 @@ int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *messag
Reg2Hex(pCurve->Echar, temp_result1, R);
/*
* 4. Compute s = k ? 1 ｝ (e + d ｝ r)(mod n). If s = 0, go to step 2
* 4. Compute s = k ? 1 * (e + d * r)(mod n). If s = 0, go to step 2
* (1) Write the curve order to N registers according
* (2) Write 0x1 to Y1 registers
* (3) Write the random integer k to X1 registers according
@ -1602,7 +1602,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
#endif
/*
* 4. Compute u1 = e ｝ w (mod n) and u2 = r ｝ w (mod n)
* 4. Compute u1 = e * w (mod n) and u2 = r * w (mod n)
* (1) Write the curve order and curve length to N ,M registers
* (2) Write e, w to X1, Y1 registers
* (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
@ -1684,7 +1684,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
#endif
/*
* 5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
* 5. Compute X' (x1' y1') = u1 * G + u2 * Q
* (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
* (2) Write the point G(x, y) to X1, Y1 registers
* (3) Write u1 to K registers
@ -1703,17 +1703,17 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
* (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
* (17) Set START(CRPT_ECC_CTL[0]) to 1
* (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
* (19) Read X1, Y1 registers to get X・(x1・, y1・)
* (19) Read X1, Y1 registers to get X('x1', y1')
* (20) Write the curve order and curve length to N ,M registers
* (21) Write x1・ to X1 registers
* (21) Write x1' to X1 registers
* (22) Write 0x0 to Y1 registers
* (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
* (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
* (25) Set START(CRPT_ECC_CTL[0]) to 1
* (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
* (27) Read X1 registers to get x1・ (mod n)
* (27) Read X1 registers to get x1' (mod n)
*
* 6. The signature is valid if x1・ = r, otherwise it is invalid
* 6. The signature is valid if x1' = r, otherwise it is invalid
*/
/*
@ -1797,7 +1797,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
run_ecc_codec(crpt, ECCOP_POINT_ADD);
/* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
/* (19) Read X1, Y1 registers to get X'(x1' y1') */
for (i = 0; i < 18; i++)
{
temp_x[i] = crpt->ECC_X1[i];
@ -1819,7 +1819,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
Hex2Reg(pCurve->Eorder, crpt->ECC_N);
/*
* (21) Write x1・ to X1 registers
* (21) Write x1' to X1 registers
* (22) Write 0x0 to Y1 registers
*/
for (i = 0; i < 18; i++)
@ -1837,11 +1837,11 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
/* (27) Read X1 registers to get x1・ (mod n) */
/* (27) Read X1 registers to get x1' (mod n) */
Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
/* 6. The signature is valid if x1・ = r, otherwise it is invalid */
/* 6. The signature is valid if x1' = r, otherwise it is invalid */
/* Compare with test pattern to check if r is correct or not */
if (ecc_strcmp(temp_hex_str, R) != 0)

2
bsp/nuvoton/libraries/nuc980/UsbHostLib/inc/usbh_lib.h
View File

@ -53,7 +53,7 @@ extern "C"
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */

2
bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_clkcfg.h
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_clkcfg.h
* @version V1.05
* @Date 2020/11/11-11:43:32
* @Date 2020/11/11-11:43:32
* @brief NuMicro generated code file
*
* SPDX-License-Identifier: Apache-2.0

8
bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_modclkcfg.c
* @version V1.05
* @Date 2020/11/11-11:43:32
* @Date 2020/11/11-11:43:32
* @brief NuMicro generated code file
*
* SPDX-License-Identifier: Apache-2.0
@ -1160,14 +1160,14 @@ void nutool_modclkcfg_init_base(void)
{
/* LXT source from external LXT */
CLK_EnableModuleClock(RTC_MODULE);
RTC->LXTCTL &= ~(RTC_LXTCTL_LIRC32KEN_Msk|RTC_LXTCTL_C32KSEL_Msk);
RTC->LXTCTL &= ~(RTC_LXTCTL_LIRC32KEN_Msk | RTC_LXTCTL_C32KSEL_Msk);
CLK_DisableModuleClock(RTC_MODULE);
/* Enable clock source */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk|CLK_PWRCTL_LXTEN_Msk|CLK_PWRCTL_HXTEN_Msk|CLK_PWRCTL_HIRC48EN_Msk|CLK_PWRCTL_MIRCEN_Msk);
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk | CLK_PWRCTL_LXTEN_Msk | CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_HIRC48EN_Msk | CLK_PWRCTL_MIRCEN_Msk);
/* Waiting for clock source ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk|CLK_STATUS_LXTSTB_Msk|CLK_STATUS_HXTSTB_Msk|CLK_STATUS_HIRC48STB_Msk|CLK_STATUS_MIRCSTB_Msk);
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_LXTSTB_Msk | CLK_STATUS_HXTSTB_Msk | CLK_STATUS_HIRC48STB_Msk | CLK_STATUS_MIRCSTB_Msk);
/* Disable PLL first to avoid unstable when setting PLL */
CLK_DisablePLL();

2
bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.h
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_modclkcfg.h
* @version V1.05
* @Date 2020/11/11-11:43:32
* @Date 2020/11/11-11:43:32
* @brief NuMicro generated code file
*
* SPDX-License-Identifier: Apache-2.0

34
bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_pincfg.c
* @version V1.21
* @Date 2020/11/11-12:06:36
* @Date 2020/11/11-12:06:36
* @brief NuMicro generated code file
*
* Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
@ -318,44 +318,44 @@ void pincfg_init_slcd(void)
SEG 33~36 : PH.7, PH.6, PH.5, PH.4
SEG 37~39 : PG.4, PG.3, PG.2
*/
/* COM 0~5 */
SYS->GPC_MFPL = (SYS->GPC_MFPL &
~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk |
SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC5MFP_Msk)) |
SYS->GPC_MFPL = (SYS->GPC_MFPL &
~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk |
SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC5MFP_Msk)) |
(LCD_COM0_PC0 | LCD_COM1_PC1 | LCD_COM2_PC2 | LCD_COM3_PC3 | LCD_COM4_PC4 | LCD_COM5_PC5);
/* COM 6~7 */
SYS->GPD_MFPH = (SYS->GPD_MFPH & ~(SYS_GPD_MFPH_PD8MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk)) |
(LCD_COM6_PD8 | LCD_COM7_PD9);
/* SEG 0 */
SYS->GPD_MFPH = (SYS->GPD_MFPH & ~SYS_GPD_MFPH_PD14MFP_Msk) | LCD_SEG0_PD14;
/* SEG 1~4 */
SYS->GPH_MFPH = (SYS->GPH_MFPH & ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk | SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk)) |
(LCD_SEG1_PH11 | LCD_SEG2_PH10 | LCD_SEG3_PH9 | LCD_SEG4_PH8);
/* SEG 5~12 */
SYS->GPE_MFPL = (SYS->GPE_MFPL &
~(SYS_GPE_MFPL_PE0MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk |
SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE7MFP_Msk)) |
SYS->GPE_MFPL = (SYS->GPE_MFPL &
~(SYS_GPE_MFPL_PE0MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk |
SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE7MFP_Msk)) |
(LCD_SEG5_PE0 | LCD_SEG6_PE1 | LCD_SEG7_PE2 | LCD_SEG8_PE3 |
LCD_SEG9_PE4 | LCD_SEG10_PE5 | LCD_SEG11_PE6 | LCD_SEG12_PE7);
/* SEG 13~14 */
SYS->GPD_MFPL = (SYS->GPD_MFPL & ~(SYS_GPD_MFPL_PD6MFP_Msk | SYS_GPD_MFPL_PD7MFP_Msk)) | (LCD_SEG13_PD6 | LCD_SEG14_PD7);
/* SEG 15~21 */
SYS->GPG_MFPH = (SYS->GPG_MFPH &
~(SYS_GPG_MFPH_PG15MFP_Msk | SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk |
SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk)) |
SYS->GPG_MFPH = (SYS->GPG_MFPH &
~(SYS_GPG_MFPH_PG15MFP_Msk | SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk |
SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk)) |
(LCD_SEG15_PG15 | LCD_SEG16_PG14 | LCD_SEG17_PG13 | LCD_SEG18_PG12 |
LCD_SEG19_PG11 | LCD_SEG20_PG10 | LCD_SEG21_PG9);
/* SEG 22~23 */
SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk)) | (LCD_SEG22_PE15 | LCD_SEG23_PE14);
/* SEG 24~29 */
SYS->GPA_MFPL = (SYS->GPA_MFPL &
~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk |
SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk)) |
(LCD_SEG24_PA0 | LCD_SEG25_PA1 | LCD_SEG26_PA2 | LCD_SEG27_PA3 | LCD_SEG28_PA4 |LCD_SEG29_PA5);
SYS->GPA_MFPL = (SYS->GPA_MFPL &
~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk |
SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk)) |
(LCD_SEG24_PA0 | LCD_SEG25_PA1 | LCD_SEG26_PA2 | LCD_SEG27_PA3 | LCD_SEG28_PA4 | LCD_SEG29_PA5);
/* SEG 30~32 */
SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk)) |
SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk)) |
(LCD_SEG30_PE10 | LCD_SEG31_PE9 | LCD_SEG32_PE8);
/* SEG 33~36 */
SYS->GPH_MFPL = (SYS->GPH_MFPL & ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk)) |

2
bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.h
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_pincfg.h
* @version V1.21
* @Date 2020/11/11-12:06:36
* @Date 2020/11/11-12:06:36
* @brief NuMicro generated code file
*
* Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.

2
bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_pincfg.c
* @version V1.20
* @Date 2020/05/27-17:17:14
* @Date 2020/05/27-17:17:14
* @brief NuMicro generated code file
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/nuvoton/numaker-pfm-m487/board/NuPinConfig/nutool_pincfg.h
View File

@ -1,7 +1,7 @@
/****************************************************************************
* @file nutool_pincfg.h
* @version V1.20
* @Date 2020/05/27-17:17:14
* @Date 2020/05/27-17:17:14
* @brief NuMicro generated code file
*
* SPDX-License-Identifier: Apache-2.0