[kernel] fixup of data racing accessing percpu objects (#8475)
Signed-off-by: Shell <smokewood@qq.com>
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cc157baf23
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@ -835,6 +835,16 @@ while (0)
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#define RT_DEBUG_SCHEDULER_AVAILABLE(need_check)
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#endif /* RT_DEBUGING_CONTEXT */
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rt_inline rt_bool_t rt_in_thread_context(void)
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{
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return rt_thread_self() != RT_NULL && rt_interrupt_get_nest() == 0;
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}
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rt_inline rt_bool_t rt_scheduler_is_available(void)
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{
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return !rt_hw_interrupt_is_disabled() && rt_critical_level() == 0 && rt_in_thread_context();
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}
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/**@}*/
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#ifdef __cplusplus
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -7,6 +7,7 @@
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* Date Author Notes
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* 2021-05-18 Jesven the first version
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* 2023-06-24 WangXiaoyao Support backtrace for user thread
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* 2024-01-06 Shell Fix barrier on irq_disable/enable
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*/
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#ifndef __ASSEMBLY__
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@ -36,7 +37,7 @@ int rt_hw_cpu_id(void)
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.weak rt_hw_cpu_id
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.type rt_hw_cpu_id, @function
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rt_hw_cpu_id:
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mrs x0, tpidr_el1 /* MPIDR_EL1: Multi-Processor Affinity Register */
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mrs x0, tpidr_el1
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ret
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/*
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@ -314,7 +315,8 @@ rt_hw_interrupt_is_disabled:
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rt_hw_interrupt_disable:
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MRS X0, DAIF
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MSR DAIFSet, #3
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DSB SY
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DSB NSH
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ISB
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RET
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/*
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@ -322,7 +324,8 @@ rt_hw_interrupt_disable:
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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DSB SY
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ISB
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DSB NSH
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AND X0, X0, #0xc0
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MRS X1, DAIF
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BIC X1, X1, #0xc0
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@ -580,4 +583,4 @@ START_POINT(vector_serror)
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STP X0, X1, [SP, #-0x10]!
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BL rt_hw_trap_serror
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b .
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START_POINT_END(vector_exception)
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START_POINT_END(vector_serror)
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@ -89,6 +89,8 @@ void rt_tick_increase(void)
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rt_base_t level;
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rt_atomic_t oldval = 0;
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RT_ASSERT(rt_interrupt_get_nest() > 0);
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RT_OBJECT_HOOK_CALL(rt_tick_hook, ());
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/* increase the global tick */
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#ifdef RT_USING_SMP
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@ -136,6 +136,7 @@ RTM_EXPORT(rt_spin_unlock_irqrestore)
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*/
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struct rt_cpu *rt_cpu_self(void)
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{
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RT_ASSERT(!rt_scheduler_is_available());
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return &_cpus[rt_hw_cpu_id()];
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}
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@ -13,6 +13,7 @@
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* 2022-01-07 Gabriel Moving __on_rt_xxxxx_hook to irq.c
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* 2022-07-04 Yunjie fix RT_DEBUG_LOG
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* 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable
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* 2024-01-05 Shell Fixup of data racing in rt_interrupt_get_nest
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*/
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#include <rthw.h>
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@ -114,7 +115,13 @@ RTM_EXPORT(rt_interrupt_leave);
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*/
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rt_weak rt_uint8_t rt_interrupt_get_nest(void)
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{
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return rt_atomic_load(&rt_interrupt_nest);
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rt_uint8_t ret;
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rt_base_t level;
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level = rt_hw_local_irq_disable();
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ret = rt_atomic_load(&rt_interrupt_nest);
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rt_hw_local_irq_enable(level);
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return ret;
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}
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RTM_EXPORT(rt_interrupt_get_nest);
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@ -31,6 +31,7 @@
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* 2023-03-27 rose_man Split into scheduler upc and scheduler_mp.c
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* 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable
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* 2023-12-10 xqyjlj use rt_hw_spinlock
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* 2024-01-05 Shell Fixup of data racing in rt_critical_level
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*/
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#include <rtthread.h>
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@ -848,8 +849,17 @@ RTM_EXPORT(rt_exit_critical);
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*/
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rt_uint16_t rt_critical_level(void)
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{
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struct rt_thread *current_thread = rt_cpu_self()->current_thread;
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return rt_atomic_load(&(current_thread->critical_lock_nest));
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rt_base_t level;
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rt_uint16_t critical_lvl;
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struct rt_thread *current_thread;
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level = rt_hw_local_irq_disable();
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current_thread = rt_cpu_self()->current_thread;
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critical_lvl = rt_atomic_load(&(current_thread->critical_lock_nest));
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rt_hw_local_irq_enable(level);
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return critical_lvl;
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}
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RTM_EXPORT(rt_critical_level);
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@ -658,6 +658,8 @@ void rt_timer_check(void)
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rt_base_t level;
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rt_list_t list;
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RT_ASSERT(rt_interrupt_get_nest() > 0);
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#ifdef RT_USING_SMP
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if (rt_hw_cpu_id() != 0)
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{
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