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[libcpu/risc-v/c906] add ioremap && default param (#7345)

This commit is contained in:
flyingcys 2023-04-24 09:21:15 +08:00 committed by GitHub
parent a09a2ea6fe
commit cbedb6b40b
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 35 additions and 14 deletions
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4
libcpu/risc-v/t-head/c906/io.h
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@ -40,13 +40,13 @@ static inline uint32_t readl(const volatile void *addr)
static inline void write_reg(
uint32_t val, volatile void *addr, unsigned offset)
{
writel(val, addr + offset);
writel(val, (void *)((rt_size_t)addr + offset));
}
static inline uint32_t read_reg(
const volatile void *addr, unsigned offset)
{
return readl(addr + offset);
return readl((void *)((rt_size_t)addr + offset));
}
#endif // ARCH_IO_H

31
libcpu/risc-v/t-head/c906/plic.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,6 +7,7 @@
* Date Author Notes
* 2021-10-19 JasonHu first version
* 2021-11-12 JasonHu fix bug that not intr on f133
* 2023-04-22 flyingcys add plic register ioremap
*/
#include <rtthread.h>
@ -30,13 +31,23 @@ struct plic_handler
rt_inline void plic_toggle(struct plic_handler *handler, int hwirq, int enable);
struct plic_handler c906_plic_handlers[C906_NR_CPUS];
static void *c906_irq_priority[INTERRUPTS_MAX] = {RT_NULL};
rt_inline void plic_irq_toggle(int hwirq, int enable)
{
int cpu = 0;
void *priority_addr;
/* set priority of interrupt, interrupt 0 is zero. */
writel(enable, c906_plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);
priority_addr = (void *)((rt_size_t)c906_plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);
#ifdef RT_USING_SMART
if (c906_irq_priority[hwirq] == RT_NULL)
{
c906_irq_priority[hwirq] = rt_ioremap(priority_addr, 0x1000);
}
priority_addr = c906_irq_priority[hwirq];
#endif
writel(enable, priority_addr);
struct plic_handler *handler = &c906_plic_handlers[cpu];
if (handler->present)
@ -76,7 +87,7 @@ void plic_complete(int irqno)
int cpu = 0;
struct plic_handler *handler = &c906_plic_handlers[cpu];
writel(irqno, handler->hart_base + CONTEXT_CLAIM);
writel(irqno, (void *)((rt_size_t)handler->hart_base + CONTEXT_CLAIM));
}
void plic_disable_irq(int irqno)
@ -101,7 +112,7 @@ void plic_handle_irq(void)
unsigned int irq;
struct plic_handler *handler = &c906_plic_handlers[cpu];
void *claim = handler->hart_base + CONTEXT_CLAIM;
void *claim = (void *)((rt_size_t)handler->hart_base + CONTEXT_CLAIM);
if (c906_plic_regs == RT_NULL || !handler->present)
{
@ -128,7 +139,7 @@ void plic_handle_irq(void)
rt_inline void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
{
uint32_t *reg = handler->enable_base + (hwirq / 32) * sizeof(uint32_t);
uint32_t *reg = (uint32_t *)((rt_size_t)handler->enable_base + (hwirq / 32) * sizeof(uint32_t));
uint32_t hwirq_mask = 1 << (hwirq % 32);
if (enable)
@ -188,11 +199,15 @@ void plic_init(void)
}
handler->present = RT_TRUE;
handler->hart_base = c906_plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
handler->enable_base = c906_plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
handler->hart_base = (void *)((rt_size_t)c906_plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART);
handler->enable_base = (void *)((rt_size_t)c906_plic_regs + ENABLE_BASE + i * ENABLE_PER_HART);
#ifdef RT_USING_SMART
handler->hart_base = rt_ioremap(handler->hart_base, 0x1000);
handler->enable_base = rt_ioremap(handler->enable_base, 0x1000);
#endif
done:
/* priority must be > threshold to trigger an interrupt */
writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
writel(threshold, (void *)((rt_size_t)handler->hart_base + CONTEXT_THRESHOLD));
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
{
plic_toggle(handler, hwirq, 0);

5
libcpu/risc-v/t-head/c906/plic.h
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@ -1,11 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-19 JasonHu first version
* 2023-04-22 flyingcys add C906_PLIC_PHY_ADDR macro judge
*/
#ifndef __RISCV64_PLIC_H__
@ -13,7 +14,9 @@
#include <rt_interrupt.h>
#ifndef C906_PLIC_PHY_ADDR
#define C906_PLIC_PHY_ADDR (0x10000000)
#endif
#define C906_PLIC_NR_EXT_IRQS (IRQ_MAX_NR)
#define C906_NR_CPUS (NR_CPUS)

4
libcpu/risc-v/t-head/c906/rt_interrupt.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -16,7 +16,9 @@
#define NR_CPUS 1
#define IRQ_OFFSET 16
#ifndef IRQ_MAX_NR
#define IRQ_MAX_NR 207
#endif
#define INTERRUPTS_MAX (IRQ_OFFSET + IRQ_MAX_NR)
enum {

5
libcpu/risc-v/t-head/c906/tick.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,8 +12,9 @@
#define TICK_H__
/* timer clock is 24 MHZ */
#ifndef TIMER_CLK_FREQ
#define TIMER_CLK_FREQ (24000000)
#endif
int tick_isr(void);
int rt_hw_tick_init(void);