From 5f4b780558366ed7fd72e08bdfada6243252d2fc Mon Sep 17 00:00:00 2001 From: Kevin Peng Date: Mon, 28 Oct 2019 14:35:50 +0800 Subject: [PATCH 1/2] LPC55S69: Integration with TF-M This patch enables TF-M running on secure side and RT-Thread running on NS side by: 1. Updates the VTOR address 2. Remove a HW initialization which is already done in TF-M 3. Add a new project and linker script to build RTT in NS Note: There are no secure service calls to TF-M in this patch Change-Id: I4023a082cfb5c8df8a4f0ecc7ffee850daaadeb4 Signed-off-by: Kevin Peng Signed-off-by: Karl Zhang --- bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c | 11 + .../LPC55S69_cm33_core0_flash_ns_mdk.scf | 110 + .../lpc55s69_nxp_evk/project_ns.uvoptx | 1811 +++++++++++++++++ .../lpc55s69_nxp_evk/project_ns.uvprojx | 1157 +++++++++++ 4 files changed, 3089 insertions(+) create mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf create mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx create mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvprojx diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c index 4a7fb3f885..22e663b1f4 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +11,7 @@ * 2010-05-02 Aozima update CMSIS to 130 * 2017-08-02 XiaoYang porting to LPC54608 bsp * 2019-08-05 Magicoe porting to LPC55S69-EVK bsp + * 2020-01-01 Karl Add RT_USING_TFM support */ #include @@ -56,11 +58,20 @@ void rt_hw_board_init() /* Set the Vector Table base location at 0x10000000 */ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); #else /* VECT_TAB_FLASH */ + +#ifdef RT_USING_TFM + /* Set the Vector Table base location at 0x00020000 when RTT with TF-M*/ + SCB->VTOR = (0x00020000 & NVIC_VTOR_MASK); +#else /* Set the Vector Table base location at 0x00000000 */ SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); #endif +#endif +#ifndef RT_USING_TFM + /* This init has finished in secure side of TF-M */ BOARD_BootClockPLL150M(); +#endif //BOARD_BootClockFROHF96M(); /* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/ diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf new file mode 100644 index 0000000000..bb14890505 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf @@ -0,0 +1,110 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* + * Original code taken from RTT project at: + * https://github.com/RT-Thread/rt-thread + * File: bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf + * Git SHA of the original version: 64945ba882d651a14933eb4e7b3d93d10d6daae1 + */ + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x1000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x00071E00 + +#define m_core1_image_start 0x00072000 +#define m_core1_image_size 0x00026000 + +#if (defined(__use_shmem__)) + #define m_data_start 0x20000000 + #define m_data_size 0x00031800 + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x20000000 + #define m_data_size 0x00033000 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx new file mode 100644 index 0000000000..7f28d506da --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx @@ -0,0 +1,1811 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvprojx b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvprojx new file mode 100644 index 0000000000..4cfb8a82cd --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvprojx @@ -0,0 +1,1157 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc55s6x + 0x4 + ARM-ADS + 6120000::V6.12::.\ARMCLANG + 6120000::V6.12::.\ARMCLANG + 1 + + + LPC55S69JBD100:cm33_core0 + NXP + NXP.LPC55S69_DFP.12.0.0 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) + 0 + $$Device:LPC55S69JBD100$fsl_device_registers.h + + + + + + + + + + $$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-lpc55s6x + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 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+ CPU_LPC55S69JBD100_cm33_core0, RT_USING_ARM_LIBC, RT_USING_TFM + + .;..\..\..\include;applications;board;board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port + + + + 1 + 0 + 0 + 0 + 0 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..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c + + + fsl_sctimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c + + + fsl_sdif.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c + + + fsl_spi.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c + + + fsl_spi_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c + + + fsl_sysctl.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c + + + fsl_usart.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c + + + fsl_usart_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c + + + fsl_utick.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c + + + fsl_wwdt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c + + + fsl_sd.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c + + + fsl_sdmmc_common.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c + + + fsl_sdmmc_event.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c + + + fsl_sdmmc_host.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c + + + arm_keil_lib_power_cm33_core0.lib + 4 + ..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib + + + + + + + + + + + + + +
From be4e2395ff7ac58ed188fc31a93353d74ed6deb6 Mon Sep 17 00:00:00 2001 From: Karl Zhang Date: Thu, 2 Jan 2020 14:42:30 +0800 Subject: [PATCH 2/2] LPC55S69: Update the flash layout to fit RTT in NS RTT fits in NS flash when enabled TF-M for secure. Change-Id: Icfd796b7fbe8fba76f713f9d5a14bbdcb5dcd9d5 Signed-off-by: Karl Zhang --- .../LPC55S69_cm33_core0_flash_ns_mdk.scf | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf index bb14890505..e0ee619399 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf @@ -14,6 +14,7 @@ ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP +** Copyright 2019-2020 Arm Limited. All rights reserved. ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -46,23 +47,23 @@ #define Heap_Size 0x1000 #endif -#define m_interrupts_start 0x00000000 +#define m_interrupts_start 0x00020000 #define m_interrupts_size 0x00000200 -#define m_text_start 0x00000200 -#define m_text_size 0x00071E00 +#define m_text_start 0x00020200 +#define m_text_size 0x00031000 #define m_core1_image_start 0x00072000 #define m_core1_image_size 0x00026000 #if (defined(__use_shmem__)) - #define m_data_start 0x20000000 - #define m_data_size 0x00031800 - #define m_rpmsg_sh_mem_start 0x20031800 - #define m_rpmsg_sh_mem_size 0x00001800 + #define m_data_start 0x20033000 + #define m_data_size 0x00010800 + #define m_rpmsg_sh_mem_start 0x20043800 + #define m_rpmsg_sh_mem_size 0x00000800 #else - #define m_data_start 0x20000000 - #define m_data_size 0x00033000 + #define m_data_start 0x20033000 + #define m_data_size 0x0000cc00 #endif #define m_usb_sram_start 0x40100000