[IFX]Add capsense support

bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/ports/slider_sample.c

@@ -38,6 +38,7 @@ typedef struct
 } led_data_t;
 
 static rt_sem_t trans_done_semphr = RT_NULL;
+static rt_thread_t sld_thread = RT_NULL;
 
 #ifndef RT_USING_PWM
     #error You need enable PWM to use this sample
@@ -222,15 +223,15 @@ int Slider_ctrl_sample(void)
 {
     rt_err_t ret = RT_EOK;
 
-    rt_thread_t thread = rt_thread_create("slider_th",
+    sld_thread = rt_thread_create("slider_th",
                                   Slider_thread_entry,
                                   RT_NULL,
                                   1024,
                                   25,
                                   10);
-    if (thread != RT_NULL)
+    if (sld_thread != RT_NULL)
     {
-        rt_thread_startup(thread);
+        rt_thread_startup(sld_thread);
     }
     else
     {

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/ports/slider_sample.c

@@ -38,6 +38,7 @@ typedef struct
 } led_data_t;
 
 static rt_sem_t trans_done_semphr = RT_NULL;
+static rt_thread_t sld_thread = RT_NULL;
 
 #ifndef RT_USING_PWM
     #error You need enable PWM to use this sample
@@ -222,15 +223,15 @@ int Slider_ctrl_sample(void)
 {
     rt_err_t ret = RT_EOK;
 
-    rt_thread_t thread = rt_thread_create("slider_th",
+    sld_thread = rt_thread_create("slider_th",
                                   Slider_thread_entry,
                                   RT_NULL,
                                   1024,
                                   25,
                                   10);
-    if (thread != RT_NULL)
+    if (sld_thread != RT_NULL)
     {
-        rt_thread_startup(thread);
+        rt_thread_startup(sld_thread);
     }
     else
     {

bsp/Infineon/psoc6-evaluationkit-062S2/.config

@@ -740,3 +740,8 @@ CONFIG_BSP_USING_UART0=y
 # CONFIG_BSP_USING_WDT is not set
 # CONFIG_BSP_USING_DAC is not set
 # CONFIG_BSP_USING_TIM is not set
+
+#
+# Board extended module Drivers
+#
+# CONFIG_BSP_USING_SLIDER is not set

bsp/Infineon/psoc6-evaluationkit-062S2/.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1522148012290462689" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1210189509587013598" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

bsp/Infineon/psoc6-evaluationkit-062S2/.settings/projcfg.ini

@@ -1,5 +1,5 @@
 #RT-Thread Studio Project Configuration
-#Thu Jan 12 11:11:44 CST 2023
+#Wed Jan 18 15:54:34 CST 2023
 project_type=rt-thread
 chip_name=CY8C624ABZI
 os_branch=full
@@ -9,12 +9,12 @@ selected_rtt_version=latest
 cfg_version=v3.0
 board_base_nano_proj=False
 is_use_scons_build=True
-output_project_path=E\:/software/RT-ThreadStudio/workspace
+output_project_path=E\:\\workspace_work\\rt-thread-5.0\\bsp\\Infineon
 project_base_bsp=true
 hardware_adapter=KitProg3
 project_name=1111
 is_base_example_project=False
 board_name=psoc6-cy8ckit-062S2-43012
 device_vendor=Infineon 
-bsp_version=1.0.0
 bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
+bsp_version=1.0.0

bsp/Infineon/psoc6-evaluationkit-062S2/.settings/project.OpenOCD.Debug.rttlaunch

@@ -12,7 +12,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd_debugger_relative_path}openocd/bin/openocd.exe"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s ../scripts -f interface/kitprog3.cfg -f target/psoc6_2m.cfg -c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot; -c &quot;gdb_port 3332&quot; -c &quot;psoc6 sflash_restrictions 1&quot; -c &quot;init; reset init&quot;"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
@@ -21,7 +21,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon psoc6 reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.hex}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
@@ -31,23 +31,23 @@
 <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="entry"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="E:\software\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\ARM\GNU_Tools_for_ARM_Embedded_Processors\10.2.1\bin\arm-none-eabi-gdb.exe"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
 <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
 <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/dist_ide_project"/>
+<listEntry value="/project"/>
 </listAttribute>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
 <listEntry value="4"/>

bsp/Infineon/psoc6-evaluationkit-062S2/board/Kconfig

@@ -250,4 +250,11 @@ menu "On-chip Peripheral Drivers"
         endif
 endmenu
 
+menu "Board extended module Drivers"
+
+    config BSP_USING_SLIDER
+        bool "Enable Slider Demo"
+        default n
+endmenu
+
 endmenu

bsp/Infineon/psoc6-evaluationkit-062S2/board/ports/slider_sample.c

@@ -38,6 +38,7 @@ typedef struct
 } led_data_t;
 
 static rt_sem_t trans_done_semphr = RT_NULL;
+static rt_thread_t sld_thread = RT_NULL;
 
 #ifndef RT_USING_PWM
     #error You need enable PWM to use this sample
@@ -222,15 +223,15 @@ int Slider_ctrl_sample(void)
 {
     rt_err_t ret = RT_EOK;
 
-    rt_thread_t thread = rt_thread_create("slider_th",
+    sld_thread = rt_thread_create("slider_th",
                                   Slider_thread_entry,
                                   RT_NULL,
                                   1024,
                                   25,
                                   10);
-    if (thread != RT_NULL)
+    if (sld_thread != RT_NULL)
     {
-        rt_thread_startup(thread);
+        rt_thread_startup(sld_thread);
     }
     else
     {

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -5,12 +5,12 @@
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -5,12 +5,12 @@
 * Simple wrapper header containing all generated files.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -5,12 +5,12 @@
 * Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c

@@ -7,7 +7,7 @@
 * CapSense Configurator 4.0.0.6195
 *
 ********************************************************************************
-* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
 * or an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -132,7 +132,7 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
     .numSns = CY_CAPSENSE_SENSOR_COUNT,
     .numWd = CY_CAPSENSE_WIDGET_COUNT,
     .csdEn = CY_CAPSENSE_ENABLE,
-    .csxEn = CY_CAPSENSE_ENABLE,
+    .csxEn = CY_CAPSENSE_DISABLE,
     #if (CY_CAPSENSE_MW_VERSION < 300)
         .mfsEn = CY_CAPSENSE_DISABLE,
     #endif
@@ -168,13 +168,13 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
     .ptrCsdContext = &cy_csd_0_context,
     .portCmod = Cmod_PORT,
     .portCsh = NULL,
-    .portCintA = CintA_PORT,
+    .portCintA = NULL,
-    .portCintB = CintB_PORT,
+    .portCintB = NULL,
     .pinCmod = Cmod_PIN,
     .portCshNum = 0u,
     .pinCsh = 0u,
-    .pinCintA = CintA_PIN,
+    .pinCintA = 0u,
-    .pinCintB = CintB_PIN,
+    .pinCintB = 0u,
     .csdShieldEn = CY_CAPSENSE_DISABLE,
     .csdInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
     #if (CY_CAPSENSE_MW_VERSION >= 300)
@@ -202,7 +202,7 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
     .csdMfsDividerOffsetF2 = 2u,
     .csxRawTarget = 40u,
     .csxIdacGainInitIndex = 2u,
-    .csxIdacAutocalEn = CY_CAPSENSE_ENABLE,
+    .csxIdacAutocalEn = CY_CAPSENSE_DISABLE,
     .csxCalibrationError = 20u,
     .csxFineInitTime = 10u,
     .csxInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
@@ -409,48 +409,28 @@ static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_
 #if (CY_CAPSENSE_ELTD_COUNT > 0)
     static const cy_stc_capsense_electrode_config_t cy_capsense_electrodeConfig[CY_CAPSENSE_ELTD_COUNT] =
     {
-        { /* Button0_Rx0 */
-            .ptrPin = &cy_capsense_pinConfig[0u],
-            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
-            .numPins = 1u,
-        },
-        { /* Button0_Tx */
-            .ptrPin = &cy_capsense_pinConfig[1u],
-            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
-            .numPins = 1u,
-        },
-        { /* Button1_Rx0 */
-            .ptrPin = &cy_capsense_pinConfig[2u],
-            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
-            .numPins = 1u,
-        },
-        { /* Button1_Tx */
-            .ptrPin = &cy_capsense_pinConfig[3u],
-            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
-            .numPins = 1u,
-        },
         { /* LinearSlider0_Sns0 */
-            .ptrPin = &cy_capsense_pinConfig[4u],
+            .ptrPin = &cy_capsense_pinConfig[0u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns1 */
-            .ptrPin = &cy_capsense_pinConfig[5u],
+            .ptrPin = &cy_capsense_pinConfig[1u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns2 */
-            .ptrPin = &cy_capsense_pinConfig[6u],
+            .ptrPin = &cy_capsense_pinConfig[2u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns3 */
-            .ptrPin = &cy_capsense_pinConfig[7u],
+            .ptrPin = &cy_capsense_pinConfig[3u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns4 */
-            .ptrPin = &cy_capsense_pinConfig[8u],
+            .ptrPin = &cy_capsense_pinConfig[4u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
@@ -459,131 +439,19 @@ static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_
 
 static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENSE_WIDGET_COUNT] =
 {
-    { /* Button0 */
+    { /* LinearSlider0 */
         .ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
         .ptrSnsContext = &cy_capsense_tuner.sensorContext[0u],
         .ptrEltdConfig = &cy_capsense_electrodeConfig[0u],
 #if (CY_CAPSENSE_BIST_SUPPORTED)
         .ptrEltdCapacitance = NULL,
         .ptrBslnInv = NULL,
-#endif
-        .ptrNoiseEnvelope = NULL,
-        .ptrRawFilterHistory = NULL,
-        .ptrRawFilterHistoryLow = NULL,
-        .iirCoeff = 128u,
-        .ptrDebounceArr = &cy_capsense_debounce[0u],
-        .ptrDiplexTable = NULL,
-        .centroidConfig = 0u,
-        .xResolution = 0u,
-        .yResolution = 0u,
-        .numSns = 1u,
-        .numCols = 1u,
-        .numRows = 1u,
-        .ptrPosFilterHistory = NULL,
-        .ptrCsxTouchHistory = NULL,
-        .ptrCsxTouchBuffer = NULL,
-        .ptrCsdTouchBuffer = NULL,
-        .ptrGestureConfig = NULL,
-        .ptrGestureContext = NULL,
-        .ballisticConfig = {
-            .accelCoeff = 9u,
-            .speedCoeff = 2u,
-            .divisorValue = 4u,
-            .speedThresholdX = 3u,
-            .speedThresholdY = 4u,
-        },
-        .ptrBallisticContext = NULL,
-        .aiirConfig = {
-            .maxK = 60u,
-            .minK = 1u,
-            .noMovTh = 3u,
-            .littleMovTh = 7u,
-            .largeMovTh = 12u,
-            .divVal = 64u,
-        },
-        .advConfig = {
-            .penultimateTh = 100u,
-            .virtualSnsTh = 100u,
-            .crossCouplingTh = 5u,
-        },
-        .posFilterConfig = 0u,
-        .rawFilterConfig = 0u,
-        #if (CY_CAPSENSE_MW_VERSION >= 300)
-            .senseMethod = CY_CAPSENSE_CSX_GROUP,
-        #else
-            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E,
-        #endif
-        .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
-    },
-    { /* Button1 */
-        .ptrWdContext = &cy_capsense_tuner.widgetContext[1u],
-        .ptrSnsContext = &cy_capsense_tuner.sensorContext[1u],
-        .ptrEltdConfig = &cy_capsense_electrodeConfig[2u],
-#if (CY_CAPSENSE_BIST_SUPPORTED)
-        .ptrEltdCapacitance = NULL,
-        .ptrBslnInv = NULL,
-#endif
-        .ptrNoiseEnvelope = NULL,
-        .ptrRawFilterHistory = NULL,
-        .ptrRawFilterHistoryLow = NULL,
-        .iirCoeff = 128u,
-        .ptrDebounceArr = &cy_capsense_debounce[1u],
-        .ptrDiplexTable = NULL,
-        .centroidConfig = 0u,
-        .xResolution = 0u,
-        .yResolution = 0u,
-        .numSns = 1u,
-        .numCols = 1u,
-        .numRows = 1u,
-        .ptrPosFilterHistory = NULL,
-        .ptrCsxTouchHistory = NULL,
-        .ptrCsxTouchBuffer = NULL,
-        .ptrCsdTouchBuffer = NULL,
-        .ptrGestureConfig = NULL,
-        .ptrGestureContext = NULL,
-        .ballisticConfig = {
-            .accelCoeff = 9u,
-            .speedCoeff = 2u,
-            .divisorValue = 4u,
-            .speedThresholdX = 3u,
-            .speedThresholdY = 4u,
-        },
-        .ptrBallisticContext = NULL,
-        .aiirConfig = {
-            .maxK = 60u,
-            .minK = 1u,
-            .noMovTh = 3u,
-            .littleMovTh = 7u,
-            .largeMovTh = 12u,
-            .divVal = 64u,
-        },
-        .advConfig = {
-            .penultimateTh = 100u,
-            .virtualSnsTh = 100u,
-            .crossCouplingTh = 5u,
-        },
-        .posFilterConfig = 0u,
-        .rawFilterConfig = 0u,
-        #if (CY_CAPSENSE_MW_VERSION >= 300)
-            .senseMethod = CY_CAPSENSE_CSX_GROUP,
-        #else
-            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E,
-        #endif
-        .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
-    },
-    { /* LinearSlider0 */
-        .ptrWdContext = &cy_capsense_tuner.widgetContext[2u],
-        .ptrSnsContext = &cy_capsense_tuner.sensorContext[2u],
-        .ptrEltdConfig = &cy_capsense_electrodeConfig[4u],
-#if (CY_CAPSENSE_BIST_SUPPORTED)
-        .ptrEltdCapacitance = NULL,
-        .ptrBslnInv = NULL,
 #endif
         .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[0u],
         .ptrRawFilterHistory = NULL,
         .ptrRawFilterHistoryLow = NULL,
         .iirCoeff = 128u,
-        .ptrDebounceArr = &cy_capsense_debounce[2u],
+        .ptrDebounceArr = &cy_capsense_debounce[0u],
         .ptrDiplexTable = NULL,
         .centroidConfig = 1u,
         .xResolution = 300u,
@@ -633,9 +501,9 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
 {
     .commonContext = {
         #if (CY_CAPSENSE_MW_VERSION < 300)
-            .configId = 0x0990,
+            .configId = 0xcb38,
         #else
-            .configId = 0x0991,
+            .configId = 0xcb39,
         #endif
 
         .tunerCmd = 0u,
@@ -656,70 +524,6 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
         .tunerCnt = 0u,
     },
     .widgetContext = {
-        { /* Button0 */
-            .fingerCap = 160u,
-            .sigPFC = 0u,
-            .resolution = 100u,
-            .maxRawCount = 0u,
-            #if (CY_CAPSENSE_MW_VERSION >= 300)
-                .maxRawCountRow = 0u,
-            #endif
-            .fingerTh = 100u,
-            .proxTh = 200u,
-            .lowBslnRst = 30u,
-            .snsClk = 32u,
-            .rowSnsClk = 16u,
-            .gestureDetected = 0u,
-            .gestureDirection = 0u,
-            .xDelta = 0,
-            .yDelta = 0,
-            .noiseTh = 40u,
-            .nNoiseTh = 40u,
-            .hysteresis = 10u,
-            .onDebounce = 3u,
-            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
-            .idacMod = { 32u, 32u, 32u, },
-            .idacGainIndex = 2u,
-            .rowIdacMod = { 32u, 32u, 32u, },
-            .bslnCoeff = 1u,
-            .status = 0u,
-            .wdTouch = {
-                .ptrPosition = NULL,
-                .numPosition = 0,
-            },
-        },
-        { /* Button1 */
-            .fingerCap = 160u,
-            .sigPFC = 0u,
-            .resolution = 100u,
-            .maxRawCount = 0u,
-            #if (CY_CAPSENSE_MW_VERSION >= 300)
-                .maxRawCountRow = 0u,
-            #endif
-            .fingerTh = 100u,
-            .proxTh = 200u,
-            .lowBslnRst = 30u,
-            .snsClk = 32u,
-            .rowSnsClk = 16u,
-            .gestureDetected = 0u,
-            .gestureDirection = 0u,
-            .xDelta = 0,
-            .yDelta = 0,
-            .noiseTh = 40u,
-            .nNoiseTh = 40u,
-            .hysteresis = 10u,
-            .onDebounce = 3u,
-            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
-            .idacMod = { 32u, 32u, 32u, },
-            .idacGainIndex = 2u,
-            .rowIdacMod = { 32u, 32u, 32u, },
-            .bslnCoeff = 1u,
-            .status = 0u,
-            .wdTouch = {
-                .ptrPosition = NULL,
-                .numPosition = 0,
-            },
-        },
         { /* LinearSlider0 */
             .fingerCap = 160u,
             .sigPFC = 0u,
@@ -754,24 +558,6 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
         },
     },
     .sensorContext = {
-        { /* Button0_Rx0 */
-            .raw = 0u,
-            .bsln = 0u,
-            .diff = 0u,
-            .status = 0u,
-            .negBslnRstCnt = 0u,
-            .idacComp = 32u,
-            .bslnExt = 0u,
-        },
-        { /* Button1_Rx0 */
-            .raw = 0u,
-            .bsln = 0u,
-            .diff = 0u,
-            .status = 0u,
-            .negBslnRstCnt = 0u,
-            .idacComp = 32u,
-            .bslnExt = 0u,
-        },
         { /* LinearSlider0_Sns0 */
             .raw = 0u,
             .bsln = 0u,

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h

@@ -11,7 +11,7 @@
 * CapSense Configurator 4.0.0.6195
 *
 ********************************************************************************
-* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
 * or an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,13 +34,13 @@
 #include <stddef.h>
 
 /* General */
-#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (1u)
-#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (5u)
-#define CY_CAPSENSE_ELTD_COUNT                                                   (9u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (5u)
 #define CY_CAPSENSE_PIN_COUNT                                                    (5u)
 #define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
 #define CY_CAPSENSE_POSITION_SIZE                                                (1u)
-#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (1u)
 #define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (5u)
 #define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
 #define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
@@ -56,9 +56,9 @@
 
 /* Sensing Methods */
 #define CY_CAPSENSE_CSD_EN                                                       (1u)
-#define CY_CAPSENSE_CSX_EN                                                       (1u)
+#define CY_CAPSENSE_CSX_EN                                                       (0u)
 #define CY_CAPSENSE_CSD_CALIBRATION_EN                                           (1u)
-#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (0u)
 #define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
 #define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
 #define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -5,12 +5,12 @@
 * Clock configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -26,26 +26,16 @@
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ********************************************************************************/
-#include <rtthread.h>
 
 #include "cycfg_clocks.h"
 
 #if defined (CY_USING_HAL)
-const cyhal_resource_inst_t CLK_PWM_obj =
+    const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
-{
+    {
-    .type = CYHAL_RSC_CLOCK,
-    .block_num = CLK_PWM_HW,
-    .channel_num = CLK_PWM_NUM,
-};
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
-{
         .type = CYHAL_RSC_CLOCK,
         .block_num = CYBSP_CSD_CLK_DIV_HW,
         .channel_num = CYBSP_CSD_CLK_DIV_NUM,
-};
+    };
 #endif //defined (CY_USING_HAL)
 
 

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -5,12 +5,12 @@
 * Clock configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -40,10 +40,6 @@
 extern "C" {
 #endif
 
-#define CLK_PWM_ENABLED 1U
-#define CLK_PWM_HW CY_SYSCLK_DIV_16_BIT
-#define CLK_PWM_NUM 0U
-
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c

@@ -5,12 +5,12 @@
 * Connectivity BT configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h

@@ -5,12 +5,12 @@
 * Connectivity BT configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -37,14 +37,14 @@
 extern "C" {
 #endif
 
-#define bt_0_power_0_ENABLED 1U
+#define bt_0_power_0_ENABLED (0)
-#define CYCFG_BT_LP_ENABLED (1u)
+#define CYCFG_BT_LP_ENABLED 0
 #define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
 #define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
-#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
+#define CYCFG_BT_HOST_WAKE_GPIO CYHAL_NC_PIN_VALUE
-#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT 0
-#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
+#define CYCFG_BT_DEV_WAKE_GPIO CYHAL_NC_PIN_VALUE
-#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_DEV_WAKE_POLARITY 0
 
 
 #if defined(__cplusplus)

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -6,12 +6,12 @@
 * design.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -5,12 +5,12 @@
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -26,7 +26,6 @@
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ********************************************************************************/
-#include <rtthread.h>
 
 #include "cycfg_peripherals.h"
 
@@ -35,32 +34,8 @@ cy_stc_csd_context_t cy_csd_0_context =
     .lockKey = CY_CSD_NONE_KEY,
 };
 
+
 void init_cycfg_peripherals(void)
 {
     Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-
-#ifdef BSP_USING_UART0
-    /* UART0 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART1
-    /* UART1 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART2
-    /* UART2 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3)
-    /* UART3 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART4
-    /* UART4 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART5
-    /* UART5 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
 }

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -5,12 +5,12 @@
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -46,24 +46,18 @@ extern "C" {
 #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
 #define CY_CAPSENSE_PERI_DIV_INDEX 0u
 #define Cmod_PORT GPIO_PRT7
-#define CintA_PORT GPIO_PRT7
-#define CintB_PORT GPIO_PRT7
 #define LinearSlider0_Sns0_PORT GPIO_PRT7
 #define LinearSlider0_Sns1_PORT GPIO_PRT8
 #define LinearSlider0_Sns2_PORT GPIO_PRT8
 #define LinearSlider0_Sns3_PORT GPIO_PRT9
 #define LinearSlider0_Sns4_PORT GPIO_PRT9
 #define Cmod_PIN 7u
-#define CintA_PIN 1u
-#define CintB_PIN 2u
 #define LinearSlider0_Sns0_PIN 3u
 #define LinearSlider0_Sns1_PIN 0u
 #define LinearSlider0_Sns2_PIN 1u
 #define LinearSlider0_Sns3_PIN 2u
 #define LinearSlider0_Sns4_PIN 3u
 #define Cmod_PORT_NUM 7u
-#define CintA_PORT_NUM 7u
-#define CintB_PORT_NUM 7u
 #define CYBSP_CSD_HW CSD0
 #define CYBSP_CSD_IRQ csd_interrupt_IRQn
 

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -5,12 +5,12 @@
 * Pin configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -29,29 +29,11 @@
 
 #include "cycfg_pins.h"
 
-#define CYBSP_SDHC_IO1_PORT GPIO_PRT13
+const cy_stc_gpio_pin_config_t CYBSP_A0_config =
-#define CYBSP_SDHC_IO1_PORT_NUM 13U
-#define CYBSP_SDHC_IO1_PIN 1U
-
-#ifndef ioss_0_port_13_pin_1_HSIOM
-    #define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC_IO1_HSIOM ioss_0_port_13_pin_1_HSIOM
-
-#define CYBSP_SDHC_IO2_PORT GPIO_PRT13
-#define CYBSP_SDHC_IO2_PORT_NUM 13U
-#define CYBSP_SDHC_IO2_PIN 2U
-
-#ifndef ioss_0_port_13_pin_2_HSIOM
-    #define ioss_0_port_13_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC_IO2_HSIOM ioss_0_port_13_pin_2_HSIOM
-
-const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO1_config =
 {
     .outVal = 1,
-    .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+    .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_SDHC_IO1_HSIOM,
+    .hsiom = CYBSP_A0_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -64,19 +46,18 @@ const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO1_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_SDHC_IO1_obj =
+    const cyhal_resource_inst_t CYBSP_A0_obj =
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_SDHC_IO1_PORT_NUM,
+        .block_num = CYBSP_A0_PORT_NUM,
-        .channel_num = CYBSP_SDHC_IO1_PIN,
+        .channel_num = CYBSP_A0_PIN,
     };
 #endif //defined (CY_USING_HAL)
-
+const cy_stc_gpio_pin_config_t CYBSP_A1_config =
-const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO2_config =
 {
     .outVal = 1,
-    .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+    .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_SDHC_IO2_HSIOM,
+    .hsiom = CYBSP_A1_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -89,14 +70,13 @@ const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO2_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_SDHC_IO2_obj =
+    const cyhal_resource_inst_t CYBSP_A1_obj =
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_SDHC_IO2_PORT_NUM,
+        .block_num = CYBSP_A1_PORT_NUM,
-        .channel_num = CYBSP_SDHC_IO2_PIN,
+        .channel_num = CYBSP_A1_PIN,
     };
 #endif //defined (CY_USING_HAL)
-
 const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
 {
     .outVal = 1,
@@ -241,31 +221,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
         .channel_num = CYBSP_CINB_PIN,
     };
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
-{
-    .outVal = 1,
-    .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_CMOD_HSIOM,
-    .intEdge = CY_GPIO_INTR_DISABLE,
-    .intMask = 0UL,
-    .vtrip = CY_GPIO_VTRIP_CMOS,
-    .slewRate = CY_GPIO_SLEW_FAST,
-    .driveSel = CY_GPIO_DRIVE_1_2,
-    .vregEn = 0UL,
-    .ibufMode = 0UL,
-    .vtripSel = 0UL,
-    .vrefSel = 0UL,
-    .vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_CMOD_obj =
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_CMOD_PORT_NUM,
-        .channel_num = CYBSP_CMOD_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 {
     .outVal = 1,
@@ -290,6 +245,30 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
         .channel_num = CYBSP_CSD_SLD0_PIN,
     };
 #endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CMOD_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CMOD_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CMOD_PORT_NUM,
+        .channel_num = CYBSP_CMOD_PIN,
+    };
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 {
     .outVal = 1,
@@ -387,34 +366,20 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
     };
 #endif //defined (CY_USING_HAL)
 
-const cy_stc_gpio_pin_config_t SMART_IO_OUTPUT_PIN_config =
-{
-    .outVal = 1,
-    .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-    .hsiom = P9_1_TCPWM1_LINE_COMPL20,
-    .intEdge = CY_GPIO_INTR_DISABLE,
-    .intMask = 0UL,
-    .vtrip = CY_GPIO_VTRIP_CMOS,
-    .slewRate = CY_GPIO_SLEW_FAST,
-    .driveSel = CY_GPIO_DRIVE_1_2,
-    .vregEn = 0UL,
-    .ibufMode = 0UL,
-    .vtripSel = 0UL,
-    .vrefSel = 0UL,
-    .vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t SMART_IO_OUTPUT_PIN_obj =
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = 9U,
-        .channel_num = 1U,
-    };
-#endif //defined (CY_USING_HAL)
-
 
 void init_cycfg_pins(void)
 {
+    Cy_GPIO_Pin_Init(CYBSP_A0_PORT, CYBSP_A0_PIN, &CYBSP_A0_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_A0_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_A1_PORT, CYBSP_A1_PIN, &CYBSP_A1_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_A1_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_CSD_RX_PORT, CYBSP_CSD_RX_PIN, &CYBSP_CSD_RX_config);
 #if defined (CY_USING_HAL)
     cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
 #endif //defined (CY_USING_HAL)
@@ -434,20 +399,22 @@ void init_cycfg_pins(void)
     cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
 #endif //defined (CY_USING_HAL)
 
+    Cy_GPIO_Pin_Init(CYBSP_CINA_PORT, CYBSP_CINA_PIN, &CYBSP_CINA_config);
 #if defined (CY_USING_HAL)
     cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
 #endif //defined (CY_USING_HAL)
 
+    Cy_GPIO_Pin_Init(CYBSP_CINB_PORT, CYBSP_CINB_PIN, &CYBSP_CINB_config);
 #if defined (CY_USING_HAL)
     cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
 #endif //defined (CY_USING_HAL)
 
 #if defined (CY_USING_HAL)
-    cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
 #endif //defined (CY_USING_HAL)
 
 #if defined (CY_USING_HAL)
-    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
 #endif //defined (CY_USING_HAL)
 
 #if defined (CY_USING_HAL)

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -10,7 +10,7 @@
 * udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -41,77 +41,107 @@
 extern "C" {
 #endif
 
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PORT_NUM 0U
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-    #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
 #if defined (CY_USING_HAL)
-    #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+    #define CYBSP_USER_LED1 (P0_0)
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_WCO_IN P0_0
+    #define CYBSP_USER_LED2 (P0_1)
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_DEBUG_UART_RX (P0_2)
+    #define CYBSP_D0 CYBSP_DEBUG_UART_RX
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_DEBUG_UART_TX (P0_3)
-#endif //defined (CY_USING_HAL)
+    #define CYBSP_D1 CYBSP_DEBUG_UART_TX
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PORT_NUM 0U
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-    #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_OUT P0_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_SW2 (P0_4)
     #define CYBSP_USER_BTN1 CYBSP_SW2
     #define CYBSP_USER_BTN CYBSP_SW2
 #endif //defined (CY_USING_HAL)
+#define CYBSP_A0_ENABLED 1U
+#define CYBSP_J2_1_ENABLED CYBSP_A0_ENABLED
+#define CYBSP_A0_PORT GPIO_PRT10
+#define CYBSP_J2_1_PORT CYBSP_A0_PORT
+#define CYBSP_A0_PORT_NUM 10U
+#define CYBSP_J2_1_PORT_NUM CYBSP_A0_PORT_NUM
+#define CYBSP_A0_PIN 0U
+#define CYBSP_J2_1_PIN CYBSP_A0_PIN
+#define CYBSP_A0_NUM 0U
+#define CYBSP_J2_1_NUM CYBSP_A0_NUM
+#define CYBSP_A0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_J2_1_DRIVEMODE CYBSP_A0_DRIVEMODE
+#define CYBSP_A0_INIT_DRIVESTATE 1
+#define CYBSP_J2_1_INIT_DRIVESTATE CYBSP_A0_INIT_DRIVESTATE
+#ifndef ioss_0_port_10_pin_0_HSIOM
+    #define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_A0_HSIOM ioss_0_port_10_pin_0_HSIOM
+#define CYBSP_J2_1_HSIOM CYBSP_A0_HSIOM
+#define CYBSP_A0_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_J2_1_IRQ CYBSP_A0_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_LED_RGB_GREEN (P0_5)
+    #define CYBSP_A0_HAL_PORT_PIN P10_0
-    #define CYBSP_USER_LED4 CYBSP_LED_RGB_GREEN
+    #define CYBSP_J2_1_HAL_PORT_PIN CYBSP_A0_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_A0 (P10_0)
+    #define CYBSP_A0 P10_0
     #define CYBSP_J2_1 CYBSP_A0
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_A1 (P10_1)
+    #define CYBSP_A0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_J2_1_HAL_IRQ CYBSP_A0_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A0_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_J2_1_HAL_DIR CYBSP_A0_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_J2_1_HAL_DRIVEMODE CYBSP_A0_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_A1_ENABLED 1U
+#define CYBSP_J2_3_ENABLED CYBSP_A1_ENABLED
+#define CYBSP_A1_PORT GPIO_PRT10
+#define CYBSP_J2_3_PORT CYBSP_A1_PORT
+#define CYBSP_A1_PORT_NUM 10U
+#define CYBSP_J2_3_PORT_NUM CYBSP_A1_PORT_NUM
+#define CYBSP_A1_PIN 1U
+#define CYBSP_J2_3_PIN CYBSP_A1_PIN
+#define CYBSP_A1_NUM 1U
+#define CYBSP_J2_3_NUM CYBSP_A1_NUM
+#define CYBSP_A1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_J2_3_DRIVEMODE CYBSP_A1_DRIVEMODE
+#define CYBSP_A1_INIT_DRIVESTATE 1
+#define CYBSP_J2_3_INIT_DRIVESTATE CYBSP_A1_INIT_DRIVESTATE
+#ifndef ioss_0_port_10_pin_1_HSIOM
+    #define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_A1_HSIOM ioss_0_port_10_pin_1_HSIOM
+#define CYBSP_J2_3_HSIOM CYBSP_A1_HSIOM
+#define CYBSP_A1_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_J2_3_IRQ CYBSP_A1_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_A1_HAL_PORT_PIN P10_1
+    #define CYBSP_J2_3_HAL_PORT_PIN CYBSP_A1_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A1 P10_1
     #define CYBSP_J2_3 CYBSP_A1
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_J2_3_HAL_IRQ CYBSP_A1_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A1_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_J2_3_HAL_DIR CYBSP_A1_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_J2_3_HAL_DRIVEMODE CYBSP_A1_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_A2 (P10_2)
     #define CYBSP_J2_5 CYBSP_A2
@@ -140,10 +170,6 @@ extern "C" {
 #if defined (CY_USING_HAL)
     #define CYBSP_QSPI_FRAM_SSEL (P11_0)
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_LED9 (P11_1)
-    #define CYBSP_USER_LED2 CYBSP_LED9
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_QSPI_SS (P11_2)
     #define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
@@ -198,7 +224,7 @@ extern "C" {
     #define CYBSP_SDHC_IO3 (P13_3)
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_SDHC_DETECT (P13_5)
+    #define CYBSP_SDHC_DETECT (P13_7)
 #endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_RX_ENABLED 1U
 #define CYBSP_CS_RX_ENABLED CYBSP_CSD_RX_ENABLED
@@ -255,19 +281,10 @@ extern "C" {
     #define CYBSP_CS_RX_HAL_DRIVEMODE CYBSP_CSD_RX_HAL_DRIVEMODE
     #define CYBSP_CS_TX_RX_HAL_DRIVEMODE CYBSP_CSD_RX_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_LED_RGB_RED (P0_0)
-    #define CYBSP_USER_LED3 CYBSP_LED_RGB_RED
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_SW4 (P1_4)
     #define CYBSP_USER_BTN2 CYBSP_SW4
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_LED4 (P0_1)
-    #define CYBSP_USER_LED1 CYBSP_LED4
-    #define CYBSP_USER_LED CYBSP_LED4
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_WIFI_SDIO_D0 (P2_0)
 #endif //defined (CY_USING_HAL)
@@ -313,24 +330,6 @@ extern "C" {
 #if defined (CY_USING_HAL)
     #define CYBSP_WIFI_HOST_WAKE (P4_1)
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_DEBUG_UART_RX (P0_2)
-    #define CYBSP_D0 CYBSP_DEBUG_UART_RX
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_DEBUG_UART_TX (P0_3)
-    #define CYBSP_D1 CYBSP_DEBUG_UART_TX
-    #define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT0
-    #define CYBSP_DEBUG_UART_TX_PIN 3U
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_DEBUG_UART_RTS (P5_2)
-    #define CYBSP_D2 CYBSP_DEBUG_UART_RTS
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_DEBUG_UART_CTS (P5_3)
-    #define CYBSP_D3 CYBSP_DEBUG_UART_CTS
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_D4 (P5_4)
 #endif //defined (CY_USING_HAL)
@@ -486,9 +485,46 @@ extern "C" {
 #if defined (CY_USING_HAL)
     #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT7
+#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
+#define CYBSP_CSD_SLD0_PORT_NUM 7U
+#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
+#ifndef ioss_0_port_7_pin_3_HSIOM
+    #define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_7_pin_3_HSIOM
+#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_LED_RGB_BLUE (P7_3)
+    #define CYBSP_CSD_SLD0_HAL_PORT_PIN P7_3
-    #define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE
+    #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0 P7_3
+    #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_D8 (P7_5)
@@ -523,47 +559,6 @@ extern "C" {
 #if defined (CY_USING_HAL)
     #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT7
-#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
-#define CYBSP_CSD_SLD0_PORT_NUM 7U
-#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
-#ifndef ioss_0_port_8_pin_3_HSIOM
-    #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
-#if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
-    #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD0 P8_3
-    #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
-    #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
-#endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_SLD1_ENABLED 1U
 #define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
 #define CYBSP_CSD_SLD1_PORT GPIO_PRT8
@@ -578,19 +573,19 @@ extern "C" {
 #define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
 #define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
 #define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
-#ifndef ioss_0_port_8_pin_4_HSIOM
+#ifndef ioss_0_port_8_pin_0_HSIOM
-    #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+    #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_0_HSIOM
 #define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
 #define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
 #define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+    #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_0
     #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD1 P8_4
+    #define CYBSP_CSD_SLD1 P8_0
     #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
@@ -619,19 +614,19 @@ extern "C" {
 #define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
 #define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
 #define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
-#ifndef ioss_0_port_8_pin_5_HSIOM
+#ifndef ioss_0_port_8_pin_1_HSIOM
-    #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+    #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_1_HSIOM
 #define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
 #define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
 #define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+    #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_1
     #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD2 P8_5
+    #define CYBSP_CSD_SLD2 P8_1
     #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
@@ -646,33 +641,41 @@ extern "C" {
     #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
     #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A8 (P9_0)
+    #define CYBSP_J2_2 CYBSP_A8
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A9 (P9_1)
+    #define CYBSP_J2_4 CYBSP_A9
+#endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_SLD3_ENABLED 1U
 #define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT9
 #define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
-#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PORT_NUM 9U
 #define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
-#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_PIN 2U
 #define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
-#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_NUM 2U
 #define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
 #define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
 #define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
 #define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
 #define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
-#ifndef ioss_0_port_8_pin_6_HSIOM
+#ifndef ioss_0_port_9_pin_2_HSIOM
-    #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+    #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_9_pin_2_HSIOM
 #define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_9_IRQn
 #define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+    #define CYBSP_CSD_SLD3_HAL_PORT_PIN P9_2
     #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD3 P8_6
+    #define CYBSP_CSD_SLD3 P9_2
     #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
@@ -689,31 +692,31 @@ extern "C" {
 #endif //defined (CY_USING_HAL)
 #define CYBSP_CSD_SLD4_ENABLED 1U
 #define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT9
 #define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
-#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PORT_NUM 9U
 #define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
-#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_PIN 3U
 #define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
-#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_NUM 3U
 #define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
 #define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
 #define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
 #define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
 #define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
-#ifndef ioss_0_port_8_pin_7_HSIOM
+#ifndef ioss_0_port_9_pin_3_HSIOM
-    #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+    #define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_9_pin_3_HSIOM
 #define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_9_IRQn
 #define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+    #define CYBSP_CSD_SLD4_HAL_PORT_PIN P9_3
     #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-    #define CYBSP_CSD_SLD4 P8_7
+    #define CYBSP_CSD_SLD4 P9_3
     #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
@@ -728,22 +731,6 @@ extern "C" {
     #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
     #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_A8 (P9_0)
-    #define CYBSP_J2_2 CYBSP_A8
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_A9 (P9_1)
-    #define CYBSP_J2_4 CYBSP_A9
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_A10 (P9_2)
-    #define CYBSP_J2_6 CYBSP_A10
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-    #define CYBSP_A11 (P9_3)
-    #define CYBSP_J2_8 CYBSP_A11
-#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
     #define CYBSP_A12 (P9_4)
     #define CYBSP_J2_10 CYBSP_A12
@@ -761,13 +748,17 @@ extern "C" {
     #define CYBSP_J2_16 CYBSP_A15
 #endif //defined (CY_USING_HAL)
 
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_A0_config;
+#define CYBSP_J2_1_config CYBSP_A0_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+    extern const cyhal_resource_inst_t CYBSP_A0_obj;
+    #define CYBSP_J2_1_obj CYBSP_A0_obj
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_A1_config;
+#define CYBSP_J2_3_config CYBSP_A1_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+    extern const cyhal_resource_inst_t CYBSP_A1_obj;
+    #define CYBSP_J2_3_obj CYBSP_A1_obj
 #endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
 #define CYBSP_CS_RX_config CYBSP_CSD_RX_config
@@ -797,16 +788,16 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
 #if defined (CY_USING_HAL)
     extern const cyhal_resource_inst_t CYBSP_CINB_obj;
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
-#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
 #define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
 #if defined (CY_USING_HAL)
     extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
     #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
 #endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
 #define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
 #if defined (CY_USING_HAL)

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -5,12 +5,12 @@
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -33,12 +33,12 @@
 
 void init_cycfg_routing(void)
 {
-    HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
-        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
-        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
-        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
     HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
         HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
         HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
         HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+    HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
 }

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -5,12 +5,12 @@
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -37,22 +37,15 @@ extern "C" {
 #include "cycfg_notices.h"
 void init_cycfg_routing(void);
 #define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
-#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
 #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
 
 #if defined(__cplusplus)
 }

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -10,7 +10,7 @@
 * udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,13 +34,6 @@
 #define CY_CFG_SYSCLK_PLL_ERROR 3
 #define CY_CFG_SYSCLK_FLL_ERROR 4
 #define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 0
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 32768
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*32768
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
 #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
 #define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
 #define CY_CFG_SYSCLK_FLL_ENABLED 1
@@ -62,7 +55,6 @@
 #define CY_CFG_SYSCLK_ILO_ENABLED 1
 #define CY_CFG_SYSCLK_ILO_HIBERNATE true
 #define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
@@ -95,12 +87,6 @@
 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
 #define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
 #define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
-//#define CY_CFG_SYSCLK_WCO_ENABLED 0
-//#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
-//#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
-//#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0
-//#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
-//#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
 #define CY_CFG_PWR_ENABLED 1
 #define CY_CFG_PWR_INIT 1
 #define CY_CFG_PWR_USING_PMIC 0
@@ -664,16 +650,6 @@ __WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
         #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
     }
 #endif //defined (CY_DEVICE_SECURE)
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
-{
- Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
-}
-#if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_ClkBakInit()
-    {
-        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
 #if (!defined(CY_DEVICE_SECURE))
     __STATIC_INLINE void Cy_SysClk_ClkFastInit()
     {
@@ -708,13 +684,6 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
         Cy_SysClk_IloHibernateOn(true);
     }
 #endif //(!defined(CY_DEVICE_SECURE))
-#if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_ClkLfInit()
-    {
-        /* The WDT is unlocked in the default startup code */
-        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
 #if (!defined(CY_DEVICE_SECURE))
     __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
     {
@@ -785,17 +754,6 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
         Cy_SysClk_ClkTimerEnable();
     }
 #endif //(!defined(CY_DEVICE_SECURE))
-#if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_WcoInit()
-    {
-        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-        if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-        {
-            cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-        }
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
 #if (!defined(CY_DEVICE_SECURE))
     __STATIC_INLINE void init_cycfg_power(void)
     {

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -5,12 +5,12 @@
 * System configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,11 +34,9 @@
 #include "cy_sysclk.h"
 #include "cy_pra.h"
 #include "cy_pra_cfg.h"
-#include "cy_systick.h"
 #if defined (CY_USING_HAL)
     #include "cyhal_hwmgr.h"
 #endif //defined (CY_USING_HAL)
-#include "cy_gpio.h"
 #include "cy_syspm.h"
 
 #if defined(__cplusplus)
@@ -47,8 +45,6 @@ extern "C" {
 
 #define cpuss_0_dap_0_ENABLED 1U
 #define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
-#define srss_0_clock_0_bakclk_0_ENABLED 1U
 #define srss_0_clock_0_fastclk_0_ENABLED 1U
 #define srss_0_clock_0_fll_0_ENABLED 1U
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
@@ -56,9 +52,6 @@ extern "C" {
 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
 #define srss_0_clock_0_imo_0_ENABLED 1U
-#define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
 #define srss_0_clock_0_pathmux_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_1_ENABLED 1U
 #define srss_0_clock_0_pathmux_2_ENABLED 1U
@@ -69,7 +62,6 @@ extern "C" {
 #define srss_0_clock_0_pll_0_ENABLED 1U
 #define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_timerclk_0_ENABLED 1U
-#define srss_0_clock_0_wco_0_ENABLED 1U
 #define srss_0_power_0_ENABLED 1U
 #define CY_CFG_PWR_MODE_LP 0x01UL
 #define CY_CFG_PWR_MODE_ULP 0x02UL

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
-<!--This file should not be modified. It was automatically generated by CapSense Configurator 4.0.0.5470-->
+<!--This file should not be modified. It was automatically generated by CapSense Configurator 4.0.0.6195-->
 <Configuration app="Capsense" major="4" minor="0" lastSavedWithToolName="CapSense Configurator" formatVersion="1">
     <DesignProperties>
         <Property id="DEVICE_TYPE" value="P6_CSDV2"/>
@@ -28,6 +28,14 @@
         <Property id="IREF_SOURCE" value="SRSS"/>
         <Property id="PROX_TOUCH_COEFF" value="300"/>
         <Property id="BIST_EN" value="false"/>
+        <Property id="BIST_WDGT_CRC_EN" value="true"/>
+        <Property id="BIST_BSLN_DUPLICATION_EN" value="true"/>
+        <Property id="BIST_BSLN_RAW_OUT_RANGE_EN" value="true"/>
+        <Property id="BIST_SNS_SHORT_EN" value="true"/>
+        <Property id="BIST_SNS_CAP_EN" value="true"/>
+        <Property id="BIST_SH_CAP_EN" value="true"/>
+        <Property id="BIST_EXTERNAL_CAP_EN" value="true"/>
+        <Property id="BIST_VDDA_EN" value="true"/>
         <Property id="BIST_SHIELD_CAP_ISC" value="BIST_IO_STRONG"/>
         <Property id="BIST_SNS_CAP_CSD_ISC" value="BIST_IO_STRONG"/>
         <Property id="BIST_SNS_CAP_CSX_ISC" value="BIST_IO_STRONG"/>
@@ -87,204 +95,6 @@
         <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
     </CsxProperties>
     <Widgets>
-        <Widget id="Button0" type="CSX_BUTTON">
-            <WidgetProperties>
-                <Property id="DIPLEXING" value="false"/>
-                <Property id="MAX_POS_X" value="300"/>
-                <Property id="MAX_POS_Y" value="300"/>
-                <Property id="FINGER_CP" value="0.16"/>
-                <Property id="SNS_CLK" value="16"/>
-                <Property id="ROW_SNS_CLK" value="16"/>
-                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
-                <Property id="TX_CLK" value="32"/>
-                <Property id="TX_CLK_SOURCE" value="AUTO"/>
-                <Property id="RESOLUTION" value="RES12BIT"/>
-                <Property id="NUM_CONV" value="100"/>
-                <Property id="IDAC_MOD0" value="32"/>
-                <Property id="IDAC_MOD1" value="32"/>
-                <Property id="IDAC_MOD2" value="32"/>
-                <Property id="ROW_IDAC_MOD0" value="32"/>
-                <Property id="ROW_IDAC_MOD1" value="32"/>
-                <Property id="ROW_IDAC_MOD2" value="32"/>
-                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
-                <Property id="FINGER_TH" value="100"/>
-                <Property id="PROX_TOUCH_TH" value="200"/>
-                <Property id="NOISE_TH" value="40"/>
-                <Property id="NNOISE_TH" value="40"/>
-                <Property id="LOW_BSLN_RST" value="30"/>
-                <Property id="HYSTERESIS" value="10"/>
-                <Property id="ON_DEBOUNCE" value="3"/>
-                <Property id="VELOCITY" value="45000"/>
-                <Property id="IIR_FILTER" value="false"/>
-                <Property id="IIR_FILTER_COEFF" value="128"/>
-                <Property id="MEDIAN_FILTER" value="false"/>
-                <Property id="AVG_FILTER" value="false"/>
-                <Property id="JITTER_FILTER" value="false"/>
-                <Property id="AIIR_FILTER" value="false"/>
-                <Property id="AIIR_NO_MOV_TH" value="3"/>
-                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
-                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
-                <Property id="AIIR_MAXK" value="60"/>
-                <Property id="AIIR_MINK" value="1"/>
-                <Property id="AIIR_DIV_VAL" value="64"/>
-                <Property id="CENTROID_TYPE" value="CSD3X3"/>
-                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
-                <Property id="EDGE_CORRECTION" value="true"/>
-                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
-                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
-                <Property id="TWO_FINGER_DETECTION" value="false"/>
-                <Property id="BALLISTIC_MULT" value="false"/>
-                <Property id="ACCEL_COEFF" value="9"/>
-                <Property id="SPEED_COEFF" value="2"/>
-                <Property id="DIVISOR" value="4"/>
-                <Property id="SPEED_TH_X" value="3"/>
-                <Property id="SPEED_TH_Y" value="4"/>
-                <Property id="GESTURE_ENABLE" value="false"/>
-                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
-                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
-                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
-                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
-                <Property id="CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
-                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
-                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SCROLL_DEBOUNCE" value="3"/>
-                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
-                <Property id="ROTATE_DEBOUNCE" value="10"/>
-                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
-                <Property id="ZOOM_DEBOUNCE" value="3"/>
-                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
-                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
-                <Property id="FLICK_DISTANCE_MIN" value="100"/>
-                <Property id="EDGE_EDGE_SIZE" value="200"/>
-                <Property id="EDGE_DISTANCE_MIN" value="200"/>
-                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
-                <Property id="EDGE_ANGLE_MAX" value="45"/>
-            </WidgetProperties>
-            <Electrodes>
-                <Electrode id="Rx0" kind="Column">
-                    <ElectrodeProperties>
-                        <Property id="IDAC0" value="32"/>
-                        <Property id="IDAC1" value="32"/>
-                        <Property id="IDAC2" value="32"/>
-                        <Property id="PINS" value="Dedicated pin"/>
-                    </ElectrodeProperties>
-                </Electrode>
-                <Electrode id="Tx" kind="Row">
-                    <ElectrodeProperties>
-                        <Property id="PINS" value="Dedicated pin"/>
-                    </ElectrodeProperties>
-                </Electrode>
-            </Electrodes>
-        </Widget>
-        <Widget id="Button1" type="CSX_BUTTON">
-            <WidgetProperties>
-                <Property id="DIPLEXING" value="false"/>
-                <Property id="MAX_POS_X" value="300"/>
-                <Property id="MAX_POS_Y" value="300"/>
-                <Property id="FINGER_CP" value="0.16"/>
-                <Property id="SNS_CLK" value="16"/>
-                <Property id="ROW_SNS_CLK" value="16"/>
-                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
-                <Property id="TX_CLK" value="32"/>
-                <Property id="TX_CLK_SOURCE" value="AUTO"/>
-                <Property id="RESOLUTION" value="RES12BIT"/>
-                <Property id="NUM_CONV" value="100"/>
-                <Property id="IDAC_MOD0" value="32"/>
-                <Property id="IDAC_MOD1" value="32"/>
-                <Property id="IDAC_MOD2" value="32"/>
-                <Property id="ROW_IDAC_MOD0" value="32"/>
-                <Property id="ROW_IDAC_MOD1" value="32"/>
-                <Property id="ROW_IDAC_MOD2" value="32"/>
-                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
-                <Property id="FINGER_TH" value="100"/>
-                <Property id="PROX_TOUCH_TH" value="200"/>
-                <Property id="NOISE_TH" value="40"/>
-                <Property id="NNOISE_TH" value="40"/>
-                <Property id="LOW_BSLN_RST" value="30"/>
-                <Property id="HYSTERESIS" value="10"/>
-                <Property id="ON_DEBOUNCE" value="3"/>
-                <Property id="VELOCITY" value="45000"/>
-                <Property id="IIR_FILTER" value="false"/>
-                <Property id="IIR_FILTER_COEFF" value="128"/>
-                <Property id="MEDIAN_FILTER" value="false"/>
-                <Property id="AVG_FILTER" value="false"/>
-                <Property id="JITTER_FILTER" value="false"/>
-                <Property id="AIIR_FILTER" value="false"/>
-                <Property id="AIIR_NO_MOV_TH" value="3"/>
-                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
-                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
-                <Property id="AIIR_MAXK" value="60"/>
-                <Property id="AIIR_MINK" value="1"/>
-                <Property id="AIIR_DIV_VAL" value="64"/>
-                <Property id="CENTROID_TYPE" value="CSD3X3"/>
-                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
-                <Property id="EDGE_CORRECTION" value="true"/>
-                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
-                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
-                <Property id="TWO_FINGER_DETECTION" value="false"/>
-                <Property id="BALLISTIC_MULT" value="false"/>
-                <Property id="ACCEL_COEFF" value="9"/>
-                <Property id="SPEED_COEFF" value="2"/>
-                <Property id="DIVISOR" value="4"/>
-                <Property id="SPEED_TH_X" value="3"/>
-                <Property id="SPEED_TH_Y" value="4"/>
-                <Property id="GESTURE_ENABLE" value="false"/>
-                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
-                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
-                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
-                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
-                <Property id="CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
-                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
-                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SCROLL_DEBOUNCE" value="3"/>
-                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
-                <Property id="ROTATE_DEBOUNCE" value="10"/>
-                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
-                <Property id="ZOOM_DEBOUNCE" value="3"/>
-                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
-                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
-                <Property id="FLICK_DISTANCE_MIN" value="100"/>
-                <Property id="EDGE_EDGE_SIZE" value="200"/>
-                <Property id="EDGE_DISTANCE_MIN" value="200"/>
-                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
-                <Property id="EDGE_ANGLE_MAX" value="45"/>
-            </WidgetProperties>
-            <Electrodes>
-                <Electrode id="Rx0" kind="Column">
-                    <ElectrodeProperties>
-                        <Property id="IDAC0" value="32"/>
-                        <Property id="IDAC1" value="32"/>
-                        <Property id="IDAC2" value="32"/>
-                        <Property id="PINS" value="Dedicated pin"/>
-                    </ElectrodeProperties>
-                </Electrode>
-                <Electrode id="Tx" kind="Row">
-                    <ElectrodeProperties>
-                        <Property id="PINS" value="Dedicated pin"/>
-                    </ElectrodeProperties>
-                </Electrode>
-            </Electrodes>
-        </Widget>
         <Widget id="LinearSlider0" type="LINEAR_SLIDER">
             <WidgetProperties>
                 <Property id="DIPLEXING" value="false"/>

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -15,20 +15,14 @@
                     <Personality template="mxs40csd" version="2.0">
                         <Param id="CapSenseEnable" value="true"/>
                         <Param id="CapSenseCore" value="4"/>
-                        <Param id="SensorCount" value="12"/>
+                        <Param id="SensorCount" value="6"/>
-                        <Param id="CapacitorCount" value="3"/>
+                        <Param id="CapacitorCount" value="1"/>
                         <Param id="SensorName0" value="Cmod"/>
-                        <Param id="SensorName1" value="CintA"/>
+                        <Param id="SensorName1" value="LinearSlider0_Sns0"/>
-                        <Param id="SensorName2" value="CintB"/>
+                        <Param id="SensorName2" value="LinearSlider0_Sns1"/>
-                        <Param id="SensorName3" value="Button0_Rx0"/>
+                        <Param id="SensorName3" value="LinearSlider0_Sns2"/>
-                        <Param id="SensorName4" value="Button0_Tx"/>
+                        <Param id="SensorName4" value="LinearSlider0_Sns3"/>
-                        <Param id="SensorName5" value="Button1_Rx0"/>
+                        <Param id="SensorName5" value="LinearSlider0_Sns4"/>
-                        <Param id="SensorName6" value="Button1_Tx"/>
-                        <Param id="SensorName7" value="LinearSlider0_Sns0"/>
-                        <Param id="SensorName8" value="LinearSlider0_Sns1"/>
-                        <Param id="SensorName9" value="LinearSlider0_Sns2"/>
-                        <Param id="SensorName10" value="LinearSlider0_Sns3"/>
-                        <Param id="SensorName11" value="LinearSlider0_Sns4"/>
                         <Param id="CapSenseConfigurator" value="0"/>
                         <Param id="CapSenseTuner" value="0"/>
                         <Param id="CsdAdcEnable" value="false"/>
@@ -50,47 +44,51 @@
                     </Personality>
                 </Block>
                 <Block location="ioss[0].port[0].pin[0]">
-                    <Alias value="CYBSP_WCO_IN"/>
+                    <Alias value="CYBSP_USER_LED1"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
                 </Block>
                 <Block location="ioss[0].port[0].pin[1]">
-                    <Alias value="CYBSP_WCO_OUT"/>
+                    <Alias value="CYBSP_USER_LED2"/>
-                    <Personality template="mxs40pin" version="1.1">
+                </Block>
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                <Block location="ioss[0].port[0].pin[2]">
-                        <Param id="initialState" value="1"/>
+                    <Alias value="CYBSP_DEBUG_UART_RX"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Alias value="CYBSP_D0"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                </Block>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                <Block location="ioss[0].port[0].pin[3]">
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Alias value="CYBSP_DEBUG_UART_TX"/>
-                        <Param id="sioOutputBuffer" value="true"/>
+                    <Alias value="CYBSP_D1"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
                 </Block>
                 <Block location="ioss[0].port[0].pin[4]">
                     <Alias value="CYBSP_SW2"/>
                     <Alias value="CYBSP_USER_BTN1"/>
                     <Alias value="CYBSP_USER_BTN"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[5]">
-                    <Alias value="CYBSP_LED_RGB_GREEN"/>
-                    <Alias value="CYBSP_USER_LED4"/>
-                </Block>
                 <Block location="ioss[0].port[10].pin[0]">
                     <Alias value="CYBSP_A0"/>
                     <Alias value="CYBSP_J2_1"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
                 </Block>
                 <Block location="ioss[0].port[10].pin[1]">
                     <Alias value="CYBSP_A1"/>
                     <Alias value="CYBSP_J2_3"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
                 </Block>
                 <Block location="ioss[0].port[10].pin[2]">
                     <Alias value="CYBSP_A2"/>
@@ -120,10 +118,6 @@
                 <Block location="ioss[0].port[11].pin[0]">
                     <Alias value="CYBSP_QSPI_FRAM_SSEL"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[1]">
-                    <Alias value="CYBSP_LED9"/>
-                    <Alias value="CYBSP_USER_LED2"/>
-                </Block>
                 <Block location="ioss[0].port[11].pin[2]">
                     <Alias value="CYBSP_QSPI_SS"/>
                     <Alias value="CYBSP_QSPI_FLASH_SSEL"/>
@@ -195,19 +189,10 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[1].pin[1]">
-                    <Alias value="CYBSP_LED_RGB_RED"/>
-                    <Alias value="CYBSP_USER_LED3"/>
-                </Block>
                 <Block location="ioss[0].port[1].pin[4]">
                     <Alias value="CYBSP_SW4"/>
                     <Alias value="CYBSP_USER_BTN2"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[5]">
-                    <Alias value="CYBSP_LED8"/>
-                    <Alias value="CYBSP_USER_LED1"/>
-                    <Alias value="CYBSP_USER_LED"/>
-                </Block>
                 <Block location="ioss[0].port[2].pin[0]">
                     <Alias value="CYBSP_WIFI_SDIO_D0"/>
                 </Block>
@@ -253,22 +238,6 @@
                 <Block location="ioss[0].port[4].pin[1]">
                     <Alias value="CYBSP_WIFI_HOST_WAKE"/>
                 </Block>
-                <Block location="ioss[0].port[5].pin[0]">
-                    <Alias value="CYBSP_DEBUG_UART_RX"/>
-                    <Alias value="CYBSP_D0"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]">
-                    <Alias value="CYBSP_DEBUG_UART_TX"/>
-                    <Alias value="CYBSP_D1"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[2]">
-                    <Alias value="CYBSP_DEBUG_UART_RTS"/>
-                    <Alias value="CYBSP_D2"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[3]">
-                    <Alias value="CYBSP_DEBUG_UART_CTS"/>
-                    <Alias value="CYBSP_D3"/>
-                </Block>
                 <Block location="ioss[0].port[5].pin[4]">
                     <Alias value="CYBSP_D4"/>
                 </Block>
@@ -355,8 +324,22 @@
                     </Personality>
                 </Block>
                 <Block location="ioss[0].port[7].pin[3]">
-                    <Alias value="CYBSP_LED_RGB_BLUE"/>
+                    <Alias value="CYBSP_CSD_SLD0"/>
-                    <Alias value="CYBSP_USER_LED5"/>
+                    <Alias value="CYBSP_CS_SLD0"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="sioInputBuffer" value="false"/>
+                        <Param id="sioTrip" value="CY_SIO_VTRIP_CMOS"/>
+                        <Param id="sioRef" value="CY_SIO_VREF_PINREF"/>
+                        <Param id="sioVoltage" value="CY_SIO_VOH_1_00"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
                 </Block>
                 <Block location="ioss[0].port[7].pin[5]">
                     <Alias value="CYBSP_D8"/>
@@ -377,49 +360,7 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[8].pin[1]">
+                <Block location="ioss[0].port[8].pin[0]">
-                    <Alias value="CYBSP_CSD_BTN0"/>
-                    <Alias value="CYBSP_CS_BTN0"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[2]">
-                    <Alias value="CYBSP_CSD_BTN1"/>
-                    <Alias value="CYBSP_CS_BTN1"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[3]">
-                    <Alias value="CYBSP_CSD_SLD0"/>
-                    <Alias value="CYBSP_CS_SLD0"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[4]">
                     <Alias value="CYBSP_CSD_SLD1"/>
                     <Alias value="CYBSP_CS_SLD1"/>
                     <Personality template="mxs40pin" version="1.1">
@@ -433,7 +374,7 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[8].pin[5]">
+                <Block location="ioss[0].port[8].pin[1]">
                     <Alias value="CYBSP_CSD_SLD2"/>
                     <Alias value="CYBSP_CS_SLD2"/>
                     <Personality template="mxs40pin" version="1.1">
@@ -441,13 +382,27 @@
                         <Param id="initialState" value="1"/>
                         <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                         <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="sioInputBuffer" value="false"/>
+                        <Param id="sioTrip" value="CY_SIO_VTRIP_CMOS"/>
+                        <Param id="sioRef" value="CY_SIO_VREF_PINREF"/>
+                        <Param id="sioVoltage" value="CY_SIO_VOH_1_00"/>
                         <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
                         <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
                         <Param id="sioOutputBuffer" value="true"/>
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[8].pin[6]">
+                <Block location="ioss[0].port[8].pin[6]"/>
+                <Block location="ioss[0].port[8].pin[7]"/>
+                <Block location="ioss[0].port[9].pin[0]">
+                    <Alias value="CYBSP_A8"/>
+                    <Alias value="CYBSP_J2_2"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[1]">
+                    <Alias value="CYBSP_A9"/>
+                    <Alias value="CYBSP_J2_4"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[2]">
                     <Alias value="CYBSP_CSD_SLD3"/>
                     <Alias value="CYBSP_CS_SLD3"/>
                     <Personality template="mxs40pin" version="1.1">
@@ -461,7 +416,7 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[8].pin[7]">
+                <Block location="ioss[0].port[9].pin[3]">
                     <Alias value="CYBSP_CSD_SLD4"/>
                     <Alias value="CYBSP_CS_SLD4"/>
                     <Personality template="mxs40pin" version="1.1">
@@ -475,22 +430,6 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[9].pin[0]">
-                    <Alias value="CYBSP_A8"/>
-                    <Alias value="CYBSP_J2_2"/>
-                </Block>
-                <Block location="ioss[0].port[9].pin[1]">
-                    <Alias value="CYBSP_A9"/>
-                    <Alias value="CYBSP_J2_4"/>
-                </Block>
-                <Block location="ioss[0].port[9].pin[2]">
-                    <Alias value="CYBSP_A10"/>
-                    <Alias value="CYBSP_J2_6"/>
-                </Block>
-                <Block location="ioss[0].port[9].pin[3]">
-                    <Alias value="CYBSP_A11"/>
-                    <Alias value="CYBSP_J2_8"/>
-                </Block>
                 <Block location="ioss[0].port[9].pin[4]">
                     <Alias value="CYBSP_A12"/>
                     <Alias value="CYBSP_J2_10"/>
@@ -519,17 +458,6 @@
                 <Block location="srss[0].clock[0]">
                     <Personality template="mxs40sysclocks" version="1.2"/>
                 </Block>
-                <Block location="srss[0].clock[0].altsystickclk[0]">
-                    <Personality template="mxs40altsystick" version="1.0">
-                        <Param id="sourceClock" value="lfclk"/>
-                        <Param id="interval" value="0"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].bakclk[0]">
-                    <Personality template="mxs40bakclk" version="1.0">
-                        <Param id="sourceClock" value="lfclk"/>
-                    </Personality>
-                </Block>
                 <Block location="srss[0].clock[0].fastclk[0]">
                     <Personality template="mxs40fastclk" version="1.0">
                         <Param id="divider" value="1"/>
@@ -557,11 +485,6 @@
                         <Param id="trim" value="1"/>
                     </Personality>
                 </Block>
-                <Block location="srss[0].clock[0].lfclk[0]">
-                    <Personality template="mxs40lfclk" version="1.1">
-                        <Param id="sourceClock" value="wco"/>
-                    </Personality>
-                </Block>
                 <Block location="srss[0].clock[0].pathmux[0]">
                     <Personality template="mxs40pathmux" version="1.0">
                         <Param id="sourceClock" value="imo"/>
@@ -616,16 +539,6 @@
                         <Param id="timerDivider" value="1"/>
                     </Personality>
                 </Block>
-                <Block location="srss[0].clock[0].wco[0]">
-                    <Personality template="mxs40wco" version="1.0">
-                        <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
-                        <Param id="clockLostDetection" value="false"/>
-                        <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
-                        <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
-                        <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
-                        <Param id="accuracyPpm" value="150"/>
-                    </Personality>
-                </Block>
                 <Block location="srss[0].power[0]">
                     <Personality template="mxs40power" version="1.3">
                         <Param id="pwrMode" value="LDO_1_1"/>
@@ -661,65 +574,30 @@
                     <Port name="csd[0].csd[0].clock[0]"/>
                     <Port name="peri[0].div_8[0].clk[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
-                </Net>
                 <Mux name="sense" location="csd[0].csd[0]">
                     <Arm>
                         <Port name="ioss[0].port[7].pin[7].analog[0]"/>
                     </Arm>
                     <Arm>
-                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
+                        <Port name="ioss[0].port[7].pin[3].analog[0]"/>
                     </Arm>
                     <Arm>
-                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
+                        <Port name="ioss[0].port[8].pin[0].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
                     </Arm>
                     <Arm>
                         <Port name="ioss[0].port[8].pin[1].analog[0]"/>
                     </Arm>
                     <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                        <Port name="ioss[0].port[9].pin[2].analog[0]"/>
                     </Arm>
                     <Arm>
-                        <Port name="ioss[0].port[8].pin[2].analog[0]"/>
+                        <Port name="ioss[0].port[9].pin[3].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[3].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[4].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[5].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[6].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[7].analog[0]"/>
                     </Arm>
                 </Mux>
             </Netlist>
         </Device>
         <Device mpn="CYW43012C0WKWBG">
-            <BlockConfig>
+            <BlockConfig/>
-                <Block location="bt[0].power[0]">
-                    <Personality template="connectivity_bt" version="1.0">
-                        <Param id="hostWakePin" value=""/>
-                        <Param id="hostWakeIrqEvent" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
-                        <Param id="devWakePin" value=""/>
-                        <Param id="devWakePolarity" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
-                    </Personality>
-                </Block>
-            </BlockConfig>
             <Netlist/>
         </Device>
     </Devices>

bsp/Infineon/psoc6-evaluationkit-062S2/project.uvoptx

@@ -73,7 +73,7 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
@@ -846,6 +846,18 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</PathWithFileName>
+      <FilenameWithoutPath>psoc6_01_cm0p_sleep.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>9</GroupNumber>
+      <FileNumber>51</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
       <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_i2c.c</PathWithFileName>
       <FilenameWithoutPath>cy_scb_i2c.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
@@ -853,7 +865,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>51</FileNumber>
+      <FileNumber>52</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -865,7 +877,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>52</FileNumber>
+      <FileNumber>53</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -877,7 +889,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>53</FileNumber>
+      <FileNumber>54</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -889,7 +901,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>54</FileNumber>
+      <FileNumber>55</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -901,7 +913,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>55</FileNumber>
+      <FileNumber>56</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -913,7 +925,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>56</FileNumber>
+      <FileNumber>57</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -925,7 +937,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>57</FileNumber>
+      <FileNumber>58</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -937,7 +949,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>58</FileNumber>
+      <FileNumber>59</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -949,7 +961,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>59</FileNumber>
+      <FileNumber>60</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -961,7 +973,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>60</FileNumber>
+      <FileNumber>61</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -973,7 +985,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>61</FileNumber>
+      <FileNumber>62</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -985,7 +997,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>62</FileNumber>
+      <FileNumber>63</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -997,7 +1009,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>63</FileNumber>
+      <FileNumber>64</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1009,7 +1021,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>64</FileNumber>
+      <FileNumber>65</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1021,7 +1033,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>65</FileNumber>
+      <FileNumber>66</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1031,18 +1043,6 @@
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>66</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_lptimer.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
     <File>
       <GroupNumber>9</GroupNumber>
       <FileNumber>67</FileNumber>
@@ -1050,47 +1050,47 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_irq_psoc.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_irq_psoc.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>68</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_mcwdt.c</PathWithFileName>
-      <FilenameWithoutPath>cy_mcwdt.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>69</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c</PathWithFileName>
-      <FilenameWithoutPath>cy_sysclk.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>70</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
       <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</PathWithFileName>
       <FilenameWithoutPath>psoc6_04_cm0p_sleep.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>9</GroupNumber>
+      <FileNumber>68</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c</PathWithFileName>
+      <FilenameWithoutPath>cyhal_lptimer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>9</GroupNumber>
+      <FileNumber>69</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_irq_psoc.c</PathWithFileName>
+      <FilenameWithoutPath>cyhal_irq_psoc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>9</GroupNumber>
+      <FileNumber>70</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_mcwdt.c</PathWithFileName>
+      <FilenameWithoutPath>cy_mcwdt.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
     <File>
       <GroupNumber>9</GroupNumber>
       <FileNumber>71</FileNumber>
@@ -1098,8 +1098,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c</PathWithFileName>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_syspm.c</FilenameWithoutPath>
+      <FilenameWithoutPath>cy_sysclk.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -1110,95 +1110,95 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</PathWithFileName>
-      <FilenameWithoutPath>psoc6_01_cm0p_sleep.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>73</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_uart.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_uart.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>74</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
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bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx

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               <Undefine></Undefine>
-              <IncludePath>..\..\..\components\finsh;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;libs\TARGET_RTT-062S2;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\..\..\include;applications;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\..\..\libcpu\arm\common;..\libraries\IFX_PSOC6_HAL\retarget-io;board\ports;.;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\libraries\HAL_Drivers\config;libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\libraries\IFX_PSOC6_HAL\capsense;board;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include</IncludePath>
+              <IncludePath>..\..\..\components\finsh;..\libraries\HAL_Drivers\config;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;applications;..\..\..\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;libs\TARGET_RTT-062S2;..\..\..\libcpu\arm\common;..\libraries\IFX_PSOC6_HAL\retarget-io;board\ports;board;..\..\..\components\libc\posix\io\stdio;.;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -669,6 +669,11 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c</FilePath>
             </File>
+            <File>
+              <FileName>psoc6_01_cm0p_sleep.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
+            </File>
             <File>
               <FileName>cy_scb_i2c.c</FileName>
               <FileType>1</FileType>
@@ -749,6 +754,11 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c</FilePath>
             </File>
+            <File>
+              <FileName>psoc6_04_cm0p_sleep.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
+            </File>
             <File>
               <FileName>cyhal_lptimer.c</FileName>
               <FileType>1</FileType>
@@ -770,20 +780,15 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c</FilePath>
             </File>
             <File>
-              <FileName>psoc6_04_cm0p_sleep.c</FileName>
+              <FileName>psoc6_02_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
             </File>
             <File>
               <FileName>cyhal_syspm.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c</FilePath>
             </File>
-            <File>
-              <FileName>psoc6_01_cm0p_sleep.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
-            </File>
             <File>
               <FileName>cyhal_uart.c</FileName>
               <FileType>1</FileType>
@@ -815,90 +820,85 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c</FilePath>
             </File>
             <File>
-              <FileName>psoc6_02_cm0p_sleep.c</FileName>
+              <FileName>psoc6_03_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
             </File>
             <File>
               <FileName>cy_syspm.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c</FilePath>
             </File>
-            <File>
-              <FileName>psoc6_03_cm0p_sleep.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
-            </File>
           </Files>
         </Group>
         <Group>
           <GroupName>libs</GroupName>
           <Files>
             <File>
-              <FileName>cycfg_connectivity_bt.c</FileName>
+              <FileName>cycfg_pins.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</FilePath>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_psoc6_cm4.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c</FilePath>
-            </File>
-            <File>
-              <FileName>cybsp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\cybsp.c</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_clocks.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_qspi_memslot.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_routing.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</FilePath>
-            </File>
-            <File>
-              <FileName>startup_psoc6_02_cm4.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_capsense.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</FilePath>
             </File>
             <File>
               <FileName>cycfg.c</FileName>
               <FileType>1</FileType>
               <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c</FilePath>
             </File>
+            <File>
+              <FileName>startup_psoc6_02_cm4.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_qspi_memslot.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_clocks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</FilePath>
+            </File>
             <File>
               <FileName>cycfg_system.c</FileName>
               <FileType>1</FileType>
               <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_dmas.c</FileName>
+              <FileName>cycfg_routing.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</FilePath>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_pins.c</FileName>
+              <FileName>cybsp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</FilePath>
+              <FilePath>libs\TARGET_RTT-062S2\cybsp.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_capsense.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_connectivity_bt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</FilePath>
             </File>
             <File>
               <FileName>cycfg_peripherals.c</FileName>
               <FileType>1</FileType>
               <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c</FilePath>
             </File>
+            <File>
+              <FileName>system_psoc6_cm4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_dmas.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</FilePath>
+            </File>
           </Files>
         </Group>
       </Groups>

bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.h

@@ -214,4 +214,7 @@
 #define BSP_USING_UART
 #define BSP_USING_UART0
 
+/* Board extended module Drivers */
+
+
 #endif