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Fix many abnormal symbols in annotations

This commit is contained in:
Stwsyburg 2023-04-17 09:12:10 +08:00 committed by Man, Jianting (Meco)
parent 371693b5ce
commit ca1b1e5164
24 changed files with 52 additions and 52 deletions
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2
bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/air32f10x_i2c.c
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@ -1161,7 +1161,7 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
}
/**
* @brief Clears the I2Cx�s interrupt pending bits.
* @brief Clears the I2Cx's interrupt pending bits.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:

6
bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/apm32e10x_pmu.c
View File

@ -103,7 +103,7 @@ void PMU_DisablePVD(void)
/*!
* @brief Configure a voltage threshold detected by a power supply voltage detector (PVD).
*
* @param level<EFBFBD><EFBFBD>specifies the PVD detection level
* @param level: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V
* @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V
@ -216,7 +216,7 @@ void PMU_EnterSTANDBYMode(void)
/*!
* @brief Read the specified PWR flag is set or not.
*
* @param flag<EFBFBD><EFBFBD>Reads the status of specifies the flag.
* @param flag: Reads the status of specifies the flag.
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUE : Wake Up flag
* @arg PMU_FLAG_SB : StandBy flag
@ -246,7 +246,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
/*!
* @brief Clears the PWR's pending flags.
*
* @param flag<EFBFBD><EFBFBD>Clears the status of specifies the flag.
* @param flag: Clears the status of specifies the flag.
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUE : Wake Up flag
* @arg PMU_FLAG_SB : StandBy flag

2
bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/apm32e10x_rcm.c
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@ -1051,7 +1051,7 @@ void RCM_ClearStatusFlag(void)
/*!
* @brief Reads the specified RCM interrupt Flag
*
* @param flag <EFBFBD><EFBFBD>Reads specifies RCM interrupt flag.
* @param flag : Reads specifies RCM interrupt flag.
* This parameter can be one of the following values:
* @arg RCM_INT_LSIRDY : LSI ready interrupt flag
* @arg RCM_INT_LSERDY : LSE ready interrupt flag

2
bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/apm32e10x_sdio.c
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@ -304,7 +304,7 @@ uint32_t SDIO_ReadDataCounter(void)
/*!
* @brief Write the SDIO Data
*
* @param Data<EFBFBD><EFBFBD>Write 32-bit data
* @param Data: Write 32-bit data
*
* @retval None
*/

8
bsp/imx6sx/iMX6_Platform_SDK/sdk/include/mx6sdl/registers/regsiomuxc.h
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@ -3104,8 +3104,8 @@ typedef union _hw_iomuxc_gpr5
* ARM WFI event out indicating on WFI state of the cores (these are status, read only bits)
*
* Values:
* - 0 - ARM Core[GPR5-index] is not in “Wait for Interrupt” mode
* - 1 - ARM Core[GPR5-index] is in “Wait for Interrupt” mode
* - 0 - ARM Core[GPR5-index] is not in "Wait for Interrupt" mode
* - 1 - ARM Core[GPR5-index] is in "Wait for Interrupt" mode
*/
//@{
#define BP_IOMUXC_GPR5_ARM_WFI (0) //!< Bit position for IOMUXC_GPR5_ARM_WFI.
@ -3120,8 +3120,8 @@ typedef union _hw_iomuxc_gpr5
* ARM WFE event out indication on WFE state of the cores (these are status, read only bits)
*
* Values:
* - 0 - ARM Core[GPR5-index - 4] is not in “Wait for Event” mode
* - 1 - ARM Core[GPR5-index - 4] is in “Wait for Event” mode
* - 0 - ARM Core[GPR5-index - 4] is not in "Wait for Event" mode
* - 1 - ARM Core[GPR5-index - 4] is in "Wait for Event" mode
*/
//@{
#define BP_IOMUXC_GPR5_ARM_WFE (4) //!< Bit position for IOMUXC_GPR5_ARM_WFE.

8
bsp/imx6sx/iMX6_Platform_SDK/sdk/include/mx6sl/registers/regsiomuxc.h
View File

@ -2260,8 +2260,8 @@ typedef union _hw_iomuxc_gpr5
* ARM WFI event out indicating on WFI state of the cores (these are status, read only bits)
*
* Values:
* - 0 - ARM Core[GPR5-index] is not in <EFBFBD><EFBFBD>Wait for Interrupt<EFBFBD><EFBFBD> mode
* - 1 - ARM Core[GPR5-index] is in <EFBFBD><EFBFBD>Wait for Interrupt<EFBFBD><EFBFBD> mode
* - 0 - ARM Core[GPR5-index] is not in "Wait for Interrupt" mode
* - 1 - ARM Core[GPR5-index] is in "Wait for Interrupt" mode
*/
//@{
#define BP_IOMUXC_GPR5_ARM_WFI (0) //!< Bit position for IOMUXC_GPR5_ARM_WFI.
@ -2276,8 +2276,8 @@ typedef union _hw_iomuxc_gpr5
* ARM WFE event out indication on WFE state of the cores (these are status, read only bits)
*
* Values:
* - 0 - ARM Core[GPR5-index - 4] is not in <EFBFBD><EFBFBD>Wait for Event<EFBFBD><EFBFBD> mode
* - 1 - ARM Core[GPR5-index - 4] is in <EFBFBD><EFBFBD>Wait for Event<EFBFBD><EFBFBD> mode
* - 0 - ARM Core[GPR5-index - 4] is not in "Wait for Event" mode
* - 1 - ARM Core[GPR5-index - 4] is in "Wait for Event" mode
*/
//@{
#define BP_IOMUXC_GPR5_ARM_WFE (4) //!< Bit position for IOMUXC_GPR5_ARM_WFE.

2
bsp/lpc824/Libraries/peri_driver/dma/dma_8xx.h
View File

@ -397,7 +397,7 @@ STATIC INLINE uint32_t Chip_DMA_GetActiveChannels(LPC_DMA_T *pDMA)
* that the channel for that bit (bit 0 = channel 0, bit 1 -
* channel 1, etc.) is busy. A low state is not busy. A DMA
* channel is considered busy when there is any operation
* related to that channel in the DMA controller<EFBFBD>s internal
* related to that channel in the DMA controller's internal
* pipeline.
*/
STATIC INLINE uint32_t Chip_DMA_GetBusyChannels(LPC_DMA_T *pDMA)

2
bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_adc.c
View File

@ -752,7 +752,7 @@ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
}
/**
* @brief Clears the ADCx’s interrupt pending bits.
* @brief Clears the ADCx's interrupt pending bits.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
* This parameter can be any combination of the following values:

2
bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_dma.c
View File

@ -486,7 +486,7 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT)
}
/**
* @brief Clears the DMAy Channelx’s interrupt pending bits.
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:

4
bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rcc.c
View File

@ -704,7 +704,7 @@ void RCC_LSICmd(FunctionalState NewState)
/**
* @brief Configures the RTC clock (RTCCLK).
* Once the RTC clock is selected it can’t be changed unless the
* Once the RTC clock is selected it can't be changed unless the
* Backup domain is reset.
* @param RCC_RTCCLKSource: specifies the RTC clock source.
* This parameter can be one of the following values:
@ -1113,7 +1113,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT)
}
/**
* @brief Clears the RCC’s interrupt pending bits.
* @brief Clears the RCC's interrupt pending bits.
* @param RCC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt

8
bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_tim.c
View File

@ -896,7 +896,7 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
}
/**
* @brief Configures the TIMx’s DMA interface.
* @brief Configures the TIMx's DMA interface.
* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
* peripheral.
* @param TIM_DMABase: DMA Base address.
@ -924,7 +924,7 @@ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurs
}
/**
* @brief Enables or disables the TIMx’s DMA Requests.
* @brief Enables or disables the TIMx's DMA Requests.
* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
* @param TIM_DMASource: specifies the DMA Request sources.
* This parameter can be any combination of the following values:
@ -2125,7 +2125,7 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
}
/**
* @brief Enables or disables the TIMx’s Hall sensor interface.
* @brief Enables or disables the TIMx's Hall sensor interface.
* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM peripheral.
* @param NewState: new state of the TIMx Hall sensor interface.
* This parameter can be: ENABLE or DISABLE.
@ -2149,7 +2149,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
}
/**
* @brief Selects the TIMx’s One Pulse Mode.
* @brief Selects the TIMx's One Pulse Mode.
* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
* @param TIM_OPMode: specifies the OPM Mode to be used.
* This parameter can be one of the following values:

2
bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/hal_rcc.c
View File

@ -687,7 +687,7 @@ ITStatus RCC_GetITStatus(RCC_IT_TypeDef it)
}
////////////////////////////////////////////////////////////////////////////////
/// @brief Clears the RCC<EFBFBD>?interrupt pending bits.
/// @brief Clears the RCC's interrupt pending bits.
/// @param it: specifies the interrupt pending bit to clear.
/// This parameter can be any combination of the following values:
/// @arg RCC_IT_LSIRDY: LSI ready interrupt

2
bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/HAL_adc.c
View File

@ -784,7 +784,7 @@ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
}
/**
* @brief Clears the ADCx’s interrupt pending bits.
* @brief Clears the ADCx's interrupt pending bits.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
* This parameter can be any combination of the following values:

2
bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/HAL_dma.c
View File

@ -476,7 +476,7 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT)
}
/**
* @brief Clears the DMAy Channelx’s interrupt pending bits.
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:

2
bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/HAL_adc.c
View File

@ -752,7 +752,7 @@ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
}
/**
* @brief Clears the ADCx’s interrupt pending bits.
* @brief Clears the ADCx's interrupt pending bits.
* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
* This parameter can be any combination of the following values:

2
bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/HAL_dma.c
View File

@ -486,7 +486,7 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT)
}
/**
* @brief Clears the DMAy Channelx’s interrupt pending bits.
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:

4
bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/HAL_rcc.c
View File

@ -703,7 +703,7 @@ void RCC_LSICmd(FunctionalState NewState)
/**
* @brief Configures the RTC clock (RTCCLK).
* Once the RTC clock is selected it can’t be changed unless the
* Once the RTC clock is selected it can't be changed unless the
* Backup domain is reset.
* @param RCC_RTCCLKSource: specifies the RTC clock source.
* This parameter can be one of the following values:
@ -1109,7 +1109,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT)
}
/**
* @brief Clears the RCC’s interrupt pending bits.
* @brief Clears the RCC's interrupt pending bits.
* @param RCC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt

8
bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/HAL_tim.c
View File

@ -896,7 +896,7 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
}
/**
* @brief Configures the TIMx’s DMA interface.
* @brief Configures the TIMx's DMA interface.
* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
* peripheral.
* @param TIM_DMABase: DMA Base address.
@ -924,7 +924,7 @@ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurs
}
/**
* @brief Enables or disables the TIMx’s DMA Requests.
* @brief Enables or disables the TIMx's DMA Requests.
* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
* @param TIM_DMASource: specifies the DMA Request sources.
* This parameter can be any combination of the following values:
@ -2125,7 +2125,7 @@ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
}
/**
* @brief Enables or disables the TIMx’s Hall sensor interface.
* @brief Enables or disables the TIMx's Hall sensor interface.
* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM peripheral.
* @param NewState: new state of the TIMx Hall sensor interface.
* This parameter can be: ENABLE or DISABLE.
@ -2149,7 +2149,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
}
/**
* @brief Selects the TIMx’s One Pulse Mode.
* @brief Selects the TIMx's One Pulse Mode.
* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
* @param TIM_OPMode: specifies the OPM Mode to be used.
* This parameter can be one of the following values:

4
bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/HAL_uart.c
View File

@ -272,7 +272,7 @@ void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewSta
}
/**
* @brief Enables or disables the UART’s DMA interface.
* @brief Enables or disables the UART's DMA interface.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3 .
@ -423,7 +423,7 @@ ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
}
/**
* @brief Clears the UARTx’s interrupt pending bits.
* @brief Clears the UARTx's interrupt pending bits.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3, UART4 or UART5.

18
bsp/raspberry-pi/raspi3-32/applications/test_device.c
View File

@ -308,11 +308,11 @@ EXIT:
}
#ifdef RT_USING_WDT
#define WDT_DEVICE_NAME "wdg" /* 鐪嬮棬鐙楄澶囧悕绉<EFBFBD> */
static rt_device_t wdg_dev; /* 鐪嬮棬鐙楄澶囧彞鏌<EFBFBD> */
#define WDT_DEVICE_NAME "wdg" /* the name of the watchdog device */
static rt_device_t wdg_dev; /* handle of the watchdog device */
static void idle_hook(void)
{
/* 鍦ㄧ┖闂茬嚎绋嬬殑鍥炶皟鍑芥暟閲屽杺鐙<EFBFBD> */
/* Feed the dog in the callback function of the idle thread */
rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL);
//rt_kprintf("feed the dog!\n ");
}
@ -321,38 +321,38 @@ rt_err_t test_wdt(void)
{
rt_kprintf("Hello Test WDT!\n");
rt_err_t ret = RT_EOK;
rt_uint32_t timeout = 1; /* 婧㈠嚭鏃堕棿锛屽崟浣嶏細绉<EFBFBD> */
rt_uint32_t timeout = 1; /* the overflow time */
char device_name[RT_NAME_MAX];
rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX);
/* 鏍规嵁璁惧鍚嶇О鏌ユ壘鐪嬮棬鐙楄澶囷紝鑾峰彇璁惧鍙ユ焺 */
/* find the watchdog device based on the device's name and obtain the device handle */
wdg_dev = rt_device_find(device_name);
if (!wdg_dev)
{
rt_kprintf("find %s failed!\n", device_name);
return -RT_ERROR;
}
/* 鍒濆鍖栬澶<EFBFBD> */
/* initialize the device */
ret = rt_device_init(wdg_dev);
if (ret != RT_EOK)
{
rt_kprintf("initialize %s failed!\n", device_name);
return -RT_ERROR;
}
/* 璁剧疆鐪嬮棬鐙楁孩鍑烘椂闂<EFBFBD> */
/* set the overflow time of the watch dog */
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout);
if (ret != RT_EOK)
{
rt_kprintf("set %s timeout failed!\n", device_name);
return -RT_ERROR;
}
/* 鍚姩鐪嬮棬鐙<EFBFBD> */
/* start the watchdog */
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
if (ret != RT_EOK)
{
rt_kprintf("start %s failed!\n", device_name);
return -RT_ERROR;
}
/* 璁剧疆绌洪棽绾跨▼鍥炶皟鍑芥暟 */
/* set idle thread callback function */
rt_thread_idle_sethook(idle_hook);
return ret;

4
bsp/tkm32F499/Libraries/Hal_lib/src/HAL_rcc.c
View File

@ -833,7 +833,7 @@ void RCC_LSICmd(FunctionalState NewState)
/**
* @brief Configures the RTC clock (RTCCLK).
* Once the RTC clock is selected it can抰 be changed unless the
* Once the RTC clock is selected it can't be changed unless the
* Backup domain is reset.
* @param RCC_RTCCLKSource: specifies the RTC clock source.
* This parameter can be one of the following values:
@ -1269,7 +1269,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT)
}
/**
* @brief Clears the RCC抯 interrupt pending bits.
* @brief Clears the RCC's interrupt pending bits.
* @param RCC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt

2
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32f10x_i2c.c
View File

@ -956,7 +956,7 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
/*******************************************************************************
* Function Name : I2C_ClearITPendingBit
* Description : Clears the I2Cx’s interrupt pending bits.
* Description : Clears the I2Cx's interrupt pending bits.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_IT: specifies the interrupt pending bit to clear.
* I2C_IT_SMBALERT: SMBus Alert interrupt.

6
bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/core_riscv.h
View File

@ -246,9 +246,9 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
/*******************************************************************************
* Function Name : SetVTFIRQ
* Description : Set VTF Interrupt
* Input : addr<EFBFBD><EFBFBD>VTF interrupt service function base address.
* IRQn<EFBFBD><EFBFBD>Interrupt Numbers
* num<EFBFBD><EFBFBD>VTF Interrupt Numbers
* Input : addr - VTF interrupt service function base address.
* IRQn - Interrupt Numbers
* num - VTF Interrupt Numbers
* NewState: DISABLE or ENABLE
* Return : None
*******************************************************************************/

2
bsp/wch/risc-v/Libraries/ch32v20x_libraries/ch32v208_hal/include/ch32v20x.h
View File

@ -4654,7 +4654,7 @@ typedef struct
#define RB_ETH_EIE_RXIE 0x40 /* RW Receive complete interrupt enable */
#define RB_ETH_EIE_LINKIE 0x10 /* RW Link Change Interrupt Enable */
#define RB_ETH_EIE_TXIE 0x08 /* RW send complete interrupt enable */
#define RB_ETH_EIE_R_EN50 0x04 /* RW TX 50<EFBFBD><EFBFBD> resistor adjustment. 1: On-chip 50<35><30> connected 0: On-chip 50<35><30> disconnected */
#define RB_ETH_EIE_R_EN50 0x04 /* RW TX 50Ω resistor adjustment. 1: On-chip 50Ω connected 0: On-chip 50Ω disconnected */
#define RB_ETH_EIE_TXERIE 0x02 /* RW Transmit Error Interrupt Enable */
#define RB_ETH_EIE_RXERIE 0x01 /* RW1 receive error flag */
#define R8_ETH_EIR (*((volatile uint8_t *)(0x40028000+4))) /* Interrupt Flag Register */