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[BSP] Add RV32M1_VEGA BSP.

This commit is contained in:
Bernard Xiong 2018-12-08 10:44:56 +08:00
parent 36b194aeb6
commit c9576c3e53
28 changed files with 3222 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

441
bsp/rv32m1_vega/ri5cy/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=1024
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40000
CONFIG_ARCH_RISCV=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using WiFi
#
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
CONFIG_RT_USING_ULOG=y
# CONFIG_ULOG_OUTPUT_LVL_A is not set
# CONFIG_ULOG_OUTPUT_LVL_E is not set
# CONFIG_ULOG_OUTPUT_LVL_W is not set
# CONFIG_ULOG_OUTPUT_LVL_I is not set
CONFIG_ULOG_OUTPUT_LVL_D=y
CONFIG_ULOG_OUTPUT_LVL=7
CONFIG_ULOG_USING_ISR_LOG=y
CONFIG_ULOG_ASSERT_ENABLE=y
CONFIG_ULOG_LINE_BUF_SIZE=128
# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set
#
# log format
#
# CONFIG_ULOG_OUTPUT_FLOAT is not set
CONFIG_ULOG_USING_COLOR=y
CONFIG_ULOG_OUTPUT_TIME=y
# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set
CONFIG_ULOG_OUTPUT_LEVEL=y
CONFIG_ULOG_OUTPUT_TAG=y
# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set
CONFIG_ULOG_BACKEND_USING_CONSOLE=y
# CONFIG_ULOG_USING_FILTER is not set
# CONFIG_ULOG_USING_SYSLOG is not set
CONFIG_ULOG_SW_VERSION_NUM=0x00101
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
CONFIG_PKG_USING_MICROPYTHON=y
CONFIG_PKG_MICROPYTHON_PATH="/packages/language/micropython"
#
# Hardware Module
#
# CONFIG_MICROPYTHON_USING_MACHINE_I2C is not set
# CONFIG_MICROPYTHON_USING_MACHINE_SPI is not set
CONFIG_MICROPYTHON_USING_MACHINE_UART=y
#
# System Module
#
CONFIG_MICROPYTHON_USING_UOS=y
CONFIG_MICROPYTHON_USING_THREAD=y
# CONFIG_MICROPYTHON_USING_USELECT is not set
# CONFIG_MICROPYTHON_USING_UCTYPES is not set
# CONFIG_MICROPYTHON_USING_UERRNO is not set
#
# Tools Module
#
# CONFIG_MICROPYTHON_USING_CMATH is not set
# CONFIG_MICROPYTHON_USING_UBINASCII is not set
# CONFIG_MICROPYTHON_USING_UHASHLIB is not set
# CONFIG_MICROPYTHON_USING_UHEAPQ is not set
CONFIG_MICROPYTHON_USING_UJSON=y
# CONFIG_MICROPYTHON_USING_URE is not set
# CONFIG_MICROPYTHON_USING_UZLIB is not set
# CONFIG_MICROPYTHON_USING_URANDOM is not set
#
# Network Module
#
# CONFIG_MICROPYTHON_USING_USOCKET is not set
# CONFIG_MICROPYTHON_USING_USSL is not set
CONFIG_PKG_MICROPYTHON_HEAP_SIZE=8192
CONFIG_PKG_USING_MICROPYTHON_LATEST_VERSION=y
# CONFIG_PKG_USING_MICROPYTHON_V10903 is not set
CONFIG_PKG_MICROPYTHON_VER="latest"
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
CONFIG_SOC_VEGA_RI5CY=y
CONFIG_BOARD_X_FRDM_VEGA=y
CONFIG_BSP_USING_UART0=y

30
bsp/rv32m1_vega/ri5cy/Kconfig Normal file
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mainmenu "RT-Thread Project Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_VEGA_RI5CY
bool
select ARCH_RISCV
config BOARD_X_FRDM_VEGA
bool
select SOC_VEGA_RI5CY
default y
source "driver/Kconfig"

14
bsp/rv32m1_vega/ri5cy/SConscript Normal file
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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

30
bsp/rv32m1_vega/ri5cy/SConstruct Normal file
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import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
objs += SConscript('../rv32m1_sdk_riscv/SConscript')
# make a building
DoBuilding(TARGET, objs)

9
bsp/rv32m1_vega/ri5cy/applications/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

20
bsp/rv32m1_vega/ri5cy/applications/main.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/11/28 Bernard The first version
*/
#include <stdio.h>
#include <stdlib.h>
#include <rtthread.h>
int main(int argc, char** argv)
{
rt_kprintf("Hello RT-Thread!\n");
return 0;
}

28
bsp/rv32m1_vega/ri5cy/applications/mnt.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#ifdef RT_USING_DFS
#include <dfs_fs.h>
int mnt_init(void)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
{
rt_kprintf("File System initialized failed!\n");
}
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif

16
bsp/rv32m1_vega/ri5cy/board/SConscript Normal file
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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
board.c
pin_mux.c
clock_config.c
fsl_host.c
''')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

76
bsp/rv32m1_vega/ri5cy/board/board.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/11/29 Bernard the first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
#include "pin_mux.h"
#include "clock_config.h"
#include <fsl_clock.h>
#include <fsl_intmux.h>
void LPIT0_IRQHandler(void)
{
rt_tick_increase();
SystemClearSystickFlag();
}
int rt_hw_systick_init(void)
{
CLOCK_SetIpSrc(kCLOCK_Lpit0, kCLOCK_IpSrcFircAsync);
SystemSetupSystick (RT_TICK_PER_SECOND, 0);
SystemClearSystickFlag();
return 0;
}
const scg_lpfll_config_t g_appScgLpFllConfig_BOARD_BootClockRUN = {
.enableMode = kSCG_LpFllEnable, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
.trimConfig = NULL,
};
void rt_hw_board_init(void)
{
BOARD_InitPins();
BOARD_BootClockRUN();
/* Init LPFLL */
CLOCK_InitLpFll(&g_appScgLpFllConfig_BOARD_BootClockRUN);
INTMUX_Init(INTMUX0);
INTMUX_EnableInterrupt(INTMUX0, 0, PORTC_IRQn);
/* initialize hardware interrupt */
rt_hw_uart_init();
rt_hw_systick_init();
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

65
bsp/rv32m1_vega/ri5cy/board/board.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <stdint.h>
extern unsigned char __bss_start__;
extern unsigned char __bss_end__;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end__
#define RT_HW_HEAP_END (void*)(0x20000000 + 0x00030000 - 0x1800)
#define BOARD_USDHC0_BASEADDR USDHC0
#define BOARD_USDHC_CD_PORT_BASE PORTC
#define BOARD_USDHC_CD_GPIO_BASE GPIOC
#define BOARD_USDHC_CD_GPIO_PIN 27
#define BOARD_USDHC_CD_PORT_IRQ PORTC_IRQn
#define BOARD_USDHC_CD_PORT_IRQ_HANDLER PORTC_IRQHandler
#define BOARD_USDHC_CD_GPIO_INIT() \
{ \
gpio_pin_config_t sw_config = {kGPIO_DigitalInput, 0}; \
GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
PORT_SetPinInterruptConfig(BOARD_USDHC_CD_PORT_BASE, BOARD_USDHC_CD_GPIO_PIN, kPORT_InterruptRisingEdge); \
}
#define BOARD_USDHC_CD_STATUS() (GPIO_ReadPinInput(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_GetPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_ClearPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (1U)
#define BOARD_USDHC0_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Sdhc0))
#define BOARD_SD_HOST_BASEADDR BOARD_USDHC0_BASEADDR
#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
#define BOARD_SD_HOST_IRQ USDHC0_IRQn
#define BOARD_SD_SUPPORT_180V (0U)
#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC0_BASEADDR
#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
#define BOARD_MMC_HOST_IRQ USDHC0_IRQn
#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
#define BOARD_MMC_PIN_CONFIG(speed, strength)
/* this define not implement, due to EVK board have no power reset circuit */
#define BOARD_SD_POWER_RESET_GPIO ()
#define BOARD_SD_POWER_RESET_GPIO_PIN ()
#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
#define BOARD_USDHC_SDCARD_POWER_CONTROL(state)
#define BOARD_SD_PIN_CONFIG(speed, strength)
#define BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
void rt_hw_board_init(void);
#endif

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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
* Note: The clock could not be set when it is being used as system clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M),
* so before setting FIRC, change to use another avaliable clock source.
*
* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
*
* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
* Wait until the system clock source is changed to target source.
*
* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
* Supported run mode and clock restrictions could be found in Reference Manual.
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v3.0
processor: RV32M1
package_id: RV32M1
mcu_data: ksdk2_0
processor_version: 0.0.0
board: RV32M1_VEGA
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "fsl_msmc.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
#ifndef SDK_SECONDARY_CORE
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_FircSafeConfig
* Description : This function is used to safely configure FIRC clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M).
* Before setting FIRC, change to use SIRC as system clock,
* then configure FIRC.
* Param fircConfig : FIRC configuration.
*
*END**************************************************************************/
static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
{
scg_sys_clk_config_t curConfig;
const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
.div1 = kSCG_AsyncClkDisable,
.div2 = kSCG_AsyncClkDivBy2,
.range = kSCG_SircRangeHigh};
scg_sys_clk_config_t sysClkSafeConfigSource = {
.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
.divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
.src = kSCG_SysClkSrcSirc /* System clock source. */
};
/* Init Sirc */
CLOCK_InitSirc(&scgSircConfig);
/* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != sysClkSafeConfigSource.src);
/* Init Firc */
CLOCK_InitFirc(fircConfig);
}
#endif
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 48 MHz}
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 48 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
{
.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
{
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init FIRC */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
/* Set SCG to FIRC mode. */
CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
#endif
}
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockHSRUN
outputs:
- {id: Bus_clock.outFreq, value: 72 MHz}
- {id: Core_clock.outFreq, value: 72 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 72 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 8 MHz}
- {id: System_clock.outFreq, value: 72 MHz}
settings:
- {id: SCGMode, value: LPFLL}
- {id: powerMode, value: HSRUN}
- {id: SCG.DIVCORE.scale, value: '1', locked: true}
- {id: SCG.DIVSLOW.scale, value: '9'}
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.TRIMDIV.scale, value: '24'}
- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockHSRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
{
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
.src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockHSRUN configuration
******************************************************************************/
void BOARD_BootClockHSRUN(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init FIRC */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
/* Set HSRUN power mode */
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC0);
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
{
}
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC1);
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
{
}
#endif
/* Set SCG to LPFLL mode. */
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
#endif
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 2 MHz}
- {id: Core_clock.outFreq, value: 4 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 4 MHz}
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 4000/9 kHz}
- {id: System_clock.outFreq, value: 4 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: powerMode, value: VLPR}
- {id: SCG.DIVBUS.scale, value: '2', locked: true}
- {id: SCG.DIVCORE.scale, value: '2', locked: true}
- {id: SCG.DIVSLOW.scale, value: '9'}
- {id: SCG.FIRCDIV1.scale, value: '1'}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
{
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
.divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
{
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
/* Set SCG to SIRC mode. */
CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
/* Init FIRC */
CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC0);
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
{
}
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC1);
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
{
}
#endif
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
#endif
}

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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief SCG set for BOARD_BootClockRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockHSRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 72000000U /*!< Core clock frequency: 72000000Hz */
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockHSRUN;
/*******************************************************************************
* API for BOARD_BootClockHSRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockHSRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockVLPR;
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_host.h"
#include "board.h"
#include "fsl_gpio.h"
#ifdef BOARD_USDHC_CD_PORT_BASE
#include "fsl_port.h"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief host controller error recovery.
* @param host base address.
*/
static void Host_ErrorRecovery(HOST_TYPE *hostBase);
/*******************************************************************************
* Variables
******************************************************************************/
/* DMA descriptor should allocate at non-cached memory */
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN);
extern volatile uint32_t g_timeMilliseconds;
static volatile bool g_sdInsertedFlag;
/*******************************************************************************
* Code
******************************************************************************/
/* Card detect. */
status_t CardInsertDetect(HOST_TYPE *hostBase)
{
return kStatus_Success;
}
/* User defined transfer function. */
static status_t USDHC_TransferFunction(USDHC_Type *base, usdhc_transfer_t *content)
{
status_t error = kStatus_Success;
usdhc_adma_config_t dmaConfig;
if (content->data != NULL)
{
memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
/* config adma */
dmaConfig.dmaMode = USDHC_DMA_MODE;
dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
dmaConfig.admaTable = g_usdhcAdma2Table;
dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
}
error = USDHC_TransferBlocking(base, &dmaConfig, content);
if (error == kStatus_Fail)
{
/* host error recovery */
Host_ErrorRecovery(base);
}
return error;
}
static void Host_ErrorRecovery(HOST_TYPE *hostBase)
{
uint32_t status = 0U;
/* get host present status */
status = USDHC_GetPresentStatusFlags(hostBase);
/* check command inhibit status flag */
if ((status & kUSDHC_CommandInhibitFlag) != 0U)
{
/* reset command line */
USDHC_Reset(hostBase, kUSDHC_ResetCommand, 100U);
}
/* check data inhibit status flag */
if ((status & kUSDHC_DataInhibitFlag) != 0U)
{
/* reset data line */
USDHC_Reset(hostBase, kUSDHC_ResetData, 100U);
}
}
status_t HOST_Init(void *host)
{
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
/* init card power control */
HOST_INIT_SD_POWER();
HOST_INIT_MMC_POWER();
/* Initializes USDHC. */
usdhcHost->config.dataTimeout = USDHC_DATA_TIMEOUT;
usdhcHost->config.endianMode = USDHC_ENDIAN_MODE;
usdhcHost->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
usdhcHost->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
usdhcHost->config.readBurstLen = USDHC_READ_BURST_LEN;
usdhcHost->config.writeBurstLen = USDHC_WRITE_BURST_LEN;
USDHC_Init(usdhcHost->base, &(usdhcHost->config));
/* Define transfer function. */
usdhcHost->transfer = USDHC_TransferFunction;
return kStatus_Success;
}
void HOST_Reset(HOST_TYPE *hostBase)
{
/* voltage switch to normal but not 1.8V */
HOST_SWITCH_VOLTAGE180V(hostBase, false);
/* Disable DDR mode */
HOST_ENABLE_DDR_MODE(hostBase, false);
/* disable tuning */
HOST_EXECUTE_STANDARD_TUNING_ENABLE(hostBase, false);
/* Disable HS400 mode */
HOST_ENABLE_HS400_MODE(hostBase, false);
/* Disable DLL */
HOST_ENABLE_STROBE_DLL(hostBase, false);
}
void HOST_Deinit(void *host)
{
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
USDHC_Deinit(usdhcHost->base);
}

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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v3.0
processor: RV32M1
package_id: RV32M1
mcu_data: ksdk2_0
processor_version: 0.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
*END**************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
#define PIN6_IDX 6u /*!< Pin number for pin 6 in a port */
#define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
#define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
#define PIN9_IDX 9u /*!< Pin number for pin 9 in a port */
#define PIN10_IDX 10u /*!< Pin number for pin 10 in a port */
#define PIN11_IDX 11u /*!< Pin number for pin 11 in a port */
#define PIN22_IDX 22u /*!< Pin number for pin 22 in a port */
#define PIN23_IDX 23u /*!< Pin number for pin 23 in a port */
#define PIN24_IDX 24u /*!< Pin number for pin 24 in a port */
#define PIN27_IDX 27u /*!< Pin number for pin 27 in a port */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
- pin_list:
- {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
- {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
- {pin_num: U11, peripheral: SDHC0, signal: CMD, pin_signal: ADC0_SE12/PTD9/SDHC0_CMD/LPSPI2_SIN/LPI2C1_SCLS/TRACE_DATA0/TPM2_CH2/FXIO0_D29, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: P10, peripheral: SDHC0, signal: 'DATA, 0', pin_signal: ADC0_SE10/PTD7/SDHC0_D0/LPSPI2_SOUT/EMVSIM0_PD/TRACE_DATA2/TPM2_CH4/FXIO0_D27, slew_rate: fast,
open_drain: disable, pull_select: up, pull_enable: enable}
- {pin_num: U9, peripheral: SDHC0, signal: 'DATA, 1', pin_signal: ADC0_SE9/PTD6/SDHC0_D1/LPSPI2_SCK/EMVSIM0_IO/TRACE_DATA3/TPM2_CH5/FXIO0_D26, slew_rate: fast,
open_drain: disable, pull_select: up, pull_enable: enable}
- {pin_num: R11, peripheral: SDHC0, signal: 'DATA, 2', pin_signal: ADC0_SE14/PTD11/SDHC0_D2/USB0_SOF_OUT/LPI2C1_SCL/CLKOUT/TPM2_CH0/FXIO0_D31, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: P11, peripheral: SDHC0, signal: 'DATA, 3', pin_signal: ADC0_SE13/PTD10/LLWU_P20/SDHC0_D3/LPSPI2_PCS0/LPI2C1_SDA/TRACE_CLK_OUT/TPM2_CH1/FXIO0_D30, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: T9, peripheral: SDHC0, signal: DCLK, pin_signal: ADC0_SE11/PTD8/LLWU_P19/SDHC0_DCLK/LPSPI2_PCS2/LPI2C1_SDAS/TRACE_DATA1/TPM2_CH3/FXIO0_D28, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: P6, peripheral: GPIOC, signal: 'GPIO, 27', pin_signal: PTC27/TPM0_CH4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
*END**************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortD); /* Clock Gate Control: 0x01u */
const port_pin_config_t portc27_pinP6_config = {
kPORT_PullDisable, /* Internal pull-up/down resistor is disabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAsGpio, /* Pin is configured as PTC27 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTC, PIN27_IDX, &portc27_pinP6_config); /* PORTC27 (pin P6) is configured as PTC27 */
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
const port_pin_config_t portd10_pinP11_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D3 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN10_IDX, &portd10_pinP11_config); /* PORTD10 (pin P11) is configured as SDHC0_D3 */
const port_pin_config_t portd11_pinR11_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D2 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN11_IDX, &portd11_pinR11_config); /* PORTD11 (pin R11) is configured as SDHC0_D2 */
const port_pin_config_t portd6_pinU9_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D1 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN6_IDX, &portd6_pinU9_config); /* PORTD6 (pin U9) is configured as SDHC0_D1 */
const port_pin_config_t portd7_pinP10_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D0 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN7_IDX, &portd7_pinP10_config); /* PORTD7 (pin P10) is configured as SDHC0_D0 */
const port_pin_config_t portd8_pinT9_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_DCLK */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN8_IDX, &portd8_pinT9_config); /* PORTD8 (pin T9) is configured as SDHC0_DCLK */
const port_pin_config_t portd9_pinU11_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_CMD */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN9_IDX, &portd9_pinU11_config); /* PORTD9 (pin U11) is configured as SDHC0_CMD */
PORT_SetPinMux(PORTA, PIN22_IDX, kPORT_MuxAsGpio); /* PORTA22 (pin D6) is configured as PTA24 */
PORT_SetPinMux(PORTA, PIN23_IDX, kPORT_MuxAsGpio); /* PORTA23 (pin D6) is configured as PTA24 */
PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio); /* PORTA24 (pin D6) is configured as PTA24 */
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/*******************************************************************************
* EOF
******************************************************************************/

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config BSP_USING_UART0
bool "Enable UART0 (PTC7/PTC8)"
default y

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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
drv_uart.c
''')
CPPPATH = [cwd]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_I2C'):
src += ['drv_i2c.c']
if GetDepend('RT_USING_DFS_ELMFAT'):
src += ['drv_sdcard.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-03-13 Liuguang the first version.
* 2018-03-19 Liuguang add GPIO interrupt mode support.
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_gpio.h"
#include "fsl_common.h"
#include "fsl_gpio.h"
#include "fsl_port.h"
#ifdef RT_USING_PIN
struct vega_pin
{
rt_uint16_t pin;
GPIO_Type *gpio;
rt_uint32_t gpio_pin;
};
struct vega_irq
{
rt_uint16_t enable;
struct rt_pin_irq_hdr irq_info;
};
#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
#define __VEGA_PIN_DEFAULT {0, 0, 0}
#define __VEGA_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN}
static const struct vega_pin vega_pin_map[] =
{
__VEGA_PIN_DEFAULT,
/* GPIOA */
__VEGA_PIN(1, GPIOA, 0),
__VEGA_PIN(2, GPIOA, 1),
__VEGA_PIN(3, GPIOA, 2),
__VEGA_PIN(4, GPIOA, 3),
__VEGA_PIN(5, GPIOA, 4),
__VEGA_PIN(6, GPIOA, 5),
__VEGA_PIN(7, GPIOA, 6),
__VEGA_PIN(8, GPIOA, 7),
__VEGA_PIN(9, GPIOA, 8),
__VEGA_PIN(10, GPIOA, 9),
__VEGA_PIN(11, GPIOA, 10),
__VEGA_PIN(12, GPIOA, 11),
__VEGA_PIN(13, GPIOA, 12),
__VEGA_PIN(14, GPIOA, 13),
__VEGA_PIN(15, GPIOA, 14),
__VEGA_PIN(16, GPIOA, 15),
__VEGA_PIN(17, GPIOA, 16),
__VEGA_PIN(18, GPIOA, 17),
__VEGA_PIN(19, GPIOA, 18),
__VEGA_PIN(20, GPIOA, 19),
__VEGA_PIN(21, GPIOA, 20),
__VEGA_PIN(22, GPIOA, 21),
__VEGA_PIN(23, GPIOA, 22),
__VEGA_PIN(24, GPIOA, 23),
__VEGA_PIN(25, GPIOA, 24),
__VEGA_PIN(26, GPIOA, 25),
__VEGA_PIN(27, GPIOA, 26),
__VEGA_PIN(28, GPIOA, 27),
__VEGA_PIN(29, GPIOA, 28),
__VEGA_PIN(30, GPIOA, 29),
__VEGA_PIN(31, GPIOA, 30),
__VEGA_PIN(32, GPIOA, 31),
/* GPIOB */
__VEGA_PIN(33, GPIOB, 0),
__VEGA_PIN(34, GPIOB, 1),
__VEGA_PIN(35, GPIOB, 2),
__VEGA_PIN(36, GPIOB, 3),
__VEGA_PIN(37, GPIOB, 4),
__VEGA_PIN(38, GPIOB, 5),
__VEGA_PIN(39, GPIOB, 6),
__VEGA_PIN(40, GPIOB, 7),
__VEGA_PIN(41, GPIOB, 8),
__VEGA_PIN(42, GPIOB, 9),
__VEGA_PIN(43, GPIOB, 10),
__VEGA_PIN(44, GPIOB, 11),
__VEGA_PIN(45, GPIOB, 12),
__VEGA_PIN(46, GPIOB, 13),
__VEGA_PIN(47, GPIOB, 14),
__VEGA_PIN(48, GPIOB, 15),
__VEGA_PIN(49, GPIOB, 16),
__VEGA_PIN(50, GPIOB, 17),
__VEGA_PIN(51, GPIOB, 18),
__VEGA_PIN(52, GPIOB, 19),
__VEGA_PIN(53, GPIOB, 20),
__VEGA_PIN(54, GPIOB, 21),
__VEGA_PIN(55, GPIOB, 22),
__VEGA_PIN(56, GPIOB, 23),
__VEGA_PIN(57, GPIOB, 24),
__VEGA_PIN(58, GPIOB, 25),
__VEGA_PIN(59, GPIOB, 26),
__VEGA_PIN(60, GPIOB, 27),
__VEGA_PIN(61, GPIOB, 28),
__VEGA_PIN(62, GPIOB, 29),
__VEGA_PIN(63, GPIOB, 30),
__VEGA_PIN(64, GPIOB, 31),
/* GPIOC */
__VEGA_PIN(65, GPIOC, 0),
__VEGA_PIN(66, GPIOC, 1),
__VEGA_PIN(67, GPIOC, 2),
__VEGA_PIN(68, GPIOC, 3),
__VEGA_PIN(69, GPIOC, 4),
__VEGA_PIN(70, GPIOC, 5),
__VEGA_PIN(71, GPIOC, 6),
__VEGA_PIN(72, GPIOC, 7),
__VEGA_PIN(73, GPIOC, 8),
__VEGA_PIN(74, GPIOC, 9),
__VEGA_PIN(75, GPIOC, 10),
__VEGA_PIN(76, GPIOC, 11),
__VEGA_PIN(77, GPIOC, 12),
__VEGA_PIN(78, GPIOC, 13),
__VEGA_PIN(79, GPIOC, 14),
__VEGA_PIN(80, GPIOC, 15),
__VEGA_PIN(81, GPIOC, 16),
__VEGA_PIN(82, GPIOC, 17),
__VEGA_PIN(83, GPIOC, 18),
__VEGA_PIN(84, GPIOC, 19),
__VEGA_PIN(85, GPIOC, 20),
__VEGA_PIN(86, GPIOC, 21),
__VEGA_PIN(87, GPIOC, 22),
__VEGA_PIN(88, GPIOC, 23),
__VEGA_PIN(89, GPIOC, 24),
__VEGA_PIN(90, GPIOC, 25),
__VEGA_PIN(91, GPIOC, 26),
__VEGA_PIN(92, GPIOC, 27),
__VEGA_PIN(93, GPIOC, 28),
__VEGA_PIN(94, GPIOC, 29),
__VEGA_PIN(95, GPIOC, 30),
__VEGA_PIN(96, GPIOC, 31),
/* GPIOD */
__VEGA_PIN(97, GPIOD, 0),
__VEGA_PIN(98, GPIOD, 1),
__VEGA_PIN(99, GPIOD, 2),
__VEGA_PIN(100, GPIOD, 3),
__VEGA_PIN(101, GPIOD, 4),
__VEGA_PIN(102, GPIOD, 5),
__VEGA_PIN(103, GPIOD, 6),
__VEGA_PIN(104, GPIOD, 7),
__VEGA_PIN(105, GPIOD, 8),
__VEGA_PIN(106, GPIOD, 9),
__VEGA_PIN(107, GPIOD, 10),
__VEGA_PIN(108, GPIOD, 11),
__VEGA_PIN(109, GPIOD, 12),
__VEGA_PIN(110, GPIOD, 13),
__VEGA_PIN(111, GPIOD, 14),
__VEGA_PIN(112, GPIOD, 15),
__VEGA_PIN(113, GPIOD, 16),
__VEGA_PIN(114, GPIOD, 17),
__VEGA_PIN(115, GPIOD, 18),
__VEGA_PIN(116, GPIOD, 19),
__VEGA_PIN(117, GPIOD, 20),
__VEGA_PIN(118, GPIOD, 21),
__VEGA_PIN(119, GPIOD, 22),
__VEGA_PIN(120, GPIOD, 23),
__VEGA_PIN(121, GPIOD, 24),
__VEGA_PIN(122, GPIOD, 25),
__VEGA_PIN(123, GPIOD, 26),
__VEGA_PIN(124, GPIOD, 27),
__VEGA_PIN(125, GPIOD, 28),
__VEGA_PIN(126, GPIOD, 29),
__VEGA_PIN(127, GPIOD, 30),
__VEGA_PIN(128, GPIOD, 31),
/* GPIOE */
__VEGA_PIN(129, GPIOE, 0),
__VEGA_PIN(130, GPIOE, 1),
__VEGA_PIN(131, GPIOE, 2),
__VEGA_PIN(132, GPIOE, 3),
__VEGA_PIN(133, GPIOE, 4),
__VEGA_PIN(134, GPIOE, 5),
__VEGA_PIN(135, GPIOE, 6),
__VEGA_PIN(136, GPIOE, 7),
__VEGA_PIN(137, GPIOE, 8),
__VEGA_PIN(138, GPIOE, 9),
__VEGA_PIN(139, GPIOE, 10),
__VEGA_PIN(140, GPIOE, 11),
__VEGA_PIN(141, GPIOE, 12),
__VEGA_PIN(142, GPIOE, 13),
__VEGA_PIN(143, GPIOE, 14),
__VEGA_PIN(144, GPIOE, 15),
__VEGA_PIN(145, GPIOE, 16),
__VEGA_PIN(146, GPIOE, 17),
__VEGA_PIN(147, GPIOE, 18),
__VEGA_PIN(148, GPIOE, 19),
__VEGA_PIN(149, GPIOE, 20),
__VEGA_PIN(150, GPIOE, 21),
__VEGA_PIN(151, GPIOE, 22),
__VEGA_PIN(152, GPIOE, 23),
__VEGA_PIN(153, GPIOE, 24),
__VEGA_PIN(154, GPIOE, 25),
__VEGA_PIN(155, GPIOE, 26),
__VEGA_PIN(156, GPIOE, 27),
__VEGA_PIN(157, GPIOE, 28),
__VEGA_PIN(158, GPIOE, 29),
__VEGA_PIN(159, GPIOE, 30),
__VEGA_PIN(160, GPIOE, 31),
};
static struct vega_irq vega_irq_map[] =
{
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
};
void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
{
if((GPIO_GetPinsInterruptFlags(base) & (1 << gpio_pin)) != 0)
{
GPIO_ClearPinsInterruptFlags(base, gpio_pin);
if(vega_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
{
vega_irq_map[gpio_pin].irq_info.hdr(vega_irq_map[gpio_pin].irq_info.args);
}
}
}
static IRQn_Type vega_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
{
IRQn_Type irq_num = NotAvail_IRQn; /* Invalid interrupt number */
if(gpio == GPIOA)
{
irq_num = PORTA_IRQn;
}
else if(gpio == GPIOB)
{
irq_num = PORTB_IRQn;
}
else if(gpio == GPIOC)
{
irq_num = PORTC_IRQn;
}
else if(gpio == GPIOD)
{
irq_num = PORTD_IRQn;
}
else if(gpio == GPIOE)
{
irq_num = PORTE_IRQn;
}
return irq_num;
}
static void vega_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
clock_ip_name_t clock;
gpio_pin_config_t gpio;
rt_uint32_t config_value = 0;
if((pin > __ARRAY_LEN(vega_pin_map)) || (pin == 0))
{
return;
}
if (vega_pin_map[pin].gpio == GPIOA)
clock = kCLOCK_PortA;
if (vega_pin_map[pin].gpio == GPIOB)
clock = kCLOCK_PortB;
if (vega_pin_map[pin].gpio == GPIOC)
clock = kCLOCK_PortC;
if (vega_pin_map[pin].gpio == GPIOD)
clock = kCLOCK_PortD;
if (vega_pin_map[pin].gpio == GPIOE)
clock = kCLOCK_PortE;
CLOCK_EnableClock(clock);
gpio.outputLogic = 0;
switch(mode)
{
case PIN_MODE_OUTPUT:
{
config_value = 0x1030U;
gpio.pinDirection = kGPIO_DigitalOutput;
}
break;
case PIN_MODE_INPUT:
{
config_value = 0x1030U;
gpio.pinDirection = kGPIO_DigitalInput;
}
break;
case PIN_MODE_INPUT_PULLDOWN:
{
config_value = 0x1030U;
gpio.pinDirection = kGPIO_DigitalInput;
}
break;
case PIN_MODE_INPUT_PULLUP:
{
config_value = 0x5030U;
gpio.pinDirection = kGPIO_DigitalInput;
}
break;
case PIN_MODE_OUTPUT_OD:
{
config_value = 0x1830U;
gpio.pinDirection = kGPIO_DigitalOutput;
}
break;
}
GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio);
}
static int vega_pin_read(rt_device_t dev, rt_base_t pin)
{
uint32_t value;
value = GPIO_ReadPinInput(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
if (value) return PIN_HIGH;
return PIN_LOW;
}
static void vega_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
if (value == PIN_HIGH)
GPIO_SetPinsOutput(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
else
GPIO_ClearPinsOutput(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
}
static rt_err_t vega_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct vega_pin* pin_map = RT_NULL;
struct vega_irq* irq_map = RT_NULL;
pin_map = &vega_pin_map[pin];
irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL)
{
return -RT_ENOSYS;
}
if(irq_map->enable == PIN_IRQ_ENABLE)
{
return -RT_EBUSY;
}
irq_map->irq_info.pin = pin;
irq_map->irq_info.hdr = hdr;
irq_map->irq_info.mode = mode;
irq_map->irq_info.args = args;
return RT_EOK;
}
static rt_err_t vega_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct vega_pin* pin_map = RT_NULL;
struct vega_irq* irq_map = RT_NULL;
pin_map = &vega_pin_map[pin];
irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL)
{
return RT_ENOSYS;
}
if(irq_map->enable == PIN_IRQ_DISABLE)
{
return RT_EOK;
}
irq_map->irq_info.pin = PIN_IRQ_PIN_NONE;
irq_map->irq_info.hdr = RT_NULL;
irq_map->irq_info.mode = PIN_IRQ_MODE_RISING;
irq_map->irq_info.args = RT_NULL;
return RT_EOK;
}
static rt_err_t vega_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
gpio_pin_config_t gpio;
IRQn_Type irq_num;
rt_uint32_t config_value = 0x1b0a0;
const struct vega_pin* pin_map = RT_NULL;
struct vega_irq* irq_map = RT_NULL;
pin_map = &vega_pin_map[pin];
irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL)
{
return -RT_ENOSYS;
}
if(enabled == PIN_IRQ_ENABLE)
{
if(irq_map->enable == PIN_IRQ_ENABLE)
{
return -RT_EBUSY;
}
if(irq_map->irq_info.pin != pin)
{
return RT_EIO;
}
irq_map->enable = PIN_IRQ_ENABLE;
gpio.pinDirection = kGPIO_DigitalInput;
gpio.outputLogic = 0;
irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
/* TODOL enable port */
EnableIRQ(irq_num);
GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio);
// GPIO_EnablePinsInterruptFlags(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
}
else if(enabled == PIN_IRQ_DISABLE)
{
if(irq_map->enable == PIN_IRQ_DISABLE)
{
return RT_EOK;
}
irq_map->enable = PIN_IRQ_DISABLE;
irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
DisableIRQ(irq_num);
}
else
{
return -RT_EINVAL;
}
return RT_EOK;
}
static const struct rt_pin_ops vega_pin_ops =
{
vega_pin_mode,
vega_pin_write,
vega_pin_read,
vega_pin_attach_irq,
vega_pin_detach_irq,
vega_pin_irq_enable
};
int rt_hw_pin_init(void)
{
int ret = RT_EOK;
ret = rt_device_pin_register("pin", &vega_pin_ops, RT_NULL);
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /*RT_USING_PIN */

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int hw_gpio_init(void);
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtdevice.h>
#include <rtthread.h>
#include <dfs_fs.h>
#include "drv_sdcard.h"
#include "fsl_card.h"
static sd_card_t g_sd;
static sd_card_t *card = &g_sd;
static struct rt_device sdcard_device;
static struct dfs_partition part;
static rt_err_t vega_sdcard_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t vega_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t vega_sdcard_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t vega_sdcard_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
status_t status;
status = SD_ReadBlocks(card, buffer, part.offset + pos, size);
if (status == kStatus_Success) return size;
rt_kprintf("read failed: %d, pos 0x%08x, size %d\n", status, pos, size);
return 0;
}
static rt_size_t vega_sdcard_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
status_t status;
status = SD_WriteBlocks(card, buffer, part.offset + pos, size);
if (status == kStatus_Success) return size;
rt_kprintf("write failed: %d, pos 0x%08x, size %d\n", status, pos, size);
return 0;
}
static rt_err_t vega_sdcard_control(rt_device_t dev, int cmd, void *args)
{
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
if (dev->user_data == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = card->blockSize;
geometry->block_size = card->blockSize;
geometry->sector_count = card->blockCount;
}
return RT_EOK;
}
int rt_hw_sdcard_init(void)
{
/* set SDHC0 clock source */
CLOCK_SetIpSrc(kCLOCK_Sdhc0, kCLOCK_IpSrcLpFllAsync);
/* Save host information. */
card->host.base = USDHC0;
card->host.sourceClock_Hz = CLOCK_GetIpFreq(kCLOCK_Sdhc0);
/* Init card. */
if (SD_Init(card))
{
rt_kprintf("SD card init failed.\r\n");
return -1;
}
else
{
bool status;
rt_uint8_t *sector;
/* get the first sector to read partition table */
sector = (rt_uint8_t *) rt_malloc(card->blockSize);
if (sector == RT_NULL)
{
rt_kprintf("allocate partition sector buffer failed\n");
return -1;
}
status = SD_ReadBlocks(card, sector, 0, 1);
if (status == true)
{
/* get the first partition */
if (dfs_filesystem_get_partition(&part, sector, 0) != 0)
{
/* there is no partition */
part.offset = 0;
part.size = 0;
}
}
else
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
/* release sector buffer */
rt_free(sector);
/* register sdcard device */
sdcard_device.type = RT_Device_Class_Block;
sdcard_device.init = vega_sdcard_init;
sdcard_device.open = vega_sdcard_open;
sdcard_device.close = vega_sdcard_close;
sdcard_device.read = vega_sdcard_read;
sdcard_device.write = vega_sdcard_write;
sdcard_device.control = vega_sdcard_control;
/* no private */
sdcard_device.user_data = (void*)card;
rt_device_register(&sdcard_device, "sd0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
}
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_sdcard_init);

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bsp/rv32m1_vega/ri5cy/driver/drv_sdcard.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef DRV_SDCARD_H__
#define DRV_SDCARD_H__
int rt_hw_sdcard_init(void);
#endif

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bsp/rv32m1_vega/ri5cy/driver/drv_uart.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard Unify UART driver for FSL library.
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_uart.h"
#include "fsl_lpuart.h"
struct fsl_uart
{
LPUART_Type *uart_base;
IRQn_Type irqn;
struct rt_serial_device *serial;
char *device_name;
};
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg);
static int uart_putc(struct rt_serial_device *serial, char c);
static int uart_getc(struct rt_serial_device *serial);
static rt_size_t uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
static void uart_irq_handler(int irqno, void *param);
const struct rt_uart_ops _uart_ops =
{
uart_configure,
uart_control,
uart_putc,
uart_getc,
uart_dma_transmit
};
static void uart_isr(struct rt_serial_device *serial);
#if defined(BSP_USING_UART0)
struct rt_serial_device serial0;
void LPUART0_IRQHandler(void)
{
uart_isr(&serial0);
}
#endif
static const struct fsl_uart uarts[] =
{
#ifdef BSP_USING_UART0
{
LPUART0,
LPUART0_IRQn,
&serial0,
"uart0",
},
#endif
};
/*
* UART Initiation
*/
int rt_hw_uart_init(void)
{
int i;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &_uart_ops;
uarts[i].serial->config = config;
/* register UART device */
rt_hw_serial_register(uarts[i].serial,
uarts[i].device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
(void *)&uarts[i]);
}
return 0;
}
/*
* UART interface
*/
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct fsl_uart *uart;
lpuart_config_t config;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct fsl_uart *)serial->parent.user_data;
LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = cfg->baud_rate;
switch (cfg->data_bits)
{
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
case DATA_BITS_7:
config.dataBitsCount = kLPUART_SevenDataBits;
break;
#endif
default:
config.dataBitsCount = kLPUART_EightDataBits;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_2:
config.stopBitCount = kLPUART_TwoStopBit;
break;
default:
config.stopBitCount = kLPUART_OneStopBit;
break;
}
switch (cfg->parity)
{
case PARITY_ODD:
config.parityMode = kLPUART_ParityOdd;
break;
case PARITY_EVEN:
config.parityMode = kLPUART_ParityEven;
break;
default:
config.parityMode = kLPUART_ParityDisabled;
break;
}
config.enableTx = true;
config.enableRx = true;
CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
uint32_t uartClkSrcFreq = CLOCK_GetIpFreq(kCLOCK_Lpuart0);
LPUART_Init(uart->uart_base, &config, uartClkSrcFreq);
LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
return RT_EOK;
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct fsl_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct fsl_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
DisableIRQ(uart->irqn);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
EnableIRQ(uart->irqn);
break;
}
return RT_EOK;
}
static int uart_putc(struct rt_serial_device *serial, char c)
{
struct fsl_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct fsl_uart *)serial->parent.user_data;
LPUART_WriteByte(uart->uart_base, c);
while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
return (1);
}
static int uart_getc(struct rt_serial_device *serial)
{
int ch;
struct fsl_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct fsl_uart *)serial->parent.user_data;
ch = -1;
if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
ch = LPUART_ReadByte(uart->uart_base);
return ch;
}
static rt_size_t uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
return (0);
}
/* UART ISR */
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct fsl_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct fsl_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
/* UART in mode Receiver */
if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/* If RX overrun. */
if (LPUART_STAT_OR_MASK & uart->uart_base->STAT)
{
/* Clear overrun flag, otherwise the RX does not work. */
uart->uart_base->STAT = ((uart->uart_base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
}
}

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bsp/rv32m1_vega/ri5cy/driver/drv_uart.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
int rt_hw_uart_init(void);
#endif /* __DRV_UART_H__ */

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bsp/rv32m1_vega/ri5cy/link.lds Normal file
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/* Entry Point */
OUTPUT_ARCH( "riscv" )
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
/* Specify the memory areas */
MEMORY
{
m_vector (RX) : ORIGIN = 0x000FFF00, LENGTH = 0x00000100
m_text (RX) : ORIGIN = 0x00000000, LENGTH = 0x000FFF00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - 0x1800
}
/* Define output sections */
SECTIONS
{
.vectors : ALIGN(4)
{
__VECTOR_TABLE = .;
KEEP(*(.vectors))
} > m_vector
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
KEEP(*(.startup))
. = ALIGN(4);
__user_vector = .;
KEEP(*(user_vectors))
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.eh_frame)
*(.init)
*(.fini)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__global_pointer = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(.sdata .sdata.*)
*(.heapsram*) /* This is only for the pulpino official test code. */
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable)
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
_edata = .;
.stack :
{
. = ALIGN(8);
__StackLimit = .;
. += STACK_SIZE;
__StackTop = .;
} > m_data
/* Initializes stack on the end of block */
PROVIDE(__stack = __StackTop);
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(.sbss)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
/* End of uninitalized data segement */
_end = .;
PROVIDE(end = .);
}

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bsp/rv32m1_vega/ri5cy/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40000
#define ARCH_RISCV
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_PIN
#define RT_USING_RTC
/* Using WiFi */
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_POSIX
/* Network */
/* Socket abstraction layer */
/* light weight TCP/IP stack */
/* Modbus master and slave stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
#define RT_USING_ULOG
#define ULOG_OUTPUT_LVL_D
#define ULOG_OUTPUT_LVL 7
#define ULOG_USING_ISR_LOG
#define ULOG_ASSERT_ENABLE
#define ULOG_LINE_BUF_SIZE 128
/* log format */
#define ULOG_USING_COLOR
#define ULOG_OUTPUT_TIME
#define ULOG_OUTPUT_LEVEL
#define ULOG_OUTPUT_TAG
#define ULOG_BACKEND_USING_CONSOLE
#define ULOG_SW_VERSION_NUM 0x00101
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
#define PKG_USING_MICROPYTHON
/* Hardware Module */
#define MICROPYTHON_USING_MACHINE_UART
/* System Module */
#define MICROPYTHON_USING_UOS
#define MICROPYTHON_USING_THREAD
/* Tools Module */
#define MICROPYTHON_USING_UJSON
/* Network Module */
#define PKG_MICROPYTHON_HEAP_SIZE 8192
#define PKG_USING_MICROPYTHON_LATEST_VERSION
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
/* Privated Packages of RealThread */
/* Network Utilities */
#define SOC_VEGA_RI5CY
#define BOARD_X_FRDM_VEGA
#define BSP_USING_UART0
#endif

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bsp/rv32m1_vega/ri5cy/rtconfig.py Normal file
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import os
# toolchains options
ARCH ='risc-v'
CPU ='rv32m1'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/unknown-gcc/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'riscv-none-embed-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=rv32imc -mabi=ilp32'
CFLAGS = DEVICE + ' -fno-builtin -fno-exceptions -ffunction-sections'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2 -Os'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
# POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
POST_ACTION = SIZE + ' $TARGET \n'

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/01 Bernard The first version
*/
#include <rthw.h>
#include <board.h>
#include <RV32M1_ri5cy.h>
typedef void (*irq_handler_t)(void);
extern const irq_handler_t isrTable[];
void SystemIrqHandler(uint32_t mcause)
{
uint32_t intNum;
if (mcause & 0x80000000) /* For external interrupt. */
{
intNum = mcause & 0x1FUL;
/* Clear pending flag in EVENT unit .*/
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
/* Now call the real irq handler for intNum */
isrTable[intNum]();
}
}

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
*/
#include "cpuport.h"
.section .text.entry
.align 2
.global IRQ_Handler
IRQ_Handler:
/* save all from thread context */
addi sp, sp, -32 * REGBYTES
STORE x1, 1 * REGBYTES(sp)
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x5, 5 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
move s0, sp
/* switch to interrupt stack */
la sp, __stack
/* interrupt handle */
call rt_interrupt_enter
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call SystemIrqHandler
call rt_interrupt_leave
/* switch to from thread stack */
move sp, s0
/* need to switch new thread */
la s0, rt_thread_switch_interrupt_flag
LOAD s2, 0(s0)
beqz s2, spurious_interrupt
/* clear switch interrupt flag */
STORE zero, 0(s0)
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
la s0, rt_interrupt_from_thread
LOAD s1, 0(s0)
STORE sp, 0(s1)
la s0, rt_interrupt_to_thread
LOAD s1, 0(s0)
LOAD sp, 0(s1)
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
spurious_interrupt:
LOAD x1, 1 * REGBYTES(sp)
/* Remain in M-mode after mret */
li t0, 0x00001800
csrs mstatus, t0
LOAD t0, 2 * REGBYTES(sp)
csrs mstatus, t0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
LOAD x6, 6 * REGBYTES(sp)
LOAD x7, 7 * REGBYTES(sp)
LOAD x8, 8 * REGBYTES(sp)
LOAD x9, 9 * REGBYTES(sp)
LOAD x10, 10 * REGBYTES(sp)
LOAD x11, 11 * REGBYTES(sp)
LOAD x12, 12 * REGBYTES(sp)
LOAD x13, 13 * REGBYTES(sp)
LOAD x14, 14 * REGBYTES(sp)
LOAD x15, 15 * REGBYTES(sp)
LOAD x16, 16 * REGBYTES(sp)
LOAD x17, 17 * REGBYTES(sp)
LOAD x18, 18 * REGBYTES(sp)
LOAD x19, 19 * REGBYTES(sp)
LOAD x20, 20 * REGBYTES(sp)
LOAD x21, 21 * REGBYTES(sp)
LOAD x22, 22 * REGBYTES(sp)
LOAD x23, 23 * REGBYTES(sp)
LOAD x24, 24 * REGBYTES(sp)
LOAD x25, 25 * REGBYTES(sp)
LOAD x26, 26 * REGBYTES(sp)
LOAD x27, 27 * REGBYTES(sp)
LOAD x28, 28 * REGBYTES(sp)
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
mret