add display controller driver for LS1B demo board
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1672 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz
parent
2e6e01550e
commit
c834d7cdbd
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@ -5,6 +5,9 @@ src_bsp = ['application.c', 'startup.c', 'board.c']
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src_drv = ['uart.c']
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if GetDepend('RT_USING_RTGUI'):
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src_drv += ['display_controller.c']
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src = File(src_bsp + src_drv)
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CPPPATH = [GetCurrentDir()]
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group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
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@ -21,6 +21,9 @@ Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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if GetDepend('RT_USING_RTGUI'):
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objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
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# build program
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env.Program(TARGET, objs)
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@ -16,8 +16,33 @@
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#include <rtthread.h>
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#include <ls1b.h>
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#ifdef RT_USING_RTGUI
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#include <rtgui/rtgui.h>
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extern void rt_hw_dc_init(void);
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#endif
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void rt_init_thread_entry(void* parameter)
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{
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#ifdef RT_USING_RTGUI
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{
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rt_device_t dc;
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/* init Display Controller */
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rt_hw_dc_init();
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/* re-init device driver */
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rt_device_init_all();
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/* find Display Controller device */
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dc = rt_device_find("dc");
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/* set Display Controller device as rtgui graphic driver */
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rtgui_graphic_set_device(dc);
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/* startup rtgui */
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rtgui_startup();
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}
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#endif
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}
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int rt_application_init()
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@ -0,0 +1,234 @@
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/*
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* File : display_controller.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-09 lgnq first version for LS1B DC
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*/
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#include <rtthread.h>
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#include "display_controller.h"
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struct vga_struct vga_mode[] =
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{
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{/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
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{/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
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{/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
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{/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
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{/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
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{/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
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{/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
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{/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
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{/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
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{/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
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{/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
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{/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
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{/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
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{/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
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{/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
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{/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
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{/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
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{/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
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};
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ALIGN(16)
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volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
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static struct rt_device_graphic_info _dc_info;
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#define abs(x) ((x<0)?(-x):x)
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#define min(a,b) ((a<b)?a:b)
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int caclulate_freq(long long XIN, long long PCLK)
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{
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int i;
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long long clk, clk1;
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int start, end;
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int mi;
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int pll,ctrl,div,div1,frac;
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pll = PLL_FREQ;
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ctrl = PLL_DIV_PARAM;
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rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
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// rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
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start = -1;
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end = 1;
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for (i=start; i<=end; i++)
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{
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clk = (12+i+(pll&0x3f))*33333333/2;
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div = clk/(long)PCLK/1000;
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clk1 = (12+i+1+(pll&0x3f))*33333333/2;
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div1 = clk1/(long)PCLK/1000;
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if (div!=div1)
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break;
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}
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if (div!=div1)
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{
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frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
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pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
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ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
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}
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else
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{
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clk = (12+start+(pll&0x3f))*33333333/2;
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clk1 = (12+end+(pll&0x3f))*33333333/2;
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if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
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{
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pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
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ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
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}
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else
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{
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pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
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ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
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}
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}
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rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
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ctrl |= 0x2a00;
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PLL_DIV_PARAM = ctrl;
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PLL_FREQ = pll;
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rt_thread_delay(10);
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// initserial(0);
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// _probe_frequencies();
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// rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
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return 0;
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}
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static rt_err_t rt_dc_init(rt_device_t dev)
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{
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int i, out, mode=-1;
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int val;
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for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
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{
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if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
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{
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mode=i;
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#ifdef LS1FSOC
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// out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
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// rt_kprintf("out=%x\n",out);
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/*inner gpu dc logic fifo pll ctrl,must large then outclk*/
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// *(volatile int *)0xbfd00414 = out+1;
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/*output pix1 clock pll ctrl*/
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// *(volatile int *)0xbfd00410 = out;
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/*output pix2 clock pll ctrl */
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// *(volatile int *)0xbfd00424 = out;
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#else
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caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
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#endif
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break;
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}
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}
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if (mode<0)
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{
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rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
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return;
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}
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DC_FB_CONFIG = 0x0;
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DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
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DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
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DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
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DC_DITHER_CONFIG = 0x0;
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DC_DITHER_TABLE_LOW = 0x0;
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DC_DITHER_TABLE_HIGH = 0x0;
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DC_PANEL_CONFIG = 0x80001311;
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DC_PANEL_TIMING = 0x0;
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DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
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DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
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DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
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DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
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#if defined(CONFIG_VIDEO_32BPP)
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DC_FB_CONFIG = 0x00100104;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
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#elif defined(CONFIG_VIDEO_16BPP)
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DC_FB_CONFIG = 0x00100103;
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DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
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#elif defined(CONFIG_VIDEO_15BPP)
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DC_FB_CONFIG = 0x00100102;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
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#elif defined(CONFIG_VIDEO_12BPP)
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DC_FB_CONFIG = 0x00100101;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
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#else //640x480-32Bits
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DC_FB_CONFIG = 0x00100104;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
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#endif //32Bits
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#ifdef LS1GSOC
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/*fix ls1g dc
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*first switch to tile mode
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*change origin register to 0
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*goback nomal mode
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*/
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{
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val = DC_FB_CONFIG;
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DC_FB_CONFIG = val | 0x10;
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DC_FB_BUFFER_ORIGIN = 0;
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DC_FB_BUFFER_ORIGIN;
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rt_thread_delay(10);
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DC_FB_CONFIG;
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DC_FB_CONFIG = val;
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}
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#endif
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return RT_EOK;
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}
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static rt_err_t rt_dc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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switch (cmd)
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{
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case RTGRAPHIC_CTRL_RECT_UPDATE:
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break;
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case RTGRAPHIC_CTRL_POWERON:
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break;
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case RTGRAPHIC_CTRL_POWEROFF:
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break;
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case RTGRAPHIC_CTRL_GET_INFO:
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rt_memcpy(args, &_dc_info, sizeof(_dc_info));
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break;
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case RTGRAPHIC_CTRL_SET_MODE:
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break;
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}
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return RT_EOK;
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}
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void rt_hw_dc_init(void)
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{
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rt_device_t dc = rt_malloc(sizeof(struct rt_device));
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if (dc == RT_NULL)
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{
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rt_kprintf("dc == RT_NULL\n");
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return; /* no memory yet */
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}
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_dc_info.bits_per_pixel = 16;
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_dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
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_dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
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_dc_info.width = FB_XSIZE;
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_dc_info.height = FB_YSIZE;
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/* init device structure */
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dc->type = RT_Device_Class_Graphic;
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dc->init = rt_dc_init;
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dc->open = RT_NULL;
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dc->close = RT_NULL;
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dc->control = rt_dc_control;
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dc->user_data = (void*)&_dc_info;
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/* register Display Controller device to RT-Thread */
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rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
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}
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@ -0,0 +1,58 @@
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/*
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* File : display_controller.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-08 lgnq first version for LS1B
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*/
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#ifndef __DISPLAY_CONTROLLER_H__
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#define __DISPLAY_CONTROLLER_H__
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#include <rtthread.h>
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#include "ls1b.h"
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#define DC_BASE 0xBC301240 //Display Controller
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/* Frame Buffer registers */
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#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
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#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
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#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
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#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
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#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
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#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
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#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
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#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
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#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
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#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
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#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
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#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
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#define DC_VSYNC __REG32(DC_BASE + 0x260)
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#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
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/* Display Controller driver for 1024x768 16bit */
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#define FB_XSIZE 1024
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#define FB_YSIZE 768
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#define CONFIG_VIDEO_16BPP
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#define APB_CLK 33333333
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#define K1BASE 0xA0000000
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#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
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#define HW_FB_ADDR KSEG1(_rt_framebuffer)
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#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
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struct vga_struct
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{
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long pclk;
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int hr,hss,hse,hfl;
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int vr,vss,vse,vfl;
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};
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#endif
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@ -140,7 +140,7 @@
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#define RT_LWIP_ETHTHREAD_STACKSIZE 512
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/* SECTION: RT-Thread/GUI */
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/* #define RT_USING_RTGUI */
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#define RT_USING_RTGUI
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/* name length of RTGUI object */
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#define RTGUI_NAME_MAX 12
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#include <rthw.h>
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#include <rtthread.h>
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#include "ls1b.h"
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#include "uart.h"
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/**
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* @addtogroup Loongson LS1B
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@ -24,30 +24,6 @@
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/*@{*/
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#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
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/* UART interrupt enable register value */
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#define UARTIER_IME (1 << 3)
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#define UARTIER_ILE (1 << 2)
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#define UARTIER_ITXE (1 << 1)
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#define UARTIER_IRXE (1 << 0)
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/* UART line control register value */
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#define UARTLCR_DLAB (1 << 7)
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#define UARTLCR_BCB (1 << 6)
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#define UARTLCR_SPB (1 << 5)
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#define UARTLCR_EPS (1 << 4)
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#define UARTLCR_PE (1 << 3)
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#define UARTLCR_SB (1 << 2)
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/* UART line status register value */
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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struct rt_uart_ls1b
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{
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struct rt_device parent;
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@ -1,5 +1,5 @@
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/*
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* File : board.c
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* File : uart.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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@ -9,12 +9,89 @@
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-08 lgnq first version
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* 2011-08-08 lgnq first version for LS1B
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*/
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#ifndef __UART_H__
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#define __UART_H__
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#include "ls1b.h"
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#define UART0_BASE 0xBFE40000
|
||||
#define UART0_1_BASE 0xBFE41000
|
||||
#define UART0_2_BASE 0xBFE42000
|
||||
#define UART0_3_BASE 0xBFE43000
|
||||
#define UART1_BASE 0xBFE44000
|
||||
#define UART1_1_BASE 0xBFE45000
|
||||
#define UART1_2_BASE 0xBFE46000
|
||||
#define UART1_3_BASE 0xBFE47000
|
||||
#define UART2_BASE 0xBFE48000
|
||||
#define UART3_BASE 0xBFE4C000
|
||||
#define UART4_BASE 0xBFE6C000
|
||||
#define UART5_BASE 0xBFE7C000
|
||||
|
||||
/* UART registers */
|
||||
#define UART_DAT(base) __REG8(base + 0x00)
|
||||
#define UART_IER(base) __REG8(base + 0x01)
|
||||
#define UART_IIR(base) __REG8(base + 0x02)
|
||||
#define UART_FCR(base) __REG8(base + 0x02)
|
||||
#define UART_LCR(base) __REG8(base + 0x03)
|
||||
#define UART_MCR(base) __REG8(base + 0x04)
|
||||
#define UART_LSR(base) __REG8(base + 0x05)
|
||||
#define UART_MSR(base) __REG8(base + 0x06)
|
||||
|
||||
#define UART_LSB(base) __REG8(base + 0x00)
|
||||
#define UART_MSB(base) __REG8(base + 0x01)
|
||||
|
||||
/* UART0 registers */
|
||||
#define UART0_DAT __REG8(UART0_BASE + 0x00)
|
||||
#define UART0_IER __REG8(UART0_BASE + 0x01)
|
||||
#define UART0_IIR __REG8(UART0_BASE + 0x02)
|
||||
#define UART0_FCR __REG8(UART0_BASE + 0x02)
|
||||
#define UART0_LCR __REG8(UART0_BASE + 0x03)
|
||||
#define UART0_MCR __REG8(UART0_BASE + 0x04)
|
||||
#define UART0_LSR __REG8(UART0_BASE + 0x05)
|
||||
#define UART0_MSR __REG8(UART0_BASE + 0x06)
|
||||
|
||||
#define UART0_LSB __REG8(UART0_BASE + 0x00)
|
||||
#define UART0_MSB __REG8(UART0_BASE + 0x01)
|
||||
|
||||
/* UART1 registers */
|
||||
#define UART1_DAT __REG8(UART1_BASE + 0x00)
|
||||
#define UART1_IER __REG8(UART1_BASE + 0x01)
|
||||
#define UART1_IIR __REG8(UART1_BASE + 0x02)
|
||||
#define UART1_FCR __REG8(UART1_BASE + 0x02)
|
||||
#define UART1_LCR __REG8(UART1_BASE + 0x03)
|
||||
#define UART1_MCR __REG8(UART1_BASE + 0x04)
|
||||
#define UART1_LSR __REG8(UART1_BASE + 0x05)
|
||||
#define UART1_MSR __REG8(UART1_BASE + 0x06)
|
||||
|
||||
#define UART1_LSB __REG8(UART1_BASE + 0x00)
|
||||
#define UART1_MSB __REG8(UART1_BASE + 0x01)
|
||||
|
||||
/* UART interrupt enable register value */
|
||||
#define UARTIER_IME (1 << 3)
|
||||
#define UARTIER_ILE (1 << 2)
|
||||
#define UARTIER_ITXE (1 << 1)
|
||||
#define UARTIER_IRXE (1 << 0)
|
||||
|
||||
/* UART line control register value */
|
||||
#define UARTLCR_DLAB (1 << 7)
|
||||
#define UARTLCR_BCB (1 << 6)
|
||||
#define UARTLCR_SPB (1 << 5)
|
||||
#define UARTLCR_EPS (1 << 4)
|
||||
#define UARTLCR_PE (1 << 3)
|
||||
#define UARTLCR_SB (1 << 2)
|
||||
|
||||
/* UART line status register value */
|
||||
#define UARTLSR_ERROR (1 << 7)
|
||||
#define UARTLSR_TE (1 << 6)
|
||||
#define UARTLSR_TFE (1 << 5)
|
||||
#define UARTLSR_BI (1 << 4)
|
||||
#define UARTLSR_FE (1 << 3)
|
||||
#define UARTLSR_PE (1 << 2)
|
||||
#define UARTLSR_OE (1 << 1)
|
||||
#define UARTLSR_DR (1 << 0)
|
||||
|
||||
void rt_hw_uart_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
* Date Author Notes
|
||||
* 2011-08-08 lgnq first version
|
||||
*/
|
||||
|
||||
#ifndef __LS1B_H__
|
||||
#define __LS1B_H__
|
||||
|
||||
|
|
@ -113,16 +114,6 @@ struct ls1b_cop_regs
|
|||
#define GMAC0_DMA_BASE 0xBFE11000
|
||||
#define GMAC1_BASE 0xBFE20000
|
||||
#define GMAC1_DMA_BASE 0xBFE21000
|
||||
#define UART0_BASE 0xBFE40000
|
||||
#define UART0_1_BASE 0xBFE41000
|
||||
#define UART0_2_BASE 0xBFE42000
|
||||
#define UART0_3_BASE 0xBFE43000
|
||||
#define UART1_BASE 0xBFE44000
|
||||
#define UART1_1_BASE 0xBFE45000
|
||||
#define UART1_2_BASE 0xBFE46000
|
||||
#define UART1_3_BASE 0xBFE47000
|
||||
#define UART2_BASE 0xBFE48000
|
||||
#define UART3_BASE 0xBFE4C000
|
||||
#define I2C0_BASE 0xBFE58000
|
||||
#define PWM0_BASE 0xBFE5C000
|
||||
#define PWM1_BASE 0xBFE5C010
|
||||
|
|
@ -131,77 +122,18 @@ struct ls1b_cop_regs
|
|||
#define WDT_BASE 0xBFE5C060
|
||||
#define RTC_BASE 0xBFE64000
|
||||
#define I2C1_BASE 0xBFE68000
|
||||
#define UART4_BASE 0xBFE6C000
|
||||
#define I2C2_BASE 0xBFE70000
|
||||
#define AC97_BASE 0xBFE74000
|
||||
#define NAND_BASE 0xBFE78000
|
||||
#define UART5_BASE 0xBFE7C000
|
||||
#define SPI_BASE 0xBFE80000
|
||||
#define CAN1_BASE 0xBF004300
|
||||
#define CAN0_BASE 0xBF004400
|
||||
|
||||
#define DC_BASE 0xBC301240 //Display Control
|
||||
|
||||
/* UART registers */
|
||||
#define UART_DAT(base) __REG8(base + 0x00)
|
||||
#define UART_IER(base) __REG8(base + 0x01)
|
||||
#define UART_IIR(base) __REG8(base + 0x02)
|
||||
#define UART_FCR(base) __REG8(base + 0x02)
|
||||
#define UART_LCR(base) __REG8(base + 0x03)
|
||||
#define UART_MCR(base) __REG8(base + 0x04)
|
||||
#define UART_LSR(base) __REG8(base + 0x05)
|
||||
#define UART_MSR(base) __REG8(base + 0x06)
|
||||
|
||||
#define UART_LSB(base) __REG8(base + 0x00)
|
||||
#define UART_MSB(base) __REG8(base + 0x01)
|
||||
|
||||
/* UART0 registers */
|
||||
#define UART0_DAT __REG8(UART0_BASE + 0x00)
|
||||
#define UART0_IER __REG8(UART0_BASE + 0x01)
|
||||
#define UART0_IIR __REG8(UART0_BASE + 0x02)
|
||||
#define UART0_FCR __REG8(UART0_BASE + 0x02)
|
||||
#define UART0_LCR __REG8(UART0_BASE + 0x03)
|
||||
#define UART0_MCR __REG8(UART0_BASE + 0x04)
|
||||
#define UART0_LSR __REG8(UART0_BASE + 0x05)
|
||||
#define UART0_MSR __REG8(UART0_BASE + 0x06)
|
||||
|
||||
#define UART0_LSB __REG8(UART0_BASE + 0x00)
|
||||
#define UART0_MSB __REG8(UART0_BASE + 0x01)
|
||||
|
||||
/* UART1 registers */
|
||||
#define UART1_DAT __REG8(UART1_BASE + 0x00)
|
||||
#define UART1_IER __REG8(UART1_BASE + 0x01)
|
||||
#define UART1_IIR __REG8(UART1_BASE + 0x02)
|
||||
#define UART1_FCR __REG8(UART1_BASE + 0x02)
|
||||
#define UART1_LCR __REG8(UART1_BASE + 0x03)
|
||||
#define UART1_MCR __REG8(UART1_BASE + 0x04)
|
||||
#define UART1_LSR __REG8(UART1_BASE + 0x05)
|
||||
#define UART1_MSR __REG8(UART1_BASE + 0x06)
|
||||
|
||||
#define UART1_LSB __REG8(UART1_BASE + 0x00)
|
||||
#define UART1_MSB __REG8(UART1_BASE + 0x01)
|
||||
|
||||
/* Watch Dog registers */
|
||||
#define WDT_EN __REG32(WDT_BASE + 0x00)
|
||||
#define WDT_SET __REG32(WDT_BASE + 0x04)
|
||||
#define WDT_TIMER __REG32(WDT_BASE + 0x08)
|
||||
|
||||
/* Frame Buffer registers */
|
||||
#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
|
||||
#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
|
||||
#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
|
||||
#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
|
||||
#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
|
||||
#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
|
||||
#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
|
||||
#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
|
||||
#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
|
||||
#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
|
||||
#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
|
||||
#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
|
||||
#define DC_VSYNC __REG32(DC_BASE + 0x260)
|
||||
#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
|
||||
|
||||
#define PLL_FREQ __REG32(0xbfe78030)
|
||||
#define PLL_DIV_PARAM __REG32(0xbfe78034)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue