diff --git a/bsp/wch/risc-v/Libraries/Kconfig b/bsp/wch/risc-v/Libraries/Kconfig index a3b0a5e995..70931c692b 100644 --- a/bsp/wch/risc-v/Libraries/Kconfig +++ b/bsp/wch/risc-v/Libraries/Kconfig @@ -1,12 +1,12 @@ config SOC_RISCV_FAMILY_CH32 bool -config SOC_RISCV_SERIES_CH32V103 +config SOC_RISCV_SERIES_CH32V1 bool select ARCH_RISCV select SOC_RISCV_FAMILY_CH32 -config SOC_RISCV_SERIES_CH32V307 +config SOC_RISCV_SERIES_CH32V3 bool select ARCH_RISCV select SOC_RISCV_FAMILY_CH32 diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c index 1d27521f74..1203303bde 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c @@ -4,340 +4,52 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2017-10-20 ZYH the first version - * 2017-11-15 ZYH update to 3.0.0 + * Date Author Notes + * 2022-08-25 liYony first version */ -#include -#include #include -#include -#include "drivers/pin.h" - +#include "drv_gpio.h" #ifdef RT_USING_PIN -#define __CH32_PIN(index, gpio, gpio_index) {index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_Pin_##gpio_index} -#define __CH32_PIN_DEFAULT {-1, 0, 0, 0} +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) -#define PIN_MODE_INPUT_AIN 0x05 -#define PIN_MODE_OUTPUT_AF_OD 0x06 -#define PIN_MODE_OUTPUT_AF_PP 0x07 +#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) +#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) -static void GPIOA_CLK_ENABLE(void) -{ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); -} - -static void GPIOB_CLK_ENABLE(void) -{ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); -} - -#if (CH32V10X_PIN_NUMBERS >36) -static void GPIOC_CLK_ENABLE(void) -{ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); -} +#if defined(GPIOZ) +#define __CH32_PORT_MAX 12u +#elif defined(GPIOK) +#define __CH32_PORT_MAX 11u +#elif defined(GPIOJ) +#define __CH32_PORT_MAX 10u +#elif defined(GPIOI) +#define __CH32_PORT_MAX 9u +#elif defined(GPIOH) +#define __CH32_PORT_MAX 8u +#elif defined(GPIOG) +#define __CH32_PORT_MAX 7u +#elif defined(GPIOF) +#define __CH32_PORT_MAX 6u +#elif defined(GPIOE) +#define __CH32_PORT_MAX 5u +#elif defined(GPIOD) +#define __CH32_PORT_MAX 4u +#elif defined(GPIOC) +#define __CH32_PORT_MAX 3u +#elif defined(GPIOB) +#define __CH32_PORT_MAX 2u +#elif defined(GPIOA) +#define __CH32_PORT_MAX 1u +#else +#define __CH32_PORT_MAX 0u +#error Unsupported CH32 GPIO peripheral. #endif -#if (CH32V10X_PIN_NUMBERS >48) -static void GPIOD_CLK_ENABLE(void) -{ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); -} -#endif +#define PIN_STPORT_MAX __CH32_PORT_MAX -#if (CH32V10X_PIN_NUMBERS >64) -static void GPIOE_CLK_ENABLE(void) -{ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); -} -#endif - - - - - -/* STM32 GPIO driver */ -struct pin_index -{ - int index; - void (*rcc)(void); - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ -#if (CH32V10X_PIN_NUMBERS == 36) - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(7, A, 0), - __CH32_PIN(8, A, 1), - __CH32_PIN(9, A, 2), - __CH32_PIN(10, A, 3), - __CH32_PIN(11, A, 4), - __CH32_PIN(12, A, 5), - __CH32_PIN(13, A, 6), - __CH32_PIN(14, A, 7), - __CH32_PIN(15, B, 0), - __CH32_PIN(16, B, 1), - __CH32_PIN(17, B, 2), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(20, A, 8), - __CH32_PIN(21, A, 9), - __CH32_PIN(22, A, 10), - __CH32_PIN(23, A, 11), - __CH32_PIN(24, A, 12), - __CH32_PIN(25, A, 13), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(28, A, 14), - __CH32_PIN(29, A, 15), - __CH32_PIN(30, B, 3), - __CH32_PIN(31, B, 4), - __CH32_PIN(32, B, 5), - __CH32_PIN(33, B, 6), - __CH32_PIN(34, B, 7), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, -#endif -#if (CH32V10X_PIN_NUMBERS == 48) - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(2, C, 13), - __CH32_PIN(3, C, 14), - __CH32_PIN(4, C, 15), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(10, A, 0), - __CH32_PIN(11, A, 1), - __CH32_PIN(12, A, 2), - __CH32_PIN(13, A, 3), - __CH32_PIN(14, A, 4), - __CH32_PIN(15, A, 5), - __CH32_PIN(16, A, 6), - __CH32_PIN(17, A, 7), - __CH32_PIN(18, B, 0), - __CH32_PIN(19, B, 1), - __CH32_PIN(20, B, 2), - __CH32_PIN(21, B, 10), - __CH32_PIN(22, B, 11), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(25, B, 12), - __CH32_PIN(26, B, 13), - __CH32_PIN(27, B, 14), - __CH32_PIN(28, B, 15), - __CH32_PIN(29, A, 8), - __CH32_PIN(30, A, 9), - __CH32_PIN(31, A, 10), - __CH32_PIN(32, A, 11), - __CH32_PIN(33, A, 12), - __CH32_PIN(34, A, 13), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(37, A, 14), - __CH32_PIN(38, A, 15), - __CH32_PIN(39, B, 3), - __CH32_PIN(40, B, 4), - __CH32_PIN(41, B, 5), - __CH32_PIN(42, B, 6), - __CH32_PIN(43, B, 7), - __CH32_PIN_DEFAULT, - __CH32_PIN(45, B, 8), - __CH32_PIN(46, B, 9), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, -#endif - -#if (CH32V10X_PIN_NUMBERS == 64) - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(2, C, 13), - __CH32_PIN(3, C, 14), - __CH32_PIN(4, C, 15), - __CH32_PIN(5, D, 0), - __CH32_PIN(6, D, 1), - __CH32_PIN_DEFAULT, - __CH32_PIN(8, C, 0), - __CH32_PIN(9, C, 1), - __CH32_PIN(10, C, 2), - __CH32_PIN(11, C, 3), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(14, A, 0), - __CH32_PIN(15, A, 1), - __CH32_PIN(16, A, 2), - __CH32_PIN(17, A, 3), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(20, A, 4), - __CH32_PIN(21, A, 5), - __CH32_PIN(22, A, 6), - __CH32_PIN(23, A, 7), - __CH32_PIN(24, C, 4), - __CH32_PIN(25, C, 5), - __CH32_PIN(26, B, 0), - __CH32_PIN(27, B, 1), - __CH32_PIN(28, B, 2), - __CH32_PIN(29, B, 10), - __CH32_PIN(30, B, 11), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(33, B, 12), - __CH32_PIN(34, B, 13), - __CH32_PIN(35, B, 14), - __CH32_PIN(36, B, 15), - __CH32_PIN(37, C, 6), - __CH32_PIN(38, C, 7), - __CH32_PIN(39, C, 8), - __CH32_PIN(40, C, 9), - __CH32_PIN(41, A, 8), - __CH32_PIN(42, A, 9), - __CH32_PIN(43, A, 10), - __CH32_PIN(44, A, 11), - __CH32_PIN(45, A, 12), - __CH32_PIN(46, A, 13), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(49, A, 14), - __CH32_PIN(50, A, 15), - __CH32_PIN(51, C, 10), - __CH32_PIN(52, C, 11), - __CH32_PIN(53, C, 12), - __CH32_PIN(54, D, 2), - __CH32_PIN(55, B, 3), - __CH32_PIN(56, B, 4), - __CH32_PIN(57, B, 5), - __CH32_PIN(58, B, 6), - __CH32_PIN(59, B, 7), - __CH32_PIN_DEFAULT, - __CH32_PIN(61, B, 8), - __CH32_PIN(62, B, 9), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, -#endif -#if (CH32V10X_PIN_NUMBERS == 100) - __CH32_PIN_DEFAULT, - __CH32_PIN(1, E, 2), - __CH32_PIN(2, E, 3), - __CH32_PIN(3, E, 4), - __CH32_PIN(4, E, 5), - __CH32_PIN(5, E, 6), - __CH32_PIN_DEFAULT, - __CH32_PIN(7, C, 13), - __CH32_PIN(8, C, 14), - __CH32_PIN(9, C, 15), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(15, C, 0), - __CH32_PIN(16, C, 1), - __CH32_PIN(17, C, 2), - __CH32_PIN(18, C, 3), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(23, A, 0), - __CH32_PIN(24, A, 1), - __CH32_PIN(25, A, 2), - __CH32_PIN(26, A, 3), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(29, A, 4), - __CH32_PIN(30, A, 5), - __CH32_PIN(31, A, 6), - __CH32_PIN(32, A, 7), - __CH32_PIN(33, C, 4), - __CH32_PIN(34, C, 5), - __CH32_PIN(35, B, 0), - __CH32_PIN(36, B, 1), - __CH32_PIN(37, B, 2), - __CH32_PIN(38, E, 7), - __CH32_PIN(39, E, 8), - __CH32_PIN(40, E, 9), - __CH32_PIN(41, E, 10), - __CH32_PIN(42, E, 11), - __CH32_PIN(43, E, 12), - __CH32_PIN(44, E, 13), - __CH32_PIN(45, E, 14), - __CH32_PIN(46, E, 15), - __CH32_PIN(47, B, 10), - __CH32_PIN(48, B, 11), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(51, B, 12), - __CH32_PIN(52, B, 13), - __CH32_PIN(53, B, 14), - __CH32_PIN(54, B, 15), - __CH32_PIN(55, D, 8), - __CH32_PIN(56, D, 9), - __CH32_PIN(57, D, 10), - __CH32_PIN(58, D, 11), - __CH32_PIN(59, D, 12), - __CH32_PIN(60, D, 13), - __CH32_PIN(61, D, 14), - __CH32_PIN(62, D, 15), - __CH32_PIN(63, C, 6), - __CH32_PIN(64, C, 7), - __CH32_PIN(65, C, 8), - __CH32_PIN(66, C, 9), - __CH32_PIN(67, A, 8), - __CH32_PIN(68, A, 9), - __CH32_PIN(69, A, 10), - __CH32_PIN(70, A, 11), - __CH32_PIN(71, A, 12), - __CH32_PIN(72, A, 13), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, - __CH32_PIN(76, A, 14), - __CH32_PIN(77, A, 15), - __CH32_PIN(78, C, 10), - __CH32_PIN(79, C, 11), - __CH32_PIN(80, C, 12), - __CH32_PIN(81, D, 0), - __CH32_PIN(82, D, 1), - __CH32_PIN(83, D, 2), - __CH32_PIN(84, D, 3), - __CH32_PIN(85, D, 4), - __CH32_PIN(86, D, 5), - __CH32_PIN(87, D, 6), - __CH32_PIN(88, D, 7), - __CH32_PIN(89, B, 3), - __CH32_PIN(90, B, 4), - __CH32_PIN(91, B, 5), - __CH32_PIN(92, B, 6), - __CH32_PIN(93, B, 7), - __CH32_PIN_DEFAULT, - __CH32_PIN(95, B, 8), - __CH32_PIN(96, B, 9), - __CH32_PIN(97, E, 0), - __CH32_PIN(98, E, 1), - __CH32_PIN_DEFAULT, - __CH32_PIN_DEFAULT, -#endif -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; static const struct pin_irq_map pin_irq_map[] = { {GPIO_Pin_0, EXTI0_IRQn}, @@ -357,94 +69,115 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_Pin_14, EXTI15_10_IRQn}, {GPIO_Pin_15, EXTI15_10_IRQn}, }; -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, -}; -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(uint8_t pin) +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { - const struct pin_index *index; - if (pin < ITEM_NUM(pins)) + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) + +static rt_base_t ch32_pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; + return -RT_EINVAL; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); } else { - index = RT_NULL; + return -RT_EINVAL; } - return index; -}; -void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - const struct pin_index *index; - index = get_pin(pin); - if (index == RT_NULL) + for (i = 3; i < name_len; i++) { - return; + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; } - GPIO_WriteBit(index->gpio, index->pin, (BitAction)value); + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; } -int ch32_pin_read(rt_device_t dev, rt_base_t pin) +static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { - int value; - const struct pin_index *index; - value = PIN_LOW; - index = get_pin(pin); - if (index == RT_NULL) + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) < PIN_STPORT_MAX) { - return value; + gpio_port = PIN_STPORT(pin); + gpio_pin = PIN_STPIN(pin); + GPIO_WriteBit(gpio_port, gpio_pin, (BitAction)value); } - value = GPIO_ReadInputDataBit(index->gpio, index->pin); +} + +static int ch32_pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (PIN_PORT(pin) < PIN_STPORT_MAX) + { + gpio_port = PIN_STPORT(pin); + gpio_pin = PIN_STPIN(pin); + value = GPIO_ReadInputDataBit(gpio_port, gpio_pin); + } + return value; } -void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +static void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { - const struct pin_index *index; GPIO_InitTypeDef GPIO_InitStruct; - index = get_pin(pin); - if (index == RT_NULL) + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) { return; } - rt_kprintf("get pin index\r\n"); - /* GPIO Periph clock enable */ - index->rcc(); + /* Configure GPIO_InitStructure */ - GPIO_InitStruct.GPIO_Pin = index->pin; + GPIO_InitStruct.GPIO_Pin = PIN_STPIN(pin); GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP; GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; + if (mode == PIN_MODE_OUTPUT) { /* output setting */ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP; } - else if (mode == PIN_MODE_INPUT_AIN) - { - /* input setting: not pull. */ - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AIN; - } else if (mode == PIN_MODE_INPUT) { /* input setting: pull up. */ @@ -454,37 +187,27 @@ void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { /* input setting: pull down. */ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD; -// GPIO_InitStruct.Pull = GPIO_PULLDOWN; } else if (mode == PIN_MODE_INPUT_PULLUP) { /* output setting: od. */ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU; -// GPIO_InitStruct.Pull = GPIO_NOPULL; } else if (mode == PIN_MODE_OUTPUT_OD) { + /* output setting: od. */ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_OD; } - else if (mode == PIN_MODE_OUTPUT_AF_OD) - { - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_OD; - } - else if (mode == PIN_MODE_OUTPUT_AF_PP) - { - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; - } - GPIO_Init(index->gpio, &GPIO_InitStruct); + GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct); } - rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) { - int i; + rt_int32_t i; for (i = 0; i < 32; i++) { - if ((0x01 << i) == bit) + if (((rt_uint32_t)0x01 << i) == bit) { return i; } @@ -495,33 +218,35 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) { rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) { return RT_NULL; } return &pin_irq_map[mapindex]; }; -rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) + +static rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) { - const struct pin_index *index; rt_base_t level; rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) { - return RT_ENOSYS; + return -RT_ENOSYS; } - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } + level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) { rt_hw_interrupt_enable(level); return RT_EOK; @@ -529,31 +254,33 @@ rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, if (pin_irq_hdr_tab[irqindex].pin != -1) { rt_hw_interrupt_enable(level); - return RT_EBUSY; + return -RT_EBUSY; } pin_irq_hdr_tab[irqindex].pin = pin; pin_irq_hdr_tab[irqindex].hdr = hdr; pin_irq_hdr_tab[irqindex].mode = mode; pin_irq_hdr_tab[irqindex].args = args; rt_hw_interrupt_enable(level); + return RT_EOK; } -rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +static rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) { - const struct pin_index *index; rt_base_t level; rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) { - return RT_ENOSYS; + return -RT_ENOSYS; } - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } + level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == -1) { @@ -565,49 +292,53 @@ rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) pin_irq_hdr_tab[irqindex].mode = 0; pin_irq_hdr_tab[irqindex].args = RT_NULL; rt_hw_interrupt_enable(level); + return RT_EOK; } -rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) +static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) { - const struct pin_index *index; const struct pin_irq_map *irqmap; rt_base_t level; rt_int32_t irqindex = -1; - GPIO_InitTypeDef GPIO_InitStruct; - EXTI_InitTypeDef EXTI_InitStructure; + rt_uint8_t gpio_port_souce=0; + GPIO_InitTypeDef GPIO_InitStruct={0}; + EXTI_InitTypeDef EXTI_InitStructure={0}; - index = get_pin(pin); - if (index == RT_NULL) + if (PIN_PORT(pin) >= PIN_STPORT_MAX) { - return RT_ENOSYS; + return -RT_ENOSYS; } + if (enabled == PIN_IRQ_ENABLE) { - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); - return RT_ENOSYS; + return -RT_ENOSYS; } + irqmap = &pin_irq_map[irqindex]; - /* GPIO Periph clock enable */ - index->rcc(); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,ENABLE); /* Configure GPIO_InitStructure */ - GPIO_InitStruct.GPIO_Pin = index->pin; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO , ENABLE); + + GPIO_InitStruct.GPIO_Pin = PIN_STPIN(pin); GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - EXTI_InitStructure.EXTI_Line=index->pin;/* �ⲿ�ж��ߺ����źŶ�Ӧ */ + EXTI_InitStructure.EXTI_Line=PIN_STPIN(pin); EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_LineCmd = ENABLE; + switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: @@ -623,31 +354,60 @@ rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin, EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; break; } + GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct); + + gpio_port_souce=PIN_PORT(pin); + + GPIO_EXTILineConfig(gpio_port_souce,(rt_uint8_t)irqindex); - GPIO_Init(index->gpio, &GPIO_InitStruct); EXTI_Init(&EXTI_InitStructure); NVIC_SetPriority(irqmap->irqno,5<<4); NVIC_EnableIRQ( irqmap->irqno ); + pin_irq_enable_mask |= irqmap->pinbit; rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) { - irqmap = get_pin_irq_map(index->pin); + irqmap = get_pin_irq_map(PIN_STPIN(pin)); if (irqmap == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } - NVIC_DisableIRQ(irqmap->irqno); + + level = rt_hw_interrupt_disable(); + + pin_irq_enable_mask &= ~irqmap->pinbit; + + if (( irqmap->pinbit>=GPIO_Pin_5 )&&( irqmap->pinbit<=GPIO_Pin_9 )) + { + if(!(pin_irq_enable_mask&(GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7|GPIO_Pin_8|GPIO_Pin_9))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if (( irqmap->pinbit>=GPIO_Pin_10 )&&( irqmap->pinbit<=GPIO_Pin_15 )) + { + if(!(pin_irq_enable_mask&(GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQ(irqmap->irqno); + } + + rt_hw_interrupt_enable(level); } else { - return RT_ENOSYS; + return -RT_ENOSYS; } + return RT_EOK; } - -const static struct rt_pin_ops _ch32_pin_ops = +static const struct rt_pin_ops _ch32_pin_ops = { ch32_pin_mode, ch32_pin_write, @@ -655,16 +415,9 @@ const static struct rt_pin_ops _ch32_pin_ops = ch32_pin_attach_irq, ch32_pin_dettach_irq, ch32_pin_irq_enable, + ch32_pin_get, }; -int rt_hw_pin_init(void) -{ - int result; - result = rt_device_pin_register("pin", &_ch32_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - rt_inline void pin_irq_hdr(int irqno) { if (pin_irq_hdr_tab[irqno].hdr) @@ -678,12 +431,12 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) pin_irq_hdr(bit2bitno(GPIO_Pin)); } - -void EXTI0_IRQHandler(void) __attribute__((interrupt())); -void EXTI1_IRQHandler(void) __attribute__((interrupt())); -void EXTI3_IRQHandler(void) __attribute__((interrupt())); -void EXTI4_IRQHandler(void) __attribute__((interrupt())); -void EXTI9_5_IRQHandler(void) __attribute__((interrupt())); +void EXTI0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void EXTI1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void EXTI2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void EXTI3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void EXTI4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void EXTI9_5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); void EXTI0_IRQHandler(void) { @@ -773,4 +526,47 @@ void EXTI9_5_IRQHandler(void) FREE_INT_SP(); } -#endif +int rt_hw_pin_init(void) +{ +#if defined(RCC_APB2Periph_GPIOA) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE); +#if defined(RCC_APB2Periph_GPIOB) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE); +#if defined(RCC_APB2Periph_GPIOC) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); +#if defined(RCC_APB2Periph_GPIOD) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD , ENABLE); +#if defined(RCC_APB2Periph_GPIOE) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE , ENABLE); +#if defined(RCC_APB2Periph_GPIOF) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF , ENABLE); +#if defined(RCC_APB2Periph_GPIOG) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG , ENABLE); +#if defined(RCC_APB2Periph_GPIOH) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOH , ENABLE); +#if defined(RCC_APB2Periph_GPIOI) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOI , ENABLE); +#if defined(RCC_APB2Periph_GPIOJ) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOJ , ENABLE); +#if defined(RCC_APB2Periph_GPIOK) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOK , ENABLE); +#if defined(RCC_APB2Periph_GPIOZ) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOZ , ENABLE); +#endif /* defined(RCC_APB2Periph_GPIOZ) */ +#endif /* defined(RCC_APB2Periph_GPIOK) */ +#endif /* defined(RCC_APB2Periph_GPIOJ) */ +#endif /* defined(RCC_APB2Periph_GPIOI) */ +#endif /* defined(RCC_APB2Periph_GPIOH) */ +#endif /* defined(RCC_APB2Periph_GPIOG) */ +#endif /* defined(RCC_APB2Periph_GPIOF) */ +#endif /* defined(RCC_APB2Periph_GPIOE) */ +#endif /* defined(RCC_APB2Periph_GPIOD) */ +#endif /* defined(RCC_APB2Periph_GPIOC) */ +#endif /* defined(RCC_APB2Periph_GPIOB) */ +#endif /* defined(RCC_APB2Periph_GPIOA) */ + + return rt_device_pin_register("pin", &_ch32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.h index f0e61e9dfc..2912d2dd13 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.h +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.h @@ -4,13 +4,35 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2021-08-10 charlown first version + * Date Author Notes + * 2022-08-25 liYony first version */ -#ifndef DRV_GPIO_H__ -#define DRV_GPIO_H__ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include "rtdevice.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __CH32_PORT(port) GPIO##port##_BASE +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__CH32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; int rt_hw_pin_init(void); +#ifdef __cplusplus +} #endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/wch/risc-v/ch32v103r-evt/.config b/bsp/wch/risc-v/ch32v103r-evt/.config index 8528eb1acd..36b7e29d46 100644 --- a/bsp/wch/risc-v/ch32v103r-evt/.config +++ b/bsp/wch/risc-v/ch32v103r-evt/.config @@ -491,7 +491,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_ADT74XX is not set # CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_RTT_ESP_IDF is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -505,7 +505,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_WM_LIBRARIES is not set # -# Kendryte SDK +# kendryte-sdk: Kendryte SDK # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set @@ -570,7 +570,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CW2015 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # # AI packages @@ -646,66 +645,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MFBD is not set # CONFIG_PKG_USING_SLCAN2RTT is not set # CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set - -# -# RT-Thread Smart -# -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set CONFIG_SOC_RISCV_FAMILY_CH32=y -CONFIG_SOC_RISCV_SERIES_CH32V103=y +CONFIG_SOC_RISCV_SERIES_CH32V1=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v103r-evt/board/Kconfig b/bsp/wch/risc-v/ch32v103r-evt/board/Kconfig index 3d8d6535ad..0641dc309d 100644 --- a/bsp/wch/risc-v/ch32v103r-evt/board/Kconfig +++ b/bsp/wch/risc-v/ch32v103r-evt/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_CH32V103R8 bool - select SOC_RISCV_SERIES_CH32V103 + select SOC_RISCV_SERIES_CH32V1 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h b/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h index 96a2dd412b..b819e796b6 100644 --- a/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h +++ b/bsp/wch/risc-v/ch32v103r-evt/rtconfig.h @@ -157,7 +157,7 @@ /* peripheral libraries and drivers */ -/* Kendryte SDK */ +/* kendryte-sdk: Kendryte SDK */ /* AI packages */ @@ -172,17 +172,8 @@ /* entertainment: terminal games and other interesting software packages */ - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - - -/* RT-Thread Smart */ - #define SOC_RISCV_FAMILY_CH32 -#define SOC_RISCV_SERIES_CH32V103 +#define SOC_RISCV_SERIES_CH32V1 /* Hardware Drivers Config */ diff --git a/bsp/wch/risc-v/ch32v307v-r1/.config b/bsp/wch/risc-v/ch32v307v-r1/.config index d419029e4b..388d5e0607 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/.config +++ b/bsp/wch/risc-v/ch32v307v-r1/.config @@ -646,7 +646,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SLCAN2RTT is not set # CONFIG_PKG_USING_SOEM is not set CONFIG_SOC_RISCV_FAMILY_CH32=y -CONFIG_SOC_RISCV_SERIES_CH32V307=y +CONFIG_SOC_RISCV_SERIES_CH32V3=y # # Hardware Drivers Config diff --git a/bsp/wch/risc-v/ch32v307v-r1/README.md b/bsp/wch/risc-v/ch32v307v-r1/README.md index 10ea06a853..d64ad38e05 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/README.md +++ b/bsp/wch/risc-v/ch32v307v-r1/README.md @@ -36,7 +36,7 @@ CH32V307V-R1 是 WCH 推出的一款基于 RISC-V 内核的开发板，最高主 #### 1、指定RISC-V GCC编译器 -推荐使用RT_Studio软件里面的编译器。 +推荐使用RT-Thread Studio软件里面的编译器。 ##### 方法一：直接指定编译器路径。 diff --git a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig index 3ec9672e64..a27f04d9fa 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig +++ b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_CH32V307VC bool - select SOC_RISCV_SERIES_CH32V307 + select SOC_RISCV_SERIES_CH32V3 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h index 0dc895a88d..3485999faa 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h +++ b/bsp/wch/risc-v/ch32v307v-r1/rtconfig.h @@ -173,7 +173,7 @@ /* entertainment: terminal games and other interesting software packages */ #define SOC_RISCV_FAMILY_CH32 -#define SOC_RISCV_SERIES_CH32V307 +#define SOC_RISCV_SERIES_CH32V3 /* Hardware Drivers Config */