Update cpuport.c
This commit is contained in:
Bernard Xiong
GitHub
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c2f028ed8d
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/*
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* File : cpuport.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first version
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* 2011-02-14 onelife Modify for EFM32
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* 2011-06-17 onelife Merge all of the C source code into cpuport.c
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* 2012-12-23 aozima stack addr align to 8byte.
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* 2012-12-29 Bernard Add exception hook.
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* 2013-07-09 aozima enhancement hard fault exception handler.
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* 2017-08-25 Archer first version
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*/
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#include <rtthread.h>
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@ -29,7 +31,7 @@
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*
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*
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* Stack Layout:
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* High |-----------------|
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* High |-----------------|
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* | $R5 |
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* |-----------------|
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* | . |
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@ -82,17 +84,17 @@ static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
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rt_base_t rt_hw_interrupt_disable(void)
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{
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rt_base_t level = __nds32__mfsr(NDS32_SR_PSW);
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rt_base_t level = __nds32__mfsr(NDS32_SR_PSW);
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GIE_DISABLE();
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GIE_DISABLE();
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return level;
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return level;
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}
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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if (level & PSW_mskGIE)
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GIE_ENABLE();
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if (level & PSW_mskGIE)
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GIE_ENABLE();
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}
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/* For relax support, must initial $gp at task init*/
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@ -113,60 +115,60 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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rt_int32_t i;
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rt_uint32_t *pxTopOfStack;
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rt_int32_t i;
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rt_uint32_t *pxTopOfStack;
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pxTopOfStack = (rt_uint32_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 4);
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pxTopOfStack = (rt_uint32_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 4);
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/* Simulate the stack frame as it would be created by a context switch */
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/* R0 ~ R5 registers */
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for (i = 5; i >= 1; i--) /* R5, R4, R3, R2 and R1. */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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*--pxTopOfStack = (rt_uint32_t)parameter; /* R0 : Argument */
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/* Simulate the stack frame as it would be created by a context switch */
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/* R0 ~ R5 registers */
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for (i = 5; i >= 1; i--) /* R5, R4, R3, R2 and R1. */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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*--pxTopOfStack = (rt_uint32_t)parameter; /* R0 : Argument */
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/* R6 ~ R30 registers */
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*--pxTopOfStack = (rt_uint32_t)texit; /* R30: $LP */
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*--pxTopOfStack = (rt_uint32_t)&_SDA_BASE_; /* R29: $GP */
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*--pxTopOfStack = (rt_uint32_t)0x2828282828; /* R28: $FP */
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/* R6 ~ R30 registers */
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*--pxTopOfStack = (rt_uint32_t)texit; /* R30: $LP */
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*--pxTopOfStack = (rt_uint32_t)&_SDA_BASE_; /* R29: $GP */
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*--pxTopOfStack = (rt_uint32_t)0x2828282828; /* R28: $FP */
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#ifdef __NDS32_REDUCE_REGS__
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*--pxTopOfStack = (rt_uint32_t)0x1515151515; /* R15 */
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for (i = 10; i >= 6; i--) /* R10 ~ R6 */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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*--pxTopOfStack = (rt_uint32_t)0x1515151515; /* R15 */
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for (i = 10; i >= 6; i--) /* R10 ~ R6 */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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#else
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for (i = 27; i >= 6; i--) /* R27 ~ R6 */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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for (i = 27; i >= 6; i--) /* R27 ~ R6 */
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*--pxTopOfStack = (rt_uint32_t)0x01010101UL * i;
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#endif
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/* IFC system register */
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/* IFC system register */
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#ifdef __TARGET_IFC_EXT
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $IFC_LP */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $IFC_LP */
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#endif
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/* ZOL system registers */
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/* ZOL system registers */
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#ifdef __TARGET_ZOL_EXT
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LC */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LE */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LB */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LC */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LE */
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*--pxTopOfStack = (rt_uint32_t)0x0; /* $LB */
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#endif
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/* IPSW and IPC system registers */
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/* Default IPSW: enable GIE, set CPL to 7, clear IFCON */
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i = (__nds32__mfsr(NDS32_SR_PSW) | PSW_mskGIE | PSW_mskCPL) & ~PSW_mskIFCON;
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*--pxTopOfStack = (rt_uint32_t)i; /* $IPSW */
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*--pxTopOfStack = (rt_uint32_t)tentry; /* $IPC */
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/* IPSW and IPC system registers */
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/* Default IPSW: enable GIE, set CPL to 7, clear IFCON */
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i = (__nds32__mfsr(NDS32_SR_PSW) | PSW_mskGIE | PSW_mskCPL) & ~PSW_mskIFCON;
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*--pxTopOfStack = (rt_uint32_t)i; /* $IPSW */
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*--pxTopOfStack = (rt_uint32_t)tentry; /* $IPC */
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/* Dummy word for 8-byte stack alignment */
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/* Dummy word for 8-byte stack alignment */
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#if defined(__TARGET_IFC_EXT) && defined(__TARGET_ZOL_EXT)
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*--pxTopOfStack = (rt_uint32_t)0xFFFFFFFF; /* Dummy */
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*--pxTopOfStack = (rt_uint32_t)0xFFFFFFFF; /* Dummy */
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#endif
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/* FPU registers */
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/* FPU registers */
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#ifdef __TARGET_FPU_EXT
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for (i = 0; i < FPU_REGS; i++)
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*--pxTopOfStack = (rt_uint32_t)0x0; /* FPU */
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for (i = 0; i < FPU_REGS; i++)
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*--pxTopOfStack = (rt_uint32_t)0x0; /* FPU */
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#endif
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return (rt_uint8_t *)pxTopOfStack;
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return (rt_uint8_t *)pxTopOfStack;
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}
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/**
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@ -190,28 +192,7 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context))
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* @return return the index of the first bit set. If value is 0, then this function
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* shall return 0.
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*/
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#if defined(__CC_ARM)
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__asm int __rt_ffs(int value)
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{
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CMP r0, #0x00
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BEQ exit
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RBIT r0, r0
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CLZ r0, r0
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ADDS r0, r0, #0x01
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exit
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BX lr
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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int __rt_ffs(int value)
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{
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if (value == 0) return value;
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__ASM("RBIT r0, r0");
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__ASM("CLZ r0, r0");
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__ASM("ADDS r0, r0, #0x01");
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}
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#elif defined(__GNUC__)
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#if defined(__GNUC__)
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int __rt_ffs(int value)
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{
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return __builtin_ffs(value);
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