libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

add Nuvoton Cortex-M0 porting. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@877 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong@gmail.com 2010-08-22 23:22:01 +00:00
parent 4eeae777dc
commit c2507af6bc
22 changed files with 8872 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2029
bsp/nuc140/CMSIS/CM0/NUC1xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

470
bsp/nuc140/CMSIS/CM0/core_cm0.c Normal file
View File

@ -0,0 +1,470 @@
/******************************************************************************
* @file: core_cm0.c
* @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Source File
* @version: V1.10
* @date: 24. Feb. 2009
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for armcc */
#define __INLINE __inline /*!< inline keyword for armcc */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for iarcc */
#define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
#define __nop __no_operation /*!< no operation intrinsic in iarcc */
#elif defined ( __GNUC__ )
#define __ASM asm /*!< asm keyword for gcc */
#define __INLINE inline /*!< inline keyword for gcc */
#endif
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Reverse byte order in integer value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int32_t value to reverse
* @return int32_t reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
#endif

801
bsp/nuc140/CMSIS/CM0/core_cm0.h Normal file
View File

@ -0,0 +1,801 @@
/******************************************************************************
* @file: core_cm0.h
* @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version: V1.10
* @date: 24. Feb. 2009
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CM0_CORE_H__
#define __CM0_CORE_H__
#define __CM0_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex core */
#include <stdint.h> /* Include standard types */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */
#endif
/**
* IO definitions
*
* define access restrictions to peripheral registers
*/
#define __I volatile const /*!< defines 'read only' permissions */
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/* System Reset */
#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
typedef struct
{
__IO uint32_t ISER[1]; /*!< Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Interrupt Priority Register */
} NVIC_Type;
/* memory mapping struct for System Control Block */
typedef struct
{
__I uint32_t CPUID; /*!< CPU ID Base Register */
__IO uint32_t ICSR; /*!< Interrupt Control State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*!< System Control Register */
__IO uint32_t CCR; /*!< Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< System Handler Control and State Register */
uint32_t RESERVED2[2];
__IO uint32_t DFSR; /*!< Debug Fault Status Register */
} SCB_Type;
/* memory mapping struct for SysTick */
typedef struct
{
__IO uint32_t CTRL; /*!< SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< SysTick Reload Value Register */
__IO uint32_t VAL; /*!< SysTick Current Value Register */
__I uint32_t CALIB; /*!< SysTick Calibration Register */
} SysTick_Type;
/* Core Debug Register */
typedef struct
{
__IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
__IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
#elif defined ( __GNUC__ )
#define __ASM asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#define __NOP __nop
#define __WFI __wfi
#define __WFE __wfe
#define __SEV __sev
#define __ISB() __isb(0)
#define __DSB() __dsb(0)
#define __DMB() __dmb(0)
#define __REV __rev
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/*
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
extern int32_t __REVSH(int16_t value);
#if (__ARMCC_VERSION < 400000)
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
static __INLINE void __WFI() { __ASM ("wfi"); }
static __INLINE void __WFE() { __ASM ("wfe"); }
static __INLINE void __SEV() { __ASM ("sev"); }
//static __INLINE void __ISB(arg) { __ASM ("isb"); }
//static __INLINE void __DSB(arg) { __ASM ("dsb"); }
//static __INLINE void __DMB(arg) { __ASM ("dmb"); }
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/* intrinsic void __set_PRIMASK(); */
/* intrinsic void __get_PRIMASK(); */
/* intrinsic uint32_t __REV(uint32_t value); */
/* intrinsic uint32_t __REVSH(uint32_t value); */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
static __INLINE void __NOP() { __ASM volatile ("nop"); }
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
static __INLINE void __WFI() { __ASM volatile ("wfi"); }
static __INLINE void __WFE() { __ASM volatile ("wfe"); }
static __INLINE void __SEV() { __ASM volatile ("sev"); }
static __INLINE void __ISB(arg) { __ASM volatile ("isb"); }
static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); }
static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); }
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
extern void __set_CONTROL(uint32_t control);
/**
* @brief Reverse byte order in integer value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in integer value
*/
extern uint32_t __REV(uint32_t value);
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/*
* Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
*
* @brief Reverse byte order in signed short value with sign extension to integer
*/
extern int32_t __REVSH(int16_t value);
#endif
/* ########################## NVIC functions #################################### */
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/**
* @brief Set the Priority Grouping in NVIC Interrupt Controller
*
* @param uint32_t priority_grouping is priority grouping field
* @return
*
* Set the priority grouping field using the required unlock sequence.
* The parameter priority_grouping is assigned to the field
* SCB->AIRCR [10:8] PRIGROUP field.
*/
static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
{
uint32_t reg_value=0;
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn_Type IRQn specifies the interrupt number
* @return none
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
/**
* @brief Disable the interrupt line for external interrupt specified
*
* @param IRQn_Type IRQn is the positive number of the external interrupt
* @return none
*
* Disable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
/**
* @brief Read the interrupt pending bit for a device specific interrupt source
*
* @param IRQn_Type IRQn is the number of the device specifc interrupt
* @return IRQn_Type Number of pending interrupt or zero
*
* Read the pending register in NVIC and return the number of the
* specified interrupt if its status is pending, otherwise it returns
* zero. The interrupt number cannot be a negative value.
*/
static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */
}
/**
* @brief Set the pending bit for an external interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return none
*
* Set the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
/**
* @brief Clear the pending bit for an external interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return none
*
* Clear the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/**
* @brief Set the priority for an interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @param priority is the priority for the interrupt
* @return none
*
* Set the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt. \n
*
* Note: The priority cannot be set for every core interrupt.
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/**
* @brief Read the priority for an interrupt
*
* @param IRQn_Type IRQn is the Number of the interrupt
* @return priority is the priority for the interrupt
*
* Read the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt.
*
* The returned priority value is automatically aligned to the implemented
* priority bits of the microcontroller.
*
* Note: The priority cannot be set for every core interrupt.
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/* ################################## SysTick function ############################################ */
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
/* SysTick constants */
#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
/**
* @brief Initialize and start the SysTick counter and its interrupt.
*
* @param uint32_t ticks is the number of ticks between two interrupts
* @return none
*
* Initialise the system tick timer and its interrupt and start the
* system tick timer / counter in free running mode to generate
* periodical interrupts.
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/* ################################## Reset function ############################################ */
/**
* @brief Initiate a system reset request.
*
* @param none
* @return none
*
* Initialize a system reset request to reset the MCU
*/
static __INLINE void NVIC_SystemReset(void)
{
SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
}
#endif

381
bsp/nuc140/CMSIS/CM0/startup/arm/startup_NUC1xx.s Normal file
View File

@ -0,0 +1,381 @@
;/*---------------------------------------------------------------------------------------------------------*/
;/* */
;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
;/* */
;/*---------------------------------------------------------------------------------------------------------*/
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
CLK_BA_base EQU 0x50000200
PWRCON EQU 0x00
AHBCLK EQU 0x04
APBCLK EQU 0x08
CLKSEL0 EQU 0x10
CLKSEL1 EQU 0x14
CLKDIV EQU 0x18
PLLCON EQU 0x20
TEST_S EQU 0x30
CLK_BA_APBCLK EQU 0x50000208
;// Define clock enable registers
ADC_COMP_CLK EQU 0x50000208
ADC_enable EQU 0x10000000
COMP_enable EQU 0x40000000
PDMA_CLK EQU 0x50000204
PDMA_enable EQU 0x00000003
;; bit 0 CPU_EN
;; bit 1 PDMA_EN
;// Define COMP registers base
COMP_base EQU 0x400D0000
CMP1CR EQU 0x00
CMP2CR EQU 0x04
CMPSR EQU 0x08
;// Define ADC registers base
ADC_base EQU 0x400E0000
ADDR0 EQU 0x00
ADDR1 EQU 0x04
ADDR2 EQU 0x08
ADDR3 EQU 0x0c
ADDR4 EQU 0x10
ADDR5 EQU 0x14
ADDR6 EQU 0x18
ADDR7 EQU 0x1c
ADCR EQU 0x20
ADCHER EQU 0x24
ADCMPR0 EQU 0x28
ADCMPR1 EQU 0x2c
ADSR EQU 0x30
ADCALR EQU 0x34
ADCFCR EQU 0x38
ADCALD EQU 0x3c
;// Pattern Table
pattern_55555555 EQU 0x55555555
pattern_aaaaaaaa EQU 0xaaaaaaaa
pattern_00005555 EQU 0x00005555
pattern_0000aaaa EQU 0x0000aaaa
pattern_05550515 EQU 0x05550515
pattern_0aaa0a2a EQU 0x0aaa0a2a
;// Define PDMA regsiter base
PDMA_BA_ch0_base EQU 0x50008000
PDMA_BA_ch1_base EQU 0x50008100
PDMA_BA_ch2_base EQU 0x50008200
PDMA_BA_ch3_base EQU 0x50008300
PDMA_BA_ch4_base EQU 0x50008400
PDMA_BA_ch5_base EQU 0x50008500
PDMA_BA_ch6_base EQU 0x50008600
PDMA_BA_ch7_base EQU 0x50008700
PDMA_BA_GCR EQU 0x50008F00
PDMA_BA_GCR_base EQU 0x50008F00
PDMA_GCRCSR EQU 0X00
PDMA_PDSSR2 EQU 0X04
PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000
PDMA_GCRISR EQU 0X0C
PDMA_GLOBAL_enable EQU 0x0000FF00
PDMA_CSR EQU 0X00
PDMA_SAR EQU 0X04
PDMA_DAR EQU 0X08
PDMA_BCR EQU 0X0C
PDMA_CSAR EQU 0X14
PDMA_CDAR EQU 0X18
PDMA_CBSR EQU 0X1C
PDMA_IER EQU 0X20
PDMA_ISR EQU 0X24
PDMA_CTCSR EQU 0X28
PDMA_SASOCR EQU 0X2C
PDMA_DASOCR EQU 0X30
PDMA_SBUF0 EQU 0X80
PDMA_SBUF1 EQU 0X84
PDMA_SBUF2 EQU 0X88
PDMA_SBUF3 EQU 0X8C
;// Define VIC control register
VIC_base EQU 0xFFFF0000
VIC_SCR15 EQU 0x003c
VIC_SVR15 EQU 0x00bc
VIC_SCR16 EQU 0x0040
VIC_SVR16 EQU 0x00c0
VIC_SCR30 EQU 0x0078
VIC_SVR30 EQU 0x00f8
VIC_MECR EQU 0x0318
VIC_MDCR EQU 0x031c
VIC_EOSCR EQU 0x0130
;//==================================
INT_BA_base EQU 0x50000300
;// Parameter table
ADC_PDMA_CFG EQU 0x00002980
ADC_PDMA_DST EQU 0xC0000000
ADC_PDMA_SRC EQU 0xE0024200
ADC_PDMA_TCBL EQU 0x00030008
;//==================================
GPIO_base EQU 0x50004000
GPIOB_PMD EQU 0x0040
GPIOB_OFFD EQU 0x0044
GPIOB_DOUT EQU 0x0048
GPIOB_DMASK EQU 0x004C
GPIOB_PIN EQU 0x0050
GPIOB_DBEN EQU 0x0054
GPIOB_IMD EQU 0x0058
GPIOB_IEN EQU 0x005C
GPIOB_ISRC EQU 0x0060
;//==================================
GCR_base EQU 0x50000000
GPB_MFP EQU 0x0034
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; maximum of 32 External Interrupts are possible
DCD BOD_IRQHandler
DCD WDT_IRQHandler
DCD EINT0_IRQHandler
DCD EINT1_IRQHandler
DCD GPAB_IRQHandler
DCD GPCDE_IRQHandler
DCD PWMA_IRQHandler
DCD PWMB_IRQHandler
DCD TMR0_IRQHandler
DCD TMR1_IRQHandler
DCD TMR2_IRQHandler
DCD TMR3_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD SPI2_IRQHandler
DCD SPI3_IRQHandler
DCD I2C0_IRQHandler
DCD I2C1_IRQHandler
DCD CAN0_IRQHandler
DCD CAN1_IRQHandler
DCD Default_Handler
DCD USBD_IRQHandler
DCD PS2_IRQHandler
DCD ACMP_IRQHandler
DCD PDMA_IRQHandler
DCD Default_Handler
DCD PWRWU_IRQHandler
DCD ADC_IRQHandler
DCD Default_Handler
DCD RTC_IRQHandler
AREA |.text|, CODE, READONLY
; Reset Handler
ENTRY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT GPAB_IRQHandler [WEAK]
EXPORT GPCDE_IRQHandler [WEAK]
EXPORT PWMA_IRQHandler [WEAK]
EXPORT PWMB_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT PS2_IRQHandler [WEAK]
EXPORT ACMP_IRQHandler [WEAK]
EXPORT PDMA_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPAB_IRQHandler
GPCDE_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
USBD_IRQHandler
PS2_IRQHandler
ACMP_IRQHandler
PDMA_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

37
bsp/nuc140/CMSIS/CM0/system_NUC1xx.c Normal file
View File

@ -0,0 +1,37 @@
/*---------------------------------------------------------------------------------------------------------*/
/* */
/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
/* */
/*---------------------------------------------------------------------------------------------------------*/
#include <stdint.h>
#include "NUC1xx.h"
/*----------------------------------------------------------------------------
Define SYSCLK
*----------------------------------------------------------------------------*/
#define __HSI (50000000UL)
/*----------------------------------------------------------------------------
Clock Definitions
*----------------------------------------------------------------------------*/
uint32_t SystemFrequency = __HSI; /*!< System Clock Frequency (Core Clock) */
/*---------------------------------------------------------------------------------------------------------*/
/* Function: SystemInit */
/* */
/* Parameters: */
/* None */
/* */
/* Returns: */
/* None */
/* */
/* Description: */
/* The necessary initializaiton of systerm. */
/* */
/*---------------------------------------------------------------------------------------------------------*/
void SystemInit (void)
{
}

39
bsp/nuc140/CMSIS/CM0/system_NUC1xx.h Normal file
View File

@ -0,0 +1,39 @@
/******************************************************************************
* @file: system_armikmcu.h
* @purpose: CMSIS ARM Cortex-M0 Device Peripheral Access Layer Header File
* @version: V0.01
* @date: 17. Feb. 2009
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_ARMCM0_H
#define __SYSTEM_ARMCM0_H
extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
* Initialise GPIO directions and values
*/
extern void SystemInit (void);
#endif

1204
bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm Normal file
View File

File diff suppressed because it is too large Load Diff

26
bsp/nuc140/application.c Normal file
View File

@ -0,0 +1,26 @@
/*
* File : app.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
/**
* @addtogroup LPC1100
*/
/*@{*/
#include <rtthread.h>
int rt_application_init()
{
return 0;
}
/*@}*/

65
bsp/nuc140/board.c Normal file
View File

@ -0,0 +1,65 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "uart.h"
#include "CMSIS/CM0/NUC1xx.h"
#include "CMSIS/CM0/core_cm0.h"
/**
* @addtogroup NUC100
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler()
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial sam7s64 board.
*/
void rt_hw_board_init()
{
SystemInit();
/* init systick */
SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_UART
/* init hardware UART device */
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device("uart1");
#endif
}
/*@}*/

20
bsp/nuc140/board.h Normal file
View File

@ -0,0 +1,20 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_init(void);
#endif

2096
bsp/nuc140/project.uvopt Normal file
View File

File diff suppressed because it is too large Load Diff

609
bsp/nuc140/project.uvproj Normal file
View File

@ -0,0 +1,609 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>RT-Thread NUC100</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>Cortex-M0</Device>
<Vendor>ARM</Vendor>
<Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>4803</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\objs\</OutputDirectory>
<OutputName>rtthread-nuc140</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments></SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments></TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4097</DriverSelection>
</Flash1>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>5</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>1</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IRAM>
<IROM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>0</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.;..\..\include;..\..\finsh</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>1</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--entry Reset_Handler --keep __fsym_* --keep __vsym_*</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Startup</GroupName>
<Files>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>.\board.c</FilePath>
</File>
<File>
<FileName>startup.c</FileName>
<FileType>1</FileType>
<FilePath>.\startup.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>.\uart.c</FilePath>
</File>
<File>
<FileName>rtconfig.h</FileName>
<FileType>5</FileType>
<FilePath>.\rtconfig.h</FilePath>
</File>
<File>
<FileName>application.c</FileName>
<FileType>1</FileType>
<FilePath>.\application.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>NUC100</GroupName>
<Files>
<File>
<FileName>fault.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\nuc1xx\fault.c</FilePath>
</File>
<File>
<FileName>interrupt.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\nuc1xx\interrupt.c</FilePath>
</File>
<File>
<FileName>stack.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\nuc1xx\stack.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\nuc1xx\context_rvds.S</FilePath>
</File>
<File>
<FileName>fault_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\nuc1xx\fault_rvds.S</FilePath>
</File>
<File>
<FileName>start_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\libcpu\arm\nuc1xx\start_rvds.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CMSIS</GroupName>
<Files>
<File>
<FileName>system_NUC1xx.c</FileName>
<FileType>1</FileType>
<FilePath>.\CMSIS\CM0\system_NUC1xx.c</FilePath>
</File>
<File>
<FileName>core_cm0.c</FileName>
<FileType>1</FileType>
<FilePath>.\CMSIS\CM0\core_cm0.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
</File>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\device.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\object.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>slab.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\slab.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\thread.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>finsh</GroupName>
<Files>
<File>
<FileName>symbol.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\symbol.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\cmd.c</FilePath>
</File>
<File>
<FileName>finsh_compiler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_compiler.c</FilePath>
</File>
<File>
<FileName>finsh_error.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_error.c</FilePath>
</File>
<File>
<FileName>finsh_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_heap.c</FilePath>
</File>
<File>
<FileName>finsh_init.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_init.c</FilePath>
</File>
<File>
<FileName>finsh_node.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_node.c</FilePath>
</File>
<File>
<FileName>finsh_ops.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_ops.c</FilePath>
</File>
<File>
<FileName>finsh_parser.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_parser.c</FilePath>
</File>
<File>
<FileName>finsh_token.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_token.c</FilePath>
</File>
<File>
<FileName>finsh_var.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_var.c</FilePath>
</File>
<File>
<FileName>finsh_vm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\finsh_vm.c</FilePath>
</File>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\finsh\shell.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>

74
bsp/nuc140/rtconfig.h Normal file
View File

@ -0,0 +1,74 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 4
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
#define RT_THREAD_PRIORITY_MAX 8
/* Tick per Second*/
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug*/
/* #define RT_THREAD_DEBUG */
/* Using Hook*/
/* #define RT_USING_HOOK */
/* SECTION: IPC */
/* Using Semaphore*/
#define RT_USING_SEMAPHORE
/* Using Mutex*/
/* #define RT_USING_MUTEX */
/* Using Event*/
/* #define RT_USING_EVENT */
/* Using MailBox*/
#define RT_USING_MAILBOX
/* Using Message Queue*/
/* #define RT_USING_MESSAGEQUEUE */
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
/* #define RT_USING_MEMPOOL */
/* Using Dynamic Heap Management*/
#define RT_USING_HEAP
/* Using Small MM*/
#define RT_USING_SMALL_MEM
#define RT_USING_TINY_SIZE
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
/* buffer size for UART reception */
#define RT_UART_RX_BUFFER_SIZE 64
/* Using UART */
#define RT_USING_UART
/* SECTION: Console options */
/* use console for rt_kprintf */
#define RT_USING_CONSOLE
/* the buffer size of console */
#define RT_CONSOLEBUF_SIZE 80
/* SECTION: finsh, a C-Express shell */
/* Using FinSH as Shell*/
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#endif

111
bsp/nuc140/startup.c Normal file
View File

@ -0,0 +1,111 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#ifdef RT_USING_FINSH
#include "finsh.h"
extern void finsh_system_init(void);
#endif
/**
* @addtogroup NUC100
*/
/*@{*/
#if defined(__CC_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#elif defined(__GNUC__)
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#endif
extern int rt_application_init(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init kernel object */
rt_system_object_init();
/* init board */
rt_hw_board_init();
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20004000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x20004000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x20004000);
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_HOOK /* if the hook is used */
/* set idle thread hook */
rt_thread_idle_sethook(rt_hw_led_flash);
#endif
#ifdef RT_USING_DEVICE
/* init all device */
rt_device_init_all();
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main (void)
{
rt_uint32_t UNUSED level;
/* disable interrupt first */
level = rt_hw_interrupt_disable();
/* invoke rtthread_startup */
rtthread_startup();
return 0;
}
/*@}*/

226
bsp/nuc140/uart.c Normal file
View File

@ -0,0 +1,226 @@
#include <rthw.h>
#include <rtthread.h>
#include "CMSIS/CM0/NUC1xx.h"
/**
* @addtogroup NUC1xx
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
#define UART_BAUDRATE 115200
struct rt_uart_nuc
{
struct rt_device parent;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
void UART0_IRQHandler(void)
{
rt_ubase_t level;
struct rt_uart_nuc* uart = &uart_device;
if (UART0->ISR.RDA_INT == 1) /* Receive Data Available */
{
while (UART0->ISR.RDA_IF == 1)
{
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = UART0->DATA;
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init (rt_device_t dev)
{
/* Multi-Function Pin: Enable UART0:Tx Rx */
SYS->GPBMFP.UART0_RX = 1;
SYS->GPBMFP.UART0_TX = 1;
/* Configure GCR to reset UART0 */
SYS->IPRSTC2.UART0_RST = 1;
SYS->IPRSTC2.UART0_RST = 0;
/* Enable UART clock */
SYSCLK->APBCLK.UART0_EN = 1;
/* Select UART clock source */
SYSCLK->CLKSEL1.UART_S = 0;
/* Data format */
UART0->LCR.WLS = 3;
/* Configure the baud rate */
*((__IO uint32_t *)&UART0->BAUD) = 0x3F000066; /* This setting is for 115200bsp with 12Mhz clock source */
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* open receive data available interrupt */
UART0->IER.RDA_IEN = 1;
/* Enable the UART Interrupt */
NVIC_EnableIRQ(UART0_IRQn);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
NVIC_DisableIRQ(UART0_IRQn);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_uart_nuc *uart = (struct rt_uart_nuc*)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
char *ptr;
ptr = (char*)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* check whether UART is empty */
while (UART0->FSR.TX_EMPTY !=1);
/* write data */
UART0->DATA = '\r';
}
/* check whether UART is empty */
while (UART0->FSR.TX_EMPTY !=1);
/* write data */
UART0->DATA = *ptr;
ptr ++;
size --;
}
}
else
{
while ( size != 0 )
{
/* check whether UART is empty */
while (UART0->FSR.TX_EMPTY !=1);
/* write data */
UART0->DATA = *ptr;
ptr++;
size--;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_nuc* uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.private = RT_NULL;
rt_device_register(&uart->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/

6
bsp/nuc140/uart.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef __UART_H__
#define __UART_H__
void rt_hw_uart_init(void);
#endif

175
libcpu/arm/nuc1xx/context_rvds.S Normal file
View File

@ -0,0 +1,175 @@
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; */
;/**
; * @addtogroup NUC100
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrput_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrput_flag to 1
LDR r2, =rt_thread_switch_interrput_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOVS r3, #0x1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
rt_hw_pend_sv PROC
EXPORT rt_hw_pend_sv
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrput_flag
LDR r1, [r0]
CMP r1, #0x00
BEQ pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrput_flag to 0
MOVS r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CMP r1, #0x00
BEQ swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
SUBS r1, r1, #0x10
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
STMIA r1!, {r4 - r7} ; push r4 - r7 register
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMIA r1!, {r4 - r7} ; pop r4 - r7 register
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
MOVS r0, #0x04
RSBS r0, #0
BX r0
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOVS r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrput_flag
MOVS r0, #1
STR r0, [r1]
; set the PendSV exception priority
; LDR r0, =NVIC_SYSPRI2
; LDR r1, =NVIC_PENDSV_PRI
; STR r1, [r0]
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
ENDP
END

47
libcpu/arm/nuc1xx/fault.c Normal file
View File

@ -0,0 +1,47 @@
/*
* File : fault.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rtthread.h>
struct stack_contex
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r12;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t psr;
};
extern void rt_hw_interrupt_thread_switch(void);
extern void list_thread(void);
extern rt_thread_t rt_current_thread;
void rt_hw_hard_fault_exception(struct stack_contex* contex)
{
rt_kprintf("psr: 0x%08x\n", contex->psr);
rt_kprintf(" pc: 0x%08x\n", contex->pc);
rt_kprintf(" lr: 0x%08x\n", contex->lr);
rt_kprintf("r12: 0x%08x\n", contex->r12);
rt_kprintf("r03: 0x%08x\n", contex->r3);
rt_kprintf("r02: 0x%08x\n", contex->r2);
rt_kprintf("r01: 0x%08x\n", contex->r1);
rt_kprintf("r00: 0x%08x\n", contex->r0);
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
while (1);
}

32
libcpu/arm/nuc1xx/fault_rvds.S Normal file
View File

@ -0,0 +1,32 @@
;/*
; * File : fault_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_hw_hard_fault_exception
rt_hw_hard_fault PROC
EXPORT rt_hw_hard_fault
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {pc}
ENDP
END

21
libcpu/arm/nuc1xx/interrupt.c Normal file
View File

@ -0,0 +1,21 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rtthread.h>
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint8_t rt_thread_switch_interrput_flag;
/*@}*/

54
libcpu/arm/nuc1xx/stack.c Normal file
View File

@ -0,0 +1,54 @@
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
*/
#include <rtthread.h>
/**
* @addtogroup NUC100
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
unsigned long *stk;
stk = (unsigned long *)stack_addr;
*(stk) = 0x01000000L; /* PSR */
*(--stk) = (unsigned long)tentry; /* entry point, pc */
*(--stk) = (unsigned long)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (unsigned long)parameter; /* r0 : argument */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

349
libcpu/arm/nuc1xx/start_rvds.S Normal file
View File

@ -0,0 +1,349 @@
;/*---------------------------------------------------------------------------------------------------------*/
;/* */
;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
;/* */
;/*---------------------------------------------------------------------------------------------------------*/
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
CLK_BA_base EQU 0x50000200
PWRCON EQU 0x00
AHBCLK EQU 0x04
APBCLK EQU 0x08
CLKSEL0 EQU 0x10
CLKSEL1 EQU 0x14
CLKDIV EQU 0x18
PLLCON EQU 0x20
TEST_S EQU 0x30
CLK_BA_APBCLK EQU 0x50000208
;// Define clock enable registers
ADC_COMP_CLK EQU 0x50000208
ADC_enable EQU 0x10000000
COMP_enable EQU 0x40000000
PDMA_CLK EQU 0x50000204
PDMA_enable EQU 0x00000003
;; bit 0 CPU_EN
;; bit 1 PDMA_EN
;// Define COMP registers base
COMP_base EQU 0x400D0000
CMP1CR EQU 0x00
CMP2CR EQU 0x04
CMPSR EQU 0x08
;// Define ADC registers base
ADC_base EQU 0x400E0000
ADDR0 EQU 0x00
ADDR1 EQU 0x04
ADDR2 EQU 0x08
ADDR3 EQU 0x0c
ADDR4 EQU 0x10
ADDR5 EQU 0x14
ADDR6 EQU 0x18
ADDR7 EQU 0x1c
ADCR EQU 0x20
ADCHER EQU 0x24
ADCMPR0 EQU 0x28
ADCMPR1 EQU 0x2c
ADSR EQU 0x30
ADCALR EQU 0x34
ADCFCR EQU 0x38
ADCALD EQU 0x3c
;// Pattern Table
pattern_55555555 EQU 0x55555555
pattern_aaaaaaaa EQU 0xaaaaaaaa
pattern_00005555 EQU 0x00005555
pattern_0000aaaa EQU 0x0000aaaa
pattern_05550515 EQU 0x05550515
pattern_0aaa0a2a EQU 0x0aaa0a2a
;// Define PDMA regsiter base
PDMA_BA_ch0_base EQU 0x50008000
PDMA_BA_ch1_base EQU 0x50008100
PDMA_BA_ch2_base EQU 0x50008200
PDMA_BA_ch3_base EQU 0x50008300
PDMA_BA_ch4_base EQU 0x50008400
PDMA_BA_ch5_base EQU 0x50008500
PDMA_BA_ch6_base EQU 0x50008600
PDMA_BA_ch7_base EQU 0x50008700
PDMA_BA_GCR EQU 0x50008F00
PDMA_BA_GCR_base EQU 0x50008F00
PDMA_GCRCSR EQU 0X00
PDMA_PDSSR2 EQU 0X04
PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000
PDMA_GCRISR EQU 0X0C
PDMA_GLOBAL_enable EQU 0x0000FF00
PDMA_CSR EQU 0X00
PDMA_SAR EQU 0X04
PDMA_DAR EQU 0X08
PDMA_BCR EQU 0X0C
PDMA_CSAR EQU 0X14
PDMA_CDAR EQU 0X18
PDMA_CBSR EQU 0X1C
PDMA_IER EQU 0X20
PDMA_ISR EQU 0X24
PDMA_CTCSR EQU 0X28
PDMA_SASOCR EQU 0X2C
PDMA_DASOCR EQU 0X30
PDMA_SBUF0 EQU 0X80
PDMA_SBUF1 EQU 0X84
PDMA_SBUF2 EQU 0X88
PDMA_SBUF3 EQU 0X8C
;// Define VIC control register
VIC_base EQU 0xFFFF0000
VIC_SCR15 EQU 0x003c
VIC_SVR15 EQU 0x00bc
VIC_SCR16 EQU 0x0040
VIC_SVR16 EQU 0x00c0
VIC_SCR30 EQU 0x0078
VIC_SVR30 EQU 0x00f8
VIC_MECR EQU 0x0318
VIC_MDCR EQU 0x031c
VIC_EOSCR EQU 0x0130
;//==================================
INT_BA_base EQU 0x50000300
;// Parameter table
ADC_PDMA_CFG EQU 0x00002980
ADC_PDMA_DST EQU 0xC0000000
ADC_PDMA_SRC EQU 0xE0024200
ADC_PDMA_TCBL EQU 0x00030008
;//==================================
GPIO_base EQU 0x50004000
GPIOB_PMD EQU 0x0040
GPIOB_OFFD EQU 0x0044
GPIOB_DOUT EQU 0x0048
GPIOB_DMASK EQU 0x004C
GPIOB_PIN EQU 0x0050
GPIOB_DBEN EQU 0x0054
GPIOB_IMD EQU 0x0058
GPIOB_IEN EQU 0x005C
GPIOB_ISRC EQU 0x0060
;//==================================
GCR_base EQU 0x50000000
GPB_MFP EQU 0x0034
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
IMPORT rt_hw_hard_fault
IMPORT rt_hw_pend_sv
IMPORT rt_hw_timer_handler
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD rt_hw_hard_fault ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD rt_hw_pend_sv ; PendSV Handler
DCD rt_hw_timer_handler ; SysTick Handler
; External Interrupts
; maximum of 32 External Interrupts are possible
DCD BOD_IRQHandler
DCD WDT_IRQHandler
DCD EINT0_IRQHandler
DCD EINT1_IRQHandler
DCD GPAB_IRQHandler
DCD GPCDE_IRQHandler
DCD PWMA_IRQHandler
DCD PWMB_IRQHandler
DCD TMR0_IRQHandler
DCD TMR1_IRQHandler
DCD TMR2_IRQHandler
DCD TMR3_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD SPI2_IRQHandler
DCD SPI3_IRQHandler
DCD I2C0_IRQHandler
DCD I2C1_IRQHandler
DCD CAN0_IRQHandler
DCD CAN1_IRQHandler
DCD Default_Handler
DCD USBD_IRQHandler
DCD PS2_IRQHandler
DCD ACMP_IRQHandler
DCD PDMA_IRQHandler
DCD Default_Handler
DCD PWRWU_IRQHandler
DCD ADC_IRQHandler
DCD Default_Handler
DCD RTC_IRQHandler
AREA |.text|, CODE, READONLY
; Reset Handler
ENTRY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT GPAB_IRQHandler [WEAK]
EXPORT GPCDE_IRQHandler [WEAK]
EXPORT PWMA_IRQHandler [WEAK]
EXPORT PWMB_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT PS2_IRQHandler [WEAK]
EXPORT ACMP_IRQHandler [WEAK]
EXPORT PDMA_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPAB_IRQHandler
GPCDE_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
USBD_IRQHandler
PS2_IRQHandler
ACMP_IRQHandler
PDMA_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END