[rpi4b] add new bsp for qemu-rpi4b
This commit is contained in:
zhujiale
Rbb666
parent
2b21b095f9
commit
c1db34983d
File diff suppressed because it is too large
Load Diff
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mainmenu "RT-Thread Project Configuration"
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BSP_DIR := .
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RTT_DIR := ../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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config BCM2711_SOC
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bool
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select ARCH_ARMV8
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select ARCH_ARM_MMU
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select RT_USING_CACHE
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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select ARCH_CPU_64BIT
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default y
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rsource "drivers/Kconfig"
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# Raspberry PI 4-dm2.0BSP说明
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## 1. 简介
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树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
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外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
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这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
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## 2. 编译说明
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推荐使用[env工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)，可以在console下进入到`bsp\raspberry-pi\raspi4-64`目录中，运行以下命令：
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```
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scons
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```
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来编译这个板级支持包。如果编译正确无误，会产生 `rtthread.elf`, `rtthread.bin` 文件。
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## 3. 支持情况
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| 驱动 | 支持情况 | 备注 |
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| ------ | ---- | :------: |
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| UART | 支持 | pl011驱动 |
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| GPIO | 尚未支持 | 等待dm2.0相关代码合入主线 |
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| SPI | 尚未支持 | 等待gpio合入主线 |
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| WATCHDOG | 尚未支持 | 等待gpio合入主线 |
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| HDMI | 尚未支持 | 等待gpio合入主线 |
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| SDIO | 支持 | 能够正常运行在qemu，但是qemu对于raspi目前只支持pio传输，后续需要硬件进行详细测试 |
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| ETH | 尚未支持 | 等待gpio合入主线 |
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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import os
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import sys
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import rtconfig
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from rtconfig import RTT_ROOT
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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CPP = rtconfig.CPP, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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env['ASCOM'] = env['ASPPCOM']
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env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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# make a building
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DoBuilding(TARGET, objs)
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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list = os.listdir(cwd)
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for item in list:
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if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
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group = group + SConscript(os.path.join(item, 'SConscript'))
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Return('group')
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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-04-16 bigmagic first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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int main(int argc, char** argv)
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{
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rt_kprintf("Hi, this is RT-Thread!!\n");
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return 0;
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}
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Binary file not shown.
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menu "Hardware Drivers Config"
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config BSP_USING_PL011
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bool "Enable pl011 for uart"
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default n
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config BSP_USING_SDHCI
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bool "Enable sdhci driver"
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select RT_USING_SDHCI
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default y
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rsource sdhci/Kconfig
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endmenu
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from building import *
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cwd = GetCurrentDir()
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src = ["board.c"]
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CPPPATH = [cwd, str(Dir('#'))]
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if GetDepend(['BSP_USING_PL011']):
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src = src + ['drv_uart.c']
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if GetDepend(['BSP_USING_SDHCI']):
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src = src + ['drv_sd.c']
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group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH)
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# build for sub-directory
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list = os.listdir(cwd)
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objs = []
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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group = group + objs
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Return('group')
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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-10-28 zhujiale The first version
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*/
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#define DBG_TAG "board"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <mm_aspace.h>
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#include <setup.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "cp15.h"
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#include "mmu.h"
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#include <mm_page.h>
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#ifdef RT_USING_SMART
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#include <lwp_arch.h>
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#endif
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void rt_hw_board_init(void)
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{
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rt_hw_common_setup();
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}
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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-10-28 zhujiale The first version
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*/
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#ifndef BOARD_H__
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#define BOARD_H__
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#include <stdint.h>
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#include "mmu.h"
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#include "ioremap.h"
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extern int __bss_end;
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#define HEAP_BEGIN ((void*)&__bss_end)
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#ifdef RT_USING_SMART
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#define HEAP_END ((size_t)KERNEL_VADDR_START + 32 * 1024 * 1024)
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#define PAGE_START HEAP_END
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#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
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#else
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#define KERNEL_VADDR_START 0x0
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#define HEAP_END (KERNEL_VADDR_START + 32 * 1024 * 1024)
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#define PAGE_START HEAP_END
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#define PAGE_END ((size_t)PAGE_START + 128 * 1024 * 1024)
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#endif
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void rt_hw_board_init(void);
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#endif
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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-10-28 zhujiale The first version
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*/
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#include <sdhci.h>
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#include <rtdevice.h>
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#include "drv_sd.h"
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#define DBG_TAG "SDHCI"
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#ifdef DRV_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_INFO
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#endif /* DRV_DEBUG */
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#include <rtdbg.h>
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#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
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struct sdhci_iproc_data {
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const struct sdhci_pltfm_data *pdata;
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rt_uint32_t caps;
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rt_uint32_t caps1;
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rt_uint32_t mmc_caps;
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rt_bool_t missing_caps;
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};
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struct sdhci_iproc_host {
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const struct sdhci_iproc_data *data;
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rt_uint32_t shadow_cmd;
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rt_uint32_t shadow_blk;
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rt_bool_t is_cmd_shadowed;
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rt_bool_t is_blk_shadowed;
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};
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static inline rt_uint32_t sdhci_iproc_readl(struct sdhci_host *host, int reg)
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{
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rt_uint32_t val = readl(host->ioaddr + reg);
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return val;
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}
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static rt_uint16_t sdhci_iproc_readw(struct sdhci_host *host, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
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rt_uint32_t val;
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rt_uint16_t word;
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if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed)
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{
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/* Get the saved transfer mode */
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val = iproc_host->shadow_cmd;
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} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
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iproc_host->is_blk_shadowed)
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{
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/* Get the saved block info */
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val = iproc_host->shadow_blk;
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} else {
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val = sdhci_iproc_readl(host, (reg & ~3));
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}
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word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
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return word;
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}
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static rt_uint8_t sdhci_iproc_readb(struct sdhci_host *host, int reg)
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{
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rt_uint32_t val = sdhci_iproc_readl(host, (reg & ~3));
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rt_uint8_t byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
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return byte;
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}
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static inline void sdhci_iproc_writel(struct sdhci_host *host, rt_uint32_t val, int reg)
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{
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LOG_D("%s: writel [0x%02x] 0x%08x\n",
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mmc_hostname(host->mmc), reg, val);
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writel(val, host->ioaddr + reg);
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if (host->clock <= 400000)
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{
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/* Round up to micro-second four SD clock delay */
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if (host->clock)
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rt_hw_us_delay((4 * 1000000 + host->clock - 1) / host->clock);
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else
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rt_hw_us_delay(10);
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}
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}
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static void sdhci_iproc_writew(struct sdhci_host *host, rt_uint16_t val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
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rt_uint32_t word_shift = REG_OFFSET_IN_BITS(reg);
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rt_uint32_t mask = 0xffff << word_shift;
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rt_uint32_t oldval, newval;
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if (reg == SDHCI_COMMAND)
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{
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/* Write the block now as we are issuing a command */
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if (iproc_host->is_blk_shadowed)
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{
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sdhci_iproc_writel(host, iproc_host->shadow_blk,
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SDHCI_BLOCK_SIZE);
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iproc_host->is_blk_shadowed = false;
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}
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oldval = iproc_host->shadow_cmd;
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iproc_host->is_cmd_shadowed = false;
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} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
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iproc_host->is_blk_shadowed)
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{
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/* Block size and count are stored in shadow reg */
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oldval = iproc_host->shadow_blk;
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} else {
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/* Read reg, all other registers are not shadowed */
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oldval = sdhci_iproc_readl(host, (reg & ~3));
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}
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newval = (oldval & ~mask) | (val << word_shift);
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if (reg == SDHCI_TRANSFER_MODE)
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{
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/* Save the transfer mode until the command is issued */
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iproc_host->shadow_cmd = newval;
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iproc_host->is_cmd_shadowed = true;
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} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT)
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{
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/* Save the block info until the command is issued */
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iproc_host->shadow_blk = newval;
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iproc_host->is_blk_shadowed = true;
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} else {
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/* Command or other regular 32-bit write */
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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}
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static void sdhci_iproc_writeb(struct sdhci_host *host, rt_uint8_t val, int reg)
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{
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rt_uint32_t oldval = sdhci_iproc_readl(host, (reg & ~3));
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rt_uint32_t byte_shift = REG_OFFSET_IN_BITS(reg);
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rt_uint32_t mask = 0xff << byte_shift;
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rt_uint32_t newval = (oldval & ~mask) | (val << byte_shift);
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
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.read_l = sdhci_iproc_readl,
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.read_w = sdhci_iproc_readw,
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.read_b = sdhci_iproc_readb,
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.write_l = sdhci_iproc_writel,
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.write_w = sdhci_iproc_writew,
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.write_b = sdhci_iproc_writeb,
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
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.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
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.ops = &sdhci_iproc_bcm2711_ops,
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};
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static const struct sdhci_iproc_data bcm2711_data = {
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.pdata = &sdhci_bcm2711_pltfm_data,
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.mmc_caps = MMC_CAP_3_3V_DDR,
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};
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rt_err_t bcm2835_probe(struct rt_platform_device *pdev)
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{
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struct sdhci_iproc_host *iproc_host;
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const struct sdhci_iproc_data *iproc_data = NULL;
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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int ret;
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iproc_data = &bcm2711_data;
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host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
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pltfm_host = sdhci_priv(host);
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iproc_host = sdhci_pltfm_priv(pltfm_host);
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iproc_host->data = iproc_data;
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto err;
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sdhci_get_property(pdev);
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host->mmc->caps |= iproc_host->data->mmc_caps;
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ret = sdhci_add_host(host);
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if (ret)
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goto err;
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return 0;
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err:
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return ret;
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}
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|
||||
static const struct rt_ofw_node_id bcm2835_ofw_ids[] =
|
||||
{
|
||||
/* { .compatible = "brcm,bcm2711-emmc2"},*/
|
||||
{ .compatible = "brcm,bcm2835-mmc"},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct rt_platform_driver bcm2835_driver =
|
||||
{
|
||||
.name = "bcm2835",
|
||||
.ids = bcm2835_ofw_ids,
|
||||
|
||||
.probe = bcm2835_probe,
|
||||
/* .remove = pl011_remove,*/
|
||||
};
|
||||
|
||||
|
||||
RT_PLATFORM_DRIVER_EXPORT(bcm2835_driver);
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-10-28 zhujiale The first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_SD_BCM2835_H_
|
||||
#define __DRV_SD_BCM2835_H_
|
||||
#include <drivers/dev_mmcsd_core.h>
|
||||
#include <rtthread.h>
|
||||
#include <drivers/mmcsd_cmd.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
struct sdhci_bcm2835 {
|
||||
struct sdhci_host *host;
|
||||
struct rt_platform_device *pdev;
|
||||
struct rt_mmcsd_req *mrq;
|
||||
|
||||
void *ioaddr;
|
||||
rt_mutex_t mutex;
|
||||
};
|
||||
#define SDCMD 0x00 /* Command to SD card - 16 R/W */
|
||||
#define SDARG 0x04 /* Argument to SD card - 32 R/W */
|
||||
#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
|
||||
#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
|
||||
#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
|
||||
#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
|
||||
#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
|
||||
#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
|
||||
#define SDHSTS 0x20 /* SD host status - 11 R/W */
|
||||
#define SDVDD 0x30 /* SD card power control - 1 R/W */
|
||||
#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
|
||||
#define SDHCFG 0x38 /* Host configuration - 2 R/W */
|
||||
#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
|
||||
#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
|
||||
#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
|
||||
|
||||
#define SDCMD_NEW_FLAG 0x8000
|
||||
#define SDCMD_FAIL_FLAG 0x4000
|
||||
#define SDCMD_BUSYWAIT 0x800
|
||||
#define SDCMD_NO_RESPONSE 0x400
|
||||
#define SDCMD_LONG_RESPONSE 0x200
|
||||
#define SDCMD_WRITE_CMD 0x80
|
||||
#define SDCMD_READ_CMD 0x40
|
||||
#define SDCMD_CMD_MASK 0x3f
|
||||
|
||||
#define SDCDIV_MAX_CDIV 0x7ff
|
||||
|
||||
#define SDHSTS_BUSY_IRPT 0x400
|
||||
#define SDHSTS_BLOCK_IRPT 0x200
|
||||
#define SDHSTS_SDIO_IRPT 0x100
|
||||
#define SDHSTS_REW_TIME_OUT 0x80
|
||||
#define SDHSTS_CMD_TIME_OUT 0x40
|
||||
#define SDHSTS_CRC16_ERROR 0x20
|
||||
#define SDHSTS_CRC7_ERROR 0x10
|
||||
#define SDHSTS_FIFO_ERROR 0x08
|
||||
/* Reserved */
|
||||
/* Reserved */
|
||||
#define SDHSTS_DATA_FLAG 0x01
|
||||
|
||||
#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
|
||||
SDHSTS_CRC16_ERROR | \
|
||||
SDHSTS_REW_TIME_OUT | \
|
||||
SDHSTS_FIFO_ERROR)
|
||||
|
||||
#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
|
||||
SDHSTS_TRANSFER_ERROR_MASK)
|
||||
|
||||
#define SDHCFG_BUSY_IRPT_EN BIT(10)
|
||||
#define SDHCFG_BLOCK_IRPT_EN BIT(8)
|
||||
#define SDHCFG_SDIO_IRPT_EN BIT(5)
|
||||
#define SDHCFG_DATA_IRPT_EN BIT(4)
|
||||
#define SDHCFG_SLOW_CARD BIT(3)
|
||||
#define SDHCFG_WIDE_EXT_BUS BIT(2)
|
||||
#define SDHCFG_WIDE_INT_BUS BIT(1)
|
||||
#define SDHCFG_REL_CMD_LINE BIT(0)
|
||||
|
||||
#define SDVDD_POWER_OFF 0
|
||||
#define SDVDD_POWER_ON 1
|
||||
|
||||
#define SDEDM_FORCE_DATA_MODE BIT(19)
|
||||
#define SDEDM_CLOCK_PULSE BIT(20)
|
||||
#define SDEDM_BYPASS BIT(21)
|
||||
|
||||
#define SDEDM_WRITE_THRESHOLD_SHIFT 9
|
||||
#define SDEDM_READ_THRESHOLD_SHIFT 14
|
||||
#define SDEDM_THRESHOLD_MASK 0x1f
|
||||
|
||||
#define SDEDM_FSM_MASK 0xf
|
||||
#define SDEDM_FSM_IDENTMODE 0x0
|
||||
#define SDEDM_FSM_DATAMODE 0x1
|
||||
#define SDEDM_FSM_READDATA 0x2
|
||||
#define SDEDM_FSM_WRITEDATA 0x3
|
||||
#define SDEDM_FSM_READWAIT 0x4
|
||||
#define SDEDM_FSM_READCRC 0x5
|
||||
#define SDEDM_FSM_WRITECRC 0x6
|
||||
#define SDEDM_FSM_WRITEWAIT1 0x7
|
||||
#define SDEDM_FSM_POWERDOWN 0x8
|
||||
#define SDEDM_FSM_POWERUP 0x9
|
||||
#define SDEDM_FSM_WRITESTART1 0xa
|
||||
#define SDEDM_FSM_WRITESTART2 0xb
|
||||
#define SDEDM_FSM_GENPULSES 0xc
|
||||
#define SDEDM_FSM_WRITEWAIT2 0xd
|
||||
#define SDEDM_FSM_STARTPOWDOWN 0xf
|
||||
|
||||
#define SDDATA_FIFO_WORDS 16
|
||||
|
||||
#define FIFO_READ_THRESHOLD 4
|
||||
#define FIFO_WRITE_THRESHOLD 4
|
||||
#define SDDATA_FIFO_PIO_BURST 8
|
||||
|
||||
#define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-05-05 Bernard The first version
|
||||
* 2022-08-24 GuEe-GUI add OFW support
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <cpuport.h>
|
||||
|
||||
#include <ioremap.h>
|
||||
|
||||
#include <drivers/serial_dm.h>
|
||||
|
||||
#define PL011_OEIM RT_BIT(10) /* overrun error interrupt mask */
|
||||
#define PL011_BEIM RT_BIT(9) /* break error interrupt mask */
|
||||
#define PL011_PEIM RT_BIT(8) /* parity error interrupt mask */
|
||||
#define PL011_FEIM RT_BIT(7) /* framing error interrupt mask */
|
||||
#define PL011_RTIM RT_BIT(6) /* receive timeout interrupt mask */
|
||||
#define PL011_TXIM RT_BIT(5) /* transmit interrupt mask */
|
||||
#define PL011_RXIM RT_BIT(4) /* receive interrupt mask */
|
||||
#define PL011_DSRMIM RT_BIT(3) /* DSR interrupt mask */
|
||||
#define PL011_DCDMIM RT_BIT(2) /* DCD interrupt mask */
|
||||
#define PL011_CTSMIM RT_BIT(1) /* CTS interrupt mask */
|
||||
#define PL011_RIMIM RT_BIT(0) /* RI interrupt mask */
|
||||
|
||||
#define PL011_DR 0x000
|
||||
#define PL011_FR 0x018
|
||||
#define PL011_IBRD 0x024
|
||||
#define PL011_FBRD 0x028
|
||||
#define PL011_LCR 0x02c
|
||||
#define PL011_CR 0x030
|
||||
#define PL011_IMSC 0x038
|
||||
#define PL011_RIS 0x03c
|
||||
#define PL011_DMACR 0x048
|
||||
|
||||
#define PL011_LCRH_SPS (1 << 7)
|
||||
#define PL011_LCRH_WLEN_8 (3 << 5)
|
||||
#define PL011_LCRH_WLEN_7 (2 << 5)
|
||||
#define PL011_LCRH_WLEN_6 (1 << 5)
|
||||
#define PL011_LCRH_WLEN_5 (0 << 5)
|
||||
#define PL011_LCRH_FEN (1 << 4)
|
||||
#define PL011_LCRH_STP2 (1 << 3)
|
||||
#define PL011_LCRH_EPS (1 << 2)
|
||||
#define PL011_LCRH_PEN (1 << 1)
|
||||
#define PL011_LCRH_BRK (1 << 0)
|
||||
|
||||
#define PL011_LCRH_WLEN(n) ((n - 5) << 5)
|
||||
|
||||
#define PL011_CR_CTSEN RT_BIT(15)
|
||||
#define PL011_CR_RTSEN RT_BIT(14)
|
||||
#define PL011_CR_RTS RT_BIT(11)
|
||||
#define PL011_CR_DTR RT_BIT(10)
|
||||
#define PL011_CR_RXE RT_BIT(9)
|
||||
#define PL011_CR_TXE RT_BIT(8)
|
||||
#define PL011_CR_LBE RT_BIT(7)
|
||||
#define PL011_CR_SIRLP RT_BIT(2)
|
||||
#define PL011_CR_SIREN RT_BIT(1)
|
||||
#define PL011_CR_UARTEN RT_BIT(0)
|
||||
|
||||
struct pl011
|
||||
{
|
||||
struct rt_serial_device parent;
|
||||
|
||||
int irq;
|
||||
void *base;
|
||||
rt_ubase_t freq;
|
||||
struct rt_clk *clk;
|
||||
struct rt_clk *pclk;
|
||||
|
||||
struct rt_spinlock spinlock;
|
||||
};
|
||||
|
||||
#define raw_to_pl011(raw) rt_container_of(raw, struct pl011, parent)
|
||||
|
||||
rt_inline rt_uint32_t pl011_read(struct pl011 *pl011, int offset)
|
||||
{
|
||||
return HWREG32(pl011->base + offset);
|
||||
}
|
||||
|
||||
rt_inline void pl011_write(struct pl011 *pl011, int offset, rt_uint32_t value)
|
||||
{
|
||||
HWREG32(pl011->base + offset) = value;
|
||||
}
|
||||
|
||||
static void pl011_isr(int irqno, void *param)
|
||||
{
|
||||
struct pl011 *pl011 = param;
|
||||
|
||||
/* Check irq */
|
||||
if (pl011_read(pl011, PL011_RIS) & PL011_RXIM)
|
||||
{
|
||||
rt_base_t level = rt_spin_lock_irqsave(&pl011->spinlock);
|
||||
|
||||
rt_hw_serial_isr(&pl011->parent, RT_SERIAL_EVENT_RX_IND);
|
||||
|
||||
rt_spin_unlock_irqrestore(&pl011->spinlock, level);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t pl011_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
rt_ubase_t quot;
|
||||
struct pl011 *pl011 = raw_to_pl011(serial);
|
||||
|
||||
/* Clear UART setting */
|
||||
pl011_write(pl011, PL011_CR, 0);
|
||||
/* Disable FIFO */
|
||||
pl011_write(pl011, PL011_LCR, 0);
|
||||
|
||||
if (cfg->baud_rate > pl011->freq / 16)
|
||||
{
|
||||
quot = RT_DIV_ROUND_CLOSEST(pl011->freq * 8, cfg->baud_rate);
|
||||
}
|
||||
else
|
||||
{
|
||||
quot = RT_DIV_ROUND_CLOSEST(pl011->freq * 4, cfg->baud_rate);
|
||||
}
|
||||
|
||||
pl011_write(pl011, PL011_IBRD, quot >> 6);
|
||||
pl011_write(pl011, PL011_FBRD, quot & 0x3f);
|
||||
/* FIFO */
|
||||
pl011_write(pl011, PL011_LCR, PL011_LCRH_WLEN(cfg->data_bits));
|
||||
|
||||
/* Art enable, TX/RX enable */
|
||||
pl011_write(pl011, PL011_CR, PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t pl011_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct pl011 *pl011 = raw_to_pl011(serial);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* Disable rx irq */
|
||||
pl011_write(pl011, PL011_IMSC, pl011_read(pl011, PL011_IMSC) & ~PL011_RXIM);
|
||||
|
||||
rt_hw_interrupt_mask(pl011->irq);
|
||||
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* Enable rx irq */
|
||||
pl011_write(pl011, PL011_IMSC, pl011_read(pl011, PL011_IMSC) | PL011_RXIM);
|
||||
|
||||
rt_hw_interrupt_umask(pl011->irq);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int pl011_uart_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct pl011 *pl011 = raw_to_pl011(serial);
|
||||
|
||||
while (pl011_read(pl011, PL011_FR) & PL011_TXIM)
|
||||
{
|
||||
rt_hw_cpu_relax();
|
||||
}
|
||||
|
||||
pl011_write(pl011, PL011_DR, c);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int pl011_uart_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch = -1;
|
||||
struct pl011 *pl011 = raw_to_pl011(serial);
|
||||
|
||||
if (!(pl011_read(pl011, PL011_FR) & PL011_RXIM))
|
||||
{
|
||||
ch = pl011_read(pl011, PL011_DR);
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops pl011_uart_ops =
|
||||
{
|
||||
.configure = pl011_uart_configure,
|
||||
.control = pl011_uart_control,
|
||||
.putc = pl011_uart_putc,
|
||||
.getc = pl011_uart_getc,
|
||||
};
|
||||
|
||||
static void pl011_early_kick(struct rt_fdt_earlycon *con, int why)
|
||||
{
|
||||
struct pl011 *pl011 = raw_to_pl011(con->data);
|
||||
|
||||
switch (why)
|
||||
{
|
||||
case FDT_EARLYCON_KICK_UPDATE:
|
||||
pl011->base = rt_ioremap((void *)con->mmio, con->size);
|
||||
break;
|
||||
|
||||
case FDT_EARLYCON_KICK_COMPLETED:
|
||||
rt_iounmap(pl011->base);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t pl011_early_setup(struct rt_fdt_earlycon *con, const char *options)
|
||||
{
|
||||
rt_err_t err = RT_EOK;
|
||||
static struct pl011 pl011 = { };
|
||||
|
||||
if (options && !con->mmio)
|
||||
{
|
||||
char *arg;
|
||||
|
||||
con->mmio = RT_NULL;
|
||||
|
||||
/*
|
||||
* The pl011 serial port must already be setup and configured in early.
|
||||
* Options are not yet supported.
|
||||
* pl011,<addr>
|
||||
* pl011,mmio32,<addr>
|
||||
*/
|
||||
serial_for_each_args(arg, options)
|
||||
{
|
||||
if (!rt_strcmp(arg, "pl011") || !rt_strcmp(arg, "mmio32"))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
if (!con->mmio)
|
||||
{
|
||||
con->mmio = (rt_ubase_t)serial_base_from_args(arg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!con->size)
|
||||
{
|
||||
con->size = 0x1000;
|
||||
}
|
||||
|
||||
if (con->mmio)
|
||||
{
|
||||
pl011.base = rt_ioremap_early((void *)con->mmio, con->size);
|
||||
}
|
||||
|
||||
if (pl011.base)
|
||||
{
|
||||
con->console_putc = (typeof(con->console_putc))&pl011_uart_putc;
|
||||
con->console_kick = pl011_early_kick;
|
||||
con->data = &pl011.parent;
|
||||
pl011.parent.config = (typeof(pl011.parent.config))RT_SERIAL_CONFIG_DEFAULT;
|
||||
}
|
||||
else
|
||||
{
|
||||
err = -RT_ERROR;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
RT_FDT_EARLYCON_EXPORT(pl011, "pl011", "arm,pl011", pl011_early_setup);
|
||||
|
||||
static void pl011_free(struct pl011 *pl011)
|
||||
{
|
||||
if (pl011->base)
|
||||
{
|
||||
rt_iounmap(pl011->base);
|
||||
}
|
||||
|
||||
/* if (!rt_is_err_or_null(pl011->clk))*/
|
||||
/* {*/
|
||||
/* rt_clk_disable(pl011->clk);*/
|
||||
/* rt_clk_put(pl011->clk);*/
|
||||
/* }*/
|
||||
|
||||
/* if (!rt_is_err_or_null(pl011->pclk))*/
|
||||
/* {*/
|
||||
/* rt_clk_disable_unprepare(pl011->pclk);*/
|
||||
/* rt_clk_put(pl011->pclk);*/
|
||||
/* }*/
|
||||
|
||||
rt_free(pl011);
|
||||
}
|
||||
|
||||
static rt_err_t pl011_probe(struct rt_platform_device *pdev)
|
||||
{
|
||||
rt_err_t err;
|
||||
const char *name;
|
||||
char isr_name[RT_NAME_MAX];
|
||||
struct rt_device *dev = &pdev->parent;
|
||||
struct pl011 *pl011 = rt_calloc(1, sizeof(*pl011));
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
if (!pl011)
|
||||
{
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
pl011->base = rt_dm_dev_iomap(dev, 0);
|
||||
|
||||
if (!pl011->base)
|
||||
{
|
||||
err = -RT_EIO;
|
||||
|
||||
goto _fail;
|
||||
}
|
||||
|
||||
pl011->irq = rt_dm_dev_get_irq(dev, 0);
|
||||
|
||||
if (pl011->irq < 0)
|
||||
{
|
||||
err = pl011->irq;
|
||||
|
||||
goto _fail;
|
||||
}
|
||||
|
||||
/* pl011->clk = rt_clk_get_by_index(dev, 0);*/
|
||||
|
||||
/* if (rt_is_err(pl011->clk))*/
|
||||
/* {*/
|
||||
/* err = rt_ptr_err(pl011->clk);*/
|
||||
|
||||
/* goto _fail;*/
|
||||
/* }*/
|
||||
|
||||
/* pl011->pclk = rt_clk_get_by_name(dev, "apb_pclk");*/
|
||||
|
||||
/* if (rt_is_err(pl011->pclk))*/
|
||||
/* {*/
|
||||
/* err = rt_ptr_err(pl011->pclk);*/
|
||||
|
||||
/* goto _fail;*/
|
||||
/* }*/
|
||||
|
||||
/* if ((err = rt_clk_prepare_enable(pl011->pclk)))*/
|
||||
/* {*/
|
||||
/* goto _fail;*/
|
||||
/* }*/
|
||||
|
||||
rt_dm_dev_bind_fwdata(&pl011->parent.parent, dev->ofw_node, &pl011->parent);
|
||||
|
||||
/* rt_clk_enable(pl011->clk);*/
|
||||
/* pl011->freq = rt_clk_get_rate(pl011->clk);*/
|
||||
|
||||
dev->user_data = pl011;
|
||||
|
||||
pl011->parent.ops = &pl011_uart_ops;
|
||||
pl011->parent.config = config;
|
||||
|
||||
rt_spin_lock_init(&pl011->spinlock);
|
||||
|
||||
serial_dev_set_name(&pl011->parent);
|
||||
name = rt_dm_dev_get_name(&pl011->parent.parent);
|
||||
|
||||
rt_hw_serial_register(&pl011->parent, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, pl011);
|
||||
rt_snprintf(isr_name, RT_NAME_MAX, "%s-pl011", name);
|
||||
rt_hw_interrupt_install(pl011->irq, pl011_isr, pl011, isr_name);
|
||||
|
||||
return RT_EOK;
|
||||
|
||||
_fail:
|
||||
pl011_free(pl011);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static rt_err_t pl011_remove(struct rt_platform_device *pdev)
|
||||
{
|
||||
struct rt_device *dev = &pdev->parent;
|
||||
struct pl011 *pl011 = dev->user_data;
|
||||
|
||||
rt_dm_dev_unbind_fwdata(dev, RT_NULL);
|
||||
|
||||
rt_hw_interrupt_mask(pl011->irq);
|
||||
rt_pic_detach_irq(pl011->irq, pl011);
|
||||
|
||||
rt_device_unregister(&pl011->parent.parent);
|
||||
|
||||
pl011_free(pl011);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_ofw_node_id pl011_ofw_ids[] =
|
||||
{
|
||||
{ .type = "ttyAMA", .compatible = "arm,pl011" },
|
||||
{ .type = "ttyAMA", .compatible = "arm,pl011-axi" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct rt_platform_driver pl011_driver =
|
||||
{
|
||||
.name = "serial-pl011",
|
||||
.ids = pl011_ofw_ids,
|
||||
|
||||
.probe = pl011_probe,
|
||||
.remove = pl011_remove,
|
||||
};
|
||||
|
||||
static int pl011_drv_register(void)
|
||||
{
|
||||
rt_platform_driver_register(&pl011_driver);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_DRIVER_EARLY_EXPORT(pl011_drv_register);
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_UART_H__
|
||||
#define DRV_UART_H__
|
||||
|
||||
/* register's bit*/
|
||||
#define PL011_FR_RI (1 << 8)
|
||||
#define PL011_FR_TXFE (1 << 7)
|
||||
#define PL011_FR_RXFF (1 << 6)
|
||||
#define PL011_FR_TXFF (1 << 5)
|
||||
#define PL011_FR_RXFE (1 << 4)
|
||||
#define PL011_FR_BUSY (1 << 3)
|
||||
#define PL011_FR_DCD (1 << 2)
|
||||
#define PL011_FR_DSR (1 << 1)
|
||||
#define PL011_FR_CTS (1 << 0)
|
||||
|
||||
#define PL011_LCRH_SPS (1 << 7)
|
||||
#define PL011_LCRH_WLEN_8 (3 << 5)
|
||||
#define PL011_LCRH_WLEN_7 (2 << 5)
|
||||
#define PL011_LCRH_WLEN_6 (1 << 5)
|
||||
#define PL011_LCRH_WLEN_5 (0 << 5)
|
||||
#define PL011_LCRH_FEN (1 << 4)
|
||||
#define PL011_LCRH_STP2 (1 << 3)
|
||||
#define PL011_LCRH_EPS (1 << 2)
|
||||
#define PL011_LCRH_PEN (1 << 1)
|
||||
#define PL011_LCRH_BRK (1 << 0)
|
||||
|
||||
#define PL011_CR_CTSEN (1 << 15)
|
||||
#define PL011_CR_RTSEN (1 << 14)
|
||||
#define PL011_CR_RTS (1 << 11)
|
||||
#define PL011_CR_DTR (1 << 10)
|
||||
#define PL011_CR_RXE (1 << 9)
|
||||
#define PL011_CR_TXE (1 << 8)
|
||||
#define PL011_CR_LBE (1 << 7)
|
||||
#define PL011_CR_SIRLP (1 << 2)
|
||||
#define PL011_CR_SIREN (1 << 1)
|
||||
#define PL011_CR_UARTEN (1 << 0)
|
||||
|
||||
#define PL011_IMSC_TXIM (1 << 5)
|
||||
#define PL011_IMSC_RXIM (1 << 4)
|
||||
|
||||
#define PL011_INTERRUPT_OVERRUN_ERROR (1 << 10)
|
||||
#define PL011_INTERRUPT_BREAK_ERROR (1 << 9)
|
||||
#define PL011_INTERRUPT_PARITY_ERROR (1 << 8)
|
||||
#define PL011_INTERRUPT_FRAMING_ERROR (1 << 7)
|
||||
#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
|
||||
#define PL011_INTERRUPT_TRANSMIT (1 << 5)
|
||||
#define PL011_INTERRUPT_RECEIVE (1 << 4)
|
||||
#define PL011_INTERRUPT_nUARTCTS (1 << 1)
|
||||
|
||||
#define PL011_REG_DR(BASE) HWREG32(BASE + 0x00)
|
||||
#define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04)
|
||||
#define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08)
|
||||
#define PL011_REG_FR(BASE) HWREG32(BASE + 0x18)
|
||||
#define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C)
|
||||
#define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20)
|
||||
#define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24)
|
||||
#define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28)
|
||||
#define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C)
|
||||
#define PL011_REG_CR(BASE) HWREG32(BASE + 0x30)
|
||||
#define PL011_REG_IFLS(BASE) HWREG32(BASE + 0x34)
|
||||
#define PL011_REG_IMSC(BASE) HWREG32(BASE + 0x38)
|
||||
#define PL011_REG_RIS(BASE) HWREG32(BASE + 0x3C)
|
||||
#define PL011_REG_MIS(BASE) HWREG32(BASE + 0x40)
|
||||
#define PL011_REG_ICR(BASE) HWREG32(BASE + 0x44)
|
||||
#define PL011_REG_DMACR(BASE) HWREG32(BASE + 0x48)
|
||||
#define PL011_REG_RESERVED2(BASE) HWREG32(BASE + 0x4C)
|
||||
#define PL011_REG_ITCR(BASE) HWREG32(BASE + 0x80)
|
||||
#define PL011_REG_ITIP(BASE) HWREG32(BASE + 0x84)
|
||||
#define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88)
|
||||
#define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C)
|
||||
|
||||
/*
|
||||
* Auxiliary
|
||||
*/
|
||||
#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */
|
||||
#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */
|
||||
#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */
|
||||
#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */
|
||||
#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */
|
||||
#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */
|
||||
#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */
|
||||
#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */
|
||||
#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */
|
||||
#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */
|
||||
#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */
|
||||
#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */
|
||||
#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */
|
||||
#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */
|
||||
#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */
|
||||
#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */
|
||||
#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */
|
||||
#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */
|
||||
#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */
|
||||
#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
void rt_hw_earlycon_ioremap_early(void);
|
||||
|
||||
#endif /* DRV_UART_H__ */
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
menuconfig RT_USING_SDHCI
|
||||
bool "Using sdhci for sd/mmc drivers"
|
||||
default n
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
from building import *
|
||||
|
||||
group = []
|
||||
|
||||
if not GetDepend(['RT_USING_SDHCI']):
|
||||
Return('group')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd + '/include']
|
||||
|
||||
src = []
|
||||
src += Glob('*.c')
|
||||
src += Glob('src/*.c')
|
||||
src += Glob('sdhci-platform/*.c')
|
||||
|
||||
group = DefineGroup('sdhci-drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
|
||||
#define _DRIVERS_MMC_SDHCI_PLTFM_H
|
||||
#include <rtthread.h>
|
||||
#include <drivers/core/dm.h>
|
||||
#include <drivers/ofw.h>
|
||||
#include <drivers/platform.h>
|
||||
#include <drivers/clk.h>
|
||||
#include "sdhci.h"
|
||||
|
||||
struct sdhci_pltfm_data
|
||||
{
|
||||
const struct sdhci_ops *ops;
|
||||
unsigned int quirks;
|
||||
unsigned int quirks2;
|
||||
};
|
||||
|
||||
struct sdhci_pltfm_host
|
||||
{
|
||||
struct rt_clk *clk;
|
||||
|
||||
/* migrate from sdhci_of_host */
|
||||
unsigned int clock;
|
||||
rt_uint64_t xfer_mode_shadow;
|
||||
|
||||
unsigned long private[];
|
||||
};
|
||||
|
||||
void sdhci_get_property(struct rt_platform_device *pdev);
|
||||
|
||||
static inline void sdhci_get_of_property(struct rt_platform_device *pdev)
|
||||
{
|
||||
return sdhci_get_property(pdev);
|
||||
}
|
||||
|
||||
|
||||
extern struct sdhci_host *sdhci_pltfm_init(struct rt_platform_device *pdev,
|
||||
const struct sdhci_pltfm_data *pdata,
|
||||
size_t priv_size);
|
||||
extern void sdhci_pltfm_free(struct rt_platform_device *pdev);
|
||||
|
||||
extern int sdhci_pltfm_init_and_add_host(struct rt_platform_device *pdev,
|
||||
const struct sdhci_pltfm_data *pdata,
|
||||
size_t priv_size);
|
||||
extern void sdhci_pltfm_remove(struct rt_platform_device *pdev);
|
||||
|
||||
extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
|
||||
|
||||
static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
|
||||
{
|
||||
return host->private;
|
||||
}
|
||||
|
||||
extern const struct dev_pm_ops sdhci_pltfm_pmops;
|
||||
static inline int sdhci_pltfm_suspend(struct rt_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int sdhci_pltfm_resume(struct rt_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,815 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#ifndef __SDHCI_HW_H
|
||||
#define __SDHCI_HW_H
|
||||
|
||||
#include "sdhci_host.h"
|
||||
#include "sdhci_misc.h"
|
||||
#include "sdhci_dma.h"
|
||||
#include "sdhci-platform.h"
|
||||
#include <drivers/mmcsd_cmd.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
#include <rtdevice.h>
|
||||
/*
|
||||
* Controller registers
|
||||
*/
|
||||
#define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff))
|
||||
#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16))
|
||||
|
||||
#define MAX_TUNING_LOOP 40
|
||||
|
||||
#define SDHCI_DMA_ADDRESS 0x00
|
||||
#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
|
||||
#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
|
||||
|
||||
#define SDHCI_BLOCK_SIZE 0x04
|
||||
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
|
||||
|
||||
#define SDHCI_BLOCK_COUNT 0x06
|
||||
|
||||
#define SDHCI_ARGUMENT 0x08
|
||||
|
||||
#define SDHCI_TRANSFER_MODE 0x0C
|
||||
#define SDHCI_TRNS_DMA 0x01
|
||||
#define SDHCI_TRNS_BLK_CNT_EN 0x02
|
||||
#define SDHCI_TRNS_AUTO_CMD12 0x04
|
||||
#define SDHCI_TRNS_AUTO_CMD23 0x08
|
||||
#define SDHCI_TRNS_AUTO_SEL 0x0C
|
||||
#define SDHCI_TRNS_READ 0x10
|
||||
#define SDHCI_TRNS_MULTI 0x20
|
||||
|
||||
#define SDHCI_COMMAND 0x0E
|
||||
#define SDHCI_CMD_RESP_MASK 0x03
|
||||
#define SDHCI_CMD_CRC 0x08
|
||||
#define SDHCI_CMD_INDEX 0x10
|
||||
#define SDHCI_CMD_DATA 0x20
|
||||
#define SDHCI_CMD_ABORTCMD 0xC0
|
||||
|
||||
#define SDHCI_CMD_RESP_NONE 0x00
|
||||
#define SDHCI_CMD_RESP_LONG 0x01
|
||||
#define SDHCI_CMD_RESP_SHORT 0x02
|
||||
#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
|
||||
|
||||
#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
|
||||
#define SDHCI_GET_CMD(c) ((c >> 8) & 0x3f)
|
||||
|
||||
#define SDHCI_RESPONSE 0x10
|
||||
|
||||
#define SDHCI_BUFFER 0x20
|
||||
|
||||
#define SDHCI_PRESENT_STATE 0x24
|
||||
#define SDHCI_CMD_INHIBIT 0x00000001
|
||||
#define SDHCI_DATA_INHIBIT 0x00000002
|
||||
#define SDHCI_DOING_WRITE 0x00000100
|
||||
#define SDHCI_DOING_READ 0x00000200
|
||||
#define SDHCI_SPACE_AVAILABLE 0x00000400
|
||||
#define SDHCI_DATA_AVAILABLE 0x00000800
|
||||
#define SDHCI_CARD_PRESENT 0x00010000
|
||||
#define SDHCI_CARD_PRES_SHIFT 16
|
||||
#define SDHCI_CD_STABLE 0x00020000
|
||||
#define SDHCI_CD_LVL 0x00040000
|
||||
#define SDHCI_CD_LVL_SHIFT 18
|
||||
#define SDHCI_WRITE_PROTECT 0x00080000
|
||||
#define SDHCI_DATA_LVL_MASK 0x00F00000
|
||||
#define SDHCI_DATA_LVL_SHIFT 20
|
||||
#define SDHCI_DATA_0_LVL_MASK 0x00100000
|
||||
#define SDHCI_CMD_LVL 0x01000000
|
||||
|
||||
#define SDHCI_HOST_CONTROL 0x28
|
||||
#define SDHCI_CTRL_LED 0x01
|
||||
#define SDHCI_CTRL_4BITBUS 0x02
|
||||
#define SDHCI_CTRL_HISPD 0x04
|
||||
#define SDHCI_CTRL_DMA_MASK 0x18
|
||||
#define SDHCI_CTRL_SDMA 0x00
|
||||
#define SDHCI_CTRL_ADMA1 0x08
|
||||
#define SDHCI_CTRL_ADMA32 0x10
|
||||
#define SDHCI_CTRL_ADMA64 0x18
|
||||
#define SDHCI_CTRL_ADMA3 0x18
|
||||
#define SDHCI_CTRL_8BITBUS 0x20
|
||||
#define SDHCI_CTRL_CDTEST_INS 0x40
|
||||
#define SDHCI_CTRL_CDTEST_EN 0x80
|
||||
|
||||
#define SDHCI_POWER_CONTROL 0x29
|
||||
#define SDHCI_POWER_ON 0x01
|
||||
#define SDHCI_POWER_180 0x0A
|
||||
#define SDHCI_POWER_300 0x0C
|
||||
#define SDHCI_POWER_330 0x0E
|
||||
/*
|
||||
* VDD2 - UHS2 or PCIe/NVMe
|
||||
* VDD2 power on/off and voltage select
|
||||
*/
|
||||
#define SDHCI_VDD2_POWER_ON 0x10
|
||||
#define SDHCI_VDD2_POWER_120 0x80
|
||||
#define SDHCI_VDD2_POWER_180 0xA0
|
||||
|
||||
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
|
||||
|
||||
#define SDHCI_WAKE_UP_CONTROL 0x2B
|
||||
#define SDHCI_WAKE_ON_INT 0x01
|
||||
#define SDHCI_WAKE_ON_INSERT 0x02
|
||||
#define SDHCI_WAKE_ON_REMOVE 0x04
|
||||
|
||||
#define SDHCI_CLOCK_CONTROL 0x2C
|
||||
#define SDHCI_DIVIDER_SHIFT 8
|
||||
#define SDHCI_DIVIDER_HI_SHIFT 6
|
||||
#define SDHCI_DIV_MASK 0xFF
|
||||
#define SDHCI_DIV_MASK_LEN 8
|
||||
#define SDHCI_DIV_HI_MASK 0x300
|
||||
#define SDHCI_PROG_CLOCK_MODE 0x0020
|
||||
#define SDHCI_CLOCK_CARD_EN 0x0004
|
||||
#define SDHCI_CLOCK_PLL_EN 0x0008
|
||||
#define SDHCI_CLOCK_INT_STABLE 0x0002
|
||||
#define SDHCI_CLOCK_INT_EN 0x0001
|
||||
|
||||
#define SDHCI_TIMEOUT_CONTROL 0x2E
|
||||
|
||||
#define SDHCI_SOFTWARE_RESET 0x2F
|
||||
#define SDHCI_RESET_ALL 0x01
|
||||
#define SDHCI_RESET_CMD 0x02
|
||||
#define SDHCI_RESET_DATA 0x04
|
||||
|
||||
#define SDHCI_INT_STATUS 0x30
|
||||
#define SDHCI_INT_ENABLE 0x34
|
||||
#define SDHCI_SIGNAL_ENABLE 0x38
|
||||
#define SDHCI_INT_RESPONSE 0x00000001
|
||||
#define SDHCI_INT_DATA_END 0x00000002
|
||||
#define SDHCI_INT_BLK_GAP 0x00000004
|
||||
#define SDHCI_INT_DMA_END 0x00000008
|
||||
#define SDHCI_INT_SPACE_AVAIL 0x00000010
|
||||
#define SDHCI_INT_DATA_AVAIL 0x00000020
|
||||
#define SDHCI_INT_CARD_INSERT 0x00000040
|
||||
#define SDHCI_INT_CARD_REMOVE 0x00000080
|
||||
#define SDHCI_INT_CARD_INT 0x00000100
|
||||
#define SDHCI_INT_RETUNE 0x00001000
|
||||
#define SDHCI_INT_CQE 0x00004000
|
||||
#define SDHCI_INT_ERROR 0x00008000
|
||||
#define SDHCI_INT_TIMEOUT 0x00010000
|
||||
#define SDHCI_INT_CRC 0x00020000
|
||||
#define SDHCI_INT_END_BIT 0x00040000
|
||||
#define SDHCI_INT_INDEX 0x00080000
|
||||
#define SDHCI_INT_DATA_TIMEOUT 0x00100000
|
||||
#define SDHCI_INT_DATA_CRC 0x00200000
|
||||
#define SDHCI_INT_DATA_END_BIT 0x00400000
|
||||
#define SDHCI_INT_BUS_POWER 0x00800000
|
||||
#define SDHCI_INT_AUTO_CMD_ERR 0x01000000
|
||||
#define SDHCI_INT_ADMA_ERROR 0x02000000
|
||||
|
||||
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
|
||||
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
|
||||
|
||||
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | SDHCI_INT_AUTO_CMD_ERR)
|
||||
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BLK_GAP)
|
||||
#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
|
||||
|
||||
#define SDHCI_CQE_INT_ERR_MASK ( \
|
||||
SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
|
||||
|
||||
#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
|
||||
|
||||
#define SDHCI_AUTO_CMD_STATUS 0x3C
|
||||
#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
|
||||
#define SDHCI_AUTO_CMD_CRC 0x00000004
|
||||
#define SDHCI_AUTO_CMD_END_BIT 0x00000008
|
||||
#define SDHCI_AUTO_CMD_INDEX 0x00000010
|
||||
|
||||
#define SDHCI_HOST_CONTROL2 0x3E
|
||||
#define SDHCI_CTRL_UHS_MASK 0x0007
|
||||
#define SDHCI_CTRL_UHS_SDR12 0x0000
|
||||
#define SDHCI_CTRL_UHS_SDR25 0x0001
|
||||
#define SDHCI_CTRL_UHS_SDR50 0x0002
|
||||
#define SDHCI_CTRL_UHS_SDR104 0x0003
|
||||
#define SDHCI_CTRL_UHS_DDR50 0x0004
|
||||
#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
|
||||
#define SDHCI_CTRL_VDD_180 0x0008
|
||||
#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
|
||||
#define SDHCI_CTRL_DRV_TYPE_B 0x0000
|
||||
#define SDHCI_CTRL_DRV_TYPE_A 0x0010
|
||||
#define SDHCI_CTRL_DRV_TYPE_C 0x0020
|
||||
#define SDHCI_CTRL_DRV_TYPE_D 0x0030
|
||||
#define SDHCI_CTRL_EXEC_TUNING 0x0040
|
||||
#define SDHCI_CTRL_TUNED_CLK 0x0080
|
||||
#define SDHCI_CMD23_ENABLE 0x0800
|
||||
#define SDHCI_CTRL_V4_MODE 0x1000
|
||||
#define SDHCI_CTRL_64BIT_ADDR 0x2000
|
||||
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
|
||||
|
||||
#define SDHCI_CAPABILITIES 0x40
|
||||
#define SDHCI_TIMEOUT_CLK_MASK RT_GENMASK(5, 0)
|
||||
#define SDHCI_TIMEOUT_CLK_SHIFT 0
|
||||
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
|
||||
#define SDHCI_CLOCK_BASE_MASK RT_GENMASK(13, 8)
|
||||
#define SDHCI_CLOCK_BASE_SHIFT 8
|
||||
#define SDHCI_CLOCK_V3_BASE_MASK RT_GENMASK(15, 8)
|
||||
#define SDHCI_MAX_BLOCK_MASK 0x00030000
|
||||
#define SDHCI_MAX_BLOCK_SHIFT 16
|
||||
#define SDHCI_CAN_DO_8BIT 0x00040000
|
||||
#define SDHCI_CAN_DO_ADMA2 0x00080000
|
||||
#define SDHCI_CAN_DO_ADMA1 0x00100000
|
||||
#define SDHCI_CAN_DO_HISPD 0x00200000
|
||||
#define SDHCI_CAN_DO_SDMA 0x00400000
|
||||
#define SDHCI_CAN_DO_SUSPEND 0x00800000
|
||||
#define SDHCI_CAN_VDD_330 0x01000000
|
||||
#define SDHCI_CAN_VDD_300 0x02000000
|
||||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
#define SDHCI_CAN_64BIT_V4 0x08000000
|
||||
#define SDHCI_CAN_64BIT 0x10000000
|
||||
|
||||
#define SDHCI_CAPABILITIES_1 0x44
|
||||
#define SDHCI_SUPPORT_SDR50 0x00000001
|
||||
#define SDHCI_SUPPORT_SDR104 0x00000002
|
||||
#define SDHCI_SUPPORT_DDR50 0x00000004
|
||||
#define SDHCI_DRIVER_TYPE_A 0x00000010
|
||||
#define SDHCI_DRIVER_TYPE_C 0x00000020
|
||||
#define SDHCI_DRIVER_TYPE_D 0x00000040
|
||||
#define SDHCI_RETUNING_TIMER_COUNT_MASK RT_GENMASK(11, 8)
|
||||
#define SDHCI_USE_SDR50_TUNING 0x00002000
|
||||
#define SDHCI_RETUNING_MODE_MASK RT_GENMASK(15, 14)
|
||||
#define SDHCI_CLOCK_MUL_MASK RT_GENMASK(23, 16)
|
||||
#define SDHCI_CAN_DO_ADMA3 0x08000000
|
||||
#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
|
||||
|
||||
#define SDHCI_MAX_CURRENT 0x48
|
||||
#define SDHCI_MAX_CURRENT_LIMIT RT_GENMASK(7, 0)
|
||||
#define SDHCI_MAX_CURRENT_330_MASK RT_GENMASK(7, 0)
|
||||
#define SDHCI_MAX_CURRENT_300_MASK RT_GENMASK(15, 8)
|
||||
#define SDHCI_MAX_CURRENT_180_MASK RT_GENMASK(23, 16)
|
||||
#define SDHCI_MAX_CURRENT_MULTIPLIER 4
|
||||
|
||||
/* 4C-4F reserved for more max current */
|
||||
|
||||
#define SDHCI_SET_ACMD12_ERROR 0x50
|
||||
#define SDHCI_SET_INT_ERROR 0x52
|
||||
|
||||
#define SDHCI_ADMA_ERROR 0x54
|
||||
|
||||
/* 55-57 reserved */
|
||||
|
||||
#define SDHCI_ADMA_ADDRESS 0x58
|
||||
#define SDHCI_ADMA_ADDRESS_HI 0x5C
|
||||
|
||||
/* 60-FB reserved */
|
||||
|
||||
#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
|
||||
#define SDHCI_PRESET_FOR_SDR12 0x66
|
||||
#define SDHCI_PRESET_FOR_SDR25 0x68
|
||||
#define SDHCI_PRESET_FOR_SDR50 0x6A
|
||||
#define SDHCI_PRESET_FOR_SDR104 0x6C
|
||||
#define SDHCI_PRESET_FOR_DDR50 0x6E
|
||||
#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
|
||||
#define SDHCI_PRESET_DRV_MASK RT_GENMASK(15, 14)
|
||||
#define BIT(nr) ((1) << (nr))
|
||||
|
||||
#define SDHCI_PRESET_CLKGEN_SEL BIT(10)
|
||||
#define SDHCI_PRESET_SDCLK_FREQ_MASK RT_GENMASK(9, 0)
|
||||
|
||||
#define SDHCI_SLOT_INT_STATUS 0xFC
|
||||
|
||||
#define SDHCI_HOST_VERSION 0xFE
|
||||
#define SDHCI_VENDOR_VER_MASK 0xFF00
|
||||
#define SDHCI_VENDOR_VER_SHIFT 8
|
||||
#define SDHCI_SPEC_VER_MASK 0x00FF
|
||||
#define SDHCI_SPEC_VER_SHIFT 0
|
||||
#define SDHCI_SPEC_100 0
|
||||
#define SDHCI_SPEC_200 1
|
||||
#define SDHCI_SPEC_300 2
|
||||
#define SDHCI_SPEC_400 3
|
||||
#define SDHCI_SPEC_410 4
|
||||
#define SDHCI_SPEC_420 5
|
||||
|
||||
/*
|
||||
* End of controller registers.
|
||||
*/
|
||||
|
||||
#define SDHCI_MAX_DIV_SPEC_200 256
|
||||
#define SDHCI_MAX_DIV_SPEC_300 2046
|
||||
|
||||
/*
|
||||
* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
|
||||
*/
|
||||
#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
|
||||
#define ilog2(v) __rt_ffs(v)
|
||||
#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
|
||||
|
||||
/* ADMA2 32-bit DMA descriptor size */
|
||||
#define SDHCI_ADMA2_32_DESC_SZ 8
|
||||
|
||||
/* ADMA2 32-bit descriptor */
|
||||
struct sdhci_adma2_32_desc
|
||||
{
|
||||
rt_uint16_t cmd;
|
||||
rt_uint16_t len;
|
||||
rt_uint16_t addr;
|
||||
} rt_align(4);
|
||||
/* ADMA2 data alignment */
|
||||
#define SDHCI_ADMA2_ALIGN 4
|
||||
#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
|
||||
|
||||
/*
|
||||
* ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
|
||||
* alignment for the descriptor table even in 32-bit DMA mode. Memory
|
||||
* allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
|
||||
*/
|
||||
#define SDHCI_ADMA2_DESC_ALIGN 8
|
||||
|
||||
/*
|
||||
* ADMA2 64-bit DMA descriptor size
|
||||
* According to SD Host Controller spec v4.10, there are two kinds of
|
||||
* descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
|
||||
* Descriptor, if Host Version 4 Enable is set in the Host Control 2
|
||||
* register, 128-bit Descriptor will be selected.
|
||||
*/
|
||||
#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
|
||||
|
||||
/*
|
||||
* ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
|
||||
* aligned.
|
||||
*/
|
||||
struct sdhci_adma2_64_desc
|
||||
{
|
||||
rt_uint16_t cmd;
|
||||
rt_uint16_t len;
|
||||
rt_uint16_t addr_lo;
|
||||
rt_uint16_t addr_hi;
|
||||
};
|
||||
|
||||
#define ADMA2_TRAN_VALID 0x21
|
||||
#define ADMA2_NOP_END_VALID 0x3
|
||||
#define ADMA2_END 0x2
|
||||
|
||||
/*
|
||||
* Maximum segments assuming a 512KiB maximum requisition size and a minimum
|
||||
* 4KiB page size. Note this also allows enough for multiple descriptors in
|
||||
* case of PAGE_SIZE >= 64KiB.
|
||||
*/
|
||||
#define SDHCI_MAX_SEGS 128
|
||||
|
||||
/* Allow for a command request and a data request at the same time */
|
||||
#define SDHCI_MAX_MRQS 2
|
||||
|
||||
/*
|
||||
* 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
|
||||
* However since the start time of the command, the time between
|
||||
* command and response, and the time between response and start of data is
|
||||
* not known, set the command transfer time to 10ms.
|
||||
*/
|
||||
#define MMC_CMD_TRANSFER_TIME (10 * 1000000L) /* max 10 ms */
|
||||
|
||||
|
||||
enum sdhci_cookie
|
||||
{
|
||||
COOKIE_UNMAPPED,
|
||||
COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
|
||||
COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
|
||||
};
|
||||
|
||||
struct sdhci_host
|
||||
{
|
||||
/* Data set by hardware interface driver */
|
||||
const char *hw_name; /* Hardware bus name */
|
||||
|
||||
unsigned int quirks; /* Deviations from spec. */
|
||||
|
||||
void *data_buf;
|
||||
/* Controller doesn't honor resets unless we touch the clock register */
|
||||
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
|
||||
/* Controller has bad caps bits, but really supports DMA */
|
||||
#define SDHCI_QUIRK_FORCE_DMA (1 << 1)
|
||||
/* Controller doesn't like to be reset when there is no card inserted. */
|
||||
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 2)
|
||||
/* Controller doesn't like clearing the power reg before a change */
|
||||
#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1 << 3)
|
||||
/* Controller has an unusable DMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_DMA (1 << 5)
|
||||
/* Controller has an unusable ADMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_ADMA (1 << 6)
|
||||
/* Controller can only DMA from 32-bit aligned addresses */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 7)
|
||||
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 8)
|
||||
/* Controller can only ADMA chunks that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9)
|
||||
/* Controller needs to be reset after each request to stay stable */
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10)
|
||||
/* Controller needs voltage and power writes to happen separately */
|
||||
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11)
|
||||
/* Controller provides an incorrect timeout value for transfers */
|
||||
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 12)
|
||||
/* Controller has an issue with buffer bits for small transfers */
|
||||
#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1 << 13)
|
||||
/* Controller does not provide transfer-complete interrupt when not busy */
|
||||
#define SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14)
|
||||
/* Controller has unreliable card detection */
|
||||
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 15)
|
||||
/* Controller reports inverted write-protect state */
|
||||
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1 << 16)
|
||||
/* Controller has unusable command queue engine */
|
||||
#define SDHCI_QUIRK_BROKEN_CQE (1 << 17)
|
||||
/* Controller does not like fast PIO transfers */
|
||||
#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18)
|
||||
/* Controller does not have a LED */
|
||||
#define SDHCI_QUIRK_NO_LED (1 << 19)
|
||||
/* Controller has to be forced to use block size of 2048 bytes */
|
||||
#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1 << 20)
|
||||
/* Controller cannot do multi-block transfers */
|
||||
#define SDHCI_QUIRK_NO_MULTIBLOCK (1 << 21)
|
||||
/* Controller can only handle 1-bit data transfers */
|
||||
#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1 << 22)
|
||||
/* Controller needs 10ms delay between applying power and clock */
|
||||
#define SDHCI_QUIRK_DELAY_AFTER_POWER (1 << 23)
|
||||
/* Controller uses SDCLK instead of TMCLK for data timeouts */
|
||||
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)
|
||||
/* Controller reports wrong base clock capability */
|
||||
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 25)
|
||||
/* Controller cannot support End Attribute in NOP ADMA descriptor */
|
||||
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1 << 26)
|
||||
/* Controller uses Auto CMD12 command to stop the transfer */
|
||||
#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1 << 28)
|
||||
/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
|
||||
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 29)
|
||||
/* Controller treats ADMA descriptors with length 0000h incorrectly */
|
||||
#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1 << 30)
|
||||
/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
|
||||
#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1 << 31)
|
||||
|
||||
unsigned int quirks2; /* More deviations from spec. */
|
||||
|
||||
#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1 << 0)
|
||||
#define SDHCI_QUIRK2_HOST_NO_CMD23 (1 << 1)
|
||||
/* The system physically doesn't support 1.8v, even if the host does */
|
||||
#define SDHCI_QUIRK2_NO_1_8_V (1 << 2)
|
||||
#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1 << 3)
|
||||
#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1 << 4)
|
||||
/* Controller has a non-standard host control register */
|
||||
#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1 << 5)
|
||||
/* Controller does not support HS200 */
|
||||
#define SDHCI_QUIRK2_BROKEN_HS200 (1 << 6)
|
||||
/* Controller does not support DDR50 */
|
||||
#define SDHCI_QUIRK2_BROKEN_DDR50 (1 << 7)
|
||||
/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
|
||||
#define SDHCI_QUIRK2_STOP_WITH_TC (1 << 8)
|
||||
/* Controller does not support 64-bit DMA */
|
||||
#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1 << 9)
|
||||
/* need clear transfer mode register before send cmd */
|
||||
#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1 << 10)
|
||||
/* Capability register bit-63 indicates HS400 support */
|
||||
#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1 << 11)
|
||||
/* forced tuned clock */
|
||||
#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12)
|
||||
/* disable the block count for single block transactions */
|
||||
#define SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13)
|
||||
/* Controller broken with using ACMD23 */
|
||||
#define SDHCI_QUIRK2_ACMD23_BROKEN (1 << 14)
|
||||
/* Broken Clock divider zero in controller */
|
||||
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1 << 15)
|
||||
/* Controller has CRC in 136 bit Command Response */
|
||||
#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1 << 16)
|
||||
/*
|
||||
* Disable HW timeout if the requested timeout is more than the maximum
|
||||
* obtainable timeout.
|
||||
*/
|
||||
#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17)
|
||||
/*
|
||||
* 32-bit block count may not support eMMC where upper bits of CMD23 are used
|
||||
* for other purposes. Consequently we support 16-bit block count by default.
|
||||
* Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
|
||||
* block count.
|
||||
*/
|
||||
#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1 << 18)
|
||||
/* Issue CMD and DATA reset together */
|
||||
#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1 << 19)
|
||||
|
||||
int irq; /* Device IRQ */
|
||||
void *ioaddr; /* Mapped address */
|
||||
char *bounce_buffer; /* For packing SDMA reads/writes */
|
||||
rt_uint64_t bounce_addr;
|
||||
unsigned int bounce_buffer_size;
|
||||
|
||||
const struct sdhci_ops *ops; /* Low level hw interface */
|
||||
|
||||
/* Internal data */
|
||||
struct mmc_host *mmc; /* MMC structure */
|
||||
struct mmc_host_ops mmc_host_ops; /* MMC host ops */
|
||||
rt_uint64_t dma_mask; /* custom DMA mask */
|
||||
|
||||
rt_spinlock_t lock;
|
||||
int flags; /* Host attributes */
|
||||
#define SDHCI_USE_SDMA (1 << 0) /* Host is SDMA capable */
|
||||
#define SDHCI_USE_ADMA (1 << 1) /* Host is ADMA capable */
|
||||
#define SDHCI_REQ_USE_DMA (1 << 2) /* Use DMA for this req. */
|
||||
#define SDHCI_DEVICE_DEAD (1 << 3) /* Device unresponsive */
|
||||
#define SDHCI_SDR50_NEEDS_TUNING (1 << 4) /* SDR50 needs tuning */
|
||||
#define SDHCI_AUTO_CMD12 (1 << 6) /* Auto CMD12 support */
|
||||
#define SDHCI_AUTO_CMD23 (1 << 7) /* Auto CMD23 support */
|
||||
#define SDHCI_PV_ENABLED (1 << 8) /* Preset value enabled */
|
||||
#define SDHCI_USE_64_BIT_DMA (1 << 12) /* Use 64-bit DMA */
|
||||
#define SDHCI_HS400_TUNING (1 << 13) /* Tuning for HS400 */
|
||||
#define SDHCI_SIGNALING_330 (1 << 14) /* Host is capable of 3.3V signaling */
|
||||
#define SDHCI_SIGNALING_180 (1 << 15) /* Host is capable of 1.8V signaling */
|
||||
#define SDHCI_SIGNALING_120 (1 << 16) /* Host is capable of 1.2V signaling */
|
||||
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
|
||||
unsigned int max_clk; /* Max possible freq (MHz) */
|
||||
unsigned int timeout_clk; /* Timeout freq (KHz) */
|
||||
rt_uint8_t max_timeout_count; /* Vendor specific max timeout count */
|
||||
unsigned int clk_mul; /* Clock Muliplier value */
|
||||
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
rt_uint8_t pwr; /* Current voltage */
|
||||
rt_uint8_t drv_type; /* Current UHS-I driver type */
|
||||
rt_bool_t reinit_uhs; /* Force UHS-related re-initialization */
|
||||
|
||||
rt_bool_t runtime_suspended; /* Host is runtime suspended */
|
||||
rt_bool_t bus_on; /* Bus power prevents runtime suspend */
|
||||
rt_bool_t preset_enabled; /* Preset is enabled */
|
||||
rt_bool_t pending_reset; /* Cmd/data reset is pending */
|
||||
rt_bool_t irq_wake_enabled; /* IRQ wakeup is enabled */
|
||||
rt_bool_t v4_mode; /* Host Version 4 Enable */
|
||||
rt_bool_t use_external_dma; /* Host selects to use external DMA */
|
||||
rt_bool_t always_defer_done; /* Always defer to complete requests */
|
||||
|
||||
struct rt_mmcsd_req *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
|
||||
struct rt_mmcsd_cmd *cmd; /* Current command */
|
||||
struct rt_mmcsd_cmd *data_cmd; /* Current data command */
|
||||
struct rt_mmcsd_cmd *deferred_cmd; /* Deferred command */
|
||||
struct rt_mmcsd_data *data; /* Current data request */
|
||||
unsigned int data_early : 1; /* Data finished before cmd */
|
||||
|
||||
unsigned int blocks; /* remaining PIO blocks */
|
||||
|
||||
int sg_count; /* Mapped sg entries */
|
||||
int max_adma; /* Max. length in ADMA descriptor */
|
||||
|
||||
void *adma_table; /* ADMA descriptor table */
|
||||
void *align_buffer; /* Bounce buffer */
|
||||
|
||||
size_t adma_table_sz; /* ADMA descriptor table size */
|
||||
size_t align_buffer_sz; /* Bounce buffer size */
|
||||
|
||||
rt_uint64_t adma_addr; /* Mapped ADMA descr. table */
|
||||
rt_uint64_t align_addr; /* Mapped bounce buffer */
|
||||
|
||||
unsigned int desc_sz; /* ADMA current descriptor size */
|
||||
unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
|
||||
|
||||
struct rt_workqueue *complete_wq; /* Request completion wq */
|
||||
struct rt_work complete_work; /* Request completion work */
|
||||
|
||||
struct rt_workqueue *irq_wq;
|
||||
struct rt_work irq_work;
|
||||
|
||||
struct rt_timer timer; /* Timer for timeouts */
|
||||
struct rt_timer data_timer; /* Timer for data timeouts */
|
||||
|
||||
rt_uint32_t caps; /* CAPABILITY_0 */
|
||||
rt_uint32_t caps1; /* CAPABILITY_1 */
|
||||
rt_bool_t read_caps; /* Capability flags have been read */
|
||||
|
||||
rt_bool_t sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
|
||||
unsigned int ocr_avail_sdio; /* OCR bit masks */
|
||||
unsigned int ocr_avail_sd;
|
||||
unsigned int ocr_avail_mmc;
|
||||
rt_uint32_t ocr_mask; /* available voltages */
|
||||
|
||||
unsigned timing; /* Current timing */
|
||||
|
||||
rt_uint32_t thread_isr;
|
||||
|
||||
/* cached registers */
|
||||
rt_uint32_t ier;
|
||||
|
||||
rt_bool_t cqe_on; /* CQE is operating */
|
||||
rt_uint32_t cqe_ier; /* CQE interrupt mask */
|
||||
rt_uint32_t cqe_err_ier; /* CQE error interrupt mask */
|
||||
|
||||
rt_wqueue_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
|
||||
unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
|
||||
|
||||
unsigned int tuning_count; /* Timer count for re-tuning */
|
||||
unsigned int tuning_mode; /* Re-tuning mode supported by host */
|
||||
unsigned int tuning_err; /* Error code for re-tuning */
|
||||
#define SDHCI_TUNING_MODE_1 0
|
||||
#define SDHCI_TUNING_MODE_2 1
|
||||
#define SDHCI_TUNING_MODE_3 2
|
||||
/* Delay (ms) between tuning commands */
|
||||
int tuning_delay;
|
||||
int tuning_loop_count;
|
||||
|
||||
/* Host SDMA buffer boundary. */
|
||||
rt_uint32_t sdma_boundary;
|
||||
|
||||
/* Host ADMA table count */
|
||||
rt_uint32_t adma_table_cnt;
|
||||
rt_uint64_t data_timeout;
|
||||
|
||||
unsigned long private[];
|
||||
};
|
||||
|
||||
struct sdhci_ops
|
||||
{
|
||||
rt_uint32_t (*read_l)(struct sdhci_host *host, int reg);
|
||||
rt_uint16_t (*read_w)(struct sdhci_host *host, int reg);
|
||||
rt_uint8_t (*read_b)(struct sdhci_host *host, int reg);
|
||||
void (*write_l)(struct sdhci_host *host, rt_uint32_t val, int reg);
|
||||
void (*write_w)(struct sdhci_host *host, rt_uint16_t val, int reg);
|
||||
void (*write_b)(struct sdhci_host *host, rt_uint8_t val, int reg);
|
||||
void (*set_clock)(struct sdhci_host *host, unsigned int clock);
|
||||
void (*set_power)(struct sdhci_host *host, unsigned char mode,
|
||||
unsigned short vdd);
|
||||
|
||||
rt_uint32_t (*irq)(struct sdhci_host *host, rt_uint32_t intmask);
|
||||
|
||||
int (*set_dma_mask)(struct sdhci_host *host);
|
||||
int (*enable_dma)(struct sdhci_host *host);
|
||||
unsigned int (*get_max_clock)(struct sdhci_host *host);
|
||||
unsigned int (*get_min_clock)(struct sdhci_host *host);
|
||||
/* get_timeout_clock should return clk rate in unit of Hz */
|
||||
unsigned int (*get_timeout_clock)(struct sdhci_host *host);
|
||||
unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
|
||||
void (*set_timeout)(struct sdhci_host *host,
|
||||
struct rt_mmcsd_cmd *cmd);
|
||||
void (*set_bus_width)(struct sdhci_host *host, int width);
|
||||
void (*platform_send_init_74_clocks)(struct sdhci_host *host,
|
||||
rt_uint8_t power_mode);
|
||||
unsigned int (*get_ro)(struct sdhci_host *host);
|
||||
void (*reset)(struct sdhci_host *host, rt_uint8_t mask);
|
||||
int (*platform_execute_tuning)(struct sdhci_host *host, rt_uint32_t opcode);
|
||||
void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
|
||||
void (*hw_reset)(struct sdhci_host *host);
|
||||
void (*adma_workaround)(struct sdhci_host *host, rt_uint32_t intmask);
|
||||
void (*card_event)(struct sdhci_host *host);
|
||||
void (*voltage_switch)(struct sdhci_host *host);
|
||||
void (*adma_write_desc)(struct sdhci_host *host, void **desc,
|
||||
rt_uint64_t addr, int len, unsigned int cmd);
|
||||
void (*copy_to_bounce_buffer)(struct sdhci_host *host,
|
||||
struct rt_mmcsd_data *data,
|
||||
unsigned int length);
|
||||
void (*request_done)(struct sdhci_host *host,
|
||||
struct rt_mmcsd_req *mrq);
|
||||
void (*dump_vendor_regs)(struct sdhci_host *host);
|
||||
};
|
||||
|
||||
static inline rt_uint8_t rt_uint8_t_read(const volatile void *addr)
|
||||
{
|
||||
return *(const volatile rt_uint8_t *)addr;
|
||||
}
|
||||
|
||||
static inline rt_uint16_t rt_uint16_t_read(const volatile void *addr)
|
||||
{
|
||||
return *(const volatile rt_uint16_t *)addr;
|
||||
}
|
||||
|
||||
static inline rt_uint32_t rt_uint32_t_read(const volatile void *addr)
|
||||
{
|
||||
return *(const volatile rt_uint32_t *)addr;
|
||||
}
|
||||
|
||||
static inline void rt_uint8_t_write(rt_uint8_t value, volatile void *addr)
|
||||
{
|
||||
*(volatile rt_uint8_t *)addr = value;
|
||||
}
|
||||
|
||||
static inline void rt_uint16_t_write(rt_uint16_t value, volatile void *addr)
|
||||
{
|
||||
*(volatile rt_uint16_t *)addr = value;
|
||||
}
|
||||
|
||||
static inline void rt_uint32_t_write(rt_uint32_t value, volatile void *addr)
|
||||
{
|
||||
*(volatile rt_uint32_t *)addr = value;
|
||||
}
|
||||
|
||||
#define readb(c) rt_uint8_t_read(c)
|
||||
#define readw(c) rt_uint16_t_read(c)
|
||||
#define readl(c) rt_uint32_t_read(c)
|
||||
#define readsb(p, d, l) ({ __raw_readsb(p,d,l); __iormb(); })
|
||||
#define readsw(p, d, l) ({ __raw_readsw(p,d,l); __iormb(); })
|
||||
#define readsl(p, d, l) ({ __raw_readsl(p,d,l); __iormb(); })
|
||||
|
||||
#define writeb(v, c) rt_uint8_t_write(v, c)
|
||||
#define writew(v, c) rt_uint16_t_write(v, c)
|
||||
#define writel(v, c) rt_uint32_t_write(v, c)
|
||||
#define writesb(p, d, l) ({ __iowmb(); __raw_writesb(p,d,l); })
|
||||
#define writesw(p, d, l) ({ __iowmb(); __raw_writesw(p,d,l); })
|
||||
#define writesl(p, d, l) ({ __iowmb(); __raw_writesl(p,d,l); })
|
||||
|
||||
static inline void sdhci_writel(struct sdhci_host *host, rt_uint32_t val, int reg)
|
||||
{
|
||||
if (host->ops->write_l)
|
||||
host->ops->write_l(host, val, reg);
|
||||
else
|
||||
writel(val, host->ioaddr + reg);
|
||||
}
|
||||
|
||||
static inline void sdhci_writew(struct sdhci_host *host, rt_uint16_t val, int reg)
|
||||
{
|
||||
if (host->ops->write_w)
|
||||
host->ops->write_w(host, val, reg);
|
||||
else
|
||||
writew(val, host->ioaddr + reg);
|
||||
}
|
||||
|
||||
static inline void sdhci_writeb(struct sdhci_host *host, rt_uint8_t val, int reg)
|
||||
{
|
||||
if (host->ops->write_b)
|
||||
host->ops->write_b(host, val, reg);
|
||||
else
|
||||
writeb(val, host->ioaddr + reg);
|
||||
}
|
||||
|
||||
static inline rt_uint32_t sdhci_readl(struct sdhci_host *host, int reg)
|
||||
{
|
||||
if (host->ops->read_l)
|
||||
return host->ops->read_l(host, reg);
|
||||
else
|
||||
return readl(host->ioaddr + reg);
|
||||
}
|
||||
|
||||
static inline rt_uint16_t sdhci_readw(struct sdhci_host *host, int reg)
|
||||
{
|
||||
if (host->ops->read_w)
|
||||
return host->ops->read_w(host, reg);
|
||||
else
|
||||
return readw(host->ioaddr + reg);
|
||||
}
|
||||
|
||||
static inline rt_uint8_t sdhci_readb(struct sdhci_host *host, int reg)
|
||||
{
|
||||
if (host->ops->read_b)
|
||||
return host->ops->read_b(host, reg);
|
||||
else
|
||||
return readb(host->ioaddr + reg);
|
||||
}
|
||||
|
||||
struct sdhci_host *sdhci_alloc_host(struct rt_device *dev, size_t priv_size);
|
||||
void sdhci_free_host(struct sdhci_host *host);
|
||||
|
||||
static inline void *sdhci_priv(struct sdhci_host *host)
|
||||
{
|
||||
return host->private;
|
||||
}
|
||||
|
||||
void __sdhci_read_caps(struct sdhci_host *host, const rt_uint16_t *ver,
|
||||
const rt_uint32_t *caps, const rt_uint32_t *caps1);
|
||||
int sdhci_setup_host(struct sdhci_host *host);
|
||||
void sdhci_cleanup_host(struct sdhci_host *host);
|
||||
int __sdhci_add_host(struct sdhci_host *host);
|
||||
int sdhci_add_host(struct sdhci_host *host);
|
||||
void sdhci_remove_host(struct sdhci_host *host, int dead);
|
||||
|
||||
static inline void sdhci_read_caps(struct sdhci_host *host)
|
||||
{
|
||||
__sdhci_read_caps(host, NULL, NULL, NULL);
|
||||
}
|
||||
|
||||
rt_uint16_t sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
|
||||
unsigned int *actual_clock);
|
||||
void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
|
||||
void sdhci_enable_clk(struct sdhci_host *host, rt_uint16_t clk);
|
||||
void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
|
||||
unsigned short vdd);
|
||||
void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
|
||||
unsigned char mode,
|
||||
unsigned short vdd);
|
||||
void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
|
||||
unsigned short vdd);
|
||||
int sdhci_get_cd_nogpio(struct mmc_host *mmc);
|
||||
void sdhci_request(struct mmc_host *mmc, struct rt_mmcsd_req *mrq);
|
||||
int sdhci_request_atomic(struct mmc_host *mmc, struct rt_mmcsd_req *mrq);
|
||||
void sdhci_set_bus_width(struct sdhci_host *host, int width);
|
||||
void sdhci_reset(struct sdhci_host *host, rt_uint8_t mask);
|
||||
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
|
||||
int sdhci_execute_tuning(struct mmc_host *mmc, rt_uint32_t opcode);
|
||||
int __sdhci_execute_tuning(struct sdhci_host *host, rt_uint32_t opcode);
|
||||
void sdhci_set_ios(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios);
|
||||
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
|
||||
struct rt_mmcsd_io_cfg *ios);
|
||||
void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
|
||||
void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
|
||||
rt_uint64_t addr, int len, unsigned int cmd);
|
||||
|
||||
void sdhci_cqe_enable(struct mmc_host *mmc);
|
||||
void sdhci_cqe_disable(struct mmc_host *mmc, rt_bool_t recovery);
|
||||
rt_bool_t sdhci_cqe_irq(struct sdhci_host *host, rt_uint32_t intmask, int *cmd_error,
|
||||
int *data_error);
|
||||
|
||||
void sdhci_dumpregs(struct sdhci_host *host);
|
||||
void sdhci_enable_v4_mode(struct sdhci_host *host);
|
||||
|
||||
void sdhci_start_tuning(struct sdhci_host *host);
|
||||
void sdhci_end_tuning(struct sdhci_host *host);
|
||||
void sdhci_reset_tuning(struct sdhci_host *host);
|
||||
void sdhci_send_tuning(struct sdhci_host *host, rt_uint32_t opcode);
|
||||
void sdhci_abort_tuning(struct sdhci_host *host, rt_uint32_t opcode);
|
||||
void sdhci_switch_external_dma(struct sdhci_host *host, rt_bool_t en);
|
||||
void sdhci_set_data_timeout_irq(struct sdhci_host *host, rt_bool_t enable);
|
||||
void __sdhci_set_timeout(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd);
|
||||
|
||||
#endif /* __SDHCI_HW_H */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#ifndef __SDHCI_DMA_H__
|
||||
#define __SDHCI_DMA_H__
|
||||
|
||||
#include "ioremap.h"
|
||||
#include <mm_aspace.h>
|
||||
enum dma_data_direction
|
||||
{
|
||||
DMA_BIDIRECTIONAL = 0,
|
||||
DMA_TO_DEVICE = 1,
|
||||
DMA_FROM_DEVICE = 2,
|
||||
DMA_NONE = 3,
|
||||
};
|
||||
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL << (n)) - 1))
|
||||
|
||||
int dma_set_mask_and_coherent(struct rt_device *dev, rt_uint64_t mask);
|
||||
unsigned long virt_to_phys(volatile void *address);
|
||||
void *dma_alloc_coherent(struct rt_device *dev, size_t size,
|
||||
rt_uint64_t *dma_handle);
|
||||
void dma_free_coherent(struct rt_device *dev, size_t size,
|
||||
void *cpu_addr, unsigned long dma_handle);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,411 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#ifndef __SDHCI_MMC_H__
|
||||
#define __SDHCI_MMC_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/mmcsd_cmd.h>
|
||||
#include <drivers/dev_mmcsd_core.h>
|
||||
#include <drivers/mmcsd_host.h>
|
||||
#include "sdhci_dma.h"
|
||||
#define mmc_dev(x) ((x)->parent)
|
||||
|
||||
#define MMC_SEND_TUNING_BLOCK_HS200 SEND_TUNING_BLOCK_HS200
|
||||
#define MMC_SEND_TUNING_BLOCK SEND_TUNING_BLOCK
|
||||
#define MMC_STOP_TRANSMISSION STOP_TRANSMISSION
|
||||
#define MMC_BUS_TEST_R 14 /* adtc R1 */
|
||||
#define MMC_WRITE_MULTIPLE_BLOCK WRITE_MULTIPLE_BLOCK
|
||||
#define MMC_READ_MULTIPLE_BLOCK READ_MULTIPLE_BLOCK
|
||||
|
||||
#define MMC_TIMING_UHS_DDR50 MMCSD_TIMING_UHS_DDR50
|
||||
#define MMC_TIMING_UHS_SDR50 MMCSD_TIMING_UHS_SDR50
|
||||
#define MMC_TIMING_MMC_HS200 MMCSD_TIMING_MMC_HS200
|
||||
#define MMC_TIMING_MMC_HS400 MMCSD_TIMING_MMC_HS400
|
||||
#define MMC_TIMING_UHS_SDR104 MMCSD_TIMING_UHS_SDR104
|
||||
#define MMC_TIMING_UHS_SDR25 MMCSD_TIMING_UHS_SDR25
|
||||
#define MMC_TIMING_MMC_DDR52 MMCSD_TIMING_MMC_DDR52
|
||||
#define MMC_TIMING_UHS_SDR12 MMCSD_TIMING_UHS_SDR12
|
||||
#define MMC_TIMING_SD_HS MMCSD_TIMING_SD_HS
|
||||
#define MMC_TIMING_MMC_HS MMCSD_TIMING_MMC_HS
|
||||
|
||||
#define MMC_POWER_OFF MMCSD_POWER_OFF
|
||||
#define MMC_POWER_UP MMCSD_POWER_UP
|
||||
#define MMC_POWER_ON MMCSD_POWER_ON
|
||||
#define MMC_POWER_UNDEFINED 3
|
||||
|
||||
#define MMC_SET_DRIVER_TYPE_B 0
|
||||
#define MMC_SET_DRIVER_TYPE_A 1
|
||||
#define MMC_SET_DRIVER_TYPE_C 2
|
||||
#define MMC_SET_DRIVER_TYPE_D 3
|
||||
|
||||
#define MMC_SIGNAL_VOLTAGE_330 0
|
||||
#define MMC_SIGNAL_VOLTAGE_180 1
|
||||
#define MMC_SIGNAL_VOLTAGE_120 2
|
||||
|
||||
#define MMC_RSP_PRESENT (1 << 16)
|
||||
#define MMC_RSP_136 (1 << 17) /* 136 bit response */
|
||||
#define MMC_RSP_CRC (1 << 18) /* expect valid crc */
|
||||
#define MMC_RSP_BUSY (1 << 19) /* card may send busy */
|
||||
#define MMC_RSP_OPCODE (1 << 20) /* response contains opcode */
|
||||
|
||||
/*
|
||||
* These are the native response types, and correspond to valid bit
|
||||
* patterns of the above flags. One additional valid pattern
|
||||
* is all zeros, which means we don't expect a response.
|
||||
*/
|
||||
#define MMC_RSP_NONE (0)
|
||||
#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
|
||||
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
|
||||
|
||||
#define MMC_CMD_ADTC CMD_ADTC
|
||||
|
||||
#define MMC_BUS_WIDTH_8 MMCSD_BUS_WIDTH_8
|
||||
#define MMC_BUS_WIDTH_4 MMCSD_BUS_WIDTH_4
|
||||
#define MMC_BUS_WIDTH_1 MMCSD_BUS_WIDTH_1
|
||||
|
||||
#define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */
|
||||
#define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */
|
||||
enum mmc_blk_status
|
||||
{
|
||||
MMC_BLK_SUCCESS = 0,
|
||||
MMC_BLK_PARTIAL,
|
||||
MMC_BLK_CMD_ERR,
|
||||
MMC_BLK_RETRY,
|
||||
MMC_BLK_ABORT,
|
||||
MMC_BLK_DATA_ERR,
|
||||
MMC_BLK_ECC_ERR,
|
||||
MMC_BLK_NOMEDIUM,
|
||||
MMC_BLK_NEW_REQUEST,
|
||||
};
|
||||
|
||||
/************************************************************************************************ */
|
||||
|
||||
#define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS400 + 1)
|
||||
|
||||
struct mmc_host;
|
||||
|
||||
struct mmc_host_ops
|
||||
{
|
||||
/*
|
||||
* It is optional for the host to implement pre_req and post_req in
|
||||
* order to support double buffering of requests (prepare one
|
||||
* request while another request is active).
|
||||
* pre_req() must always be followed by a post_req().
|
||||
* To undo a call made to pre_req(), call post_req() with
|
||||
* a nonzero err condition.
|
||||
*/
|
||||
void (*post_req)(struct mmc_host *host, struct rt_mmcsd_req *req,
|
||||
int err);
|
||||
void (*pre_req)(struct mmc_host *host, struct rt_mmcsd_req *req);
|
||||
void (*request)(struct mmc_host *host, struct rt_mmcsd_req *req);
|
||||
|
||||
/*
|
||||
* Avoid calling the next three functions too often or in a "fast
|
||||
* path", since underlaying controller might implement them in an
|
||||
* expensive and/or slow way. Also note that these functions might
|
||||
* sleep, so don't call them in the atomic contexts!
|
||||
*/
|
||||
|
||||
/*
|
||||
* Notes to the set_ios callback:
|
||||
* ios->clock might be 0. For some controllers, setting 0Hz
|
||||
* as any other frequency works. However, some controllers
|
||||
* explicitly need to disable the clock. Otherwise e.g. voltage
|
||||
* switching might fail because the SDCLK is not really quiet.
|
||||
*/
|
||||
void (*set_ios)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
|
||||
|
||||
/*
|
||||
* Return values for the get_ro callback should be:
|
||||
* 0 for a read/write card
|
||||
* 1 for a read-only card
|
||||
* -ENOSYS when not supported (equal to NULL callback)
|
||||
* or a negative errno value when something bad happened
|
||||
*/
|
||||
int (*get_ro)(struct mmc_host *host);
|
||||
|
||||
/*
|
||||
* Return values for the get_cd callback should be:
|
||||
* 0 for a absent card
|
||||
* 1 for a present card
|
||||
* -ENOSYS when not supported (equal to NULL callback)
|
||||
* or a negative errno value when something bad happened
|
||||
*/
|
||||
int (*get_cd)(struct mmc_host *host);
|
||||
|
||||
void (*enable_sdio_irq)(struct mmc_host *host, int enable);
|
||||
/* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */
|
||||
void (*ack_sdio_irq)(struct mmc_host *host);
|
||||
|
||||
int (*start_signal_voltage_switch)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
|
||||
|
||||
/* Check if the card is pulling dat[0:3] low */
|
||||
int (*card_busy)(struct mmc_host *host);
|
||||
|
||||
/* The tuning command opcode value is different for SD and eMMC cards */
|
||||
int (*execute_tuning)(struct mmc_host *host, unsigned opcode);
|
||||
|
||||
/* Prepare HS400 target operating frequency depending host driver */
|
||||
int (*prepare_hs400_tuning)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
|
||||
|
||||
/* Prepare switch to DDR during the HS400 init sequence */
|
||||
int (*hs400_prepare_ddr)(struct mmc_host *host);
|
||||
|
||||
/* Prepare for switching from HS400 to HS200 */
|
||||
void (*hs400_downgrade)(struct mmc_host *host);
|
||||
|
||||
/* Complete selection of HS400 */
|
||||
void (*hs400_complete)(struct mmc_host *host);
|
||||
|
||||
/* Prepare enhanced strobe depending host driver */
|
||||
void (*hs400_enhanced_strobe)(struct mmc_host *host,
|
||||
struct rt_mmcsd_io_cfg *ios);
|
||||
|
||||
/* Reset the eMMC card via RST_n */
|
||||
void (*hw_reset)(struct mmc_host *host);
|
||||
void (*card_event)(struct mmc_host *host);
|
||||
};
|
||||
|
||||
struct regulator;
|
||||
struct mmc_pwrseq;
|
||||
|
||||
struct mmc_supply
|
||||
{
|
||||
struct regulator *vmmc; /* Card power supply */
|
||||
struct regulator *vqmmc; /* Optional Vccq supply */
|
||||
};
|
||||
|
||||
struct mmc_ctx
|
||||
{
|
||||
struct task_struct *task;
|
||||
};
|
||||
|
||||
/* VDD voltage 3.3 ~ 3.4 */
|
||||
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
||||
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
||||
|
||||
#define MMC_CAP2_HS200_1_8V_SDR MMCSD_SUP_HS200_1V8
|
||||
#define MMC_CAP_4_BIT_DATA MMCSD_BUSWIDTH_4
|
||||
#define MMC_CAP_8_BIT_DATA MMCSD_BUSWIDTH_8
|
||||
#define MMC_CAP2_HS200 MMCSD_SUP_HS200
|
||||
#define MMC_CAP_MMC_HIGHSPEED MMCSD_SUP_HIGHSPEED
|
||||
#define MMC_CAP_SD_HIGHSPEED MMCSD_SUP_HIGHSPEED
|
||||
#define MMC_CAP_1_8V_DDR MMCSD_SUP_DDR_1V8
|
||||
#define MMC_CAP_3_3V_DDR MMCSD_SUP_DDR_3V3
|
||||
#define MMC_CAP_1_2V_DDR MMCSD_SUP_DDR_1V2
|
||||
#define MMC_CAP_NONREMOVABLE MMCSD_SUP_NONREMOVABLE
|
||||
|
||||
|
||||
#define MMC_CAP_UHS_DDR50 0
|
||||
#define MMC_CAP2_HS400 0
|
||||
#define MMC_CAP_UHS_SDR50 0
|
||||
#define MMC_CAP_UHS_SDR25 0
|
||||
#define MMC_CAP_UHS_SDR12 0
|
||||
#define MMC_CAP_UHS_SDR104 0
|
||||
#define MMC_CAP_UHS 0
|
||||
#define MMC_CAP2_HSX00_1_8V 0
|
||||
#define MMC_CAP2_HS400_ES 0
|
||||
#define MMC_CAP_NEEDS_POLL 0
|
||||
#define MMC_CAP2_HSX00_1_2V 0
|
||||
#define MMC_CAP2_HS400_1_8V 0
|
||||
#define MMC_CAP_DRIVER_TYPE_D 0
|
||||
#define MMC_CAP_DRIVER_TYPE_C 0
|
||||
#define MMC_SET_DRIVER_TYPE_B 0
|
||||
#define MMC_CAP_DRIVER_TYPE_A 0
|
||||
#define MMC_CAP2_SDIO_IRQ_NOTHREAD 0
|
||||
#define MMC_CAP_CMD23 0
|
||||
#define MMC_CAP_SDIO_IRQ 0
|
||||
|
||||
#define MMC_CAP2_NO_SDIO (1 << 19)
|
||||
#define MMC_CAP2_NO_SD (1 << 21)
|
||||
#define MMC_CAP2_NO_MMC (1 << 22)
|
||||
#define MMC_CAP2_CQE (1 << 23)
|
||||
|
||||
#define MMC_VDD_165_195 VDD_165_195
|
||||
#define MMC_VDD_20_21 VDD_20_21
|
||||
#define MMC_VDD_29_30 VDD_29_30
|
||||
#define MMC_VDD_30_31 VDD_30_31
|
||||
#define MMC_VDD_32_33 VDD_32_33
|
||||
#define MMC_VDD_33_34 VDD_33_34
|
||||
|
||||
|
||||
struct mmc_host
|
||||
{
|
||||
struct rt_mmcsd_host rthost;
|
||||
struct rt_device *parent;
|
||||
int index;
|
||||
const struct mmc_host_ops *ops;
|
||||
unsigned int f_min;
|
||||
unsigned int f_max;
|
||||
unsigned int f_init;
|
||||
rt_uint32_t ocr_avail;
|
||||
rt_uint32_t ocr_avail_sdio; /* SDIO-specific OCR */
|
||||
rt_uint32_t ocr_avail_sd; /* SD-specific OCR */
|
||||
rt_uint32_t ocr_avail_mmc; /* MMC-specific OCR */
|
||||
struct wakeup_source *ws; /* Enable consume of uevents */
|
||||
rt_uint32_t max_current_330;
|
||||
rt_uint32_t max_current_300;
|
||||
rt_uint32_t max_current_180;
|
||||
rt_uint32_t caps; /* Host capabilities */
|
||||
|
||||
rt_uint32_t caps2; /* More host capabilities */
|
||||
|
||||
|
||||
/* host specific block data */
|
||||
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
|
||||
unsigned short max_segs; /* see blk_queue_max_segments */
|
||||
unsigned short unused;
|
||||
unsigned int max_req_size; /* maximum number of bytes in one req */
|
||||
unsigned int max_blk_size; /* maximum size of one mmc block */
|
||||
unsigned int max_blk_count; /* maximum number of blocks in one req */
|
||||
unsigned int max_busy_timeout; /* max busy timeout in ms */
|
||||
struct rt_mmcsd_io_cfg ios; /* current io bus settings */
|
||||
unsigned int retune_period;
|
||||
/* group bitfields together to minimize padding */
|
||||
unsigned int use_spi_crc : 1;
|
||||
unsigned int claimed : 1; /* host exclusively claimed */
|
||||
unsigned int doing_init_tune : 1; /* initial tuning in progress */
|
||||
unsigned int can_retune : 1; /* re-tuning can be used */
|
||||
unsigned int doing_retune : 1; /* re-tuning in progress */
|
||||
unsigned int retune_now : 1; /* do re-tuning at next req */
|
||||
unsigned int retune_paused : 1; /* re-tuning is temporarily disabled */
|
||||
unsigned int retune_crc_disable : 1; /* don't trigger retune upon crc */
|
||||
unsigned int can_dma_map_merge : 1; /* merging can be used */
|
||||
unsigned int vqmmc_enabled : 1; /* vqmmc regulator is enabled */
|
||||
|
||||
int need_retune; /* re-tuning is needed */
|
||||
int hold_retune; /* hold off re-tuning */
|
||||
rt_bool_t trigger_card_event; /* card_event necessary */
|
||||
unsigned int sdio_irqs;
|
||||
rt_bool_t sdio_irq_pending;
|
||||
|
||||
struct led_trigger *led; /* activity led */
|
||||
|
||||
struct mmc_supply supply;
|
||||
|
||||
|
||||
/* Ongoing data transfer that allows commands during transfer */
|
||||
struct rt_mmcsd_req *ongoing_mrq;
|
||||
|
||||
|
||||
unsigned int actual_clock; /* Actual HC clock rate */
|
||||
rt_uint32_t pm_caps;
|
||||
unsigned long private[];
|
||||
};
|
||||
|
||||
|
||||
static inline int mmc_card_is_removable(struct mmc_host *host)
|
||||
{
|
||||
return !(host->caps & MMC_CAP_NONREMOVABLE);
|
||||
}
|
||||
|
||||
struct device_node;
|
||||
|
||||
struct mmc_host *mmc_alloc_host(int extra, struct rt_device *);
|
||||
int mmc_add_host(struct mmc_host *);
|
||||
void mmc_remove_host(struct mmc_host *);
|
||||
void mmc_free_host(struct mmc_host *);
|
||||
int mmc_of_parse(struct mmc_host *host);
|
||||
int mmc_of_parse_voltage(struct mmc_host *host, rt_uint32_t *mask);
|
||||
|
||||
static inline void *mmc_priv(struct mmc_host *host)
|
||||
{
|
||||
return (void *)host->private;
|
||||
}
|
||||
|
||||
|
||||
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
|
||||
|
||||
#define mmc_dev(x) ((x)->parent)
|
||||
#define mmc_classdev(x) (&(x)->class_dev)
|
||||
#define mmc_hostname(x) (x->parent->parent.name)
|
||||
|
||||
void mmc_detect_change(struct mmc_host *, unsigned long delay);
|
||||
void mmc_request_done(struct mmc_host *, struct rt_mmcsd_req *);
|
||||
void mmc_command_done(struct mmc_host *host, struct rt_mmcsd_req *mrq);
|
||||
|
||||
void mmc_cqe_request_done(struct mmc_host *host, struct rt_mmcsd_req *mrq);
|
||||
|
||||
/*
|
||||
* May be called from host driver's system/runtime suspend/resume callbacks,
|
||||
* to know if SDIO IRQs has been claimed.
|
||||
*/
|
||||
static inline rt_bool_t sdio_irq_claimed(struct mmc_host *host)
|
||||
{
|
||||
return host->sdio_irqs > 0;
|
||||
}
|
||||
|
||||
static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
|
||||
struct regulator *supply,
|
||||
unsigned short vdd_bit)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_regulator_get_supply(struct mmc_host *mmc);
|
||||
int mmc_regulator_enable_vqmmc(struct mmc_host *mmc);
|
||||
void mmc_regulator_disable_vqmmc(struct mmc_host *mmc);
|
||||
|
||||
void mmc_retune_timer_stop(struct mmc_host *host);
|
||||
|
||||
static inline void mmc_retune_needed(struct mmc_host *host)
|
||||
{
|
||||
if (host->can_retune)
|
||||
host->need_retune = 1;
|
||||
}
|
||||
|
||||
static inline rt_bool_t mmc_can_retune(struct mmc_host *host)
|
||||
{
|
||||
return host->can_retune == 1;
|
||||
}
|
||||
|
||||
static inline rt_bool_t mmc_doing_retune(struct mmc_host *host)
|
||||
{
|
||||
return host->doing_retune == 1;
|
||||
}
|
||||
|
||||
static inline rt_bool_t mmc_doing_tune(struct mmc_host *host)
|
||||
{
|
||||
return host->doing_retune == 1 || host->doing_init_tune == 1;
|
||||
}
|
||||
|
||||
static inline int mmc_get_dma_dir(struct rt_mmcsd_data *data)
|
||||
{
|
||||
return data->flags & DATA_DIR_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
|
||||
}
|
||||
|
||||
static inline rt_bool_t mmc_op_multi(rt_uint32_t opcode)
|
||||
{
|
||||
return opcode == MMC_WRITE_MULTIPLE_BLOCK || opcode == MMC_READ_MULTIPLE_BLOCK;
|
||||
}
|
||||
|
||||
static inline rt_bool_t mmc_op_tuning(rt_uint32_t opcode)
|
||||
{
|
||||
return opcode == MMC_SEND_TUNING_BLOCK || opcode == MMC_SEND_TUNING_BLOCK_HS200;
|
||||
}
|
||||
|
||||
int mmc_gpio_get_cd(struct mmc_host *host);
|
||||
void mmc_detect_change(struct mmc_host *host, unsigned long delay);
|
||||
int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios);
|
||||
rt_bool_t mmc_can_gpio_ro(struct mmc_host *host);
|
||||
int mmc_gpio_get_ro(struct mmc_host *host);
|
||||
|
||||
int mmc_send_tuning(struct mmc_host *host, rt_uint32_t opcode, int *cmd_error);
|
||||
int mmc_send_abort_tuning(struct mmc_host *host, rt_uint32_t opcode);
|
||||
int mmc_of_parse(struct mmc_host *host);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#ifndef __SDHCI_MISC_H__
|
||||
#define __SDHCI_MISC_H__
|
||||
|
||||
#include "sdhci_host.h"
|
||||
|
||||
#define __BF_FIELD_CHECK(...)
|
||||
#define __bf_shf(x) (__builtin_ffsll(x) - 1)
|
||||
#define FIELD_GET(_mask, _reg) \
|
||||
({ \
|
||||
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
|
||||
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
|
||||
})
|
||||
|
||||
#define FIELD_PREP(_mask, _val) \
|
||||
({ \
|
||||
__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
|
||||
((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
|
||||
})
|
||||
|
||||
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
|
||||
|
||||
#define min_t(type, x, y) (((type)x < (type)y) ? x : y)
|
||||
#define max_t(type, x, y) (((type)x > (type)y) ? x : y)
|
||||
#define min(x, y) ((x) < (y) ? (x) : (y))
|
||||
|
||||
#define from_timer(var, callback_timer, timer_fieldname) \
|
||||
container_of(callback_timer, typeof(*var), timer_fieldname)
|
||||
|
||||
|
||||
#define le32_to_cpu(x) (x)
|
||||
#define le16_to_cpu(x) (x)
|
||||
#define cpu_to_le16(x) (x)
|
||||
#define cpu_to_le32(x) (x)
|
||||
#define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff))
|
||||
#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16))
|
||||
|
||||
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
|
||||
|
||||
#define do_div(n, base) ({ \
|
||||
uint32_t __base = (base); \
|
||||
uint32_t __rem; \
|
||||
__rem = ((uint64_t)(n)) % __base; \
|
||||
(n) = ((uint64_t)(n)) / __base; \
|
||||
__rem; \
|
||||
})
|
||||
|
||||
#define fallthrough \
|
||||
do { \
|
||||
} while (0)
|
||||
|
||||
int regulator_is_supported_voltage(struct regulator *regulator,
|
||||
int min_uV, int max_uV);
|
||||
int regulator_enable(struct regulator *regulator);
|
||||
rt_bool_t mmc_can_gpio_cd(struct mmc_host *host);
|
||||
|
||||
struct regulator
|
||||
{
|
||||
const char *supply_name;
|
||||
};
|
||||
|
||||
int regulator_get_current_limit(struct regulator *regulator);
|
||||
|
||||
int regulator_enable(struct regulator *regulator);
|
||||
|
||||
void regulator_disable(struct regulator *regulator);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#include "sdhci-platform.h"
|
||||
|
||||
static const struct sdhci_ops sdhci_pltfm_ops = {
|
||||
.set_clock = sdhci_set_clock,
|
||||
.set_bus_width = sdhci_set_bus_width,
|
||||
.reset = sdhci_reset,
|
||||
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
||||
};
|
||||
|
||||
void sdhci_get_property(struct rt_platform_device *pdev)
|
||||
{
|
||||
struct rt_device *dev = &pdev->parent;
|
||||
struct sdhci_host *host = pdev->priv;
|
||||
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
||||
rt_uint32_t bus_width;
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "sdhci,auto-cmd12"))
|
||||
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "sdhci,1-bit-only") || (rt_dm_dev_prop_read_u32(dev, "bus-width", &bus_width) == 0 && bus_width == 1))
|
||||
host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "broken-cd"))
|
||||
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "no-1-8-v"))
|
||||
host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
|
||||
|
||||
rt_dm_dev_prop_read_u32(dev, "clock-frequency", &pltfm_host->clock);
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "keep-power-in-suspend"))
|
||||
host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "wakeup-source") || rt_dm_dev_prop_read_bool(dev, "enable-sdio-wakeup")) /* legacy */
|
||||
host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
|
||||
}
|
||||
|
||||
struct sdhci_host *sdhci_pltfm_init(struct rt_platform_device *pdev,
|
||||
const struct sdhci_pltfm_data *pdata,
|
||||
size_t priv_size)
|
||||
{
|
||||
struct sdhci_host *host;
|
||||
struct rt_device *dev = &pdev->parent;
|
||||
void *ioaddr;
|
||||
int irq;
|
||||
|
||||
ioaddr = rt_dm_dev_iomap(dev, 0);
|
||||
if (!ioaddr)
|
||||
{
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
irq = rt_dm_dev_get_irq(dev, 0);
|
||||
if (irq < 0)
|
||||
{
|
||||
return RT_NULL;
|
||||
}
|
||||
host = sdhci_alloc_host(dev, priv_size);
|
||||
if (!host)
|
||||
{
|
||||
return RT_NULL;
|
||||
}
|
||||
host->irq = irq;
|
||||
host->ioaddr = ioaddr;
|
||||
host->hw_name = rt_dm_dev_get_name(dev);
|
||||
|
||||
if (pdata && pdata->ops)
|
||||
host->ops = pdata->ops;
|
||||
else
|
||||
host->ops = &sdhci_pltfm_ops;
|
||||
if (pdata)
|
||||
{
|
||||
host->quirks = pdata->quirks;
|
||||
host->quirks2 = pdata->quirks2;
|
||||
}
|
||||
|
||||
pdev->priv = host;
|
||||
|
||||
return host;
|
||||
}
|
||||
|
||||
int sdhci_pltfm_init_and_add_host(struct rt_platform_device *pdev,
|
||||
const struct sdhci_pltfm_data *pdata,
|
||||
size_t priv_size)
|
||||
{
|
||||
struct sdhci_host *host;
|
||||
int ret = 0;
|
||||
|
||||
host = sdhci_pltfm_init(pdev, pdata, priv_size);
|
||||
if (!host)
|
||||
return -RT_ERROR;
|
||||
|
||||
sdhci_get_property(pdev);
|
||||
|
||||
ret = sdhci_add_host(host);
|
||||
if (ret)
|
||||
sdhci_pltfm_free(pdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sdhci_pltfm_free(struct rt_platform_device *pdev)
|
||||
{
|
||||
struct sdhci_host *host = pdev->priv;
|
||||
|
||||
sdhci_free_host(host);
|
||||
}
|
||||
|
||||
void sdhci_pltfm_remove(struct rt_platform_device *pdev)
|
||||
{
|
||||
struct sdhci_host *host = pdev->priv;
|
||||
int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
|
||||
|
||||
sdhci_remove_host(host, dead);
|
||||
sdhci_pltfm_free(pdev);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include "sdhci.h"
|
||||
#include <rtdbg.h>
|
||||
#include <mmu.h>
|
||||
#include <drivers/core/dm.h>
|
||||
|
||||
|
||||
static void plat_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
|
||||
{
|
||||
struct mmc_host *mmc = (struct mmc_host *)host;
|
||||
rt_uint32_t flags = req->cmd->flags;
|
||||
|
||||
switch (flags & RESP_MASK)
|
||||
{
|
||||
case RESP_NONE:
|
||||
flags |= MMC_RSP_NONE;
|
||||
break;
|
||||
case RESP_R1:
|
||||
flags |= MMC_RSP_R1;
|
||||
break;
|
||||
case RESP_R1B:
|
||||
flags |= MMC_RSP_R1B;
|
||||
break;
|
||||
case RESP_R2:
|
||||
flags |= MMC_RSP_R2;
|
||||
break;
|
||||
case RESP_R3:
|
||||
flags |= MMC_RSP_R3;
|
||||
break;
|
||||
case RESP_R4:
|
||||
flags |= MMC_RSP_R4;
|
||||
break;
|
||||
case RESP_R5:
|
||||
flags |= MMC_RSP_R5;
|
||||
break;
|
||||
case RESP_R6:
|
||||
flags |= MMC_RSP_R6;
|
||||
break;
|
||||
case RESP_R7:
|
||||
flags |= MMC_RSP_R7;
|
||||
break;
|
||||
}
|
||||
if (req->data)
|
||||
{
|
||||
if ((rt_uint64_t)rt_kmem_v2p(req->data->buf) > 0xffffffff)
|
||||
{
|
||||
void *dma_buffer = rt_malloc(ARCH_PAGE_SIZE);
|
||||
void *req_buf = NULL;
|
||||
|
||||
if (req->data->blks * req->data->blksize > ARCH_PAGE_SIZE)
|
||||
{
|
||||
dma_buffer = rt_realloc(dma_buffer, req->data->blks * req->data->blksize);
|
||||
}
|
||||
|
||||
if (req->data->flags & DATA_DIR_WRITE)
|
||||
{
|
||||
rt_memcpy(dma_buffer, req->data->buf, req->data->blks * req->data->blksize);
|
||||
req->data->buf = dma_buffer;
|
||||
}
|
||||
else if (req->data->flags & DATA_DIR_READ)
|
||||
{
|
||||
req_buf = req->data->buf;
|
||||
req->data->buf = dma_buffer;
|
||||
}
|
||||
req->cmd->flags |= flags;
|
||||
mmc->ops->request(mmc, req);
|
||||
|
||||
rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER);
|
||||
|
||||
if (req->data->flags & DATA_DIR_READ)
|
||||
{
|
||||
rt_memcpy(req_buf, dma_buffer, req->data->blksize * req->data->blks);
|
||||
req->data->buf = req_buf;
|
||||
}
|
||||
|
||||
rt_free(dma_buffer);
|
||||
rt_sem_release(&host->sem_ack);
|
||||
}
|
||||
else
|
||||
{
|
||||
req->cmd->flags |= flags;
|
||||
mmc->ops->request(mmc, req);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
req->cmd->flags |= flags;
|
||||
mmc->ops->request(mmc, req);
|
||||
}
|
||||
}
|
||||
|
||||
static void plat_set_ioconfig(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *iocfg)
|
||||
{
|
||||
struct mmc_host *mmc = (struct mmc_host *)host;
|
||||
|
||||
LOG_D("clock:%d,width:%d,power:%d,vdd:%d,timing:%d\n",
|
||||
iocfg->clock, iocfg->bus_width,
|
||||
iocfg->power_mode, iocfg->vdd, iocfg->timing);
|
||||
|
||||
mmc->ops->set_ios(mmc, iocfg);
|
||||
}
|
||||
|
||||
static rt_int32_t plat_get_card_status(struct rt_mmcsd_host *host)
|
||||
{
|
||||
struct mmc_host *mmc = (struct mmc_host *)host;
|
||||
|
||||
return mmc->ops->get_cd(mmc);
|
||||
}
|
||||
|
||||
static rt_int32_t plat_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode)
|
||||
{
|
||||
struct mmc_host *mmc = (struct mmc_host *)host;
|
||||
|
||||
return mmc->ops->execute_tuning(mmc, opcode);
|
||||
}
|
||||
|
||||
static void plat_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
|
||||
{
|
||||
struct mmc_host *mmc = (struct mmc_host *)host;
|
||||
|
||||
return mmc->ops->enable_sdio_irq(mmc, en);
|
||||
}
|
||||
|
||||
|
||||
static const struct rt_mmcsd_host_ops rt_mmcsd_ops = {
|
||||
.request = plat_request,
|
||||
.set_iocfg = plat_set_ioconfig,
|
||||
.get_card_status = plat_get_card_status,
|
||||
.enable_sdio_irq = plat_enable_sdio_irq,
|
||||
.execute_tuning = plat_execute_tuning,
|
||||
};
|
||||
|
||||
|
||||
void mmc_request_done(struct mmc_host *host, struct rt_mmcsd_req *mrq)
|
||||
{
|
||||
mmcsd_req_complete(&host->rthost);
|
||||
}
|
||||
|
||||
/*add host in rtt while sdhci complete*/
|
||||
int mmc_add_host(struct mmc_host *mmc)
|
||||
{
|
||||
mmc->rthost.ops = &rt_mmcsd_ops;
|
||||
mmc->rthost.flags = mmc->caps;
|
||||
mmc->rthost.freq_max = mmc->f_max;
|
||||
mmc->rthost.freq_min = 400000;
|
||||
mmc->rthost.max_dma_segs = mmc->max_segs;
|
||||
mmc->rthost.max_seg_size = mmc->max_seg_size;
|
||||
mmc->rthost.max_blk_size = mmc->max_blk_size;
|
||||
mmc->rthost.max_blk_count = mmc->max_blk_count;
|
||||
mmc->rthost.valid_ocr = VDD_33_34 | VDD_32_33 | VDD_31_32 | VDD_30_31 | VDD_165_195 | VDD_20_21;
|
||||
|
||||
|
||||
mmcsd_change(&mmc->rthost);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct mmc_host *mmc_alloc_host(int extra, struct rt_device *dev)
|
||||
{
|
||||
struct mmc_host *mmc;
|
||||
|
||||
mmc = rt_malloc(sizeof(*mmc) + extra);
|
||||
if (mmc)
|
||||
{
|
||||
rt_memset(mmc, 0, sizeof(*mmc) + extra);
|
||||
mmc->parent = dev;
|
||||
mmcsd_host_init(&mmc->rthost);
|
||||
}
|
||||
|
||||
return mmc;
|
||||
}
|
||||
|
||||
void mmc_remove_host(struct mmc_host *host)
|
||||
{
|
||||
rt_free(host);
|
||||
}
|
||||
|
||||
int mmc_abort_tuning(struct mmc_host *host, rt_uint32_t opcode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int mmc_gpio_get_cd(struct mmc_host *host)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
void mmc_detect_change(struct mmc_host *host, unsigned long delay)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_bool_t mmc_can_gpio_ro(struct mmc_host *host)
|
||||
{
|
||||
return RT_FALSE;
|
||||
}
|
||||
|
||||
int mmc_gpio_get_ro(struct mmc_host *host)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_send_abort_tuning(struct mmc_host *host, rt_uint32_t opcode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
int mmc_of_parse(struct mmc_host *host)
|
||||
{
|
||||
struct rt_device *dev = host->parent;
|
||||
rt_uint32_t bus_width;
|
||||
|
||||
if (!dev || !dev->ofw_node)
|
||||
return 0;
|
||||
|
||||
/* "bus-width" is translated to MMC_CAP_*_BIT_DATA flags */
|
||||
if (rt_dm_dev_prop_read_u32(dev, "bus-width", &bus_width) < 0)
|
||||
{
|
||||
bus_width = 1;
|
||||
}
|
||||
|
||||
switch (bus_width)
|
||||
{
|
||||
case 8:
|
||||
host->caps |= MMC_CAP_8_BIT_DATA;
|
||||
break; /* Hosts capable of 8-bit can also do 4 bits */
|
||||
case 4:
|
||||
host->caps |= MMC_CAP_4_BIT_DATA;
|
||||
break;
|
||||
case 1:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* f_max is obtained from the optional "max-frequency" property */
|
||||
rt_dm_dev_prop_read_u32(dev, "max-frequency", &host->f_max);
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "cap-mmc-highspeed"))
|
||||
{
|
||||
host->caps |= MMC_CAP_MMC_HIGHSPEED;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "mmc-hs200-1_8v"))
|
||||
{
|
||||
host->caps |= MMC_CAP2_HS200_1_8V_SDR;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "non-removable"))
|
||||
{
|
||||
host->caps |= MMC_CAP_NONREMOVABLE;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "no-sdio"))
|
||||
{
|
||||
host->caps2 |= MMC_CAP2_NO_SDIO;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "no-sd"))
|
||||
{
|
||||
host->caps2 |= MMC_CAP2_NO_SD;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-3_3v"))
|
||||
{
|
||||
host->caps |= MMC_CAP_3_3V_DDR;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-1_8v"))
|
||||
{
|
||||
host->caps |= MMC_CAP_1_8V_DDR;
|
||||
}
|
||||
|
||||
if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-1_2v"))
|
||||
{
|
||||
host->caps |= MMC_CAP_1_2V_DDR;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void mmc_free_host(struct mmc_host *host)
|
||||
{
|
||||
}
|
||||
|
||||
rt_bool_t mmc_can_gpio_cd(struct mmc_host *host)
|
||||
{
|
||||
return RT_FALSE;
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#include "sdhci.h"
|
||||
#include <rtthread.h>
|
||||
|
||||
|
||||
int dma_set_mask_and_coherent(struct rt_device *dev, rt_uint64_t mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long virt_to_phys(volatile void *address)
|
||||
{
|
||||
return (unsigned long)((rt_uint64_t)address + PV_OFFSET);
|
||||
}
|
||||
void *dma_alloc_coherent(struct rt_device *dev, size_t size,
|
||||
rt_uint64_t *dma_handle)
|
||||
{
|
||||
void *v;
|
||||
|
||||
v = rt_malloc_align(size, 2048);
|
||||
rt_kprintf("v = %p \n", v);
|
||||
if (v)
|
||||
{
|
||||
*dma_handle = virt_to_phys(v);
|
||||
v = rt_ioremap((void *)*dma_handle, size);
|
||||
rt_kprintf("v = %p *dma_handle = %p \n", v, *dma_handle);
|
||||
}
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
void dma_free_coherent(struct rt_device *dev, size_t size,
|
||||
void *cpu_addr, unsigned long dma_handle)
|
||||
{
|
||||
rt_free(cpu_addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-08-16 zhujiale first version
|
||||
*/
|
||||
#include "sdhci.h"
|
||||
|
||||
int mmc_regulator_get_supply(struct mmc_host *mmc)
|
||||
{
|
||||
mmc->supply.vmmc = -RT_NULL;
|
||||
mmc->supply.vqmmc = -RT_NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
int regulator_get_current_limit(struct regulator *regulator)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int regulator_is_supported_voltage(struct regulator *regulator,
|
||||
|
||||
int min_uV, int max_uV)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int regulator_enable(struct regulator *regulator)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
void regulator_disable(struct regulator *regulator)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
if [ ! -f "sd.bin" ]; then
|
||||
dd if=/dev/zero of=sd.bin bs=1024 count=65536
|
||||
fi
|
||||
|
||||
qemu-system-aarch64 -M raspi4b -serial stdio \
|
||||
-kernel rtthread.bin \
|
||||
-drive if=sd,file=sd.bin \
|
||||
-dtb bcm2711-rpi-4-b.dtb \
|
||||
-append 'printk.time=0 earlycon=pl011,0xfe201000 console=ttyAMA0 root=ram0 rw'
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_USING_SMART
|
||||
#define RT_USING_SMP
|
||||
#define RT_CPUS_NR 4
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 16384
|
||||
#define SYSTEM_THREAD_STACK_SIZE 16384
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 16384
|
||||
#define RT_USING_CPU_USAGE_TRACER
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
/* end of kservice optimization */
|
||||
|
||||
/* klibc optimization */
|
||||
|
||||
#define RT_KLIBC_USING_PRINTF_LONGLONG
|
||||
/* end of klibc optimization */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_PAGE_MAX_ORDER 11
|
||||
#define RT_USING_SLAB
|
||||
#define RT_USING_SLAB_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_DEVICE_OPS
|
||||
#define RT_USING_INTERRUPT_INFO
|
||||
#define RT_USING_SCHED_THREAD_CTX
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_VER_NUM 0x50200
|
||||
#define RT_USING_STDC_ATOMIC
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
|
||||
/* AArch64 Architecture Configuration */
|
||||
|
||||
#define ARCH_TEXT_OFFSET 0x200000
|
||||
#define ARCH_RAM_OFFSET 0x0
|
||||
#define ARCH_SECONDARY_CPU_STACK_SIZE 65536
|
||||
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
|
||||
#define ARCH_HEAP_SIZE 0x4000000
|
||||
#define ARCH_INIT_PAGE_SIZE 0x200000
|
||||
/* end of AArch64 Architecture Configuration */
|
||||
#define ARCH_CPU_64BIT
|
||||
#define RT_USING_CACHE
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_MM_MMU
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_MMU
|
||||
#define KERNEL_VADDR_START 0xffff000000000000
|
||||
#define ARCH_ARMV8
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 8192
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 8192
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 64
|
||||
#define RT_USING_DFS_V2
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
|
||||
/* elm-chan's FatFs, Generic FAT Filesystem Module */
|
||||
|
||||
#define RT_DFS_ELM_CODE_PAGE 437
|
||||
#define RT_DFS_ELM_WORD_ACCESS
|
||||
#define RT_DFS_ELM_USE_LFN_3
|
||||
#define RT_DFS_ELM_USE_LFN 3
|
||||
#define RT_DFS_ELM_LFN_UNICODE_0
|
||||
#define RT_DFS_ELM_LFN_UNICODE 0
|
||||
#define RT_DFS_ELM_MAX_LFN 255
|
||||
#define RT_DFS_ELM_DRIVES 2
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
|
||||
#define RT_DFS_ELM_REENTRANT
|
||||
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
|
||||
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
|
||||
#define RT_USING_DFS_DEVFS
|
||||
#define RT_USING_DFS_PTYFS
|
||||
#define RT_USING_DFS_TMPFS
|
||||
#define RT_USING_PAGECACHE
|
||||
|
||||
/* page cache config */
|
||||
|
||||
#define RT_PAGECACHE_COUNT 4096
|
||||
#define RT_PAGECACHE_ASPACE_COUNT 1024
|
||||
#define RT_PAGECACHE_PRELOAD 4
|
||||
#define RT_PAGECACHE_HASH_NR 1024
|
||||
#define RT_PAGECACHE_GC_WORK_LEVEL 90
|
||||
#define RT_PAGECACHE_GC_STOP_LEVEL 70
|
||||
/* end of page cache config */
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DM
|
||||
#define RT_USING_DEV_BUS
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 16384
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_NULL
|
||||
#define RT_USING_ZERO
|
||||
#define RT_USING_RANDOM
|
||||
#define RT_USING_RTC
|
||||
#define RT_USING_SOFT_RTC
|
||||
#define RT_USING_SDIO
|
||||
#define RT_SDIO_STACK_SIZE 16384
|
||||
#define RT_SDIO_THREAD_PRIORITY 15
|
||||
#define RT_MMCSD_STACK_SIZE 8192
|
||||
#define RT_MMCSD_THREAD_PREORITY 22
|
||||
#define RT_MMCSD_MAX_PARTITION 16
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_WDT
|
||||
#define RT_USING_TOUCH
|
||||
#define RT_USING_LCD
|
||||
#define RT_USING_OFW
|
||||
#define RT_FDT_EARLYCON_MSG_SIZE 128
|
||||
#define RT_USING_OFW_BUS_RANGES_NUMBER 8
|
||||
#define RT_USING_PIC
|
||||
#define MAX_HANDLERS 256
|
||||
#define RT_PIC_ARM_GIC
|
||||
#define RT_PIC_ARM_GIC_MAX_NR 1
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_KTIME
|
||||
#define RT_USING_CLK
|
||||
#define RT_USING_HWTIMER
|
||||
#define RT_HWTIMER_ARM_ARCH
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
#define RT_USING_POSIX_FS
|
||||
#define RT_USING_POSIX_DEVIO
|
||||
#define RT_USING_POSIX_STDIO
|
||||
#define RT_USING_POSIX_POLL
|
||||
#define RT_USING_POSIX_EPOLL
|
||||
#define RT_USING_POSIX_SIGNALFD
|
||||
#define RT_SIGNALFD_MAX_NUM 10
|
||||
#define RT_USING_POSIX_TERMIOS
|
||||
#define RT_USING_POSIX_DELAY
|
||||
#define RT_USING_POSIX_CLOCK
|
||||
#define RT_USING_POSIX_TIMER
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
#define RT_USING_SAL
|
||||
#define SAL_INTERNET_CHECK
|
||||
|
||||
/* Docking with protocol stacks */
|
||||
|
||||
#define SAL_USING_LWIP
|
||||
/* end of Docking with protocol stacks */
|
||||
#define SAL_USING_POSIX
|
||||
#define RT_USING_NETDEV
|
||||
#define NETDEV_USING_IFCONFIG
|
||||
#define NETDEV_USING_PING
|
||||
#define NETDEV_USING_NETSTAT
|
||||
#define NETDEV_USING_AUTO_DEFAULT
|
||||
#define NETDEV_IPV4 1
|
||||
#define NETDEV_IPV6 0
|
||||
#define RT_USING_LWIP
|
||||
#define RT_USING_LWIP212
|
||||
#define RT_USING_LWIP_VER_NUM 0x20102
|
||||
#define RT_LWIP_MEM_ALIGNMENT 4
|
||||
#define RT_LWIP_IGMP
|
||||
#define RT_LWIP_ICMP
|
||||
#define RT_LWIP_DNS
|
||||
#define RT_LWIP_DHCP
|
||||
#define IP_SOF_BROADCAST 1
|
||||
#define IP_SOF_BROADCAST_RECV 1
|
||||
|
||||
/* Static IPv4 Address */
|
||||
|
||||
#define RT_LWIP_IPADDR "192.168.137.100"
|
||||
#define RT_LWIP_GWADDR "192.168.137.1"
|
||||
#define RT_LWIP_MSKADDR "255.255.255.0"
|
||||
/* end of Static IPv4 Address */
|
||||
#define RT_LWIP_UDP
|
||||
#define RT_LWIP_TCP
|
||||
#define RT_LWIP_RAW
|
||||
#define RT_MEMP_NUM_NETCONN 16
|
||||
#define RT_LWIP_PBUF_NUM 16
|
||||
#define RT_LWIP_RAW_PCB_NUM 4
|
||||
#define RT_LWIP_UDP_PCB_NUM 8
|
||||
#define RT_LWIP_TCP_PCB_NUM 8
|
||||
#define RT_LWIP_TCP_SEG_NUM 40
|
||||
#define RT_LWIP_TCP_SND_BUF 8192
|
||||
#define RT_LWIP_TCP_WND 8192
|
||||
#define RT_LWIP_TCPTHREAD_PRIORITY 10
|
||||
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
|
||||
#define RT_LWIP_TCPTHREAD_STACKSIZE 32768
|
||||
#define LWIP_NO_TX_THREAD
|
||||
#define RT_LWIP_ETHTHREAD_PRIORITY 12
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 32768
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
|
||||
#define RT_LWIP_REASSEMBLY_FRAG
|
||||
#define LWIP_NETIF_STATUS_CALLBACK 1
|
||||
#define LWIP_NETIF_LINK_CALLBACK 1
|
||||
#define RT_LWIP_NETIF_NAMESIZE 6
|
||||
#define SO_REUSE 1
|
||||
#define LWIP_SO_RCVTIMEO 1
|
||||
#define LWIP_SO_SNDTIMEO 1
|
||||
#define LWIP_SO_RCVBUF 1
|
||||
#define LWIP_SO_LINGER 0
|
||||
#define RT_LWIP_NETIF_LOOPBACK
|
||||
#define LWIP_NETIF_LOOPBACK 1
|
||||
#define RT_LWIP_USING_PING
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
#define RT_USING_UTEST
|
||||
#define UTEST_THR_STACK_SIZE 8192
|
||||
#define UTEST_THR_PRIORITY 20
|
||||
#define RT_USING_RESOURCE_ID
|
||||
#define RT_USING_ADT
|
||||
#define RT_USING_ADT_AVL
|
||||
#define RT_USING_ADT_BITMAP
|
||||
#define RT_USING_ADT_HASHMAP
|
||||
#define RT_USING_ADT_REF
|
||||
/* end of Utilities */
|
||||
#define RT_USING_LWP
|
||||
#define LWP_DEBUG
|
||||
#define RT_LWP_MAX_NR 30
|
||||
#define LWP_TASK_STACK_SIZE 16384
|
||||
#define RT_CH_MSG_MAX_NR 1024
|
||||
#define LWP_TID_MAX_NR 64
|
||||
#define RT_LWP_SHM_MAX_NR 64
|
||||
#define RT_USING_LDSO
|
||||
#define LWP_USING_TERMINAL
|
||||
#define LWP_PTY_MAX_PARIS_LIMIT 64
|
||||
#define RT_USING_VDSO
|
||||
|
||||
/* Memory management */
|
||||
|
||||
#define RT_USING_MEMBLOCK
|
||||
#define RT_INIT_MEMORY_REGIONS 128
|
||||
/* end of Memory management */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
#define RT_USING_UTESTCASES
|
||||
|
||||
/* Utest Self Testcase */
|
||||
|
||||
/* end of Utest Self Testcase */
|
||||
|
||||
/* Kernel Testcase */
|
||||
|
||||
#define UTEST_SCHEDULER_TC
|
||||
|
||||
/* Kernel SMP Testcase */
|
||||
|
||||
/* end of Kernel SMP Testcase */
|
||||
/* end of Kernel Testcase */
|
||||
|
||||
/* CPP11 Testcase */
|
||||
|
||||
/* end of CPP11 Testcase */
|
||||
|
||||
/* Utest Serial Testcase */
|
||||
|
||||
/* end of Utest Serial Testcase */
|
||||
|
||||
/* Utest IPC Testcase */
|
||||
|
||||
/* end of Utest IPC Testcase */
|
||||
|
||||
/* RTT Posix Testcase */
|
||||
|
||||
/* end of RTT Posix Testcase */
|
||||
|
||||
/* Memory Management Subsytem Testcase */
|
||||
|
||||
/* end of Memory Management Subsytem Testcase */
|
||||
|
||||
/* Tmpfs Testcase */
|
||||
|
||||
/* end of Tmpfs Testcase */
|
||||
|
||||
/* SMP Testcase */
|
||||
|
||||
/* end of SMP Testcase */
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
|
||||
/* Privated Packages of RealThread */
|
||||
|
||||
|
||||
/* Network Utilities */
|
||||
|
||||
/* end of Network Utilities */
|
||||
|
||||
/* RT-Thread Smart */
|
||||
|
||||
#define PKG_USING_UKERNEL
|
||||
#define PKG_USING_UKERNEL_LATEST_VERSION
|
||||
#define RT_USING_NETIF_LOOPBACK
|
||||
#define RT_USING_DFS_PROCFS
|
||||
#define SAL_USING_AF_UNIX
|
||||
/* end of RT-Thread Smart */
|
||||
#define PKG_USING_EXT4
|
||||
#define PKG_USING_EXT4_SMART_DFS_VERSION
|
||||
/* end of Privated Packages of RealThread */
|
||||
#define BCM2711_SOC
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define BSP_USING_PL011
|
||||
#define BSP_USING_SDHCI
|
||||
#define RT_USING_SDHCI
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH ='aarch64'
|
||||
CPU ='cortex-a'
|
||||
CROSS_TOOL ='gcc'
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = r'../../..'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CPP = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -march=armv8-a -mtune=cortex-a72 -fdiagnostics-color=always'
|
||||
CPPFLAGS = ' -E -P -x assembler-with-cpp'
|
||||
CFLAGS = DEVICE + ' -Wall -Wno-cpp -D_POSIX_SOURCE'
|
||||
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -ggdb'
|
||||
AFLAGS += ' -ggdb'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
Loading…
Reference in New Issue