Merge pull request #108 from aozima/pulls

回收main函数所用的栈空间
2025-02-28 02:37:03 +08:00 · 2013-06-22 08:00:15 -07:00 · 2013-06-22 08:00:15 -07:00 · bde2e918da
commit bde2e918da
parent bee9103eaf a2ff85c03f
9 changed files with 191 additions and 110 deletions
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@ -13,6 +13,7 @@
 * 2012-06-01   aozima       set pendsv priority to 0xFF.
 * 2012-08-17   aozima       fixed bug: store r8 - r11.
 * 2013-02-20   aozima       port to gcc.
+ * 2013-06-18   aozima       add restore MSP feature.
 */
 
 	.cpu 	cortex-m3
@ -21,6 +22,7 @@
 	.thumb
 	.text

+    .equ    SCB_VTOR, 0xE000ED04            /* Vector Table Offset Register */
 	.equ	ICSR, 0xE000ED04 				/* interrupt control state register */
 	.equ	PENDSVSET_BIT, 0x10000000 		/* value to trigger PendSV exception */
 	
@ -152,6 +154,13 @@ rt_hw_context_switch_to:
 	LDR		R1, =PENDSVSET_BIT
 	STR		R1, [R0]

+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
 	CPSIE	I						/* enable interrupts at processor level */

 	/* never reach here! */
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@ -12,6 +12,7 @@
 ; * 2010-01-25     Bernard      first version
 ; * 2012-06-01     aozima       set pendsv priority to 0xFF.
 ; * 2012-08-17     aozima       fixed bug: store r8 - r11.
+; * 2013-06-18     aozima       add restore MSP feature.
 ; */

 ;/**
@ -19,6 +20,7 @@
 ; */
 ;/*@{*/

+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
@ -178,6 +180,13 @@ rt_hw_context_switch_to:
    STR     r1, [r0]
    NOP

+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    ; enable interrupts at processor level
    CPSIE   I

--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@ -12,6 +12,7 @@
 ; * 2010-01-25     Bernard      first version
 ; * 2012-06-01     aozima       set pendsv priority to 0xFF.
 ; * 2012-08-17     aozima       fixed bug: store r8 - r11.
+; * 2013-06-18     aozima       add restore MSP feature.
 ; */

 ;/**
@ -19,6 +20,7 @@
 ; */
 ;/*@{*/

+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
@ -183,6 +185,13 @@ rt_hw_context_switch_to    PROC
    STR     r1, [r0]
    NOP

+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    ; enable interrupts at processor level
    CPSIE   I

--- a/libcpu/arm/cortex-m3/context_gcc.S
+++ b/libcpu/arm/cortex-m3/context_gcc.S
@ -13,6 +13,7 @@
 * 2010-12-29   onelife   Modify for EFM32
 * 2011-06-17   onelife   Merge all of the assembly source code into context_gcc.S
 * 2011-07-12   onelife   Add interrupt context check function
+ * 2013-06-18   aozima    add restore MSP feature.
 */
 
    .cpu    cortex-m3
@ -21,6 +22,7 @@
    .thumb
    .text

+    .equ    SCB_VTOR, 0xE000ED04            /* Vector Table Offset Register */
    .equ    ICSR, 0xE000ED04                /* interrupt control state register */
    .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
    
@ -152,6 +154,13 @@ rt_hw_context_switch_to:
    LDR     R1, =PENDSVSET_BIT
    STR     R1, [R0]

+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    CPSIE   I                       /* enable interrupts at processor level */

    /* never reach here! */
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@ -11,6 +11,7 @@
 ; * Date           Author       Notes
 ; * 2009-01-17     Bernard      first version
 ; * 2009-09-27     Bernard      add protect when contex switch occurs
+; * 2013-06-18     aozima       add restore MSP feature.
 ; */

 ;/**
@ -18,6 +19,7 @@
 ; */
 ;/*@{*/

+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
@ -151,6 +153,13 @@ rt_hw_context_switch_to:
    LDR     r1, =NVIC_PENDSVSET
    STR     r1, [r0]

+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    CPSIE   I                       ; enable interrupts at processor level

    ; never reach here!
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@ -10,6 +10,7 @@
 ; * Change Logs:
 ; * Date           Author       Notes
 ; * 2009-01-17     Bernard      first version
+; * 2013-06-18     aozima       add restore MSP feature.
 ; */

 ;/**
@ -17,6 +18,7 @@
 ; */
 ;/*@{*/

+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
@ -158,6 +160,13 @@ rt_hw_context_switch_to    PROC
    LDR     r1, =NVIC_PENDSVSET
    STR     r1, [r0]

+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    ; enable interrupts at processor level
    CPSIE   I

--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@ -11,6 +11,7 @@
 * Date           Author       Notes
 * 2009-10-11     Bernard      first version
 * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2013-06-18     aozima       add restore MSP feature.
 */

 /**
@ -23,6 +24,7 @@
 .thumb
 .text

+.equ    SCB_VTOR,           0xE000ED04              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
 .equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
@ -164,6 +166,13 @@ rt_hw_context_switch_to:
    LDR r1, =NVIC_PENDSVSET
    STR r1, [r0]

+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    CPSIE   I                       /* enable interrupts at processor level */

    /* never reach here! */
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@ -12,6 +12,7 @@
 ; * 2009-01-17     Bernard      first version
 ; * 2009-09-27     Bernard      add protect when contex switch occurs
 ; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
 ; */

 ;/**
@ -19,6 +20,7 @@
 ; */
 ;/*@{*/

+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
@ -162,6 +164,13 @@ rt_hw_context_switch_to:
    LDR     r1, =NVIC_PENDSVSET
    STR     r1, [r0]

+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    CPSIE   I                       ; enable interrupts at processor level

    ; never reach here!
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@ -11,6 +11,7 @@
 ; * Date           Author       Notes
 ; * 2009-01-17     Bernard      first version.
 ; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
 ; */

 ;/**
@ -18,6 +19,7 @@
 ; */
 ;/*@{*/

+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
@ -169,6 +171,13 @@ rt_hw_context_switch_to    PROC
    LDR     r1, =NVIC_PENDSVSET
    STR     r1, [r0]

+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
    ; enable interrupts at processor level
    CPSIE   I