mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-01-19 02:13:32 +08:00
add raspi4 driver
This commit is contained in:
bigmagic
parent
5bcf84edcb
commit
bda0d303af
@ -151,7 +151,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_I2C=y
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# CONFIG_RT_I2C_DEBUG is not set
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CONFIG_RT_USING_I2C_BITOPS=y
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# CONFIG_RT_I2C_BITOPS_DEBUG is not set
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# CONFIG_RT_USING_PHY is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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@ -502,6 +505,8 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_AD7746 is not set
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# CONFIG_PKG_USING_PCA9685 is not set
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# CONFIG_PKG_USING_I2C_TOOLS is not set
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# CONFIG_PKG_USING_I2C_TOOLS_V100 is not set
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# CONFIG_PKG_USING_I2C_TOOLS_LATEST_VERSION is not set
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# CONFIG_PKG_USING_NRF24L01 is not set
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# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
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# CONFIG_PKG_USING_MAX17048 is not set
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@ -526,6 +531,7 @@ CONFIG_RT_LWIP_USING_PING=y
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# CONFIG_PKG_USING_LY68L6400 is not set
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# CONFIG_PKG_USING_DM9051 is not set
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# CONFIG_PKG_USING_SSD1306 is not set
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# CONFIG_PKG_USING_SSD1306_LATEST_VERSION is not set
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# CONFIG_PKG_USING_QKEY is not set
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#
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@ -634,6 +640,13 @@ CONFIG_BSP_USING_SPI=y
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CONFIG_BSP_USING_SPI0_BUS=y
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CONFIG_BSP_USING_SPI0_DEVICE0=y
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CONFIG_BSP_USING_SPI0_DEVICE1=y
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CONFIG_BSP_USING_I2C=y
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# CONFIG_BSP_USING_I2C0 is not set
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# CONFIG_BSP_USING_I2C1 is not set
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CONFIG_BSP_USING_I2C3=y
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# CONFIG_BSP_USING_I2C4 is not set
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# CONFIG_BSP_USING_I2C5 is not set
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# CONFIG_BSP_USING_I2C6 is not set
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CONFIG_BSP_USING_CORETIMER=y
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# CONFIG_BSP_USING_SYSTIMER is not set
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CONFIG_BSP_USING_WDT=y
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@ -50,7 +50,7 @@ menu "Hardware Drivers Config"
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select RT_USING_PIN
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default y
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menuconfig BSP_USING_SPI
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menuconfig BSP_USING_SPI
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bool "Enable SPI"
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select RT_USING_SPI
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default n
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@ -69,6 +69,32 @@ menu "Hardware Drivers Config"
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default n
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endif
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menuconfig BSP_USING_I2C
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bool "Enable I2C"
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select RT_USING_I2C
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default n
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if BSP_USING_I2C
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config BSP_USING_I2C0
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bool "Enable I2C0 BUS"
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default n
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config BSP_USING_I2C1
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bool "Enable I2C1 BUS"
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default n
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config BSP_USING_I2C3
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bool "Enable I2C3 BUS"
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default n
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config BSP_USING_I2C4
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bool "Enable I2C4 BUS"
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default n
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config BSP_USING_I2C5
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bool "Enable I2C5 BUS"
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default n
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config BSP_USING_I2C6
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bool "Enable I2C6 BUS"
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default n
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endif
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config BSP_USING_CORETIMER
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bool "Using core timer"
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select RT_USING_CORETIMER
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@ -24,7 +24,7 @@ struct mem_desc platform_mem_desc[] = {
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{0x0E000000, 0x0EE00000, 0x0E000000, DEVICE_MEM}, //framebuffer
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{0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch
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{0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
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{0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral
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{0xFE000000, 0xFEA00000, 0xFE000000, DEVICE_MEM}, //peripheral
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{0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic
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};
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368
bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c
Normal file
368
bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c
Normal file
@ -0,0 +1,368 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-28 bigmagic first version
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*/
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#include "drv_i2c.h"
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#include "drv_gpio.h"
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#include "raspi4.h"
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#include "mbox.h"
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/*
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* (3.3v) -1 2-
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* (SDA1/SDA3) -3 4-
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* (SCL1/SCL3) -5 6-
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* (SDA3) -7 8-
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* -9 10-
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* -11 12-
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* -13 14-
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* -15 16-
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* -17 18-
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* -19 20-
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* (SCL4) -21 22-
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* -23 24- (SDA4)
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* -25 26- (SCL4)
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* -27 28-
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* (SCL3) -29 30-
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* (SDA4) -31 32-
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*/
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#define DBG_TAG "drv.i2c"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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struct raspi_i2c_hw_config
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{
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rt_uint32_t bsc_num;
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rt_uint32_t bsc_rate;
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rt_uint32_t bsc_address;
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rt_uint32_t sda_pin;
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rt_uint32_t scl_pin;
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rt_uint32_t sda_mode;
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rt_uint32_t scl_mode;
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};
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rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
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{
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rt_uint32_t status;
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rt_uint32_t remaining = len;
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rt_uint32_t i = 0;
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rt_uint8_t reason = I2C_REASON_OK;
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/* Clear FIFO */
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BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
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/* Clear Status */
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BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
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/* Set Data Length */
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BSC_DLEN(base) = len;
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if (flag)
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{
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/* Start read */
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BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
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/* wait for transfer to complete */
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while (!(BSC_S(base) & BSC_S_DONE))
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{
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/* we must empty the FIFO as it is populated and not use any delay */
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while (remaining && (BSC_S(base) & BSC_S_RXD))
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{
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/* Read from FIFO, no barrier */
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buf[i] = BSC_FIFO(base);
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i++;
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remaining--;
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}
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}
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/* transfer has finished - grab any remaining stuff in FIFO */
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while (remaining && (BSC_S(base) & BSC_S_RXD))
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{
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/* Read from FIFO, no barrier */
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buf[i] = BSC_FIFO(base);
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i++;
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remaining--;
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}
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}
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else
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{
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LOG_D("i2c%d write start", flag);
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/* pre populate FIFO with max buffer */
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while (remaining && (i < BSC_FIFO_SIZE))
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{
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BSC_FIFO(base) = buf[i];
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i++;
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remaining--;
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}
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/* Enable device and start transfer */
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BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
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/* Transfer is over when BCM2835_BSC_S_DONE */
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while (!(BSC_S(base) & BSC_S_DONE))
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{
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while (remaining && (BSC_S(base) & BSC_S_TXD))
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{
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/* Write to FIFO */
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BSC_FIFO(base) = buf[i];
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i++;
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remaining--;
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}
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}
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LOG_D("i2c%d write end", flag);
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}
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status = BSC_S(base);
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if (status & BSC_S_ERR)
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{
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reason = I2C_REASON_ERROR_NACK;
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}
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else if (status & BSC_S_CLKT)
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{
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reason = I2C_REASON_ERROR_CLKT;
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}
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else if (remaining)
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{
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reason = I2C_REASON_ERROR_DATA;
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}
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BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
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return reason;
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}
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static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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rt_size_t i;
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rt_uint8_t reason;
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RT_ASSERT(bus != RT_NULL);
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struct raspi_i2c_hw_config *i2c_hw_config = (struct raspi_i2c_hw_config*)(bus->priv);
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//Slave Address
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BSC_A(i2c_hw_config->bsc_address) = msgs->addr;
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for (i = 0; i < num; i++)
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{
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if (msgs[i].flags & RT_I2C_RD)
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reason = i2c_read_or_write(i2c_hw_config->bsc_address, msgs->buf, msgs->len, 1);
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else
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reason = i2c_read_or_write(i2c_hw_config->bsc_address, msgs->buf, msgs->len, 0);
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}
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return (reason == 0)? i : 0;
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}
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static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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return 0;
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}
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static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t cmd,
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rt_uint32_t arg)
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{
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return RT_EOK;
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}
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static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
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{
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RT_ASSERT(cfg != RT_NULL);
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rt_uint32_t apb_clock = 0;
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prev_raspi_pin_mode(cfg->sda_pin, cfg->sda_mode);//sda
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prev_raspi_pin_mode(cfg->scl_pin, cfg->scl_mode);//scl
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/* use 0xFFFE mask to limit a max value and round down any odd number */
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apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
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rt_uint32_t divider = (apb_clock / cfg->bsc_rate) & 0xFFFE;
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BSC_DIV(cfg->bsc_address) = (rt_uint16_t)divider;
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return RT_EOK;
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}
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static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
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{
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.master_xfer = raspi_i2c_mst_xfer,
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.slave_xfer = raspi_i2c_slv_xfer,
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.i2c_bus_control = raspi_i2c_bus_control,
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};
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#if defined (BSP_USING_I2C0)
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#define I2C0_BUS_NAME "i2c0"
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static struct raspi_i2c_hw_config hw_device0 =
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{
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.bsc_num = 0,
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.bsc_rate = 100000,//100k
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.bsc_address = BSC0_BASE,
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.sda_pin = GPIO_PIN_0,
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.scl_pin = GPIO_PIN_1,
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.sda_mode = ALT0,
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.scl_mode = ALT0,
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};
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struct rt_i2c_bus_device device0 =
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{
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.ops = &raspi_i2c_ops,
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.priv = (void *)&hw_device0,
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};
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#endif
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#if defined (BSP_USING_I2C1)
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#define I2C1_BUS_NAME "i2c1"
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static struct raspi_i2c_hw_config hw_device1 =
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{
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.bsc_num = 1,
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.bsc_rate = 100000,//100k
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.bsc_address = BSC1_BASE,
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.sda_pin = GPIO_PIN_2,
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.scl_pin = GPIO_PIN_3,
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.sda_mode = ALT0,
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.scl_mode = ALT0,
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};
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struct rt_i2c_bus_device device1 =
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{
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.ops = &raspi_i2c_ops,
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.priv = (void *)&hw_device1,
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};
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#endif
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#if defined (BSP_USING_I2C3)
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#define I2C3_BUS_NAME "i2c3"
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static struct raspi_i2c_hw_config hw_device3 =
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{
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.bsc_num = 3,
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.bsc_rate = 100000,//100k
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.bsc_address = BSC3_BASE,
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#ifndef BSP_USING_I2C3_0
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.sda_pin = GPIO_PIN_2,
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.scl_pin = GPIO_PIN_3,
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#else
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.sda_pin = GPIO_PIN_4,
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.scl_pin = GPIO_PIN_5,
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#endif
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.sda_mode = ALT5,
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.scl_mode = ALT5,
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};
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struct rt_i2c_bus_device device3 =
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{
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.ops = &raspi_i2c_ops,
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.priv = (void *)&hw_device3,
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};
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#endif
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#if defined (BSP_USING_I2C4)
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#define I2C4_BUS_NAME "i2c4"
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static struct raspi_i2c_hw_config hw_device4 =
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{
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.bsc_num = 4,
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.bsc_rate = 100000,//100k
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.bsc_address = BSC4_BASE,
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#ifdef BSP_USING_I2C4_0
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.sda_pin = GPIO_PIN_6,
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.scl_pin = GPIO_PIN_7,
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#else
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.sda_pin = GPIO_PIN_8,
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.scl_pin = GPIO_PIN_9,
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#endif
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.sda_mode = ALT5,
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.scl_mode = ALT5,
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};
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struct rt_i2c_bus_device device4 =
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{
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.ops = &raspi_i2c_ops,
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.priv = (void *)&hw_device4,
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};
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#endif
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#if defined (BSP_USING_I2C5)
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#define I2C5_BUS_NAME "i2c5"
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static struct raspi_i2c_hw_config hw_device5 =
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{
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.bsc_num = 5,
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.bsc_rate = 100000,//100k
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.bsc_address = BSC5_BASE,
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#ifdef BSP_USING_I2C5_0
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.sda_pin = GPIO_PIN_10,
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.scl_pin = GPIO_PIN_11,
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#else
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.sda_pin = GPIO_PIN_12,
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.scl_pin = GPIO_PIN_13,
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#endif
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.sda_mode = ALT5,
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.scl_mode = ALT5,
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};
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struct rt_i2c_bus_device device5 =
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{
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.ops = &raspi_i2c_ops,
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.priv = (void *)&hw_device5,
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};
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#endif
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#if defined (BSP_USING_I2C6)
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#define I2C6_BUS_NAME "i2c6"
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static struct raspi_i2c_hw_config hw_device6 =
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{
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.bsc_num = 6,
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.bsc_rate = 100000,//100k
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.bsc_address = BSC6_BASE,
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#ifdef BSP_USING_I2C5_0
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.sda_pin = GPIO_PIN_0,
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.scl_pin = GPIO_PIN_1,
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#else
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.sda_pin = GPIO_PIN_22,
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.scl_pin = GPIO_PIN_23,
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#endif
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.sda_mode = ALT5,
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.scl_mode = ALT5,
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};
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struct rt_i2c_bus_device device6 =
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{
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.ops = &raspi_i2c_ops,
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.priv = (void *)&hw_device6,
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};
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#endif
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int rt_hw_i2c_init(void)
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{
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#if defined(BSP_USING_I2C0)
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raspi_i2c_configure(&hw_device0);
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rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
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#endif
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#if defined(BSP_USING_I2C1)
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raspi_i2c_configure(&hw_device1);
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rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
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#endif
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#if defined(BSP_USING_I2C3)
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raspi_i2c_configure(&hw_device3);
|
||||
rt_i2c_bus_device_register(&device3, I2C3_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C4)
|
||||
raspi_i2c_configure(&hw_device4);
|
||||
rt_i2c_bus_device_register(&device4, I2C4_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C5)
|
||||
raspi_i2c_configure(&hw_device5);
|
||||
rt_i2c_bus_device_register(&device5, I2C5_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C6)
|
||||
raspi_i2c_configure(&hw_device6);
|
||||
rt_i2c_bus_device_register(&device6, I2C6_BUS_NAME);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
|
||||
59
bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h
Normal file
59
bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-28 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_I2C_H__
|
||||
#define __DRV_I2C_H__
|
||||
|
||||
#include <rthw.h>
|
||||
|
||||
#define BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */
|
||||
#define BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */
|
||||
#define BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */
|
||||
#define BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */
|
||||
#define BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */
|
||||
#define BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */
|
||||
#define BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */
|
||||
#define BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */
|
||||
|
||||
/* Register masks for C Register */
|
||||
#define BSC_C_I2CEN (0x00008000) /* I2C Enable, 0 = disabled, 1 = enabled */
|
||||
#define BSC_C_INTR (0x00000400) /* Interrupt on RX */
|
||||
#define BSC_C_INTT (0x00000200) /* Interrupt on TX */
|
||||
#define BSC_C_INTD (0x00000100) /* Interrupt on DONE */
|
||||
#define BSC_C_ST (0x00000080) /* Start transfer, 1 = Start a new transfer */
|
||||
#define BSC_C_CLEAR_1 (0x00000020) /* Clear FIFO Clear */
|
||||
#define BSC_C_CLEAR_2 (0x00000010) /* Clear FIFO Clear */
|
||||
#define BSC_C_READ (0x00000001) /* Read transfer */
|
||||
|
||||
/* Register masks for S Register */
|
||||
#define BSC_S_CLKT (0x00000200) /* Clock stretch timeout */
|
||||
#define BSC_S_ERR (0x00000100) /* ACK error */
|
||||
#define BSC_S_RXF (0x00000080) /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
|
||||
#define BSC_S_TXE (0x00000040) /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
|
||||
#define BSC_S_RXD (0x00000020) /* RXD FIFO contains data */
|
||||
#define BSC_S_TXD (0x00000010) /* TXD FIFO can accept data */
|
||||
#define BSC_S_RXR (0x00000008) /* RXR FIFO needs reading (full) */
|
||||
#define BSC_S_TXW (0x00000004) /* TXW FIFO needs writing (full) */
|
||||
#define BSC_S_DONE (0x00000002) /* Transfer DONE */
|
||||
#define BSC_S_TA (0x00000001) /* Transfer Active */
|
||||
|
||||
#define BSC_FIFO_SIZE (16) /* BSC FIFO size */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_REASON_OK = 0x00, /* Success */
|
||||
I2C_REASON_ERROR_NACK = 0x01, /* Received a NACK */
|
||||
I2C_REASON_ERROR_CLKT = 0x02, /* Received Clock Stretch Timeout */
|
||||
I2C_REASON_ERROR_DATA = 0x04 /* Not all data is sent / received */
|
||||
} i2c_reason_codes;
|
||||
|
||||
int rt_hw_i2c_init(void);
|
||||
|
||||
#endif
|
||||
@ -154,6 +154,23 @@ typedef enum {
|
||||
|
||||
#define ETH_IRQ (160+29)
|
||||
|
||||
//I2C
|
||||
#define BSC0_BASE_OFFSET (0x205000)
|
||||
#define BSC1_BASE_OFFSET (0x804000)
|
||||
#define BSC3_BASE_OFFSET (0x205600)
|
||||
#define BSC4_BASE_OFFSET (0x205800)
|
||||
#define BSC5_BASE_OFFSET (0x205A80)
|
||||
#define BSC6_BASE_OFFSET (0x205C00)
|
||||
|
||||
//BSC2 and BSC7 masters are dedicated for use by the
|
||||
//HDMI interfaces and should not be accessed byuser programs.
|
||||
#define BSC0_BASE (PER_BASE + BSC0_BASE_OFFSET)
|
||||
#define BSC1_BASE (PER_BASE + BSC1_BASE_OFFSET)
|
||||
#define BSC3_BASE (PER_BASE + BSC3_BASE_OFFSET)
|
||||
#define BSC4_BASE (PER_BASE + BSC4_BASE_OFFSET)
|
||||
#define BSC5_BASE (PER_BASE + BSC5_BASE_OFFSET)
|
||||
#define BSC6_BASE (PER_BASE + BSC6_BASE_OFFSET)
|
||||
|
||||
/* the basic constants and interfaces needed by gic */
|
||||
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
|
||||
{
|
||||
|
||||
@ -100,6 +100,8 @@
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_SDIO
|
||||
#define RT_SDIO_STACK_SIZE 512
|
||||
@ -258,6 +260,8 @@
|
||||
#define BSP_USING_SPI0_BUS
|
||||
#define BSP_USING_SPI0_DEVICE0
|
||||
#define BSP_USING_SPI0_DEVICE1
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_I2C3
|
||||
#define BSP_USING_CORETIMER
|
||||
#define BSP_USING_WDT
|
||||
#define BSP_USING_ETH
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user