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fix mips stackframe and exception

This commit is contained in:
bigmagic 2020-08-26 12:03:01 +08:00
parent cf622e5177
commit bd95f3a94f
4 changed files with 24 additions and 11 deletions
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4
libcpu/Kconfig
View File

@ -82,6 +82,10 @@ config ARCH_MIPS
config ARCH_MIPS64 config ARCH_MIPS64
bool bool
select ARCH_CPU_64BIT
config ARCH_CPU_64BIT
bool
config ARCH_MIPS_XBURST config ARCH_MIPS_XBURST
bool bool

21
libcpu/mips/common/context_gcc.S
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@ -1,11 +1,12 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2020, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version * 2019-12-04 Jiaxun Yang Initial version
* 2020-07-26 lizhirui Fixed some problems
*/ */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
@ -56,12 +57,12 @@ rt_hw_context_switch_interrupt:
bnez t1, _reswitch bnez t1, _reswitch
nop nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0) LONG_S t1, 0(t0)
PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0) LONG_S a0, 0(t0)
_reswitch: _reswitch:
PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0) LONG_S a1, 0(t0)
jr ra jr ra
nop nop
@ -97,24 +98,24 @@ mips_irq_handle:
* rt_hw_context_switch_interrupt_do and do not return * rt_hw_context_switch_interrupt_do and do not return
*/ */
PTR_LA k0, rt_thread_switch_interrupt_flag PTR_LA k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0) LONG_L k1, 0(k0)
beqz k1, spurious_interrupt beqz k1, spurious_interrupt
nop nop
sw zero, 0(k0) /* clear flag */ LONG_S zero, 0(k0) /* clear flag */
nop nop
/* /*
* switch to the new thread * switch to the new thread
*/ */
PTR_LA k0, rt_interrupt_from_thread PTR_LA k0, rt_interrupt_from_thread
lw k1, 0(k0) LONG_L k1, 0(k0)
nop nop
sw sp, 0(k1) /* store sp in preempted task TCB */ LONG_S sp, 0(k1) /* store sp in preempted task TCB */
PTR_LA k0, rt_interrupt_to_thread PTR_LA k0, rt_interrupt_to_thread
lw k1, 0(k0) LONG_L k1, 0(k0)
nop nop
lw sp, 0(k1) /* get new task stack pointer */ LONG_L sp, 0(k1) /* get new task stack pointer */
j spurious_interrupt j spurious_interrupt
nop nop

8
libcpu/mips/common/exception_gcc.S
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@ -1,11 +1,12 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2020, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version * 2019-12-04 Jiaxun Yang Initial version
* 2020-07-26 lizhirui Add xtlb exception entry
*/ */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#define __ASSEMBLY__ #define __ASSEMBLY__
@ -26,6 +27,11 @@ tlb_refill_exception:
b _general_exception_handler b _general_exception_handler
nop nop
/* 0x080 - XTLB refill handler */
.org ebase_start + 0x080
b _general_exception_handler
nop
/* 0x100 - Cache error handler */ /* 0x100 - Cache error handler */
.org ebase_start + 0x100 .org ebase_start + 0x100
j cache_error_handler j cache_error_handler

2
libcpu/mips/common/stackframe.h
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@ -206,6 +206,8 @@
li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) li v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
and v0, v1 and v0, v1
or v0, a0 or v0, a0
li v1, (ST0_KX | ST0_SX | ST0_UX)
or v0, v1
mtc0 v0, CP0_STATUS mtc0 v0, CP0_STATUS
LONG_L v1, PT_EPC(sp) LONG_L v1, PT_EPC(sp)
MTC0 v1, CP0_EPC MTC0 v1, CP0_EPC