fix mips stackframe and exception
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cf622e5177
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bd95f3a94f
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@ -82,6 +82,10 @@ config ARCH_MIPS
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config ARCH_MIPS64
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bool
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select ARCH_CPU_64BIT
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config ARCH_CPU_64BIT
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bool
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config ARCH_MIPS_XBURST
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bool
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@ -1,11 +1,12 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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* 2020-07-26 lizhirui Fixed some problems
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*/
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#ifndef __ASSEMBLY__
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@ -56,12 +57,12 @@ rt_hw_context_switch_interrupt:
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bnez t1, _reswitch
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nop
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li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
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sw t1, 0(t0)
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LONG_S t1, 0(t0)
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PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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sw a0, 0(t0)
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LONG_S a0, 0(t0)
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_reswitch:
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PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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sw a1, 0(t0)
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LONG_S a1, 0(t0)
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jr ra
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nop
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@ -97,24 +98,24 @@ mips_irq_handle:
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* rt_hw_context_switch_interrupt_do and do not return
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*/
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PTR_LA k0, rt_thread_switch_interrupt_flag
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lw k1, 0(k0)
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LONG_L k1, 0(k0)
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beqz k1, spurious_interrupt
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nop
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sw zero, 0(k0) /* clear flag */
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LONG_S zero, 0(k0) /* clear flag */
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nop
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/*
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* switch to the new thread
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*/
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PTR_LA k0, rt_interrupt_from_thread
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lw k1, 0(k0)
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LONG_L k1, 0(k0)
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nop
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sw sp, 0(k1) /* store sp in preempted task TCB */
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LONG_S sp, 0(k1) /* store sp in preempted task TCB */
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PTR_LA k0, rt_interrupt_to_thread
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lw k1, 0(k0)
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LONG_L k1, 0(k0)
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nop
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lw sp, 0(k1) /* get new task stack pointer */
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LONG_L sp, 0(k1) /* get new task stack pointer */
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j spurious_interrupt
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nop
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@ -1,11 +1,12 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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* 2020-07-26 lizhirui Add xtlb exception entry
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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@ -26,6 +27,11 @@ tlb_refill_exception:
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b _general_exception_handler
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nop
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/* 0x080 - XTLB refill handler */
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.org ebase_start + 0x080
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b _general_exception_handler
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nop
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/* 0x100 - Cache error handler */
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.org ebase_start + 0x100
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j cache_error_handler
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@ -206,6 +206,8 @@
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li v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
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and v0, v1
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or v0, a0
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li v1, (ST0_KX | ST0_SX | ST0_UX)
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or v0, v1
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mtc0 v0, CP0_STATUS
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LONG_L v1, PT_EPC(sp)
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MTC0 v1, CP0_EPC
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