add operating definitions of UART0 to UART5
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05e9233de6
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@ -10,6 +10,7 @@
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard the first version
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* 2014-01-11 RTsien add definitions of UART0 to UART5
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*/
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#include <rthw.h>
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@ -162,14 +163,18 @@ static const struct rt_uart_ops am33xx_uart_ops =
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am33xx_getc,
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};
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/* UART1 device driver structure */
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struct serial_ringbuffer uart1_int_rx;
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struct am33xx_uart uart1 =
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/* UART device driver structure */
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struct serial_ringbuffer uart_int_rx[6];
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struct am33xx_uart uart[6] =
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{
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UART0_BASE,
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UART0_INT,
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{UART0_BASE,UART0_INT},
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{UART1_BASE,UART1_INT},
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{UART2_BASE,UART2_INT},
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{UART3_BASE,UART3_INT},
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{UART4_BASE,UART4_INT},
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{UART5_BASE,UART5_INT}
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};
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struct rt_serial_device serial1;
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struct rt_serial_device serial[6];
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#define write_reg(base, value) *(int*)(base) = value
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#define read_reg(base) *(int*)(base)
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@ -219,11 +224,46 @@ static void start_uart_clk(void)
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;
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/* enable uart1 */
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#ifdef RT_USING_UART1
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CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart1 clk */
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while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART2
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CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart2 clk */
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while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART3
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CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart3 clk */
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while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART4
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CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart4 clk */
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while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART5
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CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart5 clk */
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while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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/* Waiting for the L4LS UART clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10)))
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;
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@ -236,44 +276,177 @@ static void config_pinmux(void)
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ctlm_base = AM33XX_CTLM_REGS;
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/* make sure the pin mux is OK for uart */
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#ifdef RT_USING_UART1
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REG32(ctlm_base + 0x800 + 0x180) = 0x20;
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REG32(ctlm_base + 0x800 + 0x184) = 0x00;
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#endif
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#ifdef RT_USING_UART2
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REG32(ctlm_base + 0x800 + 0x150) = 0x20;
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REG32(ctlm_base + 0x800 + 0x154) = 0x00;
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#endif
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#ifdef RT_USING_UART3
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REG32(ctlm_base + 0x800 + 0x164) = 0x01;
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#endif
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#ifdef RT_USING_UART4
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REG32(ctlm_base + 0x800 + 0x070) = 0x26;
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REG32(ctlm_base + 0x800 + 0x074) = 0x06;
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#endif
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#ifdef RT_USING_UART5
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REG32(ctlm_base + 0x800 + 0x0C4) = 0x24;
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REG32(ctlm_base + 0x800 + 0x0C0) = 0x04;
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#endif
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}
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int rt_hw_serial_init(void)
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{
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struct am33xx_uart* uart;
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struct serial_configure config;
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uart = &uart1;
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uart->base = UART1_BASE;
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struct serial_configure config[6];
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poweron_per_domain();
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start_uart_clk();
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config_pinmux();
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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serial1.ops = &am33xx_uart_ops;
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serial1.int_rx = &uart1_int_rx;
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serial1.config = config;
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#ifdef RT_USING_UART0
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config[0].baud_rate = BAUD_RATE_115200;
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config[0].bit_order = BIT_ORDER_LSB;
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config[0].data_bits = DATA_BITS_8;
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config[0].parity = PARITY_NONE;
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config[0].stop_bits = STOP_BITS_1;
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config[0].invert = NRZ_NORMAL;
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serial[0].ops = &am33xx_uart_ops;
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serial[0].int_rx = &uart_int_rx[0];
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serial[0].config = config[0];
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/* enable RX interrupt */
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UART_IER_REG(uart->base) = 0x01;
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UART_IER_REG(uart[0].base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart->irq, am33xx_uart_isr, &serial1, "uart1");
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rt_hw_interrupt_control(uart->irq, 0, 0);
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rt_hw_interrupt_mask(uart->irq);
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/* register UART1 device */
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rt_hw_serial_register(&serial1, "uart1",
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rt_hw_interrupt_install(uart[0].irq, am33xx_uart_isr, &serial[0], "uart0");
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rt_hw_interrupt_control(uart[0].irq, 0, 0);
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rt_hw_interrupt_mask(uart[0].irq);
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/* register UART0 device */
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rt_hw_serial_register(&serial[0], "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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uart);
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&uart[0]);
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#endif
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#ifdef RT_USING_UART1
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config[1].baud_rate = BAUD_RATE_115200;
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config[1].bit_order = BIT_ORDER_LSB;
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config[1].data_bits = DATA_BITS_8;
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config[1].parity = PARITY_NONE;
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config[1].stop_bits = STOP_BITS_1;
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config[1].invert = NRZ_NORMAL;
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serial[1].ops = &am33xx_uart_ops;
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serial[1].int_rx = &uart_int_rx[1];
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serial[1].config = config[1];
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/* enable RX interrupt */
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UART_IER_REG(uart[1].base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart[1].irq, am33xx_uart_isr, &serial[1], "uart1");
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rt_hw_interrupt_control(uart[1].irq, 0, 0);
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rt_hw_interrupt_mask(uart[1].irq);
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/* register UART0 device */
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rt_hw_serial_register(&serial[1], "uart1",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&uart[1]);
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#endif
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#ifdef RT_USING_UART2
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config[2].baud_rate = BAUD_RATE_115200;
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config[2].bit_order = BIT_ORDER_LSB;
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config[2].data_bits = DATA_BITS_8;
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config[2].parity = PARITY_NONE;
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config[2].stop_bits = STOP_BITS_1;
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config[2].invert = NRZ_NORMAL;
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serial[2].ops = &am33xx_uart_ops;
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serial[2].int_rx = &uart_int_rx[2];
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serial[2].config = config[2];
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/* enable RX interrupt */
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UART_IER_REG(uart[2].base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart[2].irq, am33xx_uart_isr, &serial[2], "uart2");
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rt_hw_interrupt_control(uart[2].irq, 0, 0);
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rt_hw_interrupt_mask(uart[2].irq);
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/* register UART2 device */
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rt_hw_serial_register(&serial[2], "uart2",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&uart[2]);
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#endif
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#ifdef RT_USING_UART3
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config[3].baud_rate = BAUD_RATE_115200;
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config[3].bit_order = BIT_ORDER_LSB;
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config[3].data_bits = DATA_BITS_8;
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config[3].parity = PARITY_NONE;
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config[3].stop_bits = STOP_BITS_1;
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config[3].invert = NRZ_NORMAL;
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serial[3].ops = &am33xx_uart_ops;
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serial[3].int_rx = &uart_int_rx[3];
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serial[3].config = config[3];
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/* enable RX interrupt */
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UART_IER_REG(uart[3].base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart[3].irq, am33xx_uart_isr, &serial[3], "uart3");
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rt_hw_interrupt_control(uart[3].irq, 0, 0);
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rt_hw_interrupt_mask(uart[3].irq);
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/* register UART3 device */
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rt_hw_serial_register(&serial[3], "uart3",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&uart[3]);
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#endif
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#ifdef RT_USING_UART4
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config[4].baud_rate = BAUD_RATE_115200;
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config[4].bit_order = BIT_ORDER_LSB;
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config[4].data_bits = DATA_BITS_8;
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config[4].parity = PARITY_NONE;
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config[4].stop_bits = STOP_BITS_1;
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config[4].invert = NRZ_NORMAL;
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serial[4].ops = &am33xx_uart_ops;
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serial[4].int_rx = &uart_int_rx[4];
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serial[4].config = config[4];
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/* enable RX interrupt */
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UART_IER_REG(uart[4].base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart[4].irq, am33xx_uart_isr, &serial[4], "uart4");
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rt_hw_interrupt_control(uart[4].irq, 0, 0);
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rt_hw_interrupt_mask(uart[4].irq);
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/* register UART4 device */
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rt_hw_serial_register(&serial[4], "uart4",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&uart[4]);
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#endif
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#ifdef RT_USING_UART5
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config[5].baud_rate = BAUD_RATE_115200;
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config[5].bit_order = BIT_ORDER_LSB;
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config[5].data_bits = DATA_BITS_8;
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config[5].parity = PARITY_NONE;
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config[5].stop_bits = STOP_BITS_1;
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config[5].invert = NRZ_NORMAL;
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serial[5].ops = &am33xx_uart_ops;
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serial[5].int_rx = &uart_int_rx[5];
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serial[5].config = config[5];
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/* enable RX interrupt */
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UART_IER_REG(uart[5].base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart[5].irq, am33xx_uart_isr, &serial[5], "uart5");
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rt_hw_interrupt_control(uart[5].irq, 0, 0);
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rt_hw_interrupt_mask(uart[5].irq);
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/* register UART4 device */
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rt_hw_serial_register(&serial[5], "uart5",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&uart[5]);
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#endif
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return 0;
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}
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