diff --git a/bsp/stm32f107/.config b/bsp/stm32f107/.config new file mode 100644 index 0000000000..855e8b01bd --- /dev/null +++ b/bsp/stm32f107/.config @@ -0,0 +1,372 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +# CONFIG_RT_USING_MODULE is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M3=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +# CONFIG_RT_USING_USER_MAIN is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_LWP is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +# CONFIG_RT_LWIP_RAW is not set +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +CONFIG_RT_USING_RTT_CMSIS=y + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# +# CONFIG_PKG_USING_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_STM32F1=y +# CONFIG_RT_USING_UART1 is not set +CONFIG_RT_USING_UART2=y +# CONFIG_RT_USING_UART3 is not set diff --git a/bsp/stm32f107/Kconfig b/bsp/stm32f107/Kconfig new file mode 100644 index 0000000000..74b4e6f380 --- /dev/null +++ b/bsp/stm32f107/Kconfig @@ -0,0 +1,36 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example: default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config $ENV_DIR + string + option env="ENV_ROOT" + default "/" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + + +config SOC_STM32F1 + bool + select ARCH_ARM_CORTEX_M3 + default y + +source "$BSP_DIR/drivers/Kconfig" + diff --git a/bsp/stm32f107/applications/application.c b/bsp/stm32f107/applications/application.c index 81c72e0cd5..6312734000 100644 --- a/bsp/stm32f107/applications/application.c +++ b/bsp/stm32f107/applications/application.c @@ -10,6 +10,7 @@ * Change Logs: * Date Author Notes * 2009-01-05 Bernard the first version + * 2018-08-17 whj remove finsh_set_device add components */ /** @@ -38,6 +39,11 @@ extern int lwip_system_init(void); void rt_init_thread_entry(void* parameter) { +#ifdef RT_USING_COMPONENTS_INIT + /* initialization RT-Thread Components */ + rt_components_init(); +#endif + { extern void rt_platform_init(void); rt_platform_init(); @@ -72,11 +78,6 @@ void rt_init_thread_entry(void* parameter) rt_kprintf("TCP/IP initialized!\n"); #endif -#ifdef RT_USING_FINSH - /* initialize finsh */ - finsh_system_init(); - finsh_set_device(RT_CONSOLE_DEVICE_NAME); -#endif } int rt_application_init(void) diff --git a/bsp/stm32f107/drivers/Kconfig b/bsp/stm32f107/drivers/Kconfig new file mode 100644 index 0000000000..5f55ee1019 --- /dev/null +++ b/bsp/stm32f107/drivers/Kconfig @@ -0,0 +1,11 @@ +config RT_USING_UART1 + bool "Enable UART1 (PA9/10)" + default n + +config RT_USING_UART2 + bool "Enable UART2 (PD5/6)" + default y + +config RT_USING_UART3 + bool "Enable UART3 (PC10/11)" + default n diff --git a/bsp/stm32f107/drivers/SConscript b/bsp/stm32f107/drivers/SConscript index 43d7f2c19c..1be1cfe8ce 100644 --- a/bsp/stm32f107/drivers/SConscript +++ b/bsp/stm32f107/drivers/SConscript @@ -16,6 +16,13 @@ platform.c if GetDepend('RT_USING_LWIP'): src += ['stm32_eth.c'] +if GetDepend(['RT_USING_PIN']): + src += ['gpio.c'] + +# add Ethernet drivers. +if GetDepend('RT_USING_RTC'): + src += ['stm32f1_rtc.c'] + if GetDepend('RT_USING_SPI'): src += ['rt_stm32f10x_spi.c'] diff --git a/bsp/stm32f107/drivers/board.c b/bsp/stm32f107/drivers/board.c index 35665f660b..9f70058c37 100644 --- a/bsp/stm32f107/drivers/board.c +++ b/bsp/stm32f107/drivers/board.c @@ -10,6 +10,7 @@ * Change Logs: * Date Author Notes * 2009-01-05 Bernard first implementation + * 2018-08-17 whj add to new rt_console_set_device */ #include @@ -67,8 +68,14 @@ void rt_hw_board_init(void) /* Configure the SysTick */ SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND ); + rt_components_board_init(); + rt_hw_usart_init(); + +#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + } /*@}*/ diff --git a/bsp/stm32f107/drivers/gpio.c b/bsp/stm32f107/drivers/gpio.c new file mode 100644 index 0000000000..e0778f35d5 --- /dev/null +++ b/bsp/stm32f107/drivers/gpio.c @@ -0,0 +1,865 @@ +/* + * File : gpio.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2015-03-24 Bright the first version + * 2016-05-23 Margguo@gmail.com Add 48 pins IC define + */ + +#include +#include +#include + +#ifdef RT_USING_PIN + +#define STM32F10X_PIN_NUMBERS 100 //[48, 64, 100, 144 ] + +#define __STM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index} +#define __STM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0} + +/* STM32 GPIO driver */ +struct pin_index +{ + int index; + uint32_t rcc; + GPIO_TypeDef *gpio; + uint32_t pin; + uint8_t port_source; + uint8_t pin_source; +}; + +static const struct pin_index pins[] = +{ +#if (STM32F10X_PIN_NUMBERS == 48) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, APB2, C, 13), + __STM32_PIN(3, APB2, C, 14), + __STM32_PIN(4, APB2, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(10, APB2, A, 0), + __STM32_PIN(11, APB2, A, 1), + __STM32_PIN(12, APB2, A, 2), + __STM32_PIN(13, APB2, A, 3), + __STM32_PIN(14, APB2, A, 4), + __STM32_PIN(15, APB2, A, 5), + __STM32_PIN(16, APB2, A, 6), + __STM32_PIN(17, APB2, A, 7), + __STM32_PIN(18, APB2, B, 0), + __STM32_PIN(19, APB2, B, 1), + __STM32_PIN(20, APB2, B, 2), + __STM32_PIN(21, APB2, B, 10), + __STM32_PIN(22, APB2, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(25, APB2, B, 12), + __STM32_PIN(26, APB2, B, 13), + __STM32_PIN(27, APB2, B, 14), + __STM32_PIN(28, APB2, B, 15), + __STM32_PIN(29, APB2, A, 8), + __STM32_PIN(30, APB2, A, 9), + __STM32_PIN(31, APB2, A, 10), + __STM32_PIN(32, APB2, A, 11), + __STM32_PIN(33, APB2, A, 12), + __STM32_PIN(34, APB2, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(37, APB2, A, 14), + __STM32_PIN(38, APB2, A, 15), + __STM32_PIN(39, APB2, B, 3), + __STM32_PIN(40, APB2, B, 4), + __STM32_PIN(41, APB2, B, 5), + __STM32_PIN(42, APB2, B, 6), + __STM32_PIN(43, APB2, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(45, APB2, B, 8), + __STM32_PIN(46, APB2, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + +#endif +#if (STM32F10X_PIN_NUMBERS == 64) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, APB2, C, 13), + __STM32_PIN(3, APB2, C, 14), + __STM32_PIN(4, APB2, C, 15), + __STM32_PIN(5, APB2, D, 0), + __STM32_PIN(6, APB2, D, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(8, APB2, C, 0), + __STM32_PIN(9, APB2, C, 1), + __STM32_PIN(10, APB2, C, 2), + __STM32_PIN(11, APB2, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(14, APB2, A, 0), + __STM32_PIN(15, APB2, A, 1), + __STM32_PIN(16, APB2, A, 2), + __STM32_PIN(17, APB2, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(20, APB2, A, 4), + __STM32_PIN(21, APB2, A, 5), + __STM32_PIN(22, APB2, A, 6), + __STM32_PIN(23, APB2, A, 7), + __STM32_PIN(24, APB2, C, 4), + __STM32_PIN(25, APB2, C, 5), + __STM32_PIN(26, APB2, B, 0), + __STM32_PIN(27, APB2, B, 1), + __STM32_PIN(28, APB2, B, 2), + __STM32_PIN(29, APB2, B, 10), + __STM32_PIN(30, APB2, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(33, APB2, B, 12), + __STM32_PIN(34, APB2, B, 13), + __STM32_PIN(35, APB2, B, 14), + __STM32_PIN(36, APB2, B, 15), + __STM32_PIN(37, APB2, C, 6), + __STM32_PIN(38, APB2, C, 7), + __STM32_PIN(39, APB2, C, 8), + __STM32_PIN(40, APB2, C, 9), + __STM32_PIN(41, APB2, A, 8), + __STM32_PIN(42, APB2, A, 9), + __STM32_PIN(43, APB2, A, 10), + __STM32_PIN(44, APB2, A, 11), + __STM32_PIN(45, APB2, A, 12), + __STM32_PIN(46, APB2, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(49, APB2, A, 14), + __STM32_PIN(50, APB2, A, 15), + __STM32_PIN(51, APB2, C, 10), + __STM32_PIN(52, APB2, C, 11), + __STM32_PIN(53, APB2, C, 12), + __STM32_PIN(54, APB2, D, 2), + __STM32_PIN(55, APB2, B, 3), + __STM32_PIN(56, APB2, B, 4), + __STM32_PIN(57, APB2, B, 5), + __STM32_PIN(58, APB2, B, 6), + __STM32_PIN(59, APB2, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(61, APB2, B, 8), + __STM32_PIN(62, APB2, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32F10X_PIN_NUMBERS == 100) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, APB2, E, 2), + __STM32_PIN(2, APB2, E, 3), + __STM32_PIN(3, APB2, E, 4), + __STM32_PIN(4, APB2, E, 5), + __STM32_PIN(5, APB2, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, APB2, C, 13), + __STM32_PIN(8, APB2, C, 14), + __STM32_PIN(9, APB2, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(15, APB2, C, 0), + __STM32_PIN(16, APB2, C, 1), + __STM32_PIN(17, APB2, C, 2), + __STM32_PIN(18, APB2, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(23, APB2, A, 0), + __STM32_PIN(24, APB2, A, 1), + __STM32_PIN(25, APB2, A, 2), + __STM32_PIN(26, APB2, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(29, APB2, A, 4), + __STM32_PIN(30, APB2, A, 5), + __STM32_PIN(31, APB2, A, 6), + __STM32_PIN(32, APB2, A, 7), + __STM32_PIN(33, APB2, C, 4), + __STM32_PIN(34, APB2, C, 5), + __STM32_PIN(35, APB2, B, 0), + __STM32_PIN(36, APB2, B, 1), + __STM32_PIN(37, APB2, B, 2), + __STM32_PIN(38, APB2, E, 7), + __STM32_PIN(39, APB2, E, 8), + __STM32_PIN(40, APB2, E, 9), + __STM32_PIN(41, APB2, E, 10), + __STM32_PIN(42, APB2, E, 11), + __STM32_PIN(43, APB2, E, 12), + __STM32_PIN(44, APB2, E, 13), + __STM32_PIN(45, APB2, E, 14), + __STM32_PIN(46, APB2, E, 15), + __STM32_PIN(47, APB2, B, 10), + __STM32_PIN(48, APB2, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(51, APB2, B, 12), + __STM32_PIN(52, APB2, B, 13), + __STM32_PIN(53, APB2, B, 14), + __STM32_PIN(54, APB2, B, 15), + __STM32_PIN(55, APB2, D, 8), + __STM32_PIN(56, APB2, D, 9), + __STM32_PIN(57, APB2, D, 10), + __STM32_PIN(58, APB2, D, 11), + __STM32_PIN(59, APB2, D, 12), + __STM32_PIN(60, APB2, D, 13), + __STM32_PIN(61, APB2, D, 14), + __STM32_PIN(62, APB2, D, 15), + __STM32_PIN(63, APB2, C, 6), + __STM32_PIN(64, APB2, C, 7), + __STM32_PIN(65, APB2, C, 8), + __STM32_PIN(66, APB2, C, 9), + __STM32_PIN(67, APB2, A, 8), + __STM32_PIN(68, APB2, A, 9), + __STM32_PIN(69, APB2, A, 10), + __STM32_PIN(70, APB2, A, 11), + __STM32_PIN(71, APB2, A, 12), + __STM32_PIN(72, APB2, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(76, APB2, A, 14), + __STM32_PIN(77, APB2, A, 15), + __STM32_PIN(78, APB2, C, 10), + __STM32_PIN(79, APB2, C, 11), + __STM32_PIN(80, APB2, C, 12), + __STM32_PIN(81, APB2, D, 0), + __STM32_PIN(82, APB2, D, 1), + __STM32_PIN(83, APB2, D, 2), + __STM32_PIN(84, APB2, D, 3), + __STM32_PIN(85, APB2, D, 4), + __STM32_PIN(86, APB2, D, 5), + __STM32_PIN(87, APB2, D, 6), + __STM32_PIN(88, APB2, D, 7), + __STM32_PIN(89, APB2, B, 3), + __STM32_PIN(90, APB2, B, 4), + __STM32_PIN(91, APB2, B, 5), + __STM32_PIN(92, APB2, B, 6), + __STM32_PIN(93, APB2, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(95, APB2, B, 8), + __STM32_PIN(96, APB2, B, 9), + __STM32_PIN(97, APB2, E, 0), + __STM32_PIN(98, APB2, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32F10X_PIN_NUMBERS == 144) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, APB2, E, 2), + __STM32_PIN(2, APB2, E, 3), + __STM32_PIN(3, APB2, E, 4), + __STM32_PIN(4, APB2, E, 5), + __STM32_PIN(5, APB2, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, APB2, C, 13), + __STM32_PIN(8, APB2, C, 14), + __STM32_PIN(9, APB2, C, 15), + + __STM32_PIN(10, APB2, F, 0), + __STM32_PIN(11, APB2, F, 1), + __STM32_PIN(12, APB2, F, 2), + __STM32_PIN(13, APB2, F, 3), + __STM32_PIN(14, APB2, F, 4), + __STM32_PIN(15, APB2, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(18, APB2, F, 6), + __STM32_PIN(19, APB2, F, 7), + __STM32_PIN(20, APB2, F, 8), + __STM32_PIN(21, APB2, F, 9), + __STM32_PIN(22, APB2, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(26, APB2, C, 0), + __STM32_PIN(27, APB2, C, 1), + __STM32_PIN(28, APB2, C, 2), + __STM32_PIN(29, APB2, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(34, APB2, A, 0), + __STM32_PIN(35, APB2, A, 1), + __STM32_PIN(36, APB2, A, 2), + __STM32_PIN(37, APB2, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(40, APB2, A, 4), + __STM32_PIN(41, APB2, A, 5), + __STM32_PIN(42, APB2, A, 6), + __STM32_PIN(43, APB2, A, 7), + __STM32_PIN(44, APB2, C, 4), + __STM32_PIN(45, APB2, C, 5), + __STM32_PIN(46, APB2, B, 0), + __STM32_PIN(47, APB2, B, 1), + __STM32_PIN(48, APB2, B, 2), + __STM32_PIN(49, APB2, F, 11), + __STM32_PIN(50, APB2, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, APB2, F, 13), + __STM32_PIN(54, APB2, F, 14), + __STM32_PIN(55, APB2, F, 15), + __STM32_PIN(56, APB2, G, 0), + __STM32_PIN(57, APB2, G, 1), + __STM32_PIN(58, APB2, E, 7), + __STM32_PIN(59, APB2, E, 8), + __STM32_PIN(60, APB2, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(63, APB2, E, 10), + __STM32_PIN(64, APB2, E, 11), + __STM32_PIN(65, APB2, E, 12), + __STM32_PIN(66, APB2, E, 13), + __STM32_PIN(67, APB2, E, 14), + __STM32_PIN(68, APB2, E, 15), + __STM32_PIN(69, APB2, B, 10), + __STM32_PIN(70, APB2, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(73, APB2, B, 12), + __STM32_PIN(74, APB2, B, 13), + __STM32_PIN(75, APB2, B, 14), + __STM32_PIN(76, APB2, B, 15), + __STM32_PIN(77, APB2, D, 8), + __STM32_PIN(78, APB2, D, 9), + __STM32_PIN(79, APB2, D, 10), + __STM32_PIN(80, APB2, D, 11), + __STM32_PIN(81, APB2, D, 12), + __STM32_PIN(82, APB2, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(85, APB2, D, 14), + __STM32_PIN(86, APB2, D, 15), + __STM32_PIN(87, APB2, G, 2), + __STM32_PIN(88, APB2, G, 3), + __STM32_PIN(89, APB2, G, 4), + __STM32_PIN(90, APB2, G, 5), + __STM32_PIN(91, APB2, G, 6), + __STM32_PIN(92, APB2, G, 7), + __STM32_PIN(93, APB2, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(96, APB2, C, 6), + __STM32_PIN(97, APB2, C, 7), + __STM32_PIN(98, APB2, C, 8), + __STM32_PIN(99, APB2, C, 9), + __STM32_PIN(100, APB2, A, 8), + __STM32_PIN(101, APB2, A, 9), + __STM32_PIN(102, APB2, A, 10), + __STM32_PIN(103, APB2, A, 11), + __STM32_PIN(104, APB2, A, 12), + __STM32_PIN(105, APB2, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(109, APB2, A, 14), + __STM32_PIN(110, APB2, A, 15), + __STM32_PIN(111, APB2, C, 10), + __STM32_PIN(112, APB2, C, 11), + __STM32_PIN(113, APB2, C, 12), + __STM32_PIN(114, APB2, D, 0), + __STM32_PIN(115, APB2, D, 1), + __STM32_PIN(116, APB2, D, 2), + __STM32_PIN(117, APB2, D, 3), + __STM32_PIN(118, APB2, D, 4), + __STM32_PIN(119, APB2, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(122, APB2, D, 6), + __STM32_PIN(123, APB2, D, 7), + __STM32_PIN(124, APB2, G, 9), + __STM32_PIN(125, APB2, G, 10), + __STM32_PIN(126, APB2, G, 11), + __STM32_PIN(127, APB2, G, 12), + __STM32_PIN(128, APB2, G, 13), + __STM32_PIN(129, APB2, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(132, APB2, G, 15), + __STM32_PIN(133, APB2, B, 3), + __STM32_PIN(134, APB2, B, 4), + __STM32_PIN(135, APB2, B, 5), + __STM32_PIN(136, APB2, B, 6), + __STM32_PIN(137, APB2, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(139, APB2, B, 8), + __STM32_PIN(140, APB2, B, 9), + __STM32_PIN(141, APB2, E, 0), + __STM32_PIN(142, APB2, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + rt_uint32_t irqbit; + enum IRQn irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn }, + {GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn }, + {GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn }, + {GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn }, + {GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn }, + {GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn }, + {GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn }, + {GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn }, + {GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn }, + {GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn }, + {GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn}, + {GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn}, + {GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn}, + {GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn}, + {GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn}, + {GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn}, +}; +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items)/sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + if (value == PIN_LOW) + { + GPIO_ResetBits(index->gpio, index->pin); + } + else + { + GPIO_SetBits(index->gpio, index->pin); + } +} + +int stm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + + return value; +} + +void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + RCC_APB2PeriphClockCmd(index->rcc, ENABLE); + + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + } + else + { + /* input setting:default. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + } + GPIO_Init(index->gpio, &GPIO_InitStructure); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for(i = 0; i < 32; i++) + { + if((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if(mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; +rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if(pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if(pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if(pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + if(enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if(pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ + RCC_APB2PeriphClockCmd(index->rcc, ENABLE); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(index->gpio, &GPIO_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel= irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority= 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority= 2; + NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_EXTILineConfig(index->port_source, index->pin_source); + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + switch(pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + } + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + rt_hw_interrupt_enable(level); + } + else if(enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if(irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_Init(&EXTI_InitStructure); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _stm32_pin_ops = +{ + stm32_pin_mode, + stm32_pin_write, + stm32_pin_read, + stm32_pin_attach_irq, + stm32_pin_detach_irq, + stm32_pin_irq_enable, +}; + +int stm32_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(stm32_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + EXTI_ClearITPendingBit(pin_irq_map[irqno].irqbit); + if(pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} +void EXTI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(0); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(1); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(2); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(3); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(4); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI9_5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if(EXTI_GetITStatus(EXTI_Line5) != RESET) + { + pin_irq_hdr(5); + } + if(EXTI_GetITStatus(EXTI_Line6) != RESET) + { + pin_irq_hdr(6); + } + if(EXTI_GetITStatus(EXTI_Line7) != RESET) + { + pin_irq_hdr(7); + } + if(EXTI_GetITStatus(EXTI_Line8) != RESET) + { + pin_irq_hdr(8); + } + if(EXTI_GetITStatus(EXTI_Line9) != RESET) + { + pin_irq_hdr(9); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI15_10_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if(EXTI_GetITStatus(EXTI_Line10) != RESET) + { + pin_irq_hdr(10); + } + if(EXTI_GetITStatus(EXTI_Line11) != RESET) + { + pin_irq_hdr(11); + } + if(EXTI_GetITStatus(EXTI_Line12) != RESET) + { + pin_irq_hdr(12); + } + if(EXTI_GetITStatus(EXTI_Line13) != RESET) + { + pin_irq_hdr(13); + } + if(EXTI_GetITStatus(EXTI_Line14) != RESET) + { + pin_irq_hdr(14); + } + if(EXTI_GetITStatus(EXTI_Line15) != RESET) + { + pin_irq_hdr(15); + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/stm32f107/drivers/gpio.h b/bsp/stm32f107/drivers/gpio.h new file mode 100644 index 0000000000..03b744b333 --- /dev/null +++ b/bsp/stm32f107/drivers/gpio.h @@ -0,0 +1,30 @@ +/* + * File : gpio.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2015-01-05 Bernard the first version + */ +#ifndef GPIO_H__ +#define GPIO_H__ + + +struct stm32_hw_pin_userdata +{ + int pin; + uint32_t mode; +}; + +#define PIN_USERDATA_END {-1,0} + +extern struct stm32_hw_pin_userdata stm32_pins[]; + +int stm32_hw_pin_init(void); + +#endif diff --git a/bsp/stm32f107/drivers/stm32f1_rtc.c b/bsp/stm32f107/drivers/stm32f1_rtc.c new file mode 100644 index 0000000000..68fab1ce00 --- /dev/null +++ b/bsp/stm32f107/drivers/stm32f1_rtc.c @@ -0,0 +1,163 @@ +/* + * File : stm32f1_rtc.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version. + * 2011-11-26 aozima implementation time. + * 2015-07-16 FlyM rename rtc to stm32f1_rtc. remove finsh export function + */ + +#include +#include +#include "stm32f1_rtc.h" + +static struct rt_device rtc; +static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + if (dev->rx_indicate != RT_NULL) + { + /* Open Interrupt */ + } + + return RT_EOK; +} + +static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_time_t *time; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + time = (rt_time_t *)args; + /* read device */ + *time = RTC_GetCounter(); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + time = (rt_time_t *)args; + + /* Enable PWR and BKP clocks */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + + /* Allow access to BKP Domain */ + PWR_BackupAccessCmd(ENABLE); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + /* Change the current time */ + RTC_SetCounter(*time); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + BKP_WriteBackupRegister(BKP_DR1, 0xA5A5); + } + break; + } + + return RT_EOK; +} + +/******************************************************************************* +* Function Name : RTC_Configuration +* Description : Configures the RTC. +* Input : None +* Output : None +* Return : 0 reday,-1 error. +*******************************************************************************/ +int RTC_Configuration(void) +{ + u32 count=0x200000; + + /* Enable PWR and BKP clocks */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + + /* Allow access to BKP Domain */ + PWR_BackupAccessCmd(ENABLE); + + /* Reset Backup Domain */ + BKP_DeInit(); + + /* Enable LSE */ + RCC_LSEConfig(RCC_LSE_ON); + /* Wait till LSE is ready */ + while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) ); + if ( count == 0 ) + { + return -1; + } + + /* Select LSE as RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + /* Enable RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC registers synchronization */ + RTC_WaitForSynchro(); + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + /* Set RTC prescaler: set RTC period to 1sec */ + RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */ + + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + + return 0; +} + +void rt_hw_rtc_init(void) +{ + rtc.type = RT_Device_Class_RTC; + + if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5) + { + rt_kprintf("rtc is not configured\n"); + rt_kprintf("please configure with set_date and set_time\n"); + if ( RTC_Configuration() != 0) + { + rt_kprintf("rtc configure fail...\r\n"); + return ; + } + } + else + { + /* Wait for RTC registers synchronization */ + RTC_WaitForSynchro(); + } + + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rt_rtc_open; + rtc.close = RT_NULL; + rtc.read = rt_rtc_read; + rtc.write = RT_NULL; + rtc.control = rt_rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + + return; +} + + diff --git a/bsp/stm32f107/drivers/stm32f1_rtc.h b/bsp/stm32f107/drivers/stm32f1_rtc.h new file mode 100644 index 0000000000..02f463fce5 --- /dev/null +++ b/bsp/stm32f107/drivers/stm32f1_rtc.h @@ -0,0 +1,20 @@ +/* + * File : stm32f1_rtc.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +#ifndef __STM32F1_RTC_H__ +#define __STM32F1_RTC_H__ + +void rt_hw_rtc_init(void); + +#endif diff --git a/bsp/stm32f107/drivers/usart.c b/bsp/stm32f107/drivers/usart.c index 89528d54bc..c82fba3ee3 100644 --- a/bsp/stm32f107/drivers/usart.c +++ b/bsp/stm32f107/drivers/usart.c @@ -8,11 +8,12 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode - * 2013-05-13 aozima update for kehong-lingtai. - * 2015-01-31 armink make sure the serial transmit complete in putc() + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode + * 2013-05-13 aozima update for kehong-lingtai. + * 2015-01-31 armink make sure the serial transmit complete in putc() + * 2018-08-17 whj add to usart3 */ #include "stm32f10x.h" @@ -38,6 +39,11 @@ #define UART2_GPIO GPIOA #endif +/* USART3_REMAP = 1 */ +#define UART3_GPIO_TX GPIO_Pin_10 +#define UART3_GPIO_RX GPIO_Pin_11 +#define UART3_GPIO GPIOC + /* STM32 uart driver */ struct stm32_uart { @@ -184,7 +190,7 @@ void USART1_IRQHandler(void) } if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_ORE) == SET) { - USART_ReceiveData(uart->uart_device); + stm32_getc(&serial1); } /* leave interrupt */ rt_interrupt_leave(); @@ -221,7 +227,7 @@ void USART2_IRQHandler(void) } if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_ORE) == SET) { - USART_ReceiveData(uart->uart_device); + stm32_getc(&serial2); } /* leave interrupt */ @@ -229,6 +235,44 @@ void USART2_IRQHandler(void) } #endif /* RT_USING_UART2 */ +#if defined(RT_USING_UART3) +/* UART1 device driver structure */ +struct stm32_uart uart3 = +{ + USART3, + USART3_IRQn, +}; +struct rt_serial_device serial3; + +void USART3_IRQHandler(void) +{ + struct stm32_uart* uart; + + uart = &uart3; + + /* enter interrupt */ + rt_interrupt_enter(); + if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); + } + if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) + { + /* clear interrupt */ + USART_ClearITPendingBit(uart->uart_device, USART_IT_TC); + } + if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_ORE) == SET) + { + stm32_getc(&serial3); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_USING_UART3 */ + static void RCC_Configuration(void) { RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); @@ -252,6 +296,11 @@ static void RCC_Configuration(void) RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); #endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE); +#endif /* RT_USING_UART3 */ } static void GPIO_Configuration(void) @@ -281,6 +330,18 @@ static void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX; GPIO_Init(UART2_GPIO, &GPIO_InitStructure); #endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) + /* Configure USART3 Rx (PC.11) as input floating */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX; + GPIO_Init(UART3_GPIO, &GPIO_InitStructure); + + /* Configure USART3 Tx (PC.10) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX; + GPIO_Init(UART3_GPIO, &GPIO_InitStructure); +#endif /* RT_USING_UART3 */ } static void NVIC_Configuration(struct stm32_uart* uart) @@ -327,9 +388,24 @@ void rt_hw_usart_init(void) NVIC_Configuration(&uart2); - /* register UART1 device */ + /* register UART2 device */ rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) + uart = &uart3; + + config.baud_rate = BAUD_RATE_115200; + serial2.ops = &stm32_uart_ops; + serial2.config = config; + + NVIC_Configuration(&uart3); + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* RT_USING_UART3 */ } diff --git a/bsp/stm32f107/project.uvprojx b/bsp/stm32f107/project.uvprojx index f77addec77..27a78833df 100644 --- a/bsp/stm32f107/project.uvprojx +++ b/bsp/stm32f107/project.uvprojx @@ -346,7 +346,7 @@ STM32F10X_CL, RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - drivers;applications;.;Libraries/STM32F10x_StdPeriph_Driver/inc;Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x;../../components/CMSIS/Include;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/spi;../../components/drivers/include;../../components/drivers/include;../../components/libc/compilers/armlibc;../../components/finsh;../../components/net/lwip-2.0.2/src;../../components/net/lwip-2.0.2/src/include;../../components/net/lwip-2.0.2/src/include/ipv4;../../components/net/lwip-2.0.2/src/arch/include;../../components/net/lwip-2.0.2/src/include/netif;../../components/net/lwip-2.0.2/src/include/posix;../../components/dfs/include;../../components/dfs/filesystems/elmfat + applications;.;drivers;Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\components\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix @@ -376,72 +376,72 @@ - --keep *.o(FSymTab) --keep *.o(VSymTab) + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - Drivers - - - board.c - 1 - drivers/board.c - - - - - stm32f10x_it.c - 1 - drivers/stm32f10x_it.c - - - - - usart.c - 1 - drivers/usart.c - - - - - platform.c - 1 - drivers/platform.c - - - - - stm32_eth.c - 1 - drivers/stm32_eth.c - - - - - rt_stm32f10x_spi.c - 1 - drivers/rt_stm32f10x_spi.c - - - Applications application.c 1 - applications/application.c + applications\application.c startup.c 1 - applications/startup.c + applications\startup.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + + + stm32f10x_it.c + 1 + drivers\stm32f10x_it.c + + + + + usart.c + 1 + drivers\usart.c + + + + + platform.c + 1 + drivers\platform.c + + + + + stm32_eth.c + 1 + drivers\stm32_eth.c + + + + + gpio.c + 1 + drivers\gpio.c @@ -451,175 +451,175 @@ system_stm32f10x.c 1 - Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c + Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c stm32f10x_crc.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c stm32f10x_rcc.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c stm32f10x_wwdg.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c stm32f10x_pwr.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c stm32f10x_exti.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c stm32f10x_bkp.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c stm32f10x_i2c.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c stm32f10x_adc.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c stm32f10x_dac.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c stm32f10x_rtc.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c stm32f10x_fsmc.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c stm32f10x_tim.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c stm32f10x_iwdg.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c stm32f10x_spi.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c stm32f10x_flash.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c stm32f10x_sdio.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c stm32f10x_gpio.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c stm32f10x_usart.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c stm32f10x_dbgmcu.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c stm32f10x_dma.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c stm32f10x_can.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c stm32f10x_cec.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c + Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c misc.c 1 - Libraries/STM32F10x_StdPeriph_Driver/src/misc.c + Libraries\STM32F10x_StdPeriph_Driver\src\misc.c startup_stm32f10x_cl.s 2 - Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s + Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s @@ -629,91 +629,105 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c + + + + + components.c + 1 + ..\..\src\components.c device.c 1 - ../../src/device.c + ..\..\src\device.c idle.c 1 - ../../src/idle.c + ..\..\src\idle.c ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c irq.c 1 - ../../src/irq.c + ..\..\src\irq.c kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c mem.c 1 - ../../src/mem.c + ..\..\src\mem.c + + + + + memheap.c + 1 + ..\..\src\memheap.c mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c object.c 1 - ../../src/object.c + ..\..\src\object.c scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c signal.c 1 - ../../src/signal.c + ..\..\src\signal.c thread.c 1 - ../../src/thread.c + ..\..\src\thread.c timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -723,507 +737,35 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m3/cpuport.c + ..\..\libcpu\arm\cortex-m3\cpuport.c context_rvds.S 2 - ../../libcpu/arm/cortex-m3/context_rvds.S + ..\..\libcpu\arm\cortex-m3\context_rvds.S backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c showmem.c 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - - - spi_core.c - 1 - ../../components/drivers/spi/spi_core.c - - - - - spi_dev.c - 1 - ../../components/drivers/spi/spi_dev.c - - - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - - - - - - - - - - - - - libc - - - libc.c - 1 - ../../components/libc/compilers/armlibc/libc.c - - - - - libc_syms.c - 1 - ../../components/libc/compilers/armlibc/libc_syms.c - - - - - mem_std.c - 1 - ../../components/libc/compilers/armlibc/mem_std.c - - - - - stdio.c - 1 - ../../components/libc/compilers/armlibc/stdio.c - - - - - stubs.c - 1 - ../../components/libc/compilers/armlibc/stubs.c - - - - - time.c - 1 - ../../components/libc/compilers/armlibc/time.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c - - - - - lwIP - - - sys_arch.c - 1 - ../../components/net/lwip-2.0.2/src/arch/sys_arch.c - - - - - api_lib.c - 1 - ../../components/net/lwip-2.0.2/src/api/api_lib.c - - - - - api_msg.c - 1 - ../../components/net/lwip-2.0.2/src/api/api_msg.c - - - - - err.c - 1 - ../../components/net/lwip-2.0.2/src/api/err.c - - - - - netbuf.c - 1 - ../../components/net/lwip-2.0.2/src/api/netbuf.c - - - - - netdb.c - 1 - ../../components/net/lwip-2.0.2/src/api/netdb.c - - - - - netifapi.c - 1 - ../../components/net/lwip-2.0.2/src/api/netifapi.c - - - - - sockets.c - 1 - ../../components/net/lwip-2.0.2/src/api/sockets.c - - - - - tcpip.c - 1 - ../../components/net/lwip-2.0.2/src/api/tcpip.c - - - - - def.c - 1 - ../../components/net/lwip-2.0.2/src/core/def.c - - - - - dns.c - 1 - ../../components/net/lwip-2.0.2/src/core/dns.c - - - - - inet_chksum.c - 1 - ../../components/net/lwip-2.0.2/src/core/inet_chksum.c - - - - - init.c - 1 - ../../components/net/lwip-2.0.2/src/core/init.c - - - - - ip.c - 1 - ../../components/net/lwip-2.0.2/src/core/ip.c - - - - - memp.c - 1 - ../../components/net/lwip-2.0.2/src/core/memp.c - - - - - netif.c - 1 - ../../components/net/lwip-2.0.2/src/core/netif.c - - - - - pbuf.c - 1 - ../../components/net/lwip-2.0.2/src/core/pbuf.c - - - - - raw.c - 1 - ../../components/net/lwip-2.0.2/src/core/raw.c - - - - - stats.c - 1 - ../../components/net/lwip-2.0.2/src/core/stats.c - - - - - sys.c - 1 - ../../components/net/lwip-2.0.2/src/core/sys.c - - - - - tcp.c - 1 - ../../components/net/lwip-2.0.2/src/core/tcp.c - - - - - tcp_in.c - 1 - ../../components/net/lwip-2.0.2/src/core/tcp_in.c - - - - - tcp_out.c - 1 - ../../components/net/lwip-2.0.2/src/core/tcp_out.c - - - - - timeouts.c - 1 - ../../components/net/lwip-2.0.2/src/core/timeouts.c - - - - - udp.c - 1 - ../../components/net/lwip-2.0.2/src/core/udp.c - - - - - ethernet.c - 1 - ../../components/net/lwip-2.0.2/src/netif/ethernet.c - - - - - ethernetif.c - 1 - ../../components/net/lwip-2.0.2/src/netif/ethernetif.c - - - - - lowpan6.c - 1 - ../../components/net/lwip-2.0.2/src/netif/lowpan6.c - - - - - autoip.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/autoip.c - - - - - dhcp.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/dhcp.c - - - - - etharp.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/etharp.c - - - - - icmp.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/icmp.c - - - - - igmp.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/igmp.c - - - - - ip4.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/ip4.c - - - - - ip4_addr.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_addr.c - - - - - ip4_frag.c - 1 - ../../components/net/lwip-2.0.2/src/core/ipv4/ip4_frag.c + ..\..\libcpu\arm\common\showmem.c @@ -1233,42 +775,523 @@ dfs.c 1 - ../../components/dfs/src/dfs.c + ..\..\components\dfs\src\dfs.c dfs_file.c 1 - ../../components/dfs/src/dfs_file.c + ..\..\components\dfs\src\dfs_file.c dfs_fs.c 1 - ../../components/dfs/src/dfs_fs.c + ..\..\components\dfs\src\dfs_fs.c dfs_posix.c 1 - ../../components/dfs/src/dfs_posix.c + ..\..\components\dfs\src\dfs_posix.c + + + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c dfs_elm.c 1 - ../../components/dfs/filesystems/elmfat/dfs_elm.c + ..\..\components\dfs\filesystems\elmfat\dfs_elm.c ff.c 1 - ../../components/dfs/filesystems/elmfat/ff.c + ..\..\components\dfs\filesystems\elmfat\ff.c + + + + + ccsbcs.c + 1 + ..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c + + + + + lwIP + + + sys_arch.c + 1 + ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c + + + + + api_lib.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\api_lib.c + + + + + api_msg.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\api_msg.c + + + + + err.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\err.c + + + + + netbuf.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\netbuf.c + + + + + netdb.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\netdb.c + + + + + netifapi.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\netifapi.c + + + + + sockets.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\sockets.c + + + + + tcpip.c + 1 + ..\..\components\net\lwip-2.0.2\src\api\tcpip.c + + + + + def.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\def.c + + + + + dns.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\dns.c + + + + + inet_chksum.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c + + + + + init.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\init.c + + + + + ip.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ip.c + + + + + memp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\memp.c + + + + + netif.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\netif.c + + + + + pbuf.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\pbuf.c + + + + + raw.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\raw.c + + + + + stats.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\stats.c + + + + + sys.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\sys.c + + + + + tcp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\tcp.c + + + + + tcp_in.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c + + + + + tcp_out.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c + + + + + timeouts.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + + + + udp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\udp.c + + + + + ethernet.c + 1 + ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + + + + ethernetif.c + 1 + ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + + + + lowpan6.c + 1 + ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + + + + autoip.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + + + + dhcp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + + + + etharp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + + + + icmp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + + + + igmp.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + + + + ip4.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + + + + ip4_addr.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + + + + ip4_frag.c + 1 + ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c diff --git a/bsp/stm32f107/rtconfig.h b/bsp/stm32f107/rtconfig.h index 210b165a4d..bc4e8e4232 100644 --- a/bsp/stm32f107/rtconfig.h +++ b/bsp/stm32f107/rtconfig.h @@ -1,158 +1,207 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_THREAD_DEBUG +/* RT-Thread Kernel */ +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ #define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG -/* Using Software Timer */ -/* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 +/* Inter-Thread communication */ -/* SECTION: IPC */ -/* Using Semaphore*/ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX - -/* Using Event */ #define RT_USING_EVENT - -/* Using MailBox */ #define RT_USING_MAILBOX - -/* Using Message Queue */ #define RT_USING_MESSAGEQUEUE -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL +/* Memory Management */ -/* Using Dynamic Heap Management */ +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM #define RT_USING_HEAP -/* Using Small MM */ -#define RT_USING_SMALL_MEM +/* Kernel Device Object */ -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL - -#define RT_USING_SPI - -/* SECTION: Console options */ #define RT_USING_CONSOLE -/* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M3 -// -#define RT_CONSOLE_DEVICE_NAME "uart1" -// +/* RT-Thread Components */ -//
-// #define RT_USING_COMPONENTS_INIT -//
+#define RT_USING_COMPONENTS_INIT + +/* C++ features */ + + +/* Command shell */ -/* SECTION: finsh, a C-Express shell */ #define RT_USING_FINSH -/* Using symbol table */ +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ -/* SECTION: device filesystem */ #define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 #define RT_USING_DFS_ELMFAT -/* Reentrancy (thread safe) of the FatFs module. */ + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT -/* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 -/* Maximum sector size to be handled. */ -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_USING_DFS_DEVFS -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +/* Device Drivers */ -/* SECTION: lwip, a lighwight TCP/IP protocol stack */ -#define RT_USING_LWIP -/* Enable ICMP protocol*/ -#define RT_LWIP_ICMP -/* Enable UDP protocol*/ -#define RT_LWIP_UDP -/* Enable TCP protocol*/ -#define RT_LWIP_TCP -/* Enable DNS */ -#define RT_LWIP_DNS +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_PIN -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +/* Using USB */ -/* ip address of target */ -#define RT_LWIP_IPADDR "192.168.1.30" -/* gateway address of target */ -#define RT_LWIP_GWADDR "192.168.1.1" - -/* mask address of target */ -#define RT_LWIP_MSKADDR "255.255.255.0" - -/* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 - -/* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 - -/* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 -/* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 - -#define CHECKSUM_CHECK_TCP 0 -#define CHECKSUM_CHECK_IP 0 -#define CHECKSUM_CHECK_UDP 0 - -#define CHECKSUM_GEN_TCP 0 -#define CHECKSUM_GEN_IP 0 -#define CHECKSUM_GEN_UDP 0 - -// -// #define RT_USING_CMSIS_OS -// -#define RT_USING_RTT_CMSIS -// -// #define RT_USING_BSP_CMSIS +/* POSIX layer and C standard library */ #define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP202 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_NETIF_LOOPBACK 0 + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + +#define RT_USING_RTT_CMSIS + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + + +/* example package: hello */ + +#define SOC_STM32F1 +#define RT_USING_UART2 + #endif