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[rx] mannual formatted

This commit is contained in:
Meco Man 2021-03-29 07:13:22 +08:00
parent 1ba020f3c8
commit b88e579b62
5 changed files with 80 additions and 80 deletions
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2
bsp/rx/applications/startup.c
View File

@ -90,7 +90,7 @@ int main(void)
{
rt_hw_system_freq_init();
__enable_interrupt();
/* disable interrupt first */
rt_hw_interrupt_disable();

14
bsp/rx/drivers/board.c
View File

@ -17,7 +17,7 @@
*
*/
#pragma vector = VECT_CMT0_CMI0
__interrupt
__interrupt
void SysTick_Handler(void)
{
// __enable_interrupt();
@ -56,7 +56,7 @@ void rt_hw_systick_init(void)
}
void rt_hw_system_freq_init(void)
{
{
/* Declare error flag */
bool err = true;
@ -69,15 +69,15 @@ void rt_hw_system_freq_init(void)
24E6,
PDL_NO_DATA
);
/*
/*
Clock Description Frequency
----------------------------------------
Input Clock Frequency..............12MHz
Internal Clock Frequency...........96MHz
Internal Clock Frequency...........96MHz
Peripheral Clock Frequency.........48MHz
External Bus Clock Frequency.......24MHz */
/* Halt in while loop when RPDL errors detected */
/* Halt in while loop when RPDL errors detected */
while (!err);
}
@ -86,8 +86,8 @@ void rt_hw_system_freq_init(void)
*/
void rt_hw_board_init()
{
rt_hw_system_freq_init();
rt_hw_system_freq_init();
rt_hw_systick_init();
rt_hw_uart_init();
#ifdef RT_USING_CONSOLE

8
bsp/rx/drivers/board.h
View File

@ -2,10 +2,10 @@
#define __BOARD_H__
#define XTAL_FREQUENCY (12000000L)
#define ICLK_MUL (8)
#define PCLK_MUL (4)
#define BCLK_MUL (2)
#define XTAL_FREQUENCY (12000000L)
#define ICLK_MUL (8)
#define PCLK_MUL (4)
#define BCLK_MUL (2)
#define RX62N_SRAM_END 0x0000ffff

58
bsp/rx/drivers/uart.c
View File

@ -22,18 +22,18 @@
/* Clock selection control */
#define SCI_CKS_MIN 0
#define SCI_CKS_MAX 3
#define SCI_CKS_STEP 1
#define SCI_CKS_MIN 0
#define SCI_CKS_MAX 3
#define SCI_CKS_STEP 1
#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a])
#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a])
//#define IER_ADDRESS(a) ((volatile unsigned char *)&(ICU.IER[IER_SCI0_ERI0 + a])/sizeof(unsigned char))
#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) )
#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) )
#define RXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_RXI0]+ ((4*a)/sizeof(unsigned char)))
#define TXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_TXI0]+ ((4*a) / sizeof(unsigned char)))
//#define SCI1_USE_B
@ -44,8 +44,8 @@
#define SourceClk 12000000
#define rpdl_CGC_f_pclk SourceClk * 4
/* Idle output options */
#define SPACE 0
#define MARK 1
#define SPACE 0
#define MARK 1
typedef int UART_ID_Type;
typedef int IRQn_Type;
@ -55,14 +55,14 @@ typedef int IRQn_Type;
struct rx_uart
{
UART_ID_Type UART;
volatile struct st_sci __sfr * sci;
volatile struct st_sci __sfr * sci;
};
static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
#if 1
struct rx_uart *uart;
unsigned char smr_copy;
unsigned char semr_copy;
unsigned char scr_copy;
@ -81,7 +81,7 @@ static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_conf
semr_copy = 0x00u;
scmr_copy = 0x72u;
brr_divider = 0;
switch (uart->UART) {
case 0:
SYSTEM.MSTPCRB.BIT.MSTPB31 = 0;
@ -257,11 +257,11 @@ case 0:
}
/*parity*/
if (cfg->parity == PARITY_ODD)
if (cfg->parity == PARITY_ODD)
smr_copy |= BIT_5;
else if (cfg->parity == PARITY_EVEN)
else if (cfg->parity == PARITY_EVEN)
smr_copy |= BIT_4 | BIT_5;
brr_divider = rpdl_CGC_f_pclk / cfg->baud_rate;
@ -304,13 +304,13 @@ case 0:
}while (bit_interval_counter != 0);
scr_copy = 0x00u;
/*enable rx an tx*/
scr_copy |= BIT_5 | BIT_4 ;
uart->sci->SCR.BYTE &= 0x5B;
uart->sci->SCR.BYTE |= scr_copy;
*(IPR_ADDRESS(uart->UART)) = 5;
uart->sci->SSR.BYTE = 0xC0;
uart->sci->SSR.BYTE &= INV_BIT_5;
@ -363,9 +363,9 @@ case 0:
break;
}
flag |= PDL_SCI_ASYNC |
PDL_SCI_TX_CONNECTED |
PDL_SCI_RX_CONNECTED |
flag |= PDL_SCI_ASYNC |
PDL_SCI_TX_CONNECTED |
PDL_SCI_RX_CONNECTED |
PDL_SCI_CLK_INT_IO ;
/* Configure the RS232 port */
err &= R_SCI_Create(
@ -373,12 +373,12 @@ case 0:
flag,
cfg->baud_rate,
5);
uart->sci->SCR.BYTE |= BIT_4|BIT_5;
__enable_interrupt();
#endif
switch (uart->UART) {
case 0:
@ -430,7 +430,7 @@ case 0:
break;
}
return RT_EOK;
}
@ -464,7 +464,7 @@ static int rx_putc(struct rt_serial_device *serial, char c)
uart = (struct rx_uart *)serial->parent.user_data;
while (uart->sci->SSR.BIT.TDRE == 0);
uart->sci->TDR = c;
return 1;
return 1;
}
static int rx_getc(struct rt_serial_device *serial)
@ -528,15 +528,15 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial2.ops = &rx_uart_ops;
serial2.config = config;
/* register UART1 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR |
RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_RDWR |
RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_STREAM,
uart);
#endif

78
bsp/rx/rtconfig.h
View File

@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
@ -27,9 +27,9 @@
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
/* Using Semaphore*/
@ -72,9 +72,9 @@
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
#define RT_CONSOLE_DEVICE_NAME "uart2"
#define RT_CONSOLE_DEVICE_NAME "uart2"
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
@ -89,17 +89,17 @@
/* Reentrancy (thread safe) of the FatFs module. */
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 2
/* #define RT_DFS_ELM_USE_LFN 1 */
/* #define RT_DFS_ELM_CODE_PAGE 936 */
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
/* #define RT_DFS_ELM_USE_LFN 1 */
/* #define RT_DFS_ELM_CODE_PAGE 936 */
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* #define RT_USING_LWIP */
@ -113,49 +113,49 @@
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
#define RT_LWIP_TCP_PCB_NUM 5
/* Using DHCP */
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF 8192
#define RT_LWIP_TCP_SND_BUF 8192
/* TCP receive window. */
#define RT_LWIP_TCP_WND 8192
#define RT_LWIP_TCP_WND 8192
/* SECTION: RT-Thread/GUI */
/* #define RT_USING_RTGUI */
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 12
#define RTGUI_NAME_MAX 12
/* support 16 weight font */
#define RTGUI_USING_FONT16
/* support Chinese font */
@ -171,7 +171,7 @@
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* default font size in RTGUI */
#define RTGUI_DEFAULT_FONT_SIZE 16
#define RTGUI_DEFAULT_FONT_SIZE 16
/* image support */
/* #define RTGUI_IMAGE_XPM */