From 72d4e2ed50f6c71a5502e234bde1f30a28e23b00 Mon Sep 17 00:00:00 2001 From: bigamgic Date: Tue, 16 Jun 2020 09:16:07 +0800 Subject: [PATCH] add raspi4 gpio interrupt --- bsp/raspberry-pi/raspi4-32/.config | 36 ++- bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c | 308 ++++++++++++++++++- bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h | 18 ++ bsp/raspberry-pi/raspi4-32/driver/raspi4.h | 5 + bsp/raspberry-pi/raspi4-32/rtconfig.h | 6 + 5 files changed, 360 insertions(+), 13 deletions(-) diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index 67da7a97c6..6f7fc20100 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x40003 # CONFIG_RT_USING_CPU_FFS is not set CONFIG_ARCH_ARMV8=y @@ -331,7 +331,6 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -388,7 +387,6 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set # # miscellaneous packages @@ -425,6 +423,38 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set CONFIG_BCM2711_SOC=y # CONFIG_BSP_SUPPORT_FPU is not set diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c index 8b64f7afb5..e342032d55 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c @@ -6,17 +6,24 @@ * Change Logs: * Date Author Notes * 2020-04-16 bigmagic first version + * 2020-06-16 bigmagic add gpio irq */ #include "drv_gpio.h" #ifdef BSP_USING_PIN -void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) + +/* + * gpio_int[0] for BANK0 (pins 0-27) + * gpio_int[1] for BANK1 (pins 28-45) + * gpio_int[2] for BANK2 (pins 46-53) + */ +static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM]; + +uint32_t raspi_get_pin_state(uint32_t fselnum) { - uint32_t fselnum = pin / 10; - uint32_t fselrest = pin % 10; uint32_t gpfsel = 0; - + switch (fselnum) { case 0: @@ -40,10 +47,11 @@ void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) default: break; } + return gpfsel; +} - gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3))); - gpfsel |= (uint32_t)(mode << (fselrest * 3)); - +void raspi_set_pin_state(uint32_t fselnum, uint32_t gpfsel) +{ switch (fselnum) { case 0: @@ -69,9 +77,74 @@ void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) } } +static void gpio_set_pud(GPIO_PIN pin, GPIO_PUPD_FUNC mode) +{ + uint32_t fselnum = pin / 16; + uint32_t fselrest = pin % 16; + uint32_t reg_value = 0; + + switch (fselnum) + { + case 0: + reg_value = GPIO_PUP_PDN_CNTRL_REG0(GPIO_BASE); + GPIO_PUP_PDN_CNTRL_REG0(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + break; + case 1: + reg_value = GPIO_PUP_PDN_CNTRL_REG1(GPIO_BASE); + GPIO_PUP_PDN_CNTRL_REG1(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + break; + + case 2: + reg_value = GPIO_PUP_PDN_CNTRL_REG2(GPIO_BASE); + GPIO_PUP_PDN_CNTRL_REG2(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + break; + + case 3: + reg_value = GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE); + GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); + break; + default: + break; + } +} + +void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) +{ + uint32_t fselnum = pin / 10; + uint32_t fselrest = pin % 10; + uint32_t gpfsel = 0; + + gpfsel = raspi_get_pin_state(fselnum); + gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3))); + gpfsel |= (uint32_t)(mode << (fselrest * 3)); + raspi_set_pin_state(fselnum, gpfsel); +} + static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) { - prev_raspi_pin_mode((GPIO_PIN)pin, (GPIO_FUNC)mode); + GPIO_FUNC raspi_mode = OUTPUT; + + switch (mode) + { + case PIN_MODE_OUTPUT: + raspi_mode = OUTPUT; + break; + case PIN_MODE_INPUT: + raspi_mode = INPUT; + break; + case PIN_MODE_INPUT_PULLUP: + gpio_set_pud(pin, RASPI_PULL_UP); + raspi_mode = INPUT; + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio_set_pud(pin, RASPI_PULL_DOWN); + raspi_mode = INPUT; + break; + case PIN_MODE_OUTPUT_OD: + raspi_mode = OUTPUT; + break; + } + prev_raspi_pin_mode((GPIO_PIN)pin, raspi_mode); } static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) @@ -99,27 +172,162 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t valu { GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); } - } } static int raspi_pin_read(struct rt_device *device, rt_base_t pin) { - return 0; + uint32_t num = pin / 32; + uint32_t pin_level = 0; + + if(num == 0) + { + if(GPIO_REG_GPLEV0(GPIO_BASE) & (1 << pin)) + { + pin_level = 1; + } + else + { + pin_level = 0; + } + + } + else + { + if(GPIO_REG_GPLEV1(GPIO_BASE) & (1 << pin)) + { + pin_level = 1; + } + else + { + pin_level = 0; + } + } + + return pin_level; } static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { + rt_uint8_t index; + rt_uint32_t reg_value; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + _g_gpio_irq_tbl[index].irq_cb[pin] = hdr; + _g_gpio_irq_tbl[index].irq_arg[pin] = args; + _g_gpio_irq_tbl[index].irq_type[pin] = mode; + + rt_uint8_t shift = pin % 32; + rt_uint8_t pin_num = pin / 32; + rt_uint32_t mask = 1 << shift; + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPREN0(GPIO_BASE); + GPIO_REG_GPREN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPREN1(GPIO_BASE); + GPIO_REG_GPREN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + break; + case PIN_IRQ_MODE_FALLING: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPFEN0(GPIO_BASE); + GPIO_REG_GPFEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPFEN1(GPIO_BASE); + GPIO_REG_GPFEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + break; + case PIN_IRQ_MODE_RISING_FALLING: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPAREN0(GPIO_BASE); + GPIO_REG_GPAREN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN0(GPIO_BASE); + GPIO_REG_GPFEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPAREN1(GPIO_BASE); + GPIO_REG_GPAREN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + reg_value = GPIO_REG_GPFEN1(GPIO_BASE); + GPIO_REG_GPFEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPHEN0(GPIO_BASE); + GPIO_REG_GPHEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPHEN1(GPIO_BASE); + GPIO_REG_GPHEN1(GPIO_BASE) = (reg_value & ~ mask) | ( mask); + } + break; + case PIN_IRQ_MODE_LOW_LEVEL: + if(pin_num == 0) + { + reg_value = GPIO_REG_GPLEN0(GPIO_BASE); + GPIO_REG_GPLEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + else + { + reg_value = GPIO_REG_GPLEN1(GPIO_BASE); + GPIO_REG_GPLEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask); + } + break; + } return RT_EOK; } static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { + rt_uint8_t index; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + + _g_gpio_irq_tbl[index].irq_cb[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_arg[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_type[pin] = RT_NULL; + _g_gpio_irq_tbl[index].state[pin] = RT_NULL; + return RT_EOK; } rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { + rt_uint8_t index; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + + if (enabled) + _g_gpio_irq_tbl[index].state[pin] = 1; + else + _g_gpio_irq_tbl[index].state[pin] = 0; + return RT_EOK; } @@ -132,12 +340,92 @@ static const struct rt_pin_ops ops = raspi_pin_detach_irq, raspi_pin_irq_enable, }; + +static void gpio_irq_handler(int irq, void *param) +{ + struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param; + rt_uint32_t pin; + rt_uint32_t value; + rt_uint32_t tmpvalue; + + if(irq == IRQ_GPIO0) + { + /* 0~27 */ + value = GPIO_REG_GPEDS0(GPIO_BASE); + value &= 0x0fffffff; + pin = 0; + GPIO_REG_GPEDS0(GPIO_BASE) = value; + } + else if(irq == IRQ_GPIO1) + { + /* 28-45 */ + tmpvalue = GPIO_REG_GPEDS0(GPIO_BASE); + tmpvalue &= (~0x0fffffff); + GPIO_REG_GPEDS0(GPIO_BASE) = tmpvalue; + + value = GPIO_REG_GPEDS1(GPIO_BASE); + value &= 0x3fff; + GPIO_REG_GPEDS1(GPIO_BASE) = value; + value = (value) | tmpvalue; + pin = 28; + } + else if (irq == IRQ_GPIO2) + { + /* 46-53 */ + value = GPIO_REG_GPEDS1(GPIO_BASE); + value &= (~0x3fff); + GPIO_REG_GPEDS1(GPIO_BASE) = value; + pin = 46; + } + + while (value) + { + if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) + { + if(irq_def->state[pin]) + { + irq_def->irq_cb[pin](irq_def->irq_arg[pin]); + } + } + pin++; + value = value >> 1; + } +} #endif int rt_hw_gpio_init(void) { #ifdef BSP_USING_PIN rt_device_pin_register("gpio", &ops, RT_NULL); + + //disable all intr + GPIO_REG_GPEDS0(GPIO_BASE) = 0xffffffff; + GPIO_REG_GPEDS1(GPIO_BASE) = 0xffffffff; + + GPIO_REG_GPREN0(GPIO_BASE) = 0x0; + GPIO_REG_GPREN1(GPIO_BASE) = 0x0; + + GPIO_REG_GPFEN0(GPIO_BASE) = 0x0; + GPIO_REG_GPFEN1(GPIO_BASE) = 0x0; + + GPIO_REG_GPHEN0(GPIO_BASE) = 0x0; + GPIO_REG_GPHEN1(GPIO_BASE) = 0x0; + + GPIO_REG_GPAREN0(GPIO_BASE) = 0x0; + GPIO_REG_GPAREN1(GPIO_BASE) = 0x0; + + GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; + GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; + + rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); + rt_hw_interrupt_umask(IRQ_GPIO0); + + rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq"); + rt_hw_interrupt_umask(IRQ_GPIO1); + + rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq"); + rt_hw_interrupt_umask(IRQ_GPIO2); + #endif return 0; diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h index 2dde6990ef..44fa0464fd 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h @@ -17,6 +17,14 @@ #include "board.h" #include "interrupt.h" +struct gpio_irq_def +{ + void *irq_arg[32]; + void (*irq_cb[32])(void *param); + rt_uint8_t irq_type[32]; + rt_uint8_t state[32]; +}; + #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) @@ -59,6 +67,10 @@ #define GPIO_REG_GPPUDCLK1(BASE) HWREG32(BASE + 0x9C) #define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0) #define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4) +#define GPIO_PUP_PDN_CNTRL_REG0(BASE) HWREG32(BASE + 0xE4) +#define GPIO_PUP_PDN_CNTRL_REG1(BASE) HWREG32(BASE + 0xE8) +#define GPIO_PUP_PDN_CNTRL_REG2(BASE) HWREG32(BASE + 0xEC) +#define GPIO_PUP_PDN_CNTRL_REG3(BASE) HWREG32(BASE + 0xF0) typedef enum { GPIO_PIN_0, @@ -115,6 +127,12 @@ typedef enum { ALT5 = 0b010 } GPIO_FUNC; +typedef enum { + RASPI_NO_RESISTOR = 0x00, + RASPI_PULL_UP = 0x01, + RASPI_PULL_DOWN = 0x10 +} GPIO_PUPD_FUNC; + void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode); int rt_hw_gpio_init(void); diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index 6c7fe3696b..bfdf7bfecc 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -29,6 +29,11 @@ /* GPIO */ #define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET) +#define GPIO_IRQ_NUM (3) //40 pin mode +#define IRQ_GPIO0 (96 + 49) //bank0 (0 to 27) +#define IRQ_GPIO1 (96 + 50) //bank1 (28 to 45) +#define IRQ_GPIO2 (96 + 51) //bank2 (46 to 57) +#define IRQ_GPIO3 (96 + 52) //bank3 /* Timer (ARM side) */ #define ARM_TIMER_IRQ (64) diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index fa659a7e1d..c073fa5003 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -154,6 +154,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define BCM2711_SOC /* Hardware Drivers Config */