diff --git a/.gitignore b/.gitignore index 4e6126542c..ef05df0cba 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ *.idb *.ilk *.old +*.crf build Debug documentation/html diff --git a/bsp/Vango_V85xx/drivers/SConscript b/bsp/Vango_V85xx/drivers/SConscript index 30a1a338d0..c6cf664e49 100644 --- a/bsp/Vango_V85xx/drivers/SConscript +++ b/bsp/Vango_V85xx/drivers/SConscript @@ -30,6 +30,9 @@ if GetDepend('RT_USING_RTC'): if GetDepend('RT_USING_WDT'): src += ['drv_iwdt.c'] +if GetDepend('RT_USING_SPI'): + src += ['drv_spi.c'] + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/Vango_V85xx/drivers/drv_spi.c b/bsp/Vango_V85xx/drivers/drv_spi.c index 54bb9f9f92..724e3cc400 100644 --- a/bsp/Vango_V85xx/drivers/drv_spi.c +++ b/bsp/Vango_V85xx/drivers/drv_spi.c @@ -6,8 +6,9 @@ * Change Logs: * Date Author Notes * 2017-06-05 tanek first implementation. - * 2018-04-19 misonyo Porting for gd32f30x - * 2019-03-31 xuzhuoyi Porting for gd32e230 + * 2018-04-19 misonyo Porting for v85xxf30x + * 2019-03-31 xuzhuoyi Porting for v85xxe230 + * 2021-09-21 zhuxw Porting for v85xx */ #include "drv_spi.h" @@ -17,7 +18,7 @@ #if defined(RT_USING_SPI) && defined(RT_USING_PIN) #include -#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) +#if !defined(RT_USING_SPI1) && !defined(RT_USING_SPI2) #error "Please define at least one SPIx" #endif @@ -32,7 +33,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); -static struct rt_spi_ops gd32_spi_ops = +static struct rt_spi_ops v85xx_spi_ops = { configure, xfer @@ -40,124 +41,95 @@ static struct rt_spi_ops gd32_spi_ops = static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) { - spi_parameter_struct spi_init_struct; + SPI_InitType spi_init_struct; rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); - if(configuration->data_width <= 8) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - } - else if(configuration->data_width <= 16) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; - } - else + if(configuration->data_width > 8) { return RT_EIO; } { - rcu_clock_freq_enum spi_src; rt_uint32_t spi_apb_clock; rt_uint32_t max_hz; max_hz = configuration->max_hz; - DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); - DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); - DEBUG_PRINTF("max freq: %d\n", max_hz); - - if (spi_periph == SPI1) - { - spi_src = CK_APB1; - } - else - { - spi_src = CK_APB2; - } - spi_apb_clock = rcu_clock_freq_get(spi_src); + spi_apb_clock = CLK_GetPCLKFreq(); if(max_hz >= spi_apb_clock/2) { - spi_init_struct.prescale = SPI_PSC_2; + spi_init_struct.ClockDivision = SPI_CLKDIV_2; } else if (max_hz >= spi_apb_clock/4) { - spi_init_struct.prescale = SPI_PSC_4; + spi_init_struct.ClockDivision = SPI_CLKDIV_4; } else if (max_hz >= spi_apb_clock/8) { - spi_init_struct.prescale = SPI_PSC_8; + spi_init_struct.ClockDivision = SPI_CLKDIV_8; } else if (max_hz >= spi_apb_clock/16) { - spi_init_struct.prescale = SPI_PSC_16; + spi_init_struct.ClockDivision = SPI_CLKDIV_16; } else if (max_hz >= spi_apb_clock/32) { - spi_init_struct.prescale = SPI_PSC_32; + spi_init_struct.ClockDivision = SPI_CLKDIV_32; } else if (max_hz >= spi_apb_clock/64) { - spi_init_struct.prescale = SPI_PSC_64; - } - else if (max_hz >= spi_apb_clock/128) - { - spi_init_struct.prescale = SPI_PSC_128; + spi_init_struct.ClockDivision = SPI_CLKDIV_64; } else { - /* min prescaler 256 */ - spi_init_struct.prescale = SPI_PSC_256; + /* min prescaler 128 */ + spi_init_struct.ClockDivision = SPI_CLKDIV_128; } } /* baudrate */ switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_init_struct.SPH = SPI_SPH_0; + spi_init_struct.SPO = SPI_SPO_0; break; case RT_SPI_MODE_1: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; + spi_init_struct.SPH = SPI_SPH_1; + spi_init_struct.SPO = SPI_SPO_0; break; case RT_SPI_MODE_2: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; + spi_init_struct.SPH = SPI_SPH_0; + spi_init_struct.SPO = SPI_SPO_1; break; case RT_SPI_MODE_3: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_struct.SPH = SPI_SPH_1; + spi_init_struct.SPO = SPI_SPO_1; break; } - /* MSB or LSB */ - if(configuration->mode & RT_SPI_MSB) + if(!(configuration->mode & RT_SPI_MSB)) { - spi_init_struct.endian = SPI_ENDIAN_MSB; - } - else - { - spi_init_struct.endian = SPI_ENDIAN_LSB; + return RT_EIO; } - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.nss = SPI_NSS_SOFT; + spi_init_struct.Mode = SPI_MODE_MASTER; + spi_init_struct.CSNSoft = SPI_CSNSOFT_ENABLE; - spi_init(spi_periph, &spi_init_struct); + SPI_Init((SPI_TypeDef*)spi_periph, &spi_init_struct); - spi_crc_off(spi_periph); - - spi_enable(spi_periph); + SPI_Cmd((SPI_TypeDef*)spi_periph, ENABLE); return RT_EOK; }; static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) { - rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; + rt_base_t v85xx_cs_pin = (rt_base_t)device->parent.user_data; rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; struct rt_spi_configuration * config = &device->config; @@ -167,7 +139,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes /* take CS */ if(message->cs_take) { - rt_pin_write(gd32_cs_pin, PIN_LOW); + rt_pin_write(v85xx_cs_pin, PIN_LOW); DEBUG_PRINTF("spi take cs\n"); } @@ -189,16 +161,15 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes data = *send_ptr++; } - // Todo: replace register read/write by gd32f3 lib //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); + while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_TXEMPTY)); // Send the byte - spi_i2s_data_transmit(spi_periph, data); + SPI_SendData((SPI_TypeDef*)spi_periph, data); //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); + while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_RNE)); // Get the received data - data = spi_i2s_data_receive(spi_periph); + data = SPI_ReceiveData((SPI_TypeDef*)spi_periph); if(recv_ptr != RT_NULL) { @@ -207,81 +178,37 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes } DEBUG_PRINTF("spi poll transfer finsh\n"); } - else if(config->data_width <= 16) - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - while(size--) - { - rt_uint16_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - } } /* release CS */ if(message->cs_release) { - rt_pin_write(gd32_cs_pin, PIN_HIGH); + rt_pin_write(v85xx_cs_pin, PIN_HIGH); DEBUG_PRINTF("spi release cs\n"); } return message->length; }; -int gd32_hw_spi_init(void) +int v85xx_hw_spi_init(void) { int result = 0; -#ifdef RT_USING_SPI0 - static struct rt_spi_bus spi_bus0; - spi_bus0.parent.user_data = (void *)SPI0; - - result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_SPI0); - - /* SPI0 GPIO config: SCK/PA5, MISO/PA6, MOSI/PA7 */ - gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); -#endif #ifdef RT_USING_SPI1 + static struct rt_spi_bus spi_bus0; + spi_bus0.parent.user_data = (void *)SPI1; + + result = rt_spi_bus_register(&spi_bus0, "spi1", &v85xx_spi_ops); + + #endif + +#ifdef RT_USING_SPI2 static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; + spi_bus1.parent.user_data = (void *)SPI2; - result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); + result = rt_spi_bus_register(&spi_bus1, "spi2", &v85xx_spi_ops); - rcu_periph_clock_enable(RCU_SPI1); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI1 GPIO config: SCK/PB13, MISO/PB14, MOSI/PB15 */ - gpio_af_set(GPIOB, GPIO_AF_0, GPIO_PIN_13 | GPIO_PIN_14 |GPIO_PIN_15); - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13 | GPIO_PIN_14 |GPIO_PIN_15); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_14 |GPIO_PIN_15); #endif return result; } -INIT_BOARD_EXPORT(gd32_hw_spi_init); +INIT_BOARD_EXPORT(v85xx_hw_spi_init); #endif diff --git a/bsp/Vango_V85xx/drivers/drv_spi.h b/bsp/Vango_V85xx/drivers/drv_spi.h index 352ee5a4e3..438fcb8878 100644 --- a/bsp/Vango_V85xx/drivers/drv_spi.h +++ b/bsp/Vango_V85xx/drivers/drv_spi.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2012-01-01 aozima first implementation. + * 2021-09-21 zhuxw add vango v85xx spi drivers * */ diff --git a/bsp/Vango_V85xx/project.uvoptx b/bsp/Vango_V85xx/project.uvoptx new file mode 100644 index 0000000000..6a1c508a66 --- /dev/null +++ b/bsp/Vango_V85xx/project.uvoptx @@ -0,0 +1,1324 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c + lib_dma.c + 0 + 0 + + + 9 + 88 + 1 + 0 + 0 + 0 + Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c + lib_uart.c + 0 + 0 + + + 9 + 89 + 1 + 0 + 0 + 0 + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 9 + 90 + 1 + 0 + 0 + 0 + Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c + lib_tmr.c + 0 + 0 + + + + diff --git a/bsp/Vango_V85xx/project.uvprojx b/bsp/Vango_V85xx/project.uvprojx new file mode 100644 index 0000000000..336e55e0eb --- /dev/null +++ b/bsp/Vango_V85xx/project.uvprojx @@ -0,0 +1,955 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85XX + Generic + Vango.V85XX.4.0.2 + IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM)) + 0 + $$Device:V85XX$Device\Include\V85XX.h + + + + + + + + + + $$Device:V85XX$SVD\V85XX.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + V85xx, USE_STDPERIPH_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, USE_TARGET_DRIVER, RT_USING_ARM_LIBC + + applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel;Libraries\CMSIS\Vango\V85xx\Include;Libraries\CMSIS;Libraries\VangoV85xx_standard_peripheral\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + board.c + 1 + drivers\board.c + + + drv_spi.c + 1 + drivers\drv_spi.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + Kernel + + + timer.c + 1 + ..\..\src\timer.c + + + irq.c + 1 + ..\..\src\irq.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + idle.c + 1 + ..\..\src\idle.c + + + clock.c + 1 + ..\..\src\clock.c + + + object.c + 1 + ..\..\src\object.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + device.c + 1 + ..\..\src\device.c + + + components.c + 1 + ..\..\src\components.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + thread.c + 1 + ..\..\src\thread.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + unistd.c + 1 + ..\..\components\libc\compilers\common\unistd.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + delay.c + 1 + ..\..\components\libc\compilers\common\delay.c + + + + + Vango_Lib + + + lib_adc.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc.c + + + lib_pmu.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_pmu.c + + + startup_target.S + 2 + Libraries\CMSIS\Vango\V85xx\Source\Keil5\startup_target.S + + + lib_LoadNVR.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\lib_LoadNVR.c + + + lib_ana.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_ana.c + + + lib_i2c.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_i2c.c + + + lib_version.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_version.c + + + lib_gpio.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_gpio.c + + + lib_u32k.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_u32k.c + + + lib_misc.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_misc.c + + + lib_wdt.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_wdt.c + + + lib_flash.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_flash.c + + + lib_spi.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_spi.c + + + lib_CodeRAM.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\lib_CodeRAM.c + + + lib_iso7816.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_iso7816.c + + + lib_pwm.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_pwm.c + + + lib_comp.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_comp.c + + + lib_rtc.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_rtc.c + + + system_target.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\system_target.c + + + lib_cortex.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\lib_cortex.c + + + lib_clk.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_clk.c + + + lib_crypt.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_crypt.c + + + lib_lcd.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_lcd.c + + + lib_dma.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c + + + lib_uart.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c + + + lib_adc_tiny.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c + + + lib_tmr.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c + + + + + + + + + + + + + + diff --git a/bsp/Vango_V85xx/rtconfig.h b/bsp/Vango_V85xx/rtconfig.h index 4aa2d4b8d4..899ca6661a 100644 --- a/bsp/Vango_V85xx/rtconfig.h +++ b/bsp/Vango_V85xx/rtconfig.h @@ -179,5 +179,7 @@ #define BSP_USING_UART #define BSP_USING_UART2 +#define RT_USING_SPI1 +#define RT_USING_SPI2 #endif