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modified: ../../libcpu/risc-v/e310/context_gcc.S 

fix open timer intrrupt
This commit is contained in:
zhangjun 2017-07-26 16:27:54 +08:00
parent 98a6896cfa
commit b80f83f360
2 changed files with 7 additions and 9 deletions
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10
bsp/risc-v/drivers/board.c
View File

@ -27,15 +27,11 @@ static void rt_hw_timer_init(void)
GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ;
GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ;
rt_hw_interrupt_enable(1);
/* enable timer intrrupt*/
set_csr(mie, MIP_MTIP);
/* set_csr(mie, MIP_MTIP);*/
CLINT_REG(CLINT_MTIME) = 0x0;
//CLINT_REG(CLINT_MTIMECMP) = 0x10000;
set_csr(mie, MIP_MTIP);
/* set_csr(mstatus, MSTATUS_MIE);*/
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
*mtimecmp = 0x20000;
CLINT_REG(CLINT_MTIMECMP) = 0x10000;
set_csr(mstatus, MSTATUS_MIE);
return;
}
void rt_hw_board_init(void)

6
libcpu/risc-v/e310/context_gcc.S
View File

@ -32,7 +32,8 @@
rt_hw_interrupt_disable:
addi sp, sp, -12
sw a5, (sp)
csrrc a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP
li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP
csrrc a5, mie, a5
/* csrrc a5, mstatus, MSTATUS_MIE*/
lw a5, (sp)
addi sp, sp, 12
@ -45,7 +46,8 @@ rt_hw_interrupt_disable:
rt_hw_interrupt_enable:
addi sp, sp, -12
sw a5, (sp)
csrrs a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP
li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP
csrrs a5, mie, a5
/* csrrsi a5, mstatus, MSTATUS_MIE*/
lw a5, (sp)
addi sp, sp, 12