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[bsp/virt64/aarch64] Add 'qemu-virt64-aarch64' bsp

This commit is contained in:
GuEe-GUI 2021-08-06 18:35:58 +08:00
parent 73bd7a7d66
commit b7dd004de0
28 changed files with 2014 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

599
bsp/qemu-virt64-aarch64/.config Normal file
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@ -0,0 +1,599 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=2048
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
CONFIG_RT_USING_MEMTRACE=y
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_DEVICE_OPS=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_FIXED_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
CONFIG_OPPO_A55_SOC=y
# CONFIG_BSP_SUPPORT_FPU is not set
#
# Hardware Drivers Config
#
#
# BCM Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART0=y
# CONFIG_RT_USING_UART1 is not set
CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GIC390=y
CONFIG_BSP_USING_PIN=y
# CONFIG_BSP_USING_SYSTIMER is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_SDIO is not set
#
# Board Peripheral Drivers
#
# CONFIG_BSP_USING_HDMI is not set

30
bsp/qemu-virt64-aarch64/Kconfig Normal file
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mainmenu "RT-Thread Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config OPPO_A55_SOC
bool
select ARCH_ARM_CORTEX_A53
select ARCH_CPU_64BIT
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select RT_USING_RTC
default y
source "$BSP_DIR/driver/Kconfig"

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# QEMU/AArch64 VIRT BSP Introduction
[中文页](README_ZH.md) | English
## 1. Introduction
The AArch64 execution state was introduced with the ARMv8 ISA for machines executing A64 instructions. This project ported RT-Thread on QEMU AArch64 VIRT machine.
## 2. Compiling
Usage ARM Developer GNU ToolChain, it support Linux and Windows:
```
https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads/
```
Download the `xxx-aarch64-none-elf` of x86_64 hosted platform，set the `RTT_EXEC_PATH` is system environment after decompress the binary.
Enter directory `rt-thread/bsp/qemu-virt64-aarch64` and input:
```
scons
```
## 2. Execution
The project execution tool is `qemu-system-aarch64`
Download Windows platform from website:
```
https://www.qemu.org/download/
```
On Linux platform (Ubuntu, Deepin and so on), install QEMU by apt.
```
sudo apt update
sudo apt install qemu-system-arm
```
Run qemu.bat or qemu.sh in terminal:
```
heap: [0x40042aa0 - 0x40142aa0]
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Aug 6 2021
2006 - 2021 Copyright by rt-thread team
Hi, this is RT-Thread!!
msh />
```
## 3. Condition
| Driver | Condition | Remark |
| ------ | --------- | ------ |
| UART | Support | UART0 |

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# QEMU/AArch64 VIRT板级支持包说明
中文页 | [English](README.md)
## 1. 简介
AArch64是一种采用ARMv8 ISA，用于执行A64指令的机器的64位执行模式。本工程是在QEMU的AArch64 VIRT版本上进行的一份移植。
## 2. 编译说明
建议使用ARM Developer GNU交叉编译工具链，目前支持Linux/Windows平台：
```
https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads/
```
下载x86_64 Hosted平台下载对应的`xxx-aarch64-none-elf`二进制包，解压后设置`RTT_EXEC_PATH`环境变量为该编译器的bin目录下即可。
进入到`rt-thread/bsp/qemu-virt64-aarch64`目录进行输入：
```
scons
```
可以看到正常生成`rtthread.elf`与`rtthread.bin`文件。
## 3. 执行
本工程执行环境为`qemu-system-aarch64`模拟器
Windows平台下，可以在此获取到QEMU：
```
https://www.qemu.org/download/
```
Linux平台下，以Ubuntu、Deepin系列发行版为例，可通过该命令安装QEMU：
```
sudo apt update
sudo apt install qemu-system-arm
```
在终端执行qemu.bat或qemu.sh可以看到程序运行：
```
heap: [0x40042aa0 - 0x40142aa0]
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Aug 6 2021
2006 - 2021 Copyright by rt-thread team
Hi, this is RT-Thread!!
msh />
```
## 4.支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | UART0 |

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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)

9
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

18
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#include <rtthread.h>
int main(int argc, char** argv)
{
rt_kprintf("Hi, this is RT-Thread!!\n");
return 0;
}

122
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config BSP_SUPPORT_FPU
bool "Using Float"
default n
menu "Hardware Drivers Config"
menu "BCM Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Using UART"
select RT_USING_SERIAL
default y
if BSP_USING_UART
config RT_USING_UART0
bool "Enabel UART 0"
default y
config RT_USING_UART1
bool "Enabel UART 1"
default n
endif
menuconfig BSP_USING_GIC
bool "Enable GIC"
select RT_USING_GIC
default y
if BSP_USING_GIC
config BSP_USING_GIC390
bool "Enable GIC390"
default y
endif
config BSP_USING_PIN
bool "Using PIN"
select RT_USING_PIN
default y
menuconfig BSP_USING_SYSTIMER
bool "Enable SYSTIMER"
select RT_USING_SYSTIMER
default n
if BSP_USING_SYSTIMER
config RT_USING_SYSTIMER1
bool "Enable sys timer1"
default n
config RT_USING_SYSTIMER3
bool "Enable sys timer3"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
select RT_USING_I2C
default n
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default n
config BSP_USING_I2C1
bool "Enable I2C1"
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0"
default n
config BSP_USING_SPI1
bool "Enable SPI1"
default n
endif
config BSP_USING_WDT
bool "Enable WDT"
select RT_USING_WDT
default n
menuconfig BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_RTC
config BSP_USING_ALARM
bool "Enable Alarm"
select RT_USING_ALARM
default n
endif
menuconfig BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
default n
if BSP_USING_SDIO
config BSP_USING_SDIO0
bool "Enable SDIO0"
select RT_USING_SDIO
default n
endif
endmenu
menu "Board Peripheral Drivers"
menuconfig BSP_USING_HDMI
bool "Enable HDMI"
select BSP_USING_SPI
default n
if BSP_USING_HDMI
config BSP_USING_HDMI_DISPLAY
bool "HDMI DISPLAY"
default n
endif
endmenu
endmenu

14
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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
board.c
drv_uart.c
''')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
* 2021-07-31 GuEe-GUI config the memory/io address map
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include <mmu.h>
#include "drv_uart.h"
void rt_hw_vector_init(void);
static uint64_t tickval = 0;
void rt_hw_timer_isr(int vector, void *parameter)
{
uint64_t cntvct_el0;
do
{
tickval += 0xF424;
__asm__ volatile ("msr CNTV_CVAL_EL0, %0"::"r"(tickval));
__asm__ volatile ("mrs %0, CNTVCT_EL0":"=r"(cntvct_el0));
}
while (cntvct_el0 >= tickval);
rt_tick_increase();
}
int rt_hw_timer_init()
{
uint64_t val;
rt_hw_interrupt_install(27, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(27);
val = 0;
__asm__ volatile ("msr CNTV_CTL_EL0, %0"::"r"(val));
val = 0x03B9ACA0;
__asm__ volatile ("msr CNTFRQ_EL0, %0"::"r"(val));
tickval += 0xF424;
__asm__ volatile ("msr CNTV_CVAL_EL0, %0"::"r"(tickval));
val = 1;
__asm__ volatile ("msr CNTV_CTL_EL0, %0"::"r"(val));
return 0;
}
void idle_wfi(void)
{
asm volatile ("wfi");
}
/**
* Initialize the Hardware related stuffs. Called from rtthread_startup()
* after interrupt disabled.
*/
void rt_hw_board_init(void)
{
uint64_t cont;
mmu_init();
cont = (uint64_t)RT_HW_HEAP_END + 0x1fffff;
cont &= ~0x1fffff;
cont -= 0x40000000;
cont >>= 21;
/* memory location */
armv8_map_2M(0x40000000, 0x40000000, cont, MEM_ATTR_MEMORY);
/* uart location*/
armv8_map_2M(PL011_UART0_BASE, PL011_UART0_BASE, 0x1, MEM_ATTR_IO);
/* gic location*/
armv8_map_2M(GIC_PL390_DISTRIBUTOR_PPTR, GIC_PL390_DISTRIBUTOR_PPTR, 0x1, MEM_ATTR_IO);
mmu_enable();
/* initialize hardware interrupt */
rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
/* initialize uart */
rt_hw_uart_init(); // driver/drv_uart.c
/* initialize timer for os tick */
rt_hw_timer_init();
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_kprintf("heap: [0x%08x - 0x%08x]\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

47
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
* 2021-07-31 GuEe-GUI add ARM GIC definitions
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <rthw.h>
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 1 * 1024 * 1024)
/* UART */
#define PL011_UARTDR 0x000
#define PL011_UARTFR 0x018
#define PL011_UARTFR_TXFF_BIT 5
#define PL011_UART0_BASE 0x09000000
#define PL011_UART0_SIZE 0x00001000
/* DIST and CPU */
#define GIC_PL390_DISTRIBUTOR_PPTR 0x08000000
#define GIC_PL390_CONTROLLER_PPTR 0x08010000
/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
return GIC_PL390_DISTRIBUTOR_PPTR;
}
rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
{
return GIC_PL390_CONTROLLER_PPTR;
}
void rt_hw_board_init(void);
#endif

143
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/5 Bernard The first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
unsigned int readl(volatile void *addr)
{
return *(volatile unsigned int *)addr;
}
void writel(unsigned int v, volatile void *addr)
{
*(volatile unsigned int *)addr = v;
}
struct hw_uart_device
{
rt_ubase_t hw_base;
rt_uint32_t irqno;
};
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
return RT_EOK;
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct hw_uart_device *uart;
uint32_t val;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
val = readl((volatile void *)(uart->hw_base + 0x38));
val &= ~0x10;
writel(val, (volatile void *)(uart->hw_base + 0x38));
rt_hw_interrupt_mask(uart->irqno);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
val = readl((volatile void *)(uart->hw_base + 0x38));
val |= 0x10;
writel(val, (volatile void *)(uart->hw_base + 0x38));
rt_hw_interrupt_umask(uart->irqno);
break;
}
return RT_EOK;
}
static int uart_putc(struct rt_serial_device *serial, char c)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
while (readl((volatile void *)(uart->hw_base + PL011_UARTFR)) & (1 << PL011_UARTFR_TXFF_BIT))
{
}
writel(c, (volatile void *)( uart->hw_base + PL011_UARTDR));
return 1;
}
static int uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if (!(readl((volatile void *)(uart->hw_base + 0x18)) & (1 << 4)))
{
ch = readl((volatile void *)(uart->hw_base));
}
return ch;
}
static const struct rt_uart_ops _uart_ops =
{
uart_configure,
uart_control,
uart_putc,
uart_getc,
};
static void rt_hw_uart_isr(int irqno, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device*)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
#ifdef RT_USING_UART0
/* UART device driver structure */
static struct hw_uart_device _uart0_device =
{
PL011_UART0_BASE,
33,
};
static struct rt_serial_device _serial0;
#endif
int rt_hw_uart_init(void)
{
struct hw_uart_device *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART0
uart = &_uart0_device;
_serial0.ops = &_uart_ops;
_serial0.config = config;
/* register UART1 device */
rt_hw_serial_register(&_serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
#endif
return 0;
}

16
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
int rt_hw_uart_init(void);
#endif /* DRV_UART_H__ */

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/*
* File : link.lds
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* 2017-5-30 bernard first version
*/
/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
SECTIONS
{
. = 0x40000000;
. = ALIGN(4096);
.text :
{
KEEP(*(.text.entrypoint)) /* The entry point */
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(16);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(16);
/* section information for initial. */
. = ALIGN(16);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(16);
. = ALIGN(16);
_etext = .;
}
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(16);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(16);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(16);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
PROVIDE(__bss_end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
__bss_size = (__bss_end - __bss_start)>>3;

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qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 1 -kernel rtthread.elf -nographic

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qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 1 -kernel rtthread.elf -nographic -monitor pty

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 2048
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SMALL_MEM
#define RT_USING_MEMTRACE
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40004
#define ARCH_CPU_64BIT
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_RTC
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_POSIX
#define RT_LIBC_FIXED_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define OPPO_A55_SOC
/* Hardware Drivers Config */
/* BCM Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART0
#define BSP_USING_GIC
#define BSP_USING_GIC390
#define BSP_USING_PIN
/* Board Peripheral Drivers */
#endif

57
bsp/qemu-virt64-aarch64/rtconfig.py Normal file
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@ -0,0 +1,57 @@
import os
# toolchains options
ARCH ='aarch64'
CPU ='cortex-a53'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery,
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:/Program Files/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -g -march=armv8-a -mtune=cortex-a53'
CFLAGS = DEVICE + ' -Wall'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

1
bsp/raspberry-pi/raspi3-64/driver/board.h
View File

@ -12,6 +12,7 @@
#define BOARD_H__ #define BOARD_H__
#include <stdint.h> #include <stdint.h>
#include "raspi.h"
extern unsigned char __bss_start; extern unsigned char __bss_start;
extern unsigned char __bss_end; extern unsigned char __bss_end;

6
libcpu/aarch64/common/gic/SConscript
View File

@ -5,6 +5,10 @@ from building import *
cwd = GetCurrentDir() cwd = GetCurrentDir()
CPPPATH = [cwd] CPPPATH = [cwd]
gic390_group = Split('''
gic_pl390.c
''')
gic400_group = Split(''' gic400_group = Split('''
gic_pl400.c gic_pl400.c
''') ''')
@ -14,6 +18,8 @@ gic_pl500.c
''') ''')
src = () src = ()
if GetDepend('BSP_USING_GIC390'):
src = gic390_group
if GetDepend('BSP_USING_GIC400'): if GetDepend('BSP_USING_GIC400'):
src = gic400_group src = gic400_group
if GetDepend('BSP_USING_GIC500'): if GetDepend('BSP_USING_GIC500'):

273
libcpu/aarch64/common/gic/gic_pl390.c Normal file
View File

@ -0,0 +1,273 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-31 GuEe-GUI the first version
*/
#include <rtthread.h>
#include "gic_pl390.h"
#define BIT(n) (1ul<<(n))
#define MASK(n) (BIT(n)-1ul)
#define IRQ_REG(IRQ) ((IRQ) / 32)
#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
#define IRQ_MASK MASK(10)
#define IRQ_SET_ALL 0xffffffff
#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < GIC390_SPECIAL_IRQ_START)
#define TARGET_CPU_ALLINT(CPU) \
( \
(((CPU) & 0xff) << 0 ) | \
(((CPU) & 0xff) << 8 ) | \
(((CPU) & 0xff) << 16) | \
(((CPU) & 0xff) << 24) \
)
#define CPU(X) (1<<(X))
#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0))
/* memory map for GIC distributor */
struct gic_dist_map
{
rt_uint32_t enable; /* 0x000 */
rt_uint32_t ic_type; /* 0x004 */
rt_uint32_t dist_ident; /* 0x008 */
rt_uint32_t res1[29]; /* [0x00C, 0x080) */
rt_uint32_t security[32]; /* [0x080, 0x100) */
rt_uint32_t enable_set[32]; /* [0x100, 0x180) */
rt_uint32_t enable_clr[32]; /* [0x180, 0x200) */
rt_uint32_t pending_set[32]; /* [0x200, 0x280) */
rt_uint32_t pending_clr[32]; /* [0x280, 0x300) */
rt_uint32_t active[32]; /* [0x300, 0x380) */
rt_uint32_t res2[32]; /* [0x380, 0x400) */
rt_uint32_t priority[255]; /* [0x400, 0x7FC) */
rt_uint32_t res3; /* 0x7FC */
rt_uint32_t targets[255]; /* [0x800, 0xBFC) */
rt_uint32_t res4; /* 0xBFC */
rt_uint32_t config[64]; /* [0xC00, 0xD00) */
rt_uint32_t spi[32]; /* [0xD00, 0xD80) */
rt_uint32_t res5[20]; /* [0xD80, 0xDD0) */
rt_uint32_t res6; /* 0xDD0 */
rt_uint32_t legacy_int; /* 0xDD4 */
rt_uint32_t res7[2]; /* [0xDD8, 0xDE0) */
rt_uint32_t match_d; /* 0xDE0 */
rt_uint32_t enable_d; /* 0xDE4 */
rt_uint32_t res8[70]; /* [0xDE8, 0xF00) */
rt_uint32_t sgi_control; /* 0xF00 */
rt_uint32_t res9[3]; /* [0xF04, 0xF10) */
rt_uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
rt_uint32_t res10[40]; /* [0xF20, 0xFC0) */
rt_uint32_t periph_id[12]; /* [0xFC0, 0xFF0) */
rt_uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
};
/* memory map for GIC CPU interface */
struct gic_cpu_iface_map
{
rt_uint32_t icontrol; /* 0x000 */
rt_uint32_t pri_msk_c; /* 0x004 */
rt_uint32_t pb_c; /* 0x008 */
rt_uint32_t int_ack; /* 0x00C */
rt_uint32_t eoi; /* 0x010 */
rt_uint32_t run_priority; /* 0x014 */
rt_uint32_t hi_pend; /* 0x018 */
rt_uint32_t ns_alias_bp_c; /* 0x01C */
rt_uint32_t ns_alias_ack; /* 0x020 GIC400 only */
rt_uint32_t ns_alias_eoi; /* 0x024 GIC400 only */
rt_uint32_t ns_alias_hi_pend; /* 0x028 GIC400 only */
rt_uint32_t res1[5]; /* [0x02C, 0x040) */
rt_uint32_t integ_en_c; /* 0x040 PL390 only */
rt_uint32_t interrupt_out; /* 0x044 PL390 only */
rt_uint32_t res2[2]; /* [0x048, 0x050) */
rt_uint32_t match_c; /* 0x050 PL390 only */
rt_uint32_t enable_c; /* 0x054 PL390 only */
rt_uint32_t res3[30]; /* [0x058, 0x0FC) */
rt_uint32_t active_priority[4]; /* [0x0D0, 0xDC] GIC400 only */
rt_uint32_t ns_active_priority[4]; /* [0xE0,0xEC] GIC400 only */
rt_uint32_t res4[3];
rt_uint32_t cpu_if_ident; /* 0x0FC */
rt_uint32_t res5[948]; /* [0x100. 0xFC0) */
rt_uint32_t periph_id[8]; /* [0xFC0, 9xFF0) PL390 only */
rt_uint32_t component_id[4]; /* [0xFF0, 0xFFF] PL390 only */
};
volatile struct gic_dist_map *gic_dist =
(volatile struct gic_dist_map*)(GIC_PL390_DISTRIBUTOR_PPTR);
volatile struct gic_cpu_iface_map *gic_cpuiface =
(volatile struct gic_cpu_iface_map*)(GIC_PL390_CONTROLLER_PPTR);
/*
* The only sane way to get an GIC IRQ number that can be properly
* ACKED later is through the int_ack register. Unfortunately, reading
* this register changes the interrupt state to pending so future
* reads will not return the same value For this reason, we have a
* global variable to store the IRQ number.
*/
static rt_uint32_t active_irq = GIC390_IRQ_NONE;
rt_inline int is_irq_edge_triggered(int irq)
{
int word = irq / 16;
int bit = ((irq & 0xf) * 2);
return !!(gic_dist->config[word] & BIT(bit + 1));
}
rt_inline void dist_pending_clr(int irq)
{
int word = irq / 32;
int bit = irq & 0x1f;
gic_dist->pending_clr[word] = BIT(bit);
}
rt_inline void dist_init(void)
{
int i;
int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
gic_dist->enable = 0;
for (i = 0; i < nirqs; i += 32)
{
/* disable */
gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
/* clear pending */
gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
}
/* reset interrupts priority */
for (i = 32; i < nirqs; i += 4)
{
gic_dist->priority[i / 4] = 0x0;
}
/*
* reset int target to cpu 0
* (Should really query which processor we're running on and use that)
*/
for (i = 0; i < nirqs; i += 4)
{
gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
}
/* level-triggered, 1-N */
for (i = 64; i < nirqs; i += 32)
{
gic_dist->config[i / 32] = 0;
}
/* enable the int controller */
gic_dist->enable = 1;
}
rt_inline void cpu_iface_init(void)
{
rt_uint32_t i;
/* For non-Exynos4, the registers are banked per CPU, need to clear them */
gic_dist->enable_clr[0] = IRQ_SET_ALL;
gic_dist->pending_clr[0] = IRQ_SET_ALL;
gic_dist->priority[0] = 0x00;
/* put everything in group 0 */
/* clear any software generated interrupts */
for (i = 0; i < 16; i += 4)
{
gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
}
gic_cpuiface->icontrol = 0;
gic_cpuiface->pri_msk_c = 0x000000f0;
gic_cpuiface->pb_c = 0x00000003;
while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != GIC390_IRQ_NONE)
{
gic_cpuiface->eoi = i;
}
gic_cpuiface->icontrol = 0x1;
}
void arm_gic_irq_init(void)
{
dist_init();
cpu_iface_init();
}
int arm_gic_get_active_irq(void)
{
int irq;
if (!IS_IRQ_VALID(active_irq))
{
active_irq = gic_cpuiface->int_ack;
}
if (IS_IRQ_VALID(active_irq))
{
irq = active_irq & IRQ_MASK;
}
else
{
irq = GIC390_IRQ_NONE;
}
return irq;
}
void arm_gic_mask(int irq)
{
int word = irq / 32;
int bit = irq & 0x1f;
gic_dist->enable_clr[word] = BIT(bit);
}
void arm_gic_umask(int irq)
{
int word = irq / 32;
int bit = irq & 0x1f;
gic_dist->enable_set[word] = BIT(bit);
}
void arm_gic_ack(int irq)
{
if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq))
{
return;
}
if (is_irq_edge_triggered(irq))
{
dist_pending_clr(irq);
}
gic_cpuiface->eoi = active_irq;
active_irq = GIC390_IRQ_NONE;
}
int rt_hw_interrupt_get_irq(void)
{
return arm_gic_get_active_irq();
}
void rt_hw_interrupt_ack(int fiq_irq)
{
return arm_gic_ack(fiq_irq);
}

27
libcpu/aarch64/common/gic/gic_pl390.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-31 GuEe-GUI the first version
*/
#ifndef GIC_PL390_H__
#define GIC_PL390_H__
#include <board.h>
#define GIC390_SPECIAL_IRQ_START 1020
#define GIC390_IRQ_NONE 1023
void arm_gic_irq_init(void);
int arm_gic_get_active_irq(void);
void arm_gic_ack(int irq);
void arm_gic_mask(int irq);
void arm_gic_umask(int irq);
#endif

7
libcpu/aarch64/cortex-a53/entry_point.S
View File

@ -35,7 +35,7 @@ _start:
// ldr x2, =EL1_stack // ldr x2, =EL1_stack
// mov sp, x2 // mov sp, x2
ldr x1, =_start ldr x1, =init_el1_stack_limit
// set up EL1 // set up EL1
mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved
@ -109,3 +109,8 @@ _start:
bl entry bl entry
// for failsafe, halt this core too // for failsafe, halt this core too
b .L__current_cpu_idle b .L__current_cpu_idle
.bss
.align 3
init_el1_stack:
.space 4096
init_el1_stack_limit:

19
libcpu/aarch64/cortex-a53/interrupt.c
View File

@ -9,6 +9,7 @@
* 2019-07-28 zdzn add smp support * 2019-07-28 zdzn add smp support
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
* 2021-07-31 GuEe-GUI Add gic pl390 branch
*/ */
#include <rthw.h> #include <rthw.h>
@ -19,6 +20,10 @@
#include "armv8.h" #include "armv8.h"
#include "interrupt.h" #include "interrupt.h"
#ifdef BSP_USING_GIC390
#include <gic_pl390.h>
#endif
#define MAX_HANDLERS 72 #define MAX_HANDLERS 72
#ifdef RT_USING_SMP #ifdef RT_USING_SMP
@ -41,6 +46,7 @@ void rt_hw_vector_init(void)
rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S
} }
#ifndef BSP_USING_GIC
static void default_isr_handler(int vector, void *param) static void default_isr_handler(int vector, void *param)
{ {
#ifdef RT_USING_SMP #ifdef RT_USING_SMP
@ -49,12 +55,16 @@ static void default_isr_handler(int vector, void *param)
rt_kprintf("unhandled irq: %d\n",vector); rt_kprintf("unhandled irq: %d\n",vector);
#endif #endif
} }
#endif
/** /**
* This function will initialize hardware interrupt * This function will initialize hardware interrupt
*/ */
void rt_hw_interrupt_init(void) void rt_hw_interrupt_init(void)
{ {
#ifdef BSP_USING_GIC390
arm_gic_irq_init();
#else
rt_uint32_t index; rt_uint32_t index;
/* mask all of interrupts */ /* mask all of interrupts */
@ -76,6 +86,7 @@ void rt_hw_interrupt_init(void)
rt_interrupt_from_thread = 0; rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0; rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0; rt_thread_switch_interrupt_flag = 0;
#endif
} }
/** /**
@ -84,6 +95,9 @@ void rt_hw_interrupt_init(void)
*/ */
void rt_hw_interrupt_mask(int vector) void rt_hw_interrupt_mask(int vector)
{ {
#ifdef BSP_USING_GIC390
arm_gic_mask(vector);
#else
if (vector < 32) if (vector < 32)
{ {
IRQ_DISABLE1 = (1 << vector); IRQ_DISABLE1 = (1 << vector);
@ -98,6 +112,7 @@ void rt_hw_interrupt_mask(int vector)
vector = vector - 64; vector = vector - 64;
IRQ_DISABLE_BASIC = (1 << vector); IRQ_DISABLE_BASIC = (1 << vector);
} }
#endif
} }
/** /**
@ -106,6 +121,9 @@ void rt_hw_interrupt_mask(int vector)
*/ */
void rt_hw_interrupt_umask(int vector) void rt_hw_interrupt_umask(int vector)
{ {
#ifdef BSP_USING_GIC390
arm_gic_umask(vector);
#else
if (vector < 32) if (vector < 32)
{ {
IRQ_ENABLE1 = (1 << vector); IRQ_ENABLE1 = (1 << vector);
@ -120,6 +138,7 @@ void rt_hw_interrupt_umask(int vector)
vector = vector - 64; vector = vector - 64;
IRQ_ENABLE_BASIC = (1 << vector); IRQ_ENABLE_BASIC = (1 << vector);
} }
#endif
} }
/** /**

2
libcpu/aarch64/cortex-a53/interrupt.h
View File

@ -14,8 +14,6 @@
#include <rthw.h> #include <rthw.h>
#include <board.h> #include <board.h>
#include "raspi.h"
#define INT_IRQ 0x00 #define INT_IRQ 0x00
#define INT_FIQ 0x01 #define INT_FIQ 0x01

25
libcpu/aarch64/cortex-a53/trap.c
View File

@ -4,7 +4,8 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Date Author Notes * Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version * 2018-10-06 ZhaoXiaowei the first version
* 2021-07-31 GuEe-GUI Add gic_pl390 branch
*/ */
#include <rtthread.h> #include <rtthread.h>
@ -13,6 +14,10 @@
#include "interrupt.h" #include "interrupt.h"
#include "armv8.h" #include "armv8.h"
#ifdef BSP_USING_GIC390
#include <gic_pl390.h>
#endif
extern struct rt_thread *rt_current_thread; extern struct rt_thread *rt_current_thread;
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH
extern long list_thread(void); extern long list_thread(void);
@ -65,6 +70,8 @@ void rt_hw_trap_irq(void)
uint32_t irq; uint32_t irq;
rt_isr_handler_t isr_func; rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[]; extern struct rt_irq_desc isr_table[];
#ifndef BSP_USING_GIC390
uint32_t value = 0; uint32_t value = 0;
value = IRQ_PEND_BASIC & 0x3ff; value = IRQ_PEND_BASIC & 0x3ff;
#ifdef BSP_USING_CORETIMER #ifdef BSP_USING_CORETIMER
@ -100,6 +107,15 @@ void rt_hw_trap_irq(void)
value &= 0x0f; value &= 0x0f;
irq = __rt_ffs(value) + 63; irq = __rt_ffs(value) + 63;
} }
#else
irq = arm_gic_get_active_irq();
if (irq == GIC390_IRQ_NONE)
{
/* Spurious interrupt */
return;
}
#endif
/* get interrupt service routine */ /* get interrupt service routine */
isr_func = isr_table[irq].handler; isr_func = isr_table[irq].handler;
@ -113,11 +129,17 @@ void rt_hw_trap_irq(void)
/* turn to interrupt service routine */ /* turn to interrupt service routine */
isr_func(irq, param); isr_func(irq, param);
} }
#ifndef BSP_USING_GIC390
} }
#else
/* end of interrupt */
arm_gic_ack(irq);
#endif
} }
void rt_hw_trap_fiq(void) void rt_hw_trap_fiq(void)
{ {
#ifndef BSP_USING_GIC390
void *param; void *param;
uint32_t irq; uint32_t irq;
rt_isr_handler_t isr_func; rt_isr_handler_t isr_func;
@ -199,4 +221,5 @@ void rt_hw_trap_fiq(void)
isr_func(irq, param); isr_func(irq, param);
} }
} }
#endif
} }

2
src/memheap.c
View File

@ -438,7 +438,7 @@ void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize)
next_ptr->pool_ptr = heap; next_ptr->pool_ptr = heap;
#ifdef RT_USING_MEMTRACE #ifdef RT_USING_MEMTRACE
rt_memset(next_ptr->owner_thread_name, ' ', sizeof(next_ptr->owner_thread_name)); rt_memset((void *)next_ptr->owner_thread_name, ' ', sizeof(next_ptr->owner_thread_name));
#endif /* RT_USING_MEMTRACE */ #endif /* RT_USING_MEMTRACE */
next_ptr->prev = header_ptr; next_ptr->prev = header_ptr;