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add rt_hw_cpu_reset for cortex-m cpu

This commit is contained in:
hichard_ren@yeah.net 2018-08-01 11:57:56 +08:00
parent bbb879717c
commit b46e7f3172
3 changed files with 30 additions and 0 deletions
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10
libcpu/arm/cortex-m3/cpuport.c
View File

@ -110,6 +110,8 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context))
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
@ -352,6 +354,14 @@ void rt_hw_cpu_shutdown(void)
RT_ASSERT(0); RT_ASSERT(0);
} }
/**
* reset CPU
*/
RT_WEAK void rt_hw_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}
#ifdef RT_USING_CPU_FFS #ifdef RT_USING_CPU_FFS
/** /**
* This function finds the first bit set (beginning with the least significant bit) * This function finds the first bit set (beginning with the least significant bit)

10
libcpu/arm/cortex-m4/cpuport.c
View File

@ -187,6 +187,8 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
@ -431,6 +433,14 @@ void rt_hw_cpu_shutdown(void)
RT_ASSERT(0); RT_ASSERT(0);
} }
/**
* reset CPU
*/
RT_WEAK void rt_hw_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}
#ifdef RT_USING_CPU_FFS #ifdef RT_USING_CPU_FFS
/** /**
* This function finds the first bit set (beginning with the least significant bit) * This function finds the first bit set (beginning with the least significant bit)

10
libcpu/arm/cortex-m7/cpuport.c
View File

@ -187,6 +187,8 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
@ -431,6 +433,14 @@ void rt_hw_cpu_shutdown(void)
RT_ASSERT(0); RT_ASSERT(0);
} }
/**
* reset CPU
*/
RT_WEAK void rt_hw_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}
#ifdef RT_USING_CPU_FFS #ifdef RT_USING_CPU_FFS
/** /**
* This function finds the first bit set (beginning with the least significant bit) * This function finds the first bit set (beginning with the least significant bit)