diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript index 08b937f188..4761127102 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript @@ -14,15 +14,6 @@ if GetDepend(['RT_USING_PIN']): if GetDepend(['RT_USING_SERIAL']): src += ['drv_usart.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] - -if GetDepend(['RT_USING_PWM']): - src += ['drv_pwm.c'] - -if GetDepend(['RT_USING_SPI']): - src += ['drv_spi.c'] - path = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h index 73a89a2b88..bb24afa19e 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h @@ -5,9 +5,9 @@ * * Change Logs: * Date Author Notes - * 2020-04-08 Huaqi first version + * 2020-04-08 hqfang first version */ - + #ifndef __DRV_CONFIG_H__ #define __DRV_CONFIG_H__ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c index d14d4339ce..75ab81f18e 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c @@ -13,132 +13,132 @@ #ifdef RT_USING_PIN static const struct pin_index pins[] = - { +{ - __GD32_PIN(0, A, 0), - __GD32_PIN(1, A, 1), - __GD32_PIN(2, A, 2), - __GD32_PIN(3, A, 3), - __GD32_PIN(4, A, 4), - __GD32_PIN(5, A, 5), - __GD32_PIN(6, A, 6), - __GD32_PIN(7, A, 7), - __GD32_PIN(8, A, 8), - __GD32_PIN(9, A, 9), - __GD32_PIN(10, A, 10), - __GD32_PIN(11, A, 11), - __GD32_PIN(12, A, 12), - __GD32_PIN(13, A, 13), - __GD32_PIN(14, A, 14), - __GD32_PIN(15, A, 15), + __GD32_PIN(0, A, 0), + __GD32_PIN(1, A, 1), + __GD32_PIN(2, A, 2), + __GD32_PIN(3, A, 3), + __GD32_PIN(4, A, 4), + __GD32_PIN(5, A, 5), + __GD32_PIN(6, A, 6), + __GD32_PIN(7, A, 7), + __GD32_PIN(8, A, 8), + __GD32_PIN(9, A, 9), + __GD32_PIN(10, A, 10), + __GD32_PIN(11, A, 11), + __GD32_PIN(12, A, 12), + __GD32_PIN(13, A, 13), + __GD32_PIN(14, A, 14), + __GD32_PIN(15, A, 15), - __GD32_PIN(16, B, 0), - __GD32_PIN(17, B, 1), - __GD32_PIN(18, B, 2), - __GD32_PIN(19, B, 3), - __GD32_PIN(20, B, 4), - __GD32_PIN(21, B, 5), - __GD32_PIN(22, B, 6), - __GD32_PIN(23, B, 7), - __GD32_PIN(24, B, 8), - __GD32_PIN(25, B, 9), - __GD32_PIN(26, B, 10), - __GD32_PIN(27, B, 11), - __GD32_PIN(28, B, 12), - __GD32_PIN(29, B, 13), - __GD32_PIN(30, B, 14), - __GD32_PIN(31, B, 15), + __GD32_PIN(16, B, 0), + __GD32_PIN(17, B, 1), + __GD32_PIN(18, B, 2), + __GD32_PIN(19, B, 3), + __GD32_PIN(20, B, 4), + __GD32_PIN(21, B, 5), + __GD32_PIN(22, B, 6), + __GD32_PIN(23, B, 7), + __GD32_PIN(24, B, 8), + __GD32_PIN(25, B, 9), + __GD32_PIN(26, B, 10), + __GD32_PIN(27, B, 11), + __GD32_PIN(28, B, 12), + __GD32_PIN(29, B, 13), + __GD32_PIN(30, B, 14), + __GD32_PIN(31, B, 15), - __GD32_PIN(32, C, 0), - __GD32_PIN(33, C, 1), - __GD32_PIN(34, C, 2), - __GD32_PIN(35, C, 3), - __GD32_PIN(36, C, 4), - __GD32_PIN(37, C, 5), - __GD32_PIN(38, C, 6), - __GD32_PIN(39, C, 7), - __GD32_PIN(40, C, 8), - __GD32_PIN(41, C, 9), - __GD32_PIN(42, C, 10), - __GD32_PIN(43, C, 11), - __GD32_PIN(44, C, 12), - __GD32_PIN(45, C, 13), - __GD32_PIN(46, C, 14), - __GD32_PIN(47, C, 15), + __GD32_PIN(32, C, 0), + __GD32_PIN(33, C, 1), + __GD32_PIN(34, C, 2), + __GD32_PIN(35, C, 3), + __GD32_PIN(36, C, 4), + __GD32_PIN(37, C, 5), + __GD32_PIN(38, C, 6), + __GD32_PIN(39, C, 7), + __GD32_PIN(40, C, 8), + __GD32_PIN(41, C, 9), + __GD32_PIN(42, C, 10), + __GD32_PIN(43, C, 11), + __GD32_PIN(44, C, 12), + __GD32_PIN(45, C, 13), + __GD32_PIN(46, C, 14), + __GD32_PIN(47, C, 15), - __GD32_PIN(48, D, 0), - __GD32_PIN(49, D, 1), - __GD32_PIN(50, D, 2), - __GD32_PIN(51, D, 3), - __GD32_PIN(52, D, 4), - __GD32_PIN(53, D, 5), - __GD32_PIN(54, D, 6), - __GD32_PIN(55, D, 7), - __GD32_PIN(56, D, 8), - __GD32_PIN(57, D, 9), - __GD32_PIN(58, D, 10), - __GD32_PIN(59, D, 11), - __GD32_PIN(60, D, 12), - __GD32_PIN(61, D, 13), - __GD32_PIN(62, D, 14), - __GD32_PIN(63, D, 15), + __GD32_PIN(48, D, 0), + __GD32_PIN(49, D, 1), + __GD32_PIN(50, D, 2), + __GD32_PIN(51, D, 3), + __GD32_PIN(52, D, 4), + __GD32_PIN(53, D, 5), + __GD32_PIN(54, D, 6), + __GD32_PIN(55, D, 7), + __GD32_PIN(56, D, 8), + __GD32_PIN(57, D, 9), + __GD32_PIN(58, D, 10), + __GD32_PIN(59, D, 11), + __GD32_PIN(60, D, 12), + __GD32_PIN(61, D, 13), + __GD32_PIN(62, D, 14), + __GD32_PIN(63, D, 15), - __GD32_PIN(64, E, 0), - __GD32_PIN(65, E, 1), - __GD32_PIN(66, E, 2), - __GD32_PIN(67, E, 3), - __GD32_PIN(68, E, 4), - __GD32_PIN(69, E, 5), - __GD32_PIN(70, E, 6), - __GD32_PIN(71, E, 7), - __GD32_PIN(72, E, 8), - __GD32_PIN(73, E, 9), - __GD32_PIN(74, E, 10), - __GD32_PIN(75, E, 11), - __GD32_PIN(76, E, 12), - __GD32_PIN(77, E, 13), - __GD32_PIN(78, E, 14), - __GD32_PIN(79, E, 15), + __GD32_PIN(64, E, 0), + __GD32_PIN(65, E, 1), + __GD32_PIN(66, E, 2), + __GD32_PIN(67, E, 3), + __GD32_PIN(68, E, 4), + __GD32_PIN(69, E, 5), + __GD32_PIN(70, E, 6), + __GD32_PIN(71, E, 7), + __GD32_PIN(72, E, 8), + __GD32_PIN(73, E, 9), + __GD32_PIN(74, E, 10), + __GD32_PIN(75, E, 11), + __GD32_PIN(76, E, 12), + __GD32_PIN(77, E, 13), + __GD32_PIN(78, E, 14), + __GD32_PIN(79, E, 15), }; static const struct pin_irq_map pin_irq_map[] = - { - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI5_9_IRQn}, - {GPIO_PIN_6, EXTI5_9_IRQn}, - {GPIO_PIN_7, EXTI5_9_IRQn}, - {GPIO_PIN_8, EXTI5_9_IRQn}, - {GPIO_PIN_9, EXTI5_9_IRQn}, - {GPIO_PIN_10, EXTI10_15_IRQn}, - {GPIO_PIN_11, EXTI10_15_IRQn}, - {GPIO_PIN_12, EXTI10_15_IRQn}, - {GPIO_PIN_13, EXTI10_15_IRQn}, - {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_9_IRQn}, + {GPIO_PIN_6, EXTI5_9_IRQn}, + {GPIO_PIN_7, EXTI5_9_IRQn}, + {GPIO_PIN_8, EXTI5_9_IRQn}, + {GPIO_PIN_9, EXTI5_9_IRQn}, + {GPIO_PIN_10, EXTI10_15_IRQn}, + {GPIO_PIN_11, EXTI10_15_IRQn}, + {GPIO_PIN_12, EXTI10_15_IRQn}, + {GPIO_PIN_13, EXTI10_15_IRQn}, + {GPIO_PIN_14, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, }; static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = - { - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, }; static uint32_t pin_irq_enable_mask = 0; @@ -205,29 +205,30 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) pin_mode = GPIO_MODE_OUT_PP; - switch (mode) { - case PIN_MODE_OUTPUT: - /* output setting */ - pin_mode = GPIO_MODE_OUT_PP; - break; - case PIN_MODE_OUTPUT_OD: - /* output setting: od. */ - pin_mode = GPIO_MODE_OUT_OD; - break; - case PIN_MODE_INPUT: - /* input setting: not pull. */ - pin_mode = GPIO_MODE_IN_FLOATING; - break; - case PIN_MODE_INPUT_PULLUP: - /* input setting: pull up. */ - pin_mode = GPIO_MODE_IPU; - break; - case PIN_MODE_INPUT_PULLDOWN: - /* input setting: pull down. */ - pin_mode = GPIO_MODE_IPD; - break; - default: - break; + switch (mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + pin_mode = GPIO_MODE_OUT_PP; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + pin_mode = GPIO_MODE_OUT_OD; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + pin_mode = GPIO_MODE_IN_FLOATING; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + pin_mode = GPIO_MODE_IPU; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + pin_mode = GPIO_MODE_IPD; + break; + default: + break; } gpio_init(index->gpio, pin_mode, GPIO_OSPEED_50MHZ, index->pin); @@ -276,9 +277,9 @@ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) { rt_hw_interrupt_enable(level); return RT_EOK; @@ -362,19 +363,20 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, irqmap = &pin_irq_map[irqindex]; - switch (pin_irq_hdr_tab[irqindex].mode) { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return RT_EINVAL; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; } /* connect EXTI line to GPIO pin */ gpio_exti_source_select(index->gpio, index->pin); @@ -398,20 +400,20 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, { return RT_EINVAL; } - if (( irqmap->pinbit>=GPIO_PIN_5 )&&( irqmap->pinbit<=GPIO_PIN_9 )) + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) { - if(!(pin_irq_enable_mask&(GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9))) - { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { ECLIC_DisableIRQ(irqmap->irqno); } } - else if (( irqmap->pinbit>=GPIO_PIN_10 )&&( irqmap->pinbit<=GPIO_PIN_15 )) + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) { - if(!(pin_irq_enable_mask&(GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15))) - { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { ECLIC_DisableIRQ(irqmap->irqno); } - } + } else { ECLIC_DisableIRQ(irqmap->irqno); @@ -425,13 +427,13 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_EOK; } const static struct rt_pin_ops _gd32_pin_ops = - { - gd32_pin_mode, - gd32_pin_write, - gd32_pin_read, - gd32_pin_attach_irq, - gd32_pin_dettach_irq, - gd32_pin_irq_enable, +{ + gd32_pin_mode, + gd32_pin_write, + gd32_pin_read, + gd32_pin_attach_irq, + gd32_pin_dettach_irq, + gd32_pin_irq_enable, }; rt_inline void pin_irq_hdr(int irqno) @@ -444,7 +446,7 @@ rt_inline void pin_irq_hdr(int irqno) void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) { - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) + if (RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) { pin_irq_hdr(exti_line); exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h index add6e04542..93d24a8317 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-06 balanceTWK first version + * 2020-04-15 hqfang Modify for gd32vf103 */ #ifndef __DRV_GPIO_H__ @@ -21,13 +22,13 @@ #define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN) #define __GD32_PIN(index, gpio, gpio_index) \ - { \ - index, GPIO##gpio, GPIO_PIN_##gpio_index \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ } #define __GD32_PIN_RESERVE \ - { \ - -1, 0, 0 \ + { \ + -1, 0, 0 \ } /* GD32 GPIO driver */ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c index 79e6136166..00fac33b3e 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2019-07-23 tyustli first version - * 2020-04-02 fanghuaqi Modified for Nuclei + * 2020-04-02 hqfang modified for Nuclei */ #include @@ -19,7 +19,8 @@ /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif -enum { +enum +{ #ifdef BSP_USING_UART0 GDUART0_INDEX, #endif @@ -37,38 +38,50 @@ enum { #endif }; -static struct gd32_uart_config uart_config[] = { +static struct gd32_uart_config uart_config[] = +{ #ifdef BSP_USING_UART0 - { "uart0", + { + "uart0", USART0, - USART0_IRQn, }, + USART0_IRQn, + }, #endif #ifdef BSP_USING_UART1 - { "uart1", + { + "uart1", USART1, - USART1_IRQn, }, + USART1_IRQn, + }, #endif #ifdef BSP_USING_UART2 - { "uart2", + { + "uart2", USART2, - USART2_IRQn, }, + USART2_IRQn, + }, #endif #ifdef BSP_USING_UART3 - { "uart3", + { + "uart3", USART3, - USART3_IRQn, }, + USART3_IRQn, + }, #endif #ifdef BSP_USING_UART4 - { "uart4", + { + "uart4", UART4, - UART4_IRQn, }, + UART4_IRQn, + }, #endif }; static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; static rt_err_t gd32_configure(struct rt_serial_device *serial, - struct serial_configure *cfg) { + struct serial_configure *cfg) +{ struct gd32_uart *usart_obj; struct gd32_uart_config *usart; RT_ASSERT(serial != RT_NULL); @@ -81,7 +94,8 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, usart_deinit(usart->uart_base); usart_baudrate_set(usart->uart_base, cfg->baud_rate); - switch (cfg->data_bits) { + switch (cfg->data_bits) + { case DATA_BITS_8: usart_word_length_set(usart->uart_base, USART_WL_8BIT); break; @@ -94,7 +108,8 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, break; } - switch (cfg->stop_bits) { + switch (cfg->stop_bits) + { case STOP_BITS_1: usart_stop_bit_set(usart->uart_base, USART_STB_1BIT); break; @@ -106,7 +121,8 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, break; } - switch (cfg->parity) { + switch (cfg->parity) + { case PARITY_NONE: usart_parity_config(usart->uart_base, USART_PM_NONE); break; @@ -130,7 +146,8 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, } static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, - void *arg) { + void *arg) +{ struct gd32_uart *usart_obj; struct gd32_uart_config *usart; @@ -139,7 +156,8 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, usart = usart_obj->config; RT_ASSERT(usart != RT_NULL); - switch (cmd) { + switch (cmd) + { case RT_DEVICE_CTRL_CLR_INT: ECLIC_DisableIRQ(usart->irqn); usart_interrupt_disable(usart->uart_base, USART_INT_RBNE); @@ -154,7 +172,8 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, return RT_EOK; } -static int gd32_putc(struct rt_serial_device *serial, char ch) { +static int gd32_putc(struct rt_serial_device *serial, char ch) +{ struct gd32_uart *usart_obj; struct gd32_uart_config *usart; @@ -169,7 +188,8 @@ static int gd32_putc(struct rt_serial_device *serial, char ch) { return 1; } -static int gd32_getc(struct rt_serial_device *serial) { +static int gd32_getc(struct rt_serial_device *serial) +{ int ch; struct gd32_uart *usart_obj; struct gd32_uart_config *usart; @@ -180,7 +200,8 @@ static int gd32_getc(struct rt_serial_device *serial) { RT_ASSERT(usart != RT_NULL); ch = -1; - if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)) { + if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)) + { ch = usart_data_receive(usart->uart_base) & 0xff; } @@ -188,10 +209,12 @@ static int gd32_getc(struct rt_serial_device *serial) { } static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control, - gd32_putc, gd32_getc, - RT_NULL }; + gd32_putc, gd32_getc, + RT_NULL +}; -static void usart_isr(struct rt_serial_device *serial) { +static void usart_isr(struct rt_serial_device *serial) +{ struct gd32_uart *usart_obj; struct gd32_uart_config *usart; @@ -202,20 +225,26 @@ static void usart_isr(struct rt_serial_device *serial) { if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE) != RESET) - && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))) { + && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))) + { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE); usart_flag_clear(usart->uart_base, USART_FLAG_RBNE); - } else { - if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET) { + } + else + { + if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET) + { usart_flag_clear(usart->uart_base, USART_FLAG_CTSF); } - if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET) { + if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET) + { usart_flag_clear(usart->uart_base, USART_FLAG_LBDF); } - if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET) { + if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET) + { usart_flag_clear(usart->uart_base, USART_FLAG_TC); } } @@ -223,7 +252,8 @@ static void usart_isr(struct rt_serial_device *serial) { #ifdef BSP_USING_UART0 -void USART0_IRQHandler(void) { +void USART0_IRQHandler(void) +{ rt_interrupt_enter(); usart_isr(&uart_obj[GDUART0_INDEX].serial); @@ -235,7 +265,8 @@ void USART0_IRQHandler(void) { #ifdef BSP_USING_UART1 -void USART1_IRQHandler(void) { +void USART1_IRQHandler(void) +{ rt_interrupt_enter(); usart_isr(&uart_obj[GDUART1_INDEX].serial); @@ -247,7 +278,8 @@ void USART1_IRQHandler(void) { #ifdef BSP_USING_UART2 -void USART2_IRQHandler(void) { +void USART2_IRQHandler(void) +{ rt_interrupt_enter(); usart_isr(&uart_obj[GDUART2_INDEX].serial); @@ -259,7 +291,8 @@ void USART2_IRQHandler(void) { #ifdef BSP_USING_UART3 -void UART3_IRQHandler(void) { +void UART3_IRQHandler(void) +{ rt_interrupt_enter(); usart_isr(&uart_obj[GDUART3_INDEX].serial); @@ -271,7 +304,8 @@ void UART3_IRQHandler(void) { #ifdef BSP_USING_UART4 -void UART4_IRQHandler(void) { +void UART4_IRQHandler(void) +{ rt_interrupt_enter(); usart_isr(&uart_obj[GDUART4_INDEX].serial); @@ -281,7 +315,8 @@ void UART4_IRQHandler(void) { #endif -int rt_hw_usart_init(void) { +int rt_hw_usart_init(void) +{ rt_size_t obj_num; int index; @@ -289,7 +324,8 @@ int rt_hw_usart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; rt_err_t result = 0; - for (index = 0; index < obj_num; index++) { + for (index = 0; index < obj_num; index++) + { /* init UART object */ uart_obj[index].config = &uart_config[index]; uart_obj[index].serial.ops = &gd32_uart_ops; @@ -297,9 +333,9 @@ int rt_hw_usart_init(void) { /* register UART device */ result = rt_hw_serial_register(&uart_obj[index].serial, - uart_obj[index].config->name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX - | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]); + uart_obj[index].config->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h index e9ab47ee19..176720c4a2 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-15 hqfang first version + */ #ifndef __DRV_UART_H__ #define __DRV_UART_H__