AArch64: fixup fpu storage's size in stack and append Q16 ~ Q31 (#7815)
Signed-off-by: GuEe-GUI <GuEe-GUI@github.com>
This commit is contained in:
GUI
GitHub
parent
2741bec8f7
commit
b424169e17
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@ -8,9 +8,14 @@
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* 2021-05-18 Jesven first version
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include "rtconfig.h"
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#include "asm-generic.h"
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#include "asm-fpu.h"
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#include "armv8.h"
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/*********************
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* SPSR BIT *
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@ -32,67 +37,6 @@
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#define SPSR_Z(v) ((v) << 30)
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#define SPSR_N(v) ((v) << 31)
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/*********************
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* CONTEXT_OFFSET *
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*********************/
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#define CONTEXT_OFFSET_ELR_EL1 0x0
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#define CONTEXT_OFFSET_SPSR_EL1 0x8
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#define CONTEXT_OFFSET_SP_EL0 0x10
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#define CONTEXT_OFFSET_X30 0x18
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#define CONTEXT_OFFSET_FPCR 0x20
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#define CONTEXT_OFFSET_FPSR 0x28
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#define CONTEXT_OFFSET_X28 0x30
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#define CONTEXT_OFFSET_X29 0x38
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#define CONTEXT_OFFSET_X26 0x40
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#define CONTEXT_OFFSET_X27 0x48
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#define CONTEXT_OFFSET_X24 0x50
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#define CONTEXT_OFFSET_X25 0x58
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#define CONTEXT_OFFSET_X22 0x60
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#define CONTEXT_OFFSET_X23 0x68
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#define CONTEXT_OFFSET_X20 0x70
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#define CONTEXT_OFFSET_X21 0x78
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#define CONTEXT_OFFSET_X18 0x80
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#define CONTEXT_OFFSET_X19 0x88
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#define CONTEXT_OFFSET_X16 0x90
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#define CONTEXT_OFFSET_X17 0x98
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#define CONTEXT_OFFSET_X14 0xa0
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#define CONTEXT_OFFSET_X15 0xa8
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#define CONTEXT_OFFSET_X12 0xb0
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#define CONTEXT_OFFSET_X13 0xb8
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#define CONTEXT_OFFSET_X10 0xc0
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#define CONTEXT_OFFSET_X11 0xc8
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#define CONTEXT_OFFSET_X8 0xd0
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#define CONTEXT_OFFSET_X9 0xd8
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#define CONTEXT_OFFSET_X6 0xe0
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#define CONTEXT_OFFSET_X7 0xe8
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#define CONTEXT_OFFSET_X4 0xf0
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#define CONTEXT_OFFSET_X5 0xf8
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#define CONTEXT_OFFSET_X2 0x100
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#define CONTEXT_OFFSET_X3 0x108
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#define CONTEXT_OFFSET_X0 0x110
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#define CONTEXT_OFFSET_X1 0x118
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#define CONTEXT_OFFSET_Q15 0x120
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#define CONTEXT_OFFSET_Q14 0x130
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#define CONTEXT_OFFSET_Q13 0x140
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#define CONTEXT_OFFSET_Q12 0x150
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#define CONTEXT_OFFSET_Q11 0x160
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#define CONTEXT_OFFSET_Q10 0x170
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#define CONTEXT_OFFSET_Q9 0x180
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#define CONTEXT_OFFSET_Q8 0x190
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#define CONTEXT_OFFSET_Q7 0x1a0
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#define CONTEXT_OFFSET_Q6 0x1b0
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#define CONTEXT_OFFSET_Q5 0x1c0
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#define CONTEXT_OFFSET_Q4 0x1d0
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#define CONTEXT_OFFSET_Q3 0x1e0
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#define CONTEXT_OFFSET_Q2 0x1f0
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#define CONTEXT_OFFSET_Q1 0x200
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#define CONTEXT_OFFSET_Q0 0x210
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#define CONTEXT_FPU_SIZE 0x100
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#define CONTEXT_SIZE 0x220
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/**************************************************/
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.text
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@ -370,50 +314,6 @@ arch_ret_to_user:
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1:
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eret
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/*
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struct rt_hw_exp_stack
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{
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unsigned long pc; 0
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unsigned long cpsr;
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unsigned long sp_el0; 0x10
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unsigned long x30;
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unsigned long fpcr; 0x20
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unsigned long fpsr;
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unsigned long x28; 0x30
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unsigned long x29;
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unsigned long x26; 0x40
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unsigned long x27;
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unsigned long x24; 0x50
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unsigned long x25;
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unsigned long x22; 0x60
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unsigned long x23;
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unsigned long x20; 0x70
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unsigned long x21;
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unsigned long x18; 0x80
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unsigned long x19;
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unsigned long x16; 0x90
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unsigned long x17;
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unsigned long x14; 0xa0
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unsigned long x15;
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unsigned long x12; 0xb0
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unsigned long x13;
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unsigned long x10; 0xc0
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unsigned long x11;
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unsigned long x8; 0xd0
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unsigned long x9;
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unsigned long x6; 0xe0
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unsigned long x7;
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unsigned long x4; 0xf0
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unsigned long x5;
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unsigned long x2; 0x100
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unsigned long x3;
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unsigned long x0; 0x110
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unsigned long x1;
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unsigned long long fpu[16]; 0x120
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0x220 = 0x120 + 0x10 * 0x10
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};
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*/
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.global lwp_check_debug
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lwp_check_debug:
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ldr x0, =rt_dbg_ops
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@ -11,47 +11,132 @@
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#ifndef __ARMV8_H__
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#define __ARMV8_H__
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#ifdef __ASSEMBLY__
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/*********************
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* CONTEXT_OFFSET *
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*********************/
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#define CONTEXT_OFFSET_ELR_EL1 0x0
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#define CONTEXT_OFFSET_SPSR_EL1 0x8
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#define CONTEXT_OFFSET_SP_EL0 0x10
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#define CONTEXT_OFFSET_X30 0x18
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#define CONTEXT_OFFSET_FPCR 0x20
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#define CONTEXT_OFFSET_FPSR 0x28
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#define CONTEXT_OFFSET_X28 0x30
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#define CONTEXT_OFFSET_X29 0x38
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#define CONTEXT_OFFSET_X26 0x40
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#define CONTEXT_OFFSET_X27 0x48
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#define CONTEXT_OFFSET_X24 0x50
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#define CONTEXT_OFFSET_X25 0x58
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#define CONTEXT_OFFSET_X22 0x60
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#define CONTEXT_OFFSET_X23 0x68
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#define CONTEXT_OFFSET_X20 0x70
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#define CONTEXT_OFFSET_X21 0x78
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#define CONTEXT_OFFSET_X18 0x80
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#define CONTEXT_OFFSET_X19 0x88
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#define CONTEXT_OFFSET_X16 0x90
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#define CONTEXT_OFFSET_X17 0x98
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#define CONTEXT_OFFSET_X14 0xa0
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#define CONTEXT_OFFSET_X15 0xa8
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#define CONTEXT_OFFSET_X12 0xb0
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#define CONTEXT_OFFSET_X13 0xb8
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#define CONTEXT_OFFSET_X10 0xc0
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#define CONTEXT_OFFSET_X11 0xc8
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#define CONTEXT_OFFSET_X8 0xd0
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#define CONTEXT_OFFSET_X9 0xd8
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#define CONTEXT_OFFSET_X6 0xe0
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#define CONTEXT_OFFSET_X7 0xe8
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#define CONTEXT_OFFSET_X4 0xf0
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#define CONTEXT_OFFSET_X5 0xf8
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#define CONTEXT_OFFSET_X2 0x100
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#define CONTEXT_OFFSET_X3 0x108
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#define CONTEXT_OFFSET_X0 0x110
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#define CONTEXT_OFFSET_X1 0x118
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#define CONTEXT_OFFSET_Q31 0x120
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#define CONTEXT_OFFSET_Q30 0x130
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#define CONTEXT_OFFSET_Q29 0x140
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#define CONTEXT_OFFSET_Q28 0x150
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#define CONTEXT_OFFSET_Q27 0x160
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#define CONTEXT_OFFSET_Q26 0x170
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#define CONTEXT_OFFSET_Q25 0x180
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#define CONTEXT_OFFSET_Q24 0x190
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#define CONTEXT_OFFSET_Q23 0x1a0
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#define CONTEXT_OFFSET_Q22 0x1b0
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#define CONTEXT_OFFSET_Q21 0x1c0
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#define CONTEXT_OFFSET_Q20 0x1d0
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#define CONTEXT_OFFSET_Q19 0x1e0
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#define CONTEXT_OFFSET_Q18 0x1f0
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#define CONTEXT_OFFSET_Q17 0x200
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#define CONTEXT_OFFSET_Q16 0x210
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#define CONTEXT_OFFSET_Q15 0x220
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#define CONTEXT_OFFSET_Q14 0x230
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#define CONTEXT_OFFSET_Q13 0x240
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#define CONTEXT_OFFSET_Q12 0x250
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#define CONTEXT_OFFSET_Q11 0x260
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#define CONTEXT_OFFSET_Q10 0x270
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#define CONTEXT_OFFSET_Q9 0x280
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#define CONTEXT_OFFSET_Q8 0x290
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#define CONTEXT_OFFSET_Q7 0x2a0
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#define CONTEXT_OFFSET_Q6 0x2b0
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#define CONTEXT_OFFSET_Q5 0x2c0
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#define CONTEXT_OFFSET_Q4 0x2d0
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#define CONTEXT_OFFSET_Q3 0x2e0
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#define CONTEXT_OFFSET_Q2 0x2f0
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#define CONTEXT_OFFSET_Q1 0x300
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#define CONTEXT_OFFSET_Q0 0x310
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#define CONTEXT_FPU_SIZE (32 * 16)
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#define CONTEXT_SIZE (0x120 + CONTEXT_FPU_SIZE)
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#else /* !__ASSEMBLY__ */
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#include <rtdef.h>
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typedef struct { rt_uint64_t value[2]; } rt_uint128_t;
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/* the exception stack without VFP registers */
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struct rt_hw_exp_stack
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{
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unsigned long pc;
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unsigned long cpsr;
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unsigned long sp_el0;
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unsigned long x30;
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unsigned long fpcr;
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unsigned long fpsr;
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unsigned long x28;
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unsigned long x29;
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unsigned long x26;
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unsigned long x27;
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unsigned long x24;
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unsigned long x25;
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unsigned long x22;
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unsigned long x23;
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unsigned long x20;
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unsigned long x21;
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unsigned long x18;
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unsigned long x19;
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unsigned long x16;
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unsigned long x17;
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unsigned long x14;
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unsigned long x15;
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unsigned long x12;
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unsigned long x13;
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unsigned long x10;
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unsigned long x11;
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unsigned long x8;
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unsigned long x9;
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unsigned long x6;
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unsigned long x7;
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unsigned long x4;
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unsigned long x5;
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unsigned long x2;
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unsigned long x3;
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unsigned long x0;
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unsigned long x1;
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rt_uint64_t pc;
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rt_uint64_t cpsr;
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rt_uint64_t sp_el0;
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rt_uint64_t x30;
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rt_uint64_t fpcr;
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rt_uint64_t fpsr;
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rt_uint64_t x28;
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rt_uint64_t x29;
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rt_uint64_t x26;
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rt_uint64_t x27;
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rt_uint64_t x24;
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rt_uint64_t x25;
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rt_uint64_t x22;
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rt_uint64_t x23;
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rt_uint64_t x20;
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rt_uint64_t x21;
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rt_uint64_t x18;
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rt_uint64_t x19;
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rt_uint64_t x16;
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rt_uint64_t x17;
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rt_uint64_t x14;
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rt_uint64_t x15;
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rt_uint64_t x12;
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rt_uint64_t x13;
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rt_uint64_t x10;
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rt_uint64_t x11;
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rt_uint64_t x8;
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rt_uint64_t x9;
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rt_uint64_t x6;
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rt_uint64_t x7;
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rt_uint64_t x4;
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rt_uint64_t x5;
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rt_uint64_t x2;
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rt_uint64_t x3;
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rt_uint64_t x0;
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rt_uint64_t x1;
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unsigned long long fpu[16];
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rt_uint128_t fpu[32];
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};
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#define SP_ELx ((unsigned long)0x01)
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@ -64,4 +149,6 @@ rt_ubase_t rt_hw_get_current_el(void);
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void rt_hw_set_elx_env(void);
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void rt_hw_set_current_vbar(rt_ubase_t addr);
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#endif /* __ASSEMBLY__ */
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#endif
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@ -1,11 +1,12 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-18 Jesven the first version
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* 2023-07-13 GuEe-GUI append Q16 ~ Q31
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*/
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.macro SAVE_FPU, reg
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@ -25,8 +26,40 @@
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STR Q13, [\reg, #-0x10]!
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STR Q14, [\reg, #-0x10]!
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STR Q15, [\reg, #-0x10]!
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STR Q16, [\reg, #-0x10]!
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STR Q17, [\reg, #-0x10]!
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STR Q18, [\reg, #-0x10]!
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STR Q19, [\reg, #-0x10]!
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STR Q20, [\reg, #-0x10]!
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STR Q21, [\reg, #-0x10]!
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STR Q22, [\reg, #-0x10]!
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STR Q23, [\reg, #-0x10]!
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STR Q24, [\reg, #-0x10]!
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STR Q25, [\reg, #-0x10]!
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STR Q26, [\reg, #-0x10]!
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STR Q27, [\reg, #-0x10]!
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STR Q28, [\reg, #-0x10]!
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STR Q29, [\reg, #-0x10]!
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STR Q30, [\reg, #-0x10]!
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STR Q31, [\reg, #-0x10]!
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.endm
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.macro RESTORE_FPU, reg
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LDR Q31, [\reg], #0x10
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LDR Q30, [\reg], #0x10
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LDR Q29, [\reg], #0x10
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LDR Q28, [\reg], #0x10
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LDR Q27, [\reg], #0x10
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LDR Q26, [\reg], #0x10
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LDR Q25, [\reg], #0x10
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LDR Q24, [\reg], #0x10
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LDR Q23, [\reg], #0x10
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LDR Q22, [\reg], #0x10
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LDR Q21, [\reg], #0x10
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LDR Q20, [\reg], #0x10
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LDR Q19, [\reg], #0x10
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LDR Q18, [\reg], #0x10
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LDR Q17, [\reg], #0x10
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LDR Q16, [\reg], #0x10
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LDR Q15, [\reg], #0x10
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LDR Q14, [\reg], #0x10
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LDR Q13, [\reg], #0x10
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@ -1,11 +1,12 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-12 RT-Thread init
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* 2023-07-13 GuEe-GUI append fpu: Q16 ~ Q31
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*/
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#include <board.h>
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#include <rtthread.h>
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@ -32,38 +33,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
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stk = (rt_ubase_t *)stack_addr;
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*(--stk) = (rt_ubase_t)0; /* Q0 */
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*(--stk) = (rt_ubase_t)0; /* Q0 */
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*(--stk) = (rt_ubase_t)0; /* Q1 */
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*(--stk) = (rt_ubase_t)0; /* Q1 */
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*(--stk) = (rt_ubase_t)0; /* Q2 */
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*(--stk) = (rt_ubase_t)0; /* Q2 */
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*(--stk) = (rt_ubase_t)0; /* Q3 */
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*(--stk) = (rt_ubase_t)0; /* Q3 */
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*(--stk) = (rt_ubase_t)0; /* Q4 */
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*(--stk) = (rt_ubase_t)0; /* Q4 */
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*(--stk) = (rt_ubase_t)0; /* Q5 */
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*(--stk) = (rt_ubase_t)0; /* Q5 */
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*(--stk) = (rt_ubase_t)0; /* Q6 */
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*(--stk) = (rt_ubase_t)0; /* Q6 */
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*(--stk) = (rt_ubase_t)0; /* Q7 */
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*(--stk) = (rt_ubase_t)0; /* Q7 */
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*(--stk) = (rt_ubase_t)0; /* Q8 */
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*(--stk) = (rt_ubase_t)0; /* Q8 */
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*(--stk) = (rt_ubase_t)0; /* Q9 */
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*(--stk) = (rt_ubase_t)0; /* Q9 */
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*(--stk) = (rt_ubase_t)0; /* Q10 */
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*(--stk) = (rt_ubase_t)0; /* Q10 */
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*(--stk) = (rt_ubase_t)0; /* Q11 */
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*(--stk) = (rt_ubase_t)0; /* Q11 */
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*(--stk) = (rt_ubase_t)0; /* Q12 */
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*(--stk) = (rt_ubase_t)0; /* Q12 */
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*(--stk) = (rt_ubase_t)0; /* Q13 */
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*(--stk) = (rt_ubase_t)0; /* Q13 */
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*(--stk) = (rt_ubase_t)0; /* Q14 */
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*(--stk) = (rt_ubase_t)0; /* Q14 */
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*(--stk) = (rt_ubase_t)0; /* Q15 */
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*(--stk) = (rt_ubase_t)0; /* Q15 */
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for (int i = 0; i < 32; ++i)
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{
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stk -= sizeof(rt_uint128_t) / sizeof(rt_ubase_t);
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*(rt_uint128_t *)stk = (rt_uint128_t) { 0 };
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}
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*(--stk) = (rt_ubase_t)0; /* X1 */
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*(--stk) = (rt_ubase_t)parameter; /* X0 */
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Reference in New Issue