[bsp][stm32]完善stm32g0系列部分外设中断处理 (#8509)
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0c96b26c23
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@ -18,72 +18,104 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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/* DMA1 channel1 */
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#if defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx)
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define DMA_Channelx_IRQn DMA1_Ch4_5_DMAMUX1_OVR_IRQn
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define DMA_Channelx_IRQHandler DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#elif defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel1
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#define DMA_Channelx_IRQn DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
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#define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler
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#define SPI1_RX_DMA_IRQ DMA1_Channel1_IRQn
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#else
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#ifdef BSP_UART1_RX_USING_DMA
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#define DMA_Channelx_IRQn DMA1_Ch4_7_DMAMUX1_OVR_IRQn
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#undef BSP_UART1_RX_USING_DMA
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#define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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#endif
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#ifdef BSP_SPI2_RX_USING_DMA
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#undef BSP_SPI2_RX_USING_DMA
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#endif
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_RX_DMA_INSTANCE DMA1_Channel1
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#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
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#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
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#ifdef BSP_SPI2_RX_USING_DMA
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#undef BSP_SPI2_RX_USING_DMA
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#endif
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#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel1
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA1_Channel1_IRQn
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#endif
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#endif
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/* DMA1 channle2-3 */
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/* DMA1 channel2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_3_IRQn
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#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA1_Channel2_3_IRQn
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#endif
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/* DMA1 channle3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
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#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
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#define SPI1_TX_DMA_IRQ DMA1_Channel2_3_IRQn
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#define SPI1_TX_DMA_IRQ DMA1_Channel2_3_IRQn
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#ifdef BSP_UART2_RX_USING_DMA
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#undef BSP_UART2_RX_USING_DMA
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#endif
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#ifdef BSP_SPI2_TX_USING_DMA
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#undef BSP_SPI2_TX_USING_DMA
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#endif
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#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Channel2
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#define UART2_RX_DMA_IRQ DMA1_Channel2_3_IRQn
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#ifdef BSP_SPI2_TX_USING_DMA
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#undef BSP_SPI2_TX_USING_DMA
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#endif
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#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel2
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
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#define SPI2_TX_DMA_IRQ DMA1_Channel2_3_IRQn
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#define SPI2_TX_DMA_IRQ DMA1_Channel2_3_IRQn
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#endif
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#endif
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/* DMA1 channle4 */
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#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_RX_DMA_INSTANCE DMA1_Channel4
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#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
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#define UART1_RX_DMA_IRQ DMA_Channelx_IRQn
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#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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/* DMA1 channle5 */
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#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_TX_DMA_INSTANCE DMA1_Channel5
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#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
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#define UART1_TX_DMA_IRQ DMA_Channelx_IRQn
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#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
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#define SPI2_TX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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#if !(defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx))
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/* DMA1 channle6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Channel6
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#define UART2_RX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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/* DMA1 channle7 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Channel7
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#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
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#define UART2_TX_DMA_IRQ DMA_Channelx_IRQn
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#endif
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#endif
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/* DMA1 channle1 */
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#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
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#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
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#define LPUART1_DMA_RX_IRQHandler DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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#define LPUART1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define LPUART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define LPUART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define LPUART1_RX_DMA_INSTANCE DMA1_Channel5
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#define LPUART1_RX_DMA_INSTANCE DMA1_Channel1
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#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
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#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
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#define LPUART1_RX_DMA_IRQ DMA1_Ch4_7_DMAMUX1_OVR_IRQn
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#define LPUART1_RX_DMA_IRQ DMA1_Channel1_IRQn
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#endif
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#endif
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -55,12 +55,21 @@ extern "C" {
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#ifdef BSP_USING_SPI2
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#ifdef BSP_USING_SPI2
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#ifndef SPI2_BUS_CONFIG
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#ifndef SPI2_BUS_CONFIG
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#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#define SPI2_BUS_CONFIG \
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{ \
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.Instance = SPI2, \
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.bus_name = "spi2", \
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.irq_type = SPI2_3_IRQn, \
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}
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#else
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#define SPI2_BUS_CONFIG \
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#define SPI2_BUS_CONFIG \
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{ \
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{ \
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.Instance = SPI2, \
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.Instance = SPI2, \
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.bus_name = "spi2", \
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.bus_name = "spi2", \
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.irq_type = SPI2_IRQn, \
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.irq_type = SPI2_IRQn, \
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}
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}
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#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
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#endif /* SPI2_BUS_CONFIG */
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#endif /* SPI2_BUS_CONFIG */
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#endif /* BSP_USING_SPI2 */
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#endif /* BSP_USING_SPI2 */
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@ -41,12 +41,21 @@ extern "C" {
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#ifdef BSP_USING_TIM3
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#ifdef BSP_USING_TIM3
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#ifndef TIM3_CONFIG
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#ifndef TIM3_CONFIG
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#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#define TIM3_CONFIG \
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{ \
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.tim_handle.Instance = TIM3, \
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.tim_irqn = TIM3_TIM4_IRQn, \
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.name = "timer3", \
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}
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#else
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#define TIM3_CONFIG \
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#define TIM3_CONFIG \
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{ \
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{ \
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.tim_handle.Instance = TIM3, \
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.tim_handle.Instance = TIM3, \
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.tim_irqn = TIM3_IRQn, \
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.tim_irqn = TIM3_IRQn, \
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.name = "timer3", \
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.name = "timer3", \
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}
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}
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#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
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#endif /* TIM3_CONFIG */
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#endif /* TIM3_CONFIG */
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#endif /* BSP_USING_TIM3 */
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#endif /* BSP_USING_TIM3 */
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#if defined(BSP_USING_LPUART1)
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#if defined(BSP_USING_LPUART1)
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#ifndef LPUART1_CONFIG
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#ifndef LPUART1_CONFIG
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#if defined(STM32G071xx) || defined(STM32G081xx)
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#define LPUART1_CONFIG \
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#define LPUART1_CONFIG \
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{ \
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{ \
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.name = "lpuart1", \
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.name = "lpuart1", \
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.Instance = LPUART1, \
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.Instance = LPUART1, \
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.irq_type = USART3_4_LPUART1_IRQn, \
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.irq_type = USART3_4_LPUART1_IRQn, \
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}
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}
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#define LPUART1_IRQHandler USART3_4_LPUART1_IRQHandler
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#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#define LPUART1_CONFIG \
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{ \
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.name = "lpuart1", \
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.Instance = LPUART1, \
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.irq_type = USART3_4_5_6_LPUART1_IRQn, \
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}
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#endif /* defined(STM32G071xx) || defined(STM32G081xx) */
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#endif /* LPUART1_CONFIG */
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#endif /* LPUART1_CONFIG */
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#if defined(BSP_LPUART1_RX_USING_DMA)
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#if defined(BSP_LPUART1_RX_USING_DMA)
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#ifndef LPUART1_DMA_CONFIG
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#ifndef LPUART1_DMA_CONFIG
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#if defined(BSP_UART1_RX_USING_DMA)
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#if defined(BSP_UART1_RX_USING_DMA)
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#ifndef UART1_DMA_RX_CONFIG
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#ifndef UART1_DMA_RX_CONFIG
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#define UART1_DMA_RX_CONFIG \
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#define UART1_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.request = UART1_RX_DMA_REQUEST, \
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.request = UART1_RX_DMA_REQUEST, \
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#endif /* UART1_DMA_RX_CONFIG */
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#endif /* UART1_DMA_RX_CONFIG */
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#endif /* BSP_UART1_RX_USING_DMA */
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#endif /* BSP_UART1_RX_USING_DMA */
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#if defined(BSP_UART1_TX_USING_DMA)
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#ifndef UART1_DMA_TX_CONFIG
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#define UART1_DMA_TX_CONFIG \
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{ \
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.Instance = UART1_TX_DMA_INSTANCE, \
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.request = UART1_TX_DMA_REQUEST, \
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.dma_rcc = UART1_TX_DMA_RCC, \
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.dma_irq = UART1_TX_DMA_IRQ, \
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}
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#endif /* UART1_DMA_TX_CONFIG */
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#endif /* BSP_UART1_TX_USING_DMA */
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#if defined(BSP_USING_UART2)
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#if defined(BSP_USING_UART2)
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#ifndef UART2_CONFIG
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#ifndef UART2_CONFIG
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#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
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#if defined(BSP_UART2_RX_USING_DMA)
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#if defined(BSP_UART2_RX_USING_DMA)
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#ifndef UART2_DMA_RX_CONFIG
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#ifndef UART2_DMA_RX_CONFIG
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#define UART2_DMA_RX_CONFIG \
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#define UART2_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.request = UART2_RX_DMA_REQUEST, \
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.request = UART2_RX_DMA_REQUEST, \
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#endif /* UART2_DMA_RX_CONFIG */
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#endif /* UART2_DMA_RX_CONFIG */
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#endif /* BSP_UART2_RX_USING_DMA */
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#endif /* BSP_UART2_RX_USING_DMA */
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#if defined(BSP_UART2_TX_USING_DMA)
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#ifndef UART2_DMA_TX_CONFIG
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#define UART2_DMA_TX_CONFIG \
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{ \
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.Instance = UART2_TX_DMA_INSTANCE, \
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.request = UART2_TX_DMA_REQUEST, \
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.dma_rcc = UART2_TX_DMA_RCC, \
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.dma_irq = UART2_TX_DMA_IRQ, \
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}
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#endif /* UART2_DMA_TX_CONFIG */
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#endif /* BSP_UART2_TX_USING_DMA */
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#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
#ifndef UART3_CONFIG
|
#ifndef UART3_CONFIG
|
||||||
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
|
|
@ -157,14 +157,16 @@ static rt_err_t rt_rtc_config(void)
|
||||||
|
|
||||||
HAL_PWR_EnableBkUpAccess();
|
HAL_PWR_EnableBkUpAccess();
|
||||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||||
#ifdef BSP_RTC_USING_LSI
|
#if defined(BSP_RTC_USING_LSI)
|
||||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
||||||
#else
|
#elif defined(BSP_RTC_USING_LSE)
|
||||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||||
|
#else
|
||||||
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
|
||||||
#endif
|
#endif
|
||||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||||
|
|
||||||
#if defined(SOC_SERIES_STM32WL)
|
#if defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0)
|
||||||
__HAL_RCC_RTCAPB_CLK_ENABLE();
|
__HAL_RCC_RTCAPB_CLK_ENABLE();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -194,7 +196,9 @@ static rt_err_t rt_rtc_config(void)
|
||||||
RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
|
RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||||
RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||||
RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
||||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
|
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L0) \
|
||||||
|
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) \
|
||||||
|
|| defined(SOC_SERIES_STM32G0)
|
||||||
|
|
||||||
/* set the frequency division */
|
/* set the frequency division */
|
||||||
#ifdef BSP_RTC_USING_LSI
|
#ifdef BSP_RTC_USING_LSI
|
||||||
|
@ -237,26 +241,24 @@ static rt_err_t stm32_rtc_init(void)
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_RTC_USING_LSI) || defined(BSP_RTC_USING_LSE)
|
||||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||||
#ifdef BSP_RTC_USING_LSI
|
#ifdef BSP_RTC_USING_LSI
|
||||||
#ifdef SOC_SERIES_STM32WB
|
#ifdef SOC_SERIES_STM32WB
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
|
||||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
|
||||||
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
|
|
||||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
|
||||||
#else
|
#else
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
|
||||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
#endif
|
||||||
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
|
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
|
||||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
||||||
#endif
|
|
||||||
#else
|
#else
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
|
||||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||||
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
|
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
|
||||||
#endif
|
#endif
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||||
|
#endif
|
||||||
|
|
||||||
if (rt_rtc_config() != RT_EOK)
|
if (rt_rtc_config() != RT_EOK)
|
||||||
{
|
{
|
||||||
|
|
|
@ -1039,7 +1039,45 @@ void SPI2_DMA_RX_TX_IRQHandler(void)
|
||||||
SPI2_DMA_RX_IRQHandler();
|
SPI2_DMA_RX_IRQHandler();
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
#endif /* SOC_SERIES_STM32F0 */
|
#elif defined(SOC_SERIES_STM32G0)
|
||||||
|
#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
|
||||||
|
void SPI1_DMA_RX_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
#if defined(BSP_SPI1_TX_USING_DMA)
|
||||||
|
SPI1_DMA_TX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_SPI1_RX_USING_DMA)
|
||||||
|
SPI1_DMA_RX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) */
|
||||||
|
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
|
||||||
|
void SPI2_DMA_RX_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
#if defined(BSP_SPI2_TX_USING_DMA)
|
||||||
|
SPI2_DMA_TX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_SPI2_RX_USING_DMA)
|
||||||
|
SPI2_DMA_RX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) */
|
||||||
|
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
|
||||||
|
void SPI2_3_IRQHandler(void)
|
||||||
|
{
|
||||||
|
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
|
||||||
|
SPI2_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
|
||||||
|
SPI3_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */
|
||||||
|
#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||||
|
#endif /* defined(SOC_SERIES_STM32F0) */
|
||||||
|
|
||||||
int rt_hw_spi_init(void)
|
int rt_hw_spi_init(void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -623,6 +623,23 @@ void TIM2_IRQHandler(void)
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
#if defined(BSP_USING_TIM3) || defined(BSP_USING_TIM4)
|
||||||
|
void TIM3_TIM4_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
#ifdef BSP_USING_TIM3
|
||||||
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_TIM4
|
||||||
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
|
||||||
|
#endif
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#else
|
||||||
#ifdef BSP_USING_TIM3
|
#ifdef BSP_USING_TIM3
|
||||||
void TIM3_IRQHandler(void)
|
void TIM3_IRQHandler(void)
|
||||||
{
|
{
|
||||||
|
@ -643,6 +660,7 @@ void TIM4_IRQHandler(void)
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
#ifdef BSP_USING_TIM5
|
#ifdef BSP_USING_TIM5
|
||||||
void TIM5_IRQHandler(void)
|
void TIM5_IRQHandler(void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -827,6 +827,63 @@ void LPUART1_DMA_RX_IRQHandler(void)
|
||||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
|
||||||
#endif /* BSP_USING_LPUART1*/
|
#endif /* BSP_USING_LPUART1*/
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32G0)
|
||||||
|
#if defined(BSP_USING_UART2)
|
||||||
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
void USART2_LPUART2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
USART2_IRQHandler();
|
||||||
|
}
|
||||||
|
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||||
|
#endif /* defined(BSP_USING_UART2) */
|
||||||
|
#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
|
||||||
|
|| defined(BSP_USING_LPUART1)
|
||||||
|
#if defined(STM32G070xx)
|
||||||
|
void USART3_4_IRQHandler(void)
|
||||||
|
#elif defined(STM32G071xx) || defined(STM32G081xx)
|
||||||
|
void USART3_4_LPUART1_IRQHandler(void)
|
||||||
|
#elif defined(STM32G0B0xx)
|
||||||
|
void USART3_4_5_6_IRQHandler(void)
|
||||||
|
#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
void USART3_4_5_6_LPUART1_IRQHandler(void)
|
||||||
|
#endif /* defined(STM32G070xx) */
|
||||||
|
{
|
||||||
|
#if defined(BSP_USING_UART3)
|
||||||
|
USART3_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART4)
|
||||||
|
UART4_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART5)
|
||||||
|
UART5_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART6)
|
||||||
|
USART6_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_LPUART1)
|
||||||
|
LPUART1_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA)
|
||||||
|
void UART_DMA_RX_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
|
||||||
|
UART1_DMA_TX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
|
||||||
|
UART1_DMA_RX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
|
||||||
|
UART2_DMA_TX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
|
||||||
|
UART2_DMA_RX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(RT_SERIAL_USING_DMA) */
|
||||||
|
#endif /* defined(SOC_SERIES_STM32G0) */
|
||||||
|
|
||||||
static void stm32_uart_get_dma_config(void)
|
static void stm32_uart_get_dma_config(void)
|
||||||
{
|
{
|
||||||
#ifdef BSP_USING_UART1
|
#ifdef BSP_USING_UART1
|
||||||
|
@ -940,6 +997,15 @@ static void stm32_uart_get_dma_config(void)
|
||||||
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
|
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART1
|
||||||
|
uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
|
||||||
|
#ifdef BSP_LPUART1_RX_USING_DMA
|
||||||
|
uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
|
static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
|
||||||
|
uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef RT_SERIAL_USING_DMA
|
#ifdef RT_SERIAL_USING_DMA
|
||||||
|
|
|
@ -862,6 +862,64 @@ void LPUART1_DMA_RX_IRQHandler(void)
|
||||||
}
|
}
|
||||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
|
||||||
#endif /* BSP_USING_LPUART1*/
|
#endif /* BSP_USING_LPUART1*/
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32G0)
|
||||||
|
#if defined(BSP_USING_UART2)
|
||||||
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
void USART2_LPUART2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
USART2_IRQHandler();
|
||||||
|
}
|
||||||
|
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
|
||||||
|
#endif /* defined(BSP_USING_UART2) */
|
||||||
|
#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
|
||||||
|
|| defined(BSP_USING_LPUART1)
|
||||||
|
#if defined(STM32G070xx)
|
||||||
|
void USART3_4_IRQHandler(void)
|
||||||
|
#elif defined(STM32G071xx) || defined(STM32G081xx)
|
||||||
|
void USART3_4_LPUART1_IRQHandler(void)
|
||||||
|
#elif defined(STM32G0B0xx)
|
||||||
|
void USART3_4_5_6_IRQHandler(void)
|
||||||
|
#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
||||||
|
void USART3_4_5_6_LPUART1_IRQHandler(void)
|
||||||
|
#endif /* defined(STM32G070xx) */
|
||||||
|
{
|
||||||
|
#if defined(BSP_USING_UART3)
|
||||||
|
USART3_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART4)
|
||||||
|
UART4_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART5)
|
||||||
|
UART5_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART6)
|
||||||
|
USART6_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_LPUART1)
|
||||||
|
LPUART1_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA)
|
||||||
|
void UART_DMA_RX_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
|
||||||
|
UART1_DMA_TX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
|
||||||
|
UART1_DMA_RX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
|
||||||
|
UART2_DMA_TX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
|
||||||
|
UART2_DMA_RX_IRQHandler();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* defined(RT_SERIAL_USING_DMA) */
|
||||||
|
#endif /* defined(SOC_SERIES_STM32G0) */
|
||||||
|
|
||||||
static void stm32_uart_get_config(void)
|
static void stm32_uart_get_config(void)
|
||||||
{
|
{
|
||||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||||
|
@ -1024,6 +1082,20 @@ static void stm32_uart_get_config(void)
|
||||||
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
|
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_LPUART1
|
||||||
|
uart_obj[LPUART1_INDEX].serial.config = config;
|
||||||
|
uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
|
||||||
|
|
||||||
|
uart_obj[LPUART1_INDEX].serial.config.rx_bufsz = BSP_LPUART1_RX_BUFSIZE;
|
||||||
|
uart_obj[LPUART1_INDEX].serial.config.tx_bufsz = BSP_LPUART1_TX_BUFSIZE;
|
||||||
|
|
||||||
|
#ifdef BSP_LPUART1_RX_USING_DMA
|
||||||
|
uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
|
static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
|
||||||
|
uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef RT_SERIAL_USING_DMA
|
#ifdef RT_SERIAL_USING_DMA
|
||||||
|
|
|
@ -30,6 +30,18 @@ menu "On-chip Peripheral Drivers"
|
||||||
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
|
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
|
||||||
default n
|
default n
|
||||||
|
|
||||||
|
config BSP_LPUART1_RX_BUFSIZE
|
||||||
|
int "Set LPUART1 RX buffer size"
|
||||||
|
range 64 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
|
config BSP_LPUART1_TX_BUFSIZE
|
||||||
|
int "Set LPUART1 TX buffer size"
|
||||||
|
range 0 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
config BSP_USING_UART1
|
config BSP_USING_UART1
|
||||||
bool "Enable UART1"
|
bool "Enable UART1"
|
||||||
default n
|
default n
|
||||||
|
@ -39,6 +51,23 @@ menu "On-chip Peripheral Drivers"
|
||||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||||
default n
|
default n
|
||||||
|
|
||||||
|
config BSP_UART1_TX_USING_DMA
|
||||||
|
bool "Enable UART1 TX DMA"
|
||||||
|
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART1_RX_BUFSIZE
|
||||||
|
int "Set UART1 RX buffer size"
|
||||||
|
range 64 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
|
config BSP_UART1_TX_BUFSIZE
|
||||||
|
int "Set UART1 TX buffer size"
|
||||||
|
range 0 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
config BSP_USING_UART2
|
config BSP_USING_UART2
|
||||||
bool "Enable UART2"
|
bool "Enable UART2"
|
||||||
default n
|
default n
|
||||||
|
@ -47,6 +76,23 @@ menu "On-chip Peripheral Drivers"
|
||||||
bool "Enable UART2 RX DMA"
|
bool "Enable UART2 RX DMA"
|
||||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||||
default n
|
default n
|
||||||
|
|
||||||
|
config BSP_UART2_TX_USING_DMA
|
||||||
|
bool "Enable UART2 TX DMA"
|
||||||
|
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART2_RX_BUFSIZE
|
||||||
|
int "Set UART2 RX buffer size"
|
||||||
|
range 64 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
|
config BSP_UART2_TX_BUFSIZE
|
||||||
|
int "Set UART2 TX buffer size"
|
||||||
|
range 0 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
endif
|
endif
|
||||||
|
|
||||||
menuconfig BSP_USING_TIM
|
menuconfig BSP_USING_TIM
|
||||||
|
|
Loading…
Reference in New Issue