[bsp][stm32]完善stm32g0系列部分外设中断处理 (#8509)

This commit is contained in:
yangpengya 2024-01-27 09:56:52 +08:00 committed by GitHub
parent 0c96b26c23
commit b3da34b784
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GPG Key ID: B5690EEEBB952194
10 changed files with 390 additions and 66 deletions

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@ -18,72 +18,104 @@
extern "C" { extern "C" {
#endif #endif
/* DMA1 channel1 */ #if defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx)
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #define DMA_Channelx_IRQn DMA1_Ch4_5_DMAMUX1_OVR_IRQn
#define SPI1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler #define DMA_Channelx_IRQHandler DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN #elif defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
#define SPI1_RX_DMA_INSTANCE DMA1_Channel1 #define DMA_Channelx_IRQn DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX #define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler
#define SPI1_RX_DMA_IRQ DMA1_Channel1_IRQn #else
#ifdef BSP_UART1_RX_USING_DMA #define DMA_Channelx_IRQn DMA1_Ch4_7_DMAMUX1_OVR_IRQn
#undef BSP_UART1_RX_USING_DMA #define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
#endif
#ifdef BSP_SPI2_RX_USING_DMA
#undef BSP_SPI2_RX_USING_DMA
#endif
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART1_RX_DMA_INSTANCE DMA1_Channel1
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
#ifdef BSP_SPI2_RX_USING_DMA
#undef BSP_SPI2_RX_USING_DMA
#endif
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Channel1
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
#define SPI2_RX_DMA_IRQ DMA1_Channel1_IRQn
#endif #endif
/* DMA1 channle2-3 */ /* DMA1 channel2 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
#define SPI1_RX_DMA_IRQ DMA1_Channel2_3_IRQn
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Channel2
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
#define SPI2_RX_DMA_IRQ DMA1_Channel2_3_IRQn
#endif
/* DMA1 channle3 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA1_Channel2_3_IRQHandler #define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI1_TX_DMA_INSTANCE DMA1_Channel2 #define SPI1_TX_DMA_INSTANCE DMA1_Channel3
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX #define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
#define SPI1_TX_DMA_IRQ DMA1_Channel2_3_IRQn #define SPI1_TX_DMA_IRQ DMA1_Channel2_3_IRQn
#ifdef BSP_UART2_RX_USING_DMA
#undef BSP_UART2_RX_USING_DMA
#endif
#ifdef BSP_SPI2_TX_USING_DMA
#undef BSP_SPI2_TX_USING_DMA
#endif
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Channel2_3_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Channel2
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
#define UART2_RX_DMA_IRQ DMA1_Channel2_3_IRQn
#ifdef BSP_SPI2_TX_USING_DMA
#undef BSP_SPI2_TX_USING_DMA
#endif
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) #elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_DMA_TX_IRQHandler DMA1_Channel2_3_IRQHandler #define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Channel2 #define SPI2_TX_DMA_INSTANCE DMA1_Channel3
#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX #define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
#define SPI2_TX_DMA_IRQ DMA1_Channel2_3_IRQn #define SPI2_TX_DMA_IRQ DMA1_Channel2_3_IRQn
#endif #endif
/* DMA1 channle4 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART1_RX_DMA_INSTANCE DMA1_Channel4
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
#define UART1_RX_DMA_IRQ DMA_Channelx_IRQn
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
#define SPI2_RX_DMA_IRQ DMA_Channelx_IRQn
#endif
/* DMA1 channle5 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART1_TX_DMA_INSTANCE DMA1_Channel5
#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
#define UART1_TX_DMA_IRQ DMA_Channelx_IRQn
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
#define SPI2_TX_DMA_IRQ DMA_Channelx_IRQn
#endif
#if !(defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx))
/* DMA1 channle6 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Channel6
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
#define UART2_RX_DMA_IRQ DMA_Channelx_IRQn
#endif
/* DMA1 channle7 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler
#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_TX_DMA_INSTANCE DMA1_Channel7
#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
#define UART2_TX_DMA_IRQ DMA_Channelx_IRQn
#endif
#endif
/* DMA1 channle1 */
#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE) #if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
#define LPUART1_DMA_RX_IRQHandler DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler #define LPUART1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
#define LPUART1_RX_DMA_RCC RCC_AHBENR_DMA1EN #define LPUART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define LPUART1_RX_DMA_INSTANCE DMA1_Channel5 #define LPUART1_RX_DMA_INSTANCE DMA1_Channel1
#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
#define LPUART1_RX_DMA_IRQ DMA1_Ch4_7_DMAMUX1_OVR_IRQn #define LPUART1_RX_DMA_IRQ DMA1_Channel1_IRQn
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus

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@ -55,12 +55,21 @@ extern "C" {
#ifdef BSP_USING_SPI2 #ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG #ifndef SPI2_BUS_CONFIG
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_3_IRQn, \
}
#else
#define SPI2_BUS_CONFIG \ #define SPI2_BUS_CONFIG \
{ \ { \
.Instance = SPI2, \ .Instance = SPI2, \
.bus_name = "spi2", \ .bus_name = "spi2", \
.irq_type = SPI2_IRQn, \ .irq_type = SPI2_IRQn, \
} }
#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
#endif /* SPI2_BUS_CONFIG */ #endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */ #endif /* BSP_USING_SPI2 */

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@ -41,12 +41,21 @@ extern "C" {
#ifdef BSP_USING_TIM3 #ifdef BSP_USING_TIM3
#ifndef TIM3_CONFIG #ifndef TIM3_CONFIG
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
#define TIM3_CONFIG \
{ \
.tim_handle.Instance = TIM3, \
.tim_irqn = TIM3_TIM4_IRQn, \
.name = "timer3", \
}
#else
#define TIM3_CONFIG \ #define TIM3_CONFIG \
{ \ { \
.tim_handle.Instance = TIM3, \ .tim_handle.Instance = TIM3, \
.tim_irqn = TIM3_IRQn, \ .tim_irqn = TIM3_IRQn, \
.name = "timer3", \ .name = "timer3", \
} }
#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
#endif /* TIM3_CONFIG */ #endif /* TIM3_CONFIG */
#endif /* BSP_USING_TIM3 */ #endif /* BSP_USING_TIM3 */

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@ -19,13 +19,21 @@ extern "C" {
#if defined(BSP_USING_LPUART1) #if defined(BSP_USING_LPUART1)
#ifndef LPUART1_CONFIG #ifndef LPUART1_CONFIG
#if defined(STM32G071xx) || defined(STM32G081xx)
#define LPUART1_CONFIG \ #define LPUART1_CONFIG \
{ \ { \
.name = "lpuart1", \ .name = "lpuart1", \
.Instance = LPUART1, \ .Instance = LPUART1, \
.irq_type = USART3_4_LPUART1_IRQn, \ .irq_type = USART3_4_LPUART1_IRQn, \
} }
#define LPUART1_IRQHandler USART3_4_LPUART1_IRQHandler #elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
#define LPUART1_CONFIG \
{ \
.name = "lpuart1", \
.Instance = LPUART1, \
.irq_type = USART3_4_5_6_LPUART1_IRQn, \
}
#endif /* defined(STM32G071xx) || defined(STM32G081xx) */
#endif /* LPUART1_CONFIG */ #endif /* LPUART1_CONFIG */
#if defined(BSP_LPUART1_RX_USING_DMA) #if defined(BSP_LPUART1_RX_USING_DMA)
#ifndef LPUART1_DMA_CONFIG #ifndef LPUART1_DMA_CONFIG
@ -53,7 +61,7 @@ extern "C" {
#if defined(BSP_UART1_RX_USING_DMA) #if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG #ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \ #define UART1_DMA_RX_CONFIG \
{ \ { \
.Instance = UART1_RX_DMA_INSTANCE, \ .Instance = UART1_RX_DMA_INSTANCE, \
.request = UART1_RX_DMA_REQUEST, \ .request = UART1_RX_DMA_REQUEST, \
@ -63,6 +71,18 @@ extern "C" {
#endif /* UART1_DMA_RX_CONFIG */ #endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */ #endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.request = UART1_TX_DMA_REQUEST, \
.dma_rcc = UART1_TX_DMA_RCC, \
.dma_irq = UART1_TX_DMA_IRQ, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2) #if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG #ifndef UART2_CONFIG
#if defined(STM32G0B1xx) || defined(STM32G0C1xx) #if defined(STM32G0B1xx) || defined(STM32G0C1xx)
@ -85,7 +105,7 @@ extern "C" {
#if defined(BSP_UART2_RX_USING_DMA) #if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG #ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \ #define UART2_DMA_RX_CONFIG \
{ \ { \
.Instance = UART2_RX_DMA_INSTANCE, \ .Instance = UART2_RX_DMA_INSTANCE, \
.request = UART2_RX_DMA_REQUEST, \ .request = UART2_RX_DMA_REQUEST, \
@ -95,6 +115,18 @@ extern "C" {
#endif /* UART2_DMA_RX_CONFIG */ #endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */ #endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.request = UART2_TX_DMA_REQUEST, \
.dma_rcc = UART2_TX_DMA_RCC, \
.dma_irq = UART2_TX_DMA_IRQ, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3) #if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG #ifndef UART3_CONFIG
#if defined(STM32G0B1xx) || defined(STM32G0C1xx) #if defined(STM32G0B1xx) || defined(STM32G0C1xx)

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@ -157,14 +157,16 @@ static rt_err_t rt_rtc_config(void)
HAL_PWR_EnableBkUpAccess(); HAL_PWR_EnableBkUpAccess();
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
#ifdef BSP_RTC_USING_LSI #if defined(BSP_RTC_USING_LSI)
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#else #elif defined(BSP_RTC_USING_LSE)
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#else
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
#endif #endif
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
#if defined(SOC_SERIES_STM32WL) #if defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0)
__HAL_RCC_RTCAPB_CLK_ENABLE(); __HAL_RCC_RTCAPB_CLK_ENABLE();
#endif #endif
@ -194,7 +196,9 @@ static rt_err_t rt_rtc_config(void)
RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE; RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L0) \
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) \
|| defined(SOC_SERIES_STM32G0)
/* set the frequency division */ /* set the frequency division */
#ifdef BSP_RTC_USING_LSI #ifdef BSP_RTC_USING_LSI
@ -237,26 +241,24 @@ static rt_err_t stm32_rtc_init(void)
#endif #endif
#endif #endif
#if defined(BSP_RTC_USING_LSI) || defined(BSP_RTC_USING_LSE)
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0};
#ifdef BSP_RTC_USING_LSI #ifdef BSP_RTC_USING_LSI
#ifdef SOC_SERIES_STM32WB #ifdef SOC_SERIES_STM32WB
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
#else #else
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; #endif
RCC_OscInitStruct.LSEState = RCC_LSE_OFF; RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_ON;
#endif
#else #else
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
#endif #endif
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
HAL_RCC_OscConfig(&RCC_OscInitStruct); HAL_RCC_OscConfig(&RCC_OscInitStruct);
#endif
if (rt_rtc_config() != RT_EOK) if (rt_rtc_config() != RT_EOK)
{ {

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@ -1039,7 +1039,45 @@ void SPI2_DMA_RX_TX_IRQHandler(void)
SPI2_DMA_RX_IRQHandler(); SPI2_DMA_RX_IRQHandler();
#endif #endif
} }
#endif /* SOC_SERIES_STM32F0 */ #elif defined(SOC_SERIES_STM32G0)
#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
void SPI1_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_SPI1_TX_USING_DMA)
SPI1_DMA_TX_IRQHandler();
#endif
#if defined(BSP_SPI1_RX_USING_DMA)
SPI1_DMA_RX_IRQHandler();
#endif
}
#endif /* defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) */
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
void SPI2_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_SPI2_TX_USING_DMA)
SPI2_DMA_TX_IRQHandler();
#endif
#if defined(BSP_SPI2_RX_USING_DMA)
SPI2_DMA_RX_IRQHandler();
#endif
}
#endif /* defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) */
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
void SPI2_3_IRQHandler(void)
{
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
SPI2_IRQHandler();
#endif
#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
SPI3_IRQHandler();
#endif
}
#endif /* defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */
#endif /* defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) */
#endif /* defined(SOC_SERIES_STM32F0) */
int rt_hw_spi_init(void) int rt_hw_spi_init(void)
{ {

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@ -623,6 +623,23 @@ void TIM2_IRQHandler(void)
rt_interrupt_leave(); rt_interrupt_leave();
} }
#endif #endif
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
#if defined(BSP_USING_TIM3) || defined(BSP_USING_TIM4)
void TIM3_TIM4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
#ifdef BSP_USING_TIM3
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
#endif
#ifdef BSP_USING_TIM4
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
#endif
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#else
#ifdef BSP_USING_TIM3 #ifdef BSP_USING_TIM3
void TIM3_IRQHandler(void) void TIM3_IRQHandler(void)
{ {
@ -643,6 +660,7 @@ void TIM4_IRQHandler(void)
rt_interrupt_leave(); rt_interrupt_leave();
} }
#endif #endif
#endif
#ifdef BSP_USING_TIM5 #ifdef BSP_USING_TIM5
void TIM5_IRQHandler(void) void TIM5_IRQHandler(void)
{ {

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@ -827,6 +827,63 @@ void LPUART1_DMA_RX_IRQHandler(void)
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */ #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
#endif /* BSP_USING_LPUART1*/ #endif /* BSP_USING_LPUART1*/
#if defined(SOC_SERIES_STM32G0)
#if defined(BSP_USING_UART2)
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
void USART2_LPUART2_IRQHandler(void)
{
USART2_IRQHandler();
}
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
#endif /* defined(BSP_USING_UART2) */
#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
|| defined(BSP_USING_LPUART1)
#if defined(STM32G070xx)
void USART3_4_IRQHandler(void)
#elif defined(STM32G071xx) || defined(STM32G081xx)
void USART3_4_LPUART1_IRQHandler(void)
#elif defined(STM32G0B0xx)
void USART3_4_5_6_IRQHandler(void)
#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
void USART3_4_5_6_LPUART1_IRQHandler(void)
#endif /* defined(STM32G070xx) */
{
#if defined(BSP_USING_UART3)
USART3_IRQHandler();
#endif
#if defined(BSP_USING_UART4)
UART4_IRQHandler();
#endif
#if defined(BSP_USING_UART5)
UART5_IRQHandler();
#endif
#if defined(BSP_USING_UART6)
USART6_IRQHandler();
#endif
#if defined(BSP_USING_LPUART1)
LPUART1_IRQHandler();
#endif
}
#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
#if defined(RT_SERIAL_USING_DMA)
void UART_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
UART1_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
UART1_DMA_RX_IRQHandler();
#endif
#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
UART2_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
UART2_DMA_RX_IRQHandler();
#endif
}
#endif /* defined(RT_SERIAL_USING_DMA) */
#endif /* defined(SOC_SERIES_STM32G0) */
static void stm32_uart_get_dma_config(void) static void stm32_uart_get_dma_config(void)
{ {
#ifdef BSP_USING_UART1 #ifdef BSP_USING_UART1
@ -940,6 +997,15 @@ static void stm32_uart_get_dma_config(void)
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
#endif #endif
#endif #endif
#ifdef BSP_USING_LPUART1
uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
#ifdef BSP_LPUART1_RX_USING_DMA
uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
#endif
#endif
} }
#ifdef RT_SERIAL_USING_DMA #ifdef RT_SERIAL_USING_DMA

View File

@ -862,6 +862,64 @@ void LPUART1_DMA_RX_IRQHandler(void)
} }
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */ #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
#endif /* BSP_USING_LPUART1*/ #endif /* BSP_USING_LPUART1*/
#if defined(SOC_SERIES_STM32G0)
#if defined(BSP_USING_UART2)
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
void USART2_LPUART2_IRQHandler(void)
{
USART2_IRQHandler();
}
#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
#endif /* defined(BSP_USING_UART2) */
#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
|| defined(BSP_USING_LPUART1)
#if defined(STM32G070xx)
void USART3_4_IRQHandler(void)
#elif defined(STM32G071xx) || defined(STM32G081xx)
void USART3_4_LPUART1_IRQHandler(void)
#elif defined(STM32G0B0xx)
void USART3_4_5_6_IRQHandler(void)
#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
void USART3_4_5_6_LPUART1_IRQHandler(void)
#endif /* defined(STM32G070xx) */
{
#if defined(BSP_USING_UART3)
USART3_IRQHandler();
#endif
#if defined(BSP_USING_UART4)
UART4_IRQHandler();
#endif
#if defined(BSP_USING_UART5)
UART5_IRQHandler();
#endif
#if defined(BSP_USING_UART6)
USART6_IRQHandler();
#endif
#if defined(BSP_USING_LPUART1)
LPUART1_IRQHandler();
#endif
}
#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
#if defined(RT_SERIAL_USING_DMA)
void UART_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
UART1_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
UART1_DMA_RX_IRQHandler();
#endif
#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
UART2_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
UART2_DMA_RX_IRQHandler();
#endif
}
#endif /* defined(RT_SERIAL_USING_DMA) */
#endif /* defined(SOC_SERIES_STM32G0) */
static void stm32_uart_get_config(void) static void stm32_uart_get_config(void)
{ {
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
@ -1024,6 +1082,20 @@ static void stm32_uart_get_config(void)
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
#endif #endif
#endif #endif
#ifdef BSP_USING_LPUART1
uart_obj[LPUART1_INDEX].serial.config = config;
uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
uart_obj[LPUART1_INDEX].serial.config.rx_bufsz = BSP_LPUART1_RX_BUFSIZE;
uart_obj[LPUART1_INDEX].serial.config.tx_bufsz = BSP_LPUART1_TX_BUFSIZE;
#ifdef BSP_LPUART1_RX_USING_DMA
uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
#endif
#endif
} }
#ifdef RT_SERIAL_USING_DMA #ifdef RT_SERIAL_USING_DMA

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@ -30,6 +30,18 @@ menu "On-chip Peripheral Drivers"
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
default n default n
config BSP_LPUART1_RX_BUFSIZE
int "Set LPUART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_LPUART1_TX_BUFSIZE
int "Set LPUART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_USING_UART1 config BSP_USING_UART1
bool "Enable UART1" bool "Enable UART1"
default n default n
@ -39,6 +51,23 @@ menu "On-chip Peripheral Drivers"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART1_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_USING_UART2 config BSP_USING_UART2
bool "Enable UART2" bool "Enable UART2"
default n default n
@ -47,6 +76,23 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART2 RX DMA" bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART2_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256
endif endif
menuconfig BSP_USING_TIM menuconfig BSP_USING_TIM