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fix a eth driver bug to avoid crush 

fix a eth driver bug to avoid crush
This commit is contained in:
Alex 2015-05-13 08:50:14 +08:00
parent a58078d18a
commit b25e602afb
17 changed files with 10672 additions and 9239 deletions
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16028
bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h
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File diff suppressed because it is too large Load Diff

14
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h
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@ -43,12 +43,12 @@
#define _TIM
#define _UART
#define _USB
#define _WDG
#define _WDG
//#define _MARVELL
//#define _IP1826D
#define _M7NORFLASH
#define _ME_6095_F
//#define _MARVELL
//#define _IP1826D
#define _M7NORFLASH
#define _ME_6095_F
#define USE_FULL_ASSERT 1
@ -76,8 +76,8 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
/**
* System clock frequency, unit is Hz.
*/
#define SYSTEM_CLOCK_FREQ 300000000
//250000000
#define SYSTEM_CLOCK_FREQ 300000000
//250000000
//300000000
/**

834
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h
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@ -1,417 +1,417 @@
/**
*****************************************************************************
* @file cmem7_eth.h
*
* @brief CMEM7 ethernet header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_ETH_H
#define __CMEM7_ETH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup ETH_SPEED
* @{
*/
#define ETH_SPEED_10M 0x0
#define ETH_SPEED_100M 0x1
#define ETH_SPEED_1000M 0x2
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
((SPEED) == ETH_SPEED_100M) || \
((SPEED) == ETH_SPEED_1000M))
/**
* @}
*/
/** @defgroup ETH_DUPLEX
* @{
*/
#define ETH_DUPLEX_HALF 0x0
#define ETH_DUPLEX_FULL 0x1
#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \
((DUPLEX) == ETH_DUPLEX_FULL))
/**
* @}
*/
/** @defgroup ETH_INT
* @{
*/
#define ETH_INT_TX_COMPLETE_FRAME 0x0001
#define ETH_INT_TX_STOP 0x0002
#define ETH_INT_TX_BUF_UNAVAI 0x0004
#define ETH_INT_RX_OVERFLOW 0x0010
#define ETH_INT_TX_UNDERFLOW 0x0020
#define ETH_INT_RX_COMPLETE_FRAME 0x0040
#define ETH_INT_RX_BUF_UNAVAI 0x0080
#define ETH_INT_RX_STOP 0x0100
#define ETH_INT_BUS_FATAL_ERROR 0x2000
#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \
ETH_INT_TX_STOP | \
ETH_INT_TX_BUF_UNAVAI | \
ETH_INT_RX_OVERFLOW | \
ETH_INT_TX_UNDERFLOW | \
ETH_INT_RX_COMPLETE_FRAME | \
ETH_INT_RX_BUF_UNAVAI | \
ETH_INT_RX_STOP | \
ETH_INT_BUS_FATAL_ERROR)
#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
/**
* @}
*/
/**
* @brief EFUSE receive filter structure
*/
typedef struct
{
BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */
BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */
BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */
BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */
BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */
uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */
} ETH_FrameFilter;
/**
* @brief Ethernet initialization structure
*/
typedef struct
{
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
BOOL ETH_RxEn; /*!< Rx enable */
BOOL ETH_TxEn; /*!< Tx enable */
BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */
BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */
uint8_t ETH_MacAddr[6]; /*!< MAC address */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
} ETH_InitTypeDef;
/**
* @brief Ethernet Tx descriptor structure
*/
typedef struct {
union {
uint32_t TX0;
struct {
uint32_t : 1;
uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */
uint32_t : 1;
uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */
uint32_t : 1;
uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */
uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */
uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */
uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */
uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */
uint32_t : 2;
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */
uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */
uint32_t : 8;
uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */
uint32_t : 2;
uint32_t FS : 1; /*!< first segment flag */
uint32_t LS : 1; /*!< last segment flag */
uint32_t : 2;
} TX0_b;
} TX_0;
union {
uint32_t TX1;
struct {
uint32_t SIZE : 13; /*!< buffer size */
uint32_t : 19;
} TX1_b;
} TX_1;
uint32_t bufAddr; /*!< address of buffer */
uint32_t nextDescAddr; /*!< address of next descriptor */
uint64_t reserved;
uint64_t timeStamp; /*!< time stamp while last segment */
} ETH_TX_DESC;
/**
* @brief Ethernet Rx descriptor structure
*/
typedef struct {
union {
uint32_t RX0;
struct {
uint32_t : 1;
uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
uint32_t : 5;
uint32_t TTSE : 1; /*!< timestamp available while last segment */
uint32_t LS : 1; /*!< [OUT] last segment flag */
uint32_t FS : 1; /*!< [OUT] first segment flag */
uint32_t : 1;
uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
uint32_t : 2;
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
uint32_t FL : 14; /*!< [OUT] frame length while last segment */
uint32_t : 2;
} RX0_b;
} RX_0;
union {
uint32_t RX1;
struct {
uint32_t SIZE : 13; /*!< buffer size */
uint32_t : 19;
} RX1_b;
} RX_1;
uint32_t bufAddr; /*!< buffer address */
uint32_t nextDescAddr; /*!< address of next descriptor */
uint64_t reserved;
uint64_t timeStamp; /*!< time stamp while the last segment */
} ETH_RX_DESC;
/**
* @brief Read data from phy chip
* @param[in] phyAddr Address of phy chip
* @param[in] phyReg Address of phy's register to be read
* @retval uint32_t value of phy's register
*/
uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
/**
* @brief Write data to phy chip
* @param[in] phyAddr Address of phy chip
* @param[in] phyReg Address of phy's register to be written
* @param[in] data Data to be written
* @retval None
*/
void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/**
* @brief Fills each ETH_InitStruct member with its default value.
* @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void ETH_StructInit(ETH_InitTypeDef* init);
/**
* @brief Ethernet initialization
* @note This function should be called at first before any other interfaces.
* @param[in] init A pointer to structure ETH_InitTypeDef
* @retval BOOL The bit indicates if ethernet is initialized successfully
*/
BOOL ETH_Init(ETH_InitTypeDef *init);
/**
* @brief Enable or disable ethernet interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void ETH_ITConfig(uint32_t Int, BOOL enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL ETH_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval None
*/
void ETH_ClearITPendingBit(uint32_t Int);
/**
* @brief Get ethernte MAC address
* @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
* @retval None
*/
void ETH_GetMacAddr(uint8_t *mac);
/**
* @brief Set ethernet transmission descriptor ring
* @note Make sure that memory occupied by descriptors should be in physical
* memory and keep valid before ethernet transmission is finished.
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* has a 'nextDescAddr' pointed to first node.
* @retval BOOL The bit indicates if valid ring is set
*/
BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
/**
* @brief Start ethernet transmission
* @param None
* @retval None
*/
void ETH_StartTx(void);
/**
* @brief Stop ethernet transmission
* @param None
* @retval None
*/
void ETH_StopTx(void);
/**
* @brief Resume ethernet transmission\n
* While ethernet doesn't have enough buffer to transmit data, it will
* pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
* must call this function to start ethernet again after new buffer
* prepared.
* @param None
* @retval None
*/
void ETH_ResumeTx(void);
/**
* @brief Get free transmission descriptor\n
* @param None
* @retval ETH_TX_DESC* A pointer of free transmission descriptor,
* NULL if no free descriptor
*/
ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
/**
* @brief Check if a transmission descriptor is free or not
* @param[in] desc A pointer of a transmission descriptor
* @retval BOOL True if the transmission descriptor is free, or flase.
*/
BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
/**
* @brief Release a transmission descriptor to ethernet\n
* After users prepared data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
/**
* @brief Set buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @param[in] bufAddr buffer address to be sent
* @retval None
*/
void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
/**
* @brief Set ethernet receive descriptor ring
* @note Make sure that memory occupied by descriptors should be in physical
* memory and keep valid before ethernet receive is finished.
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* has a 'nextDescAddr' pointed to first node.
* @retval BOOL The bit indicates if valid ring is set
*/
BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
/**
* @brief Start ethernet receive
* @param None
* @retval None
*/
void ETH_StartRx(void);
/**
* @brief Stop ethernet receive
* @param None
* @retval None
*/
void ETH_StopRx(void);
/**
* @brief Resume ethernet receive\n
* While ethernet doesn't have enough buffer to receive data, it will
* pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
* must call this function to start ethernet again after new buffer
* prepared.
* @param None
* @retval None
*/
void ETH_ResumeRx(void);
/**
* @brief Get the free descriptor which contains received data\n
* @param None
* @retval ETH_RX_DESC* A pointer of free receive descriptor,
* NULL if no free descriptor
*/
ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
/**
* @brief Check if a receive descriptor is free or not
* @param[in] desc A pointer of a receive descriptor
* @retval BOOL True if the receive descriptor is free, or flase.
*/
BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
/**
* @brief Release a receive descriptor to ethernet\n
* After users handled data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
/**
* @brief Set buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @param[in] bufAddr buffer address to be received
* @retval None
*/
void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_ETH_H */
/**
*****************************************************************************
* @file cmem7_eth.h
*
* @brief CMEM7 ethernet header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_ETH_H
#define __CMEM7_ETH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup ETH_SPEED
* @{
*/
#define ETH_SPEED_10M 0x0
#define ETH_SPEED_100M 0x1
#define ETH_SPEED_1000M 0x2
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
((SPEED) == ETH_SPEED_100M) || \
((SPEED) == ETH_SPEED_1000M))
/**
* @}
*/
/** @defgroup ETH_DUPLEX
* @{
*/
#define ETH_DUPLEX_HALF 0x0
#define ETH_DUPLEX_FULL 0x1
#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \
((DUPLEX) == ETH_DUPLEX_FULL))
/**
* @}
*/
/** @defgroup ETH_INT
* @{
*/
#define ETH_INT_TX_COMPLETE_FRAME 0x0001
#define ETH_INT_TX_STOP 0x0002
#define ETH_INT_TX_BUF_UNAVAI 0x0004
#define ETH_INT_RX_OVERFLOW 0x0010
#define ETH_INT_TX_UNDERFLOW 0x0020
#define ETH_INT_RX_COMPLETE_FRAME 0x0040
#define ETH_INT_RX_BUF_UNAVAI 0x0080
#define ETH_INT_RX_STOP 0x0100
#define ETH_INT_BUS_FATAL_ERROR 0x2000
#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \
ETH_INT_TX_STOP | \
ETH_INT_TX_BUF_UNAVAI | \
ETH_INT_RX_OVERFLOW | \
ETH_INT_TX_UNDERFLOW | \
ETH_INT_RX_COMPLETE_FRAME | \
ETH_INT_RX_BUF_UNAVAI | \
ETH_INT_RX_STOP | \
ETH_INT_BUS_FATAL_ERROR)
#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
/**
* @}
*/
/**
* @brief EFUSE receive filter structure
*/
typedef struct
{
BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */
BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */
BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */
BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */
BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */
uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */
} ETH_FrameFilter;
/**
* @brief Ethernet initialization structure
*/
typedef struct
{
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
BOOL ETH_RxEn; /*!< Rx enable */
BOOL ETH_TxEn; /*!< Tx enable */
BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */
BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */
uint8_t ETH_MacAddr[6]; /*!< MAC address */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
} ETH_InitTypeDef;
/**
* @brief Ethernet Tx descriptor structure
*/
typedef struct {
union {
uint32_t TX0;
struct {
uint32_t : 1;
uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */
uint32_t : 1;
uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */
uint32_t : 1;
uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */
uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */
uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */
uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */
uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */
uint32_t : 2;
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */
uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */
uint32_t : 8;
uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */
uint32_t : 2;
uint32_t FS : 1; /*!< first segment flag */
uint32_t LS : 1; /*!< last segment flag */
uint32_t : 2;
} TX0_b;
} TX_0;
union {
uint32_t TX1;
struct {
uint32_t SIZE : 13; /*!< buffer size */
uint32_t : 19;
} TX1_b;
} TX_1;
uint32_t bufAddr; /*!< address of buffer */
uint32_t nextDescAddr; /*!< address of next descriptor */
uint64_t reserved;
uint64_t timeStamp; /*!< time stamp while last segment */
} ETH_TX_DESC;
/**
* @brief Ethernet Rx descriptor structure
*/
typedef struct {
union {
uint32_t RX0;
struct {
uint32_t : 1;
uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
uint32_t : 5;
uint32_t TTSE : 1; /*!< timestamp available while last segment */
uint32_t LS : 1; /*!< [OUT] last segment flag */
uint32_t FS : 1; /*!< [OUT] first segment flag */
uint32_t : 1;
uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
uint32_t : 2;
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
uint32_t FL : 14; /*!< [OUT] frame length while last segment */
uint32_t : 2;
} RX0_b;
} RX_0;
union {
uint32_t RX1;
struct {
uint32_t SIZE : 13; /*!< buffer size */
uint32_t : 19;
} RX1_b;
} RX_1;
uint32_t bufAddr; /*!< buffer address */
uint32_t nextDescAddr; /*!< address of next descriptor */
uint64_t reserved;
uint64_t timeStamp; /*!< time stamp while the last segment */
} ETH_RX_DESC;
/**
* @brief Read data from phy chip
* @param[in] phyAddr Address of phy chip
* @param[in] phyReg Address of phy's register to be read
* @retval uint32_t value of phy's register
*/
uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
/**
* @brief Write data to phy chip
* @param[in] phyAddr Address of phy chip
* @param[in] phyReg Address of phy's register to be written
* @param[in] data Data to be written
* @retval None
*/
void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/**
* @brief Fills each ETH_InitStruct member with its default value.
* @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void ETH_StructInit(ETH_InitTypeDef* init);
/**
* @brief Ethernet initialization
* @note This function should be called at first before any other interfaces.
* @param[in] init A pointer to structure ETH_InitTypeDef
* @retval BOOL The bit indicates if ethernet is initialized successfully
*/
BOOL ETH_Init(ETH_InitTypeDef *init);
/**
* @brief Enable or disable ethernet interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void ETH_ITConfig(uint32_t Int, BOOL enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL ETH_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval None
*/
void ETH_ClearITPendingBit(uint32_t Int);
/**
* @brief Get ethernte MAC address
* @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
* @retval None
*/
void ETH_GetMacAddr(uint8_t *mac);
/**
* @brief Set ethernet transmission descriptor ring
* @note Make sure that memory occupied by descriptors should be in physical
* memory and keep valid before ethernet transmission is finished.
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* has a 'nextDescAddr' pointed to first node.
* @retval BOOL The bit indicates if valid ring is set
*/
BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
/**
* @brief Start ethernet transmission
* @param None
* @retval None
*/
void ETH_StartTx(void);
/**
* @brief Stop ethernet transmission
* @param None
* @retval None
*/
void ETH_StopTx(void);
/**
* @brief Resume ethernet transmission\n
* While ethernet doesn't have enough buffer to transmit data, it will
* pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
* must call this function to start ethernet again after new buffer
* prepared.
* @param None
* @retval None
*/
void ETH_ResumeTx(void);
/**
* @brief Get free transmission descriptor\n
* @param None
* @retval ETH_TX_DESC* A pointer of free transmission descriptor,
* NULL if no free descriptor
*/
ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
/**
* @brief Check if a transmission descriptor is free or not
* @param[in] desc A pointer of a transmission descriptor
* @retval BOOL True if the transmission descriptor is free, or flase.
*/
BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
/**
* @brief Release a transmission descriptor to ethernet\n
* After users prepared data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
/**
* @brief Set buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @param[in] bufAddr buffer address to be sent
* @retval None
*/
void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
/**
* @brief Set ethernet receive descriptor ring
* @note Make sure that memory occupied by descriptors should be in physical
* memory and keep valid before ethernet receive is finished.
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* has a 'nextDescAddr' pointed to first node.
* @retval BOOL The bit indicates if valid ring is set
*/
BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
/**
* @brief Start ethernet receive
* @param None
* @retval None
*/
void ETH_StartRx(void);
/**
* @brief Stop ethernet receive
* @param None
* @retval None
*/
void ETH_StopRx(void);
/**
* @brief Resume ethernet receive\n
* While ethernet doesn't have enough buffer to receive data, it will
* pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
* must call this function to start ethernet again after new buffer
* prepared.
* @param None
* @retval None
*/
void ETH_ResumeRx(void);
/**
* @brief Get the free descriptor which contains received data\n
* @param None
* @retval ETH_RX_DESC* A pointer of free receive descriptor,
* NULL if no free descriptor
*/
ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
/**
* @brief Check if a receive descriptor is free or not
* @param[in] desc A pointer of a receive descriptor
* @retval BOOL True if the receive descriptor is free, or flase.
*/
BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
/**
* @brief Release a receive descriptor to ethernet\n
* After users handled data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
/**
* @brief Set buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @param[in] bufAddr buffer address to be received
* @retval None
*/
void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_ETH_H */

16
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h
View File

@ -200,14 +200,14 @@ void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
* @param[out] data A pointer to the data to be written
* @retval None
*/
void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
void flash_WaitInWritting(void) ;
void flash_WaitReadFifoNotEmpty(void);
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ;
void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
void flash_WaitInWritting(void) ;
void flash_WaitReadFifoNotEmpty(void);
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ;
#ifdef __cplusplus

22
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h
View File

@ -139,17 +139,17 @@ void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLev
* @retval None
*/
void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask);
void GPIO_clrBits(uint32_t mask);
uint32_t GPIO_getBits(uint32_t mask);
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask);
void GPIO_clrBits(uint32_t mask);
uint32_t GPIO_getBits(uint32_t mask);
#ifdef __cplusplus
}

20
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h
View File

@ -101,16 +101,16 @@
#ifdef _WDG
#include "cmem7_wdg.h"
#endif
#ifdef _MARVELL
#include <marvel_98dx242.h>
#include <s24g_i2c.h>
#endif
#ifdef _IP1826D
#include <ip1826d_v00.h>
#endif
#ifdef _MARVELL
#include <marvel_98dx242.h>
#include <s24g_i2c.h>
#endif
#ifdef _IP1826D
#include <ip1826d_v00.h>
#endif
#ifdef __cplusplus
}

552
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h
View File

@ -1,276 +1,276 @@
/**
*****************************************************************************
* @file cmem7_misc.h
*
* @brief CMEM7 miscellaneous header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_MISC_H
#define __CMEM7_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/**
* @brief NVIC initialization structure
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete Capital-micro Devices IRQ Channels list, please
refer to cmem7.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/** @defgroup NVIC_VectTab
* @{
*/
#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000)
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup NVIC_LP
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup NVIC_PriorityGroup
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
/**
* @}
*/
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values, ref as @ref NVIC_VectTab:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple
* of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values, ref as @ref NVIC_LP:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
/**
* @brief Memory map from address 'from' to 'address 'to' and open icache or not
* @param[in] from address to be mapped from
* @param[in] to address to be mapped to
* @param[in] isIcacheOn icache is on or off
* @retval None
*/
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
/**
* @brief Convert the mapping destination address to source address
* @param[in] to address to be mapped to
* @retval uint32_t address to be mapped from
*/
uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
/**
* @brief Convert the mapping source address to destination address
* @param[in] from address to be mapped from
* @retval uint32_t address to be mapped to
*/
uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
/**
* @brief Set NMI irq number, it should be one of @ref IRQn_Type.
* @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
* interrupt routine if the specific 'irq' occurs. By default, NMI irq number
* is 0, same as ETH_INT_IRQn
* @param[in] irq irq number
* @retval None
*/
void GLB_SetNmiIrqNum(uint32_t irq);
/** @defgroup SYS_CLK_SEL
* @{
*/
#define SYS_CLK_SEL_OSC 0x0
#define SYS_CLK_SEL_DLL 0x1
#define SYS_CLK_SEL_CRYSTAL 0x2
#define SYS_CLK_SEL_EXTERNAL 0x3
/**
* @}
*/
/**
* @brief Select system clock source, it should be one of @ref SYS_CLK_SEL.
* @Note You MUST make sure externel clock has been stabled if clock
* source is external before call this function.
* Default value is SYS_CLK_SEL_OSC
* @param[in] irq irq number
* @retval None
*/
void GLB_SelectSysClkSource(uint8_t source);
/**
* @brief Simulate instruction 'STRB' or 'STRH' with 'BFI'
* @Note In M7, you have to write a register in 32-bit alignment,
* not in 8-bit or 16-bit.
* @param[in] addr register address to be written
* @param[in] value value to be written
* @param[in] lsb LSB in register to be written
* @param[in] len bit length to be written
* @retval None
*/
//#define aaaa(len) __asm("LDR len, 11")
#define CMEM7_BFI(addr, value, lsb, len) \
do { \
unsigned long tmp; \
unsigned long tmp1 = (unsigned long)addr; \
\
__asm("LDR tmp, [tmp1]\n" \
"BFI tmp, "#value", "#lsb", "#len" \n" \
"STR tmp, [tmp1]\n"); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_MISC_H */
/**
*****************************************************************************
* @file cmem7_misc.h
*
* @brief CMEM7 miscellaneous header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_MISC_H
#define __CMEM7_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/**
* @brief NVIC initialization structure
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete Capital-micro Devices IRQ Channels list, please
refer to cmem7.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/** @defgroup NVIC_VectTab
* @{
*/
#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000)
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup NVIC_LP
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup NVIC_PriorityGroup
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
/**
* @}
*/
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values, ref as @ref NVIC_VectTab:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple
* of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values, ref as @ref NVIC_LP:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
/**
* @brief Memory map from address 'from' to 'address 'to' and open icache or not
* @param[in] from address to be mapped from
* @param[in] to address to be mapped to
* @param[in] isIcacheOn icache is on or off
* @retval None
*/
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
/**
* @brief Convert the mapping destination address to source address
* @param[in] to address to be mapped to
* @retval uint32_t address to be mapped from
*/
uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
/**
* @brief Convert the mapping source address to destination address
* @param[in] from address to be mapped from
* @retval uint32_t address to be mapped to
*/
uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
/**
* @brief Set NMI irq number, it should be one of @ref IRQn_Type.
* @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
* interrupt routine if the specific 'irq' occurs. By default, NMI irq number
* is 0, same as ETH_INT_IRQn
* @param[in] irq irq number
* @retval None
*/
void GLB_SetNmiIrqNum(uint32_t irq);
/** @defgroup SYS_CLK_SEL
* @{
*/
#define SYS_CLK_SEL_OSC 0x0
#define SYS_CLK_SEL_DLL 0x1
#define SYS_CLK_SEL_CRYSTAL 0x2
#define SYS_CLK_SEL_EXTERNAL 0x3
/**
* @}
*/
/**
* @brief Select system clock source, it should be one of @ref SYS_CLK_SEL.
* @Note You MUST make sure externel clock has been stabled if clock
* source is external before call this function.
* Default value is SYS_CLK_SEL_OSC
* @param[in] irq irq number
* @retval None
*/
void GLB_SelectSysClkSource(uint8_t source);
/**
* @brief Simulate instruction 'STRB' or 'STRH' with 'BFI'
* @Note In M7, you have to write a register in 32-bit alignment,
* not in 8-bit or 16-bit.
* @param[in] addr register address to be written
* @param[in] value value to be written
* @param[in] lsb LSB in register to be written
* @param[in] len bit length to be written
* @retval None
*/
//#define aaaa(len) __asm("LDR len, 11")
#define CMEM7_BFI(addr, value, lsb, len) \
do { \
unsigned long tmp; \
unsigned long tmp1 = (unsigned long)addr; \
\
__asm("LDR tmp, [tmp1]\n" \
"BFI tmp, "#value", "#lsb", "#len" \n" \
"STR tmp, [tmp1]\n"); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_MISC_H */

178
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h
View File

@ -1,89 +1,89 @@
/**
*****************************************************************************
* @file cmem7_rtc.h
*
* @brief CMEM7 RTC header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_RTC_H
#define __CMEM7_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup RTC_Int
* @{
*/
#define RTC_Int_Second ((uint32_t)0x00000001)
#define RTC_Int_Millsecond ((uint32_t)0x00000002)
#define RTC_Int_All ((uint32_t)0x00000003)
#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
/**
* @}
*/
/**
* @brief Enable or disable RTC interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void RTC_ITConfig(uint32_t Int, BOOL Enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL RTC_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval None
*/
void RTC_ClearITPendingBit(uint32_t Int);
/**
* @brief Get seconds since power up
* @param None
* @retval uint32_t Seconds since power up
*/
uint32_t RTC_GetSecond(void);
/**
* @brief Get current millseconds
* @param None
* @retval uint32_t Current millseconds
*/
uint16_t RTC_GetMillSecond(void);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_RTC_H */
/**
*****************************************************************************
* @file cmem7_rtc.h
*
* @brief CMEM7 RTC header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_RTC_H
#define __CMEM7_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup RTC_Int
* @{
*/
#define RTC_Int_Second ((uint32_t)0x00000001)
#define RTC_Int_Millsecond ((uint32_t)0x00000002)
#define RTC_Int_All ((uint32_t)0x00000003)
#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
/**
* @}
*/
/**
* @brief Enable or disable RTC interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void RTC_ITConfig(uint32_t Int, BOOL Enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL RTC_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval None
*/
void RTC_ClearITPendingBit(uint32_t Int);
/**
* @brief Get seconds since power up
* @param None
* @retval uint32_t Seconds since power up
*/
uint32_t RTC_GetSecond(void);
/**
* @brief Get current millseconds
* @param None
* @retval uint32_t Current millseconds
*/
uint16_t RTC_GetMillSecond(void);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_RTC_H */

220
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h
View File

@ -1,110 +1,110 @@
/**
*****************************************************************************
* @file cmem7_wdg.h
*
* @brief CMEM7 watchdog header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_WDG_H
#define __CMEM7_WDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup WDG_INT
* @{
*/
#define WDG_INT_QUARTER 0
#define WDG_INT_HALF 1
#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \
((INT) == WDG_INT_HALF))
/**
* @}
*/
/** @defgroup WDG_TRIGGER_MODE
* @{
*/
#define WDG_TRIGGER_MODE_EDGE 0
#define WDG_TRIGGER_MODE_LEVEL 1
#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \
((TRI) == WDG_TRIGGER_MODE_LEVEL))
/**
* @}
*/
/**
* @brief Deinitializes the Watchdog peripheral registers to their default reset values.
* @param[in] None
* @retval None
*/
void WDG_DeInit(void);
/**
* @brief Watchdog initialization
* @note This function should be called at first before any other interfaces.
* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
* @param[in] ResetMillSecond MillSeconds lasts before global reset
* @retval None
*/
void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
/**
* @brief Enable or disable watchdog interrupt.
* @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
* @param[in] Enable The bit indicates if the specific interrupt are enable or not
* @retval None
*/
void WDG_ITConfig(uint8_t Int, BOOL Enable);
/**
* @brief Check the specific interrupt are set or not
* @param None
* @retval BOOL The bit indicates if the specific interrupt are set or not
*/
BOOL WDG_GetITStatus(void);
/**
* @brief Clear the specific interrupt
* @param None
* @retval None
*/
void WDG_ClearITPendingBit(void);
/**
* @brief Enable or disable watchdog.
* @param[in] Enable The bit indicates if watchdog is enable or not
* @retval None
*/
void WDG_Cmd(BOOL Enable);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_WDG_H */
/**
*****************************************************************************
* @file cmem7_wdg.h
*
* @brief CMEM7 watchdog header file
*
*
* @version V1.0
* @date 3. September 2013
*
* @note
*
*****************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
*****************************************************************************
*/
#ifndef __CMEM7_WDG_H
#define __CMEM7_WDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmem7.h"
#include "cmem7_conf.h"
/** @defgroup WDG_INT
* @{
*/
#define WDG_INT_QUARTER 0
#define WDG_INT_HALF 1
#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \
((INT) == WDG_INT_HALF))
/**
* @}
*/
/** @defgroup WDG_TRIGGER_MODE
* @{
*/
#define WDG_TRIGGER_MODE_EDGE 0
#define WDG_TRIGGER_MODE_LEVEL 1
#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \
((TRI) == WDG_TRIGGER_MODE_LEVEL))
/**
* @}
*/
/**
* @brief Deinitializes the Watchdog peripheral registers to their default reset values.
* @param[in] None
* @retval None
*/
void WDG_DeInit(void);
/**
* @brief Watchdog initialization
* @note This function should be called at first before any other interfaces.
* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
* @param[in] ResetMillSecond MillSeconds lasts before global reset
* @retval None
*/
void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
/**
* @brief Enable or disable watchdog interrupt.
* @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
* @param[in] Enable The bit indicates if the specific interrupt are enable or not
* @retval None
*/
void WDG_ITConfig(uint8_t Int, BOOL Enable);
/**
* @brief Check the specific interrupt are set or not
* @param None
* @retval BOOL The bit indicates if the specific interrupt are set or not
*/
BOOL WDG_GetITStatus(void);
/**
* @brief Clear the specific interrupt
* @param None
* @retval None
*/
void WDG_ClearITPendingBit(void);
/**
* @brief Enable or disable watchdog.
* @param[in] Enable The bit indicates if watchdog is enable or not
* @retval None
*/
void WDG_Cmd(BOOL Enable);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_WDG_H */

9
bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c
View File

@ -108,7 +108,8 @@ static uint8_t flash_ReadInnerStatusHigh() {
return (uint8_t)NOR_FLASH->DATA;
}
static void flash_WaitInWritting() {
//static void flash_WaitInWritting() {
void flash_WaitInWritting(void) {
FLASH_INNER_STATUS s;
while (NOR_FLASH->STATUS_b.BUSY);
@ -173,7 +174,8 @@ static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
NOR_FLASH->TRIGGER_b.OP_START = TRUE;
}
static void flash_WaitReadFifoNotEmpty() {
//static void flash_WaitReadFifoNotEmpty() {
void flash_WaitReadFifoNotEmpty(void) {
while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
if (wait) {
(*wait)();
@ -181,7 +183,8 @@ static void flash_WaitReadFifoNotEmpty() {
}
}
static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
//static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
uint16_t count = 0;
while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {

75
bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c
View File

@ -179,3 +179,78 @@ void GPIO_EnablePwm(uint8_t Channel, BOOL Enable) {
}
}
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask)
{
static uint32_t g_GPIO_OUT_UNMASK;
static uint32_t g_GPIO_OUT_DATA;
static uint32_t g_GPIO_OE;
g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
g_GPIO_OUT_DATA = GPIO->GPIO_OUT_DATA ;
g_GPIO_OE = GPIO->GPIO_OE ;
g_GPIO_OUT_UNMASK |=mask;
g_GPIO_OE |=mask;
g_GPIO_OUT_DATA |=mask;
GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
GPIO->GPIO_OUT_DATA =g_GPIO_OUT_DATA ;
GPIO->GPIO_OE =g_GPIO_OE ;
}
void GPIO_clrBits(uint32_t mask)
{
static uint32_t g_GPIO_OUT_UNMASK;
static uint32_t g_GPIO_OUT_DATA;
static uint32_t g_GPIO_OE;
g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
g_GPIO_OUT_DATA = GPIO->GPIO_OUT_DATA ;
g_GPIO_OE = GPIO->GPIO_OE ;
g_GPIO_OUT_UNMASK |=mask;
g_GPIO_OE |=mask;
g_GPIO_OUT_DATA &=(~ mask);
GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
GPIO->GPIO_OUT_DATA =g_GPIO_OUT_DATA ;
GPIO->GPIO_OE =g_GPIO_OE ;
}
uint32_t GPIO_getBits(uint32_t mask)
{
static uint32_t g_GPIO_OUT_UNMASK;
//static uint32_t g_GPIO_OUT_DATA;
static uint32_t g_GPIO_OE;
uint32_t get_delay = 0;
uint32_t saved_mask;
saved_mask=mask;
g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
g_GPIO_OE = GPIO->GPIO_OE ;
g_GPIO_OUT_UNMASK &=(~mask);
g_GPIO_OE &=(~mask);
GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
GPIO->GPIO_OE =g_GPIO_OE ;
for(get_delay=0;get_delay<100;get_delay++)
{
}
//get_delay=(GPIO->GPIO_IN)&saved_mask;
if(((GPIO->GPIO_IN)&saved_mask)==saved_mask)
{
return(1);
}
else
{
return(0);
}
}
/**
xjf 20150324
**/

46
bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c
View File

@ -92,8 +92,20 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState)
}
}
#define DEF_IBUS_OFFSET 0x1FFE0000
#define DEF_EXT_ADDR 0x08020000
static BOOL isMappingOn() {
/* If default values aren't changed */
if ((GLOBAL_CTRL->IBUSOFF == DEF_IBUS_OFFSET) &&
(GLOBAL_CTRL->EXTADDR == DEF_EXT_ADDR)) {
return FALSE;
}
return TRUE;
}
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
int n;
volatile int n;
GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
GLOBAL_CTRL->EXTADDR = to;
@ -104,6 +116,38 @@ void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
for (n = 0; n < 100; n++);
}
/*
* ------------------------------------------------------------------
* | 0 - 0x20000 | --> 0x20000000 | -> 0x40000000 | -> 0xFFFFFFFF |
* | code SRAM | map to region | data SRAM | map from region |
* ------------------------------------------------------------------
*/
#define MAPPING_FROM_REGION_START 0x40000000
#define MAPPING_TO_REGION_END 0x20000000
uint32_t GLB_ConvertToMappingFromAddr(uint32_t to) {
if (!isMappingOn()) {
return to;
}
if ((to > MAPPING_TO_REGION_END) || (to < GLOBAL_CTRL->EXTADDR)) {
return to;
}
return (to + GLOBAL_CTRL->IBUSOFF);
}
uint32_t GLB_ConvertToMappingToAddr(uint32_t from) {
if (!isMappingOn()) {
return from;
}
if (from < MAPPING_FROM_REGION_START) {
return from;
}
return (from - GLOBAL_CTRL->IBUSOFF);
}
void GLB_SetNmiIrqNum(uint32_t irq) {
GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
}

10
bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c
View File

@ -28,7 +28,7 @@
#define SECONDS_IN_A_DAY (86400)
void RTC_EnableInt(uint32_t Int, BOOL Enable) {
void RTC_ITConfig(uint32_t Int, BOOL Enable) {
assert_param(IS_RTC_INT(Int));
if (Enable) {
@ -38,7 +38,7 @@ void RTC_EnableInt(uint32_t Int, BOOL Enable) {
}
}
BOOL RTC_GetIntStatus(uint32_t Int) {
BOOL RTC_GetITStatus(uint32_t Int) {
assert_param(IS_RTC_INT(Int));
if (0 != (RTC->INT_STATUS & Int)) {
@ -48,7 +48,7 @@ BOOL RTC_GetIntStatus(uint32_t Int) {
return FALSE;
}
void RTC_ClearInt(uint32_t Int) {
void RTC_ClearITPendingBit(uint32_t Int) {
assert_param(IS_RTC_INT(Int));
RTC->INT_STATUS = Int;
@ -58,6 +58,6 @@ uint32_t RTC_GetSecond() {
return RTC->SECOND;
}
uint16_t RTC_GetMicroSecond() {
return RTC->MICROSECOND_b.MS;
uint16_t RTC_GetMillSecond() {
return RTC->MILLSECOND_b.MS;
}

17
bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c
View File

@ -30,29 +30,34 @@ static uint32_t wdg_GetClock() {
return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1));
}
void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond) {
void WDG_DeInit(void){
SOFT_RESET->SOFTRST_b.WDT_n = 0;
SOFT_RESET->SOFTRST_b.WDT_n = 1;
}
void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond) {
assert_param(IS_WDG_TRIGGER_MODE(trigger));
WDG->INT_CTRL_b.TRIGGER_MODE = trigger;
WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMicroSecond / 1000;
WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMillSecond / 1000;
}
void WDG_EnableInt(uint8_t Int, BOOL Enable) {
void WDG_ITConfig(uint8_t Int, BOOL Enable) {
assert_param(IS_WDG_INT(Int));
WDG->CTRL_b.INT_LEN = Int;
WDG->INT_CTRL_b.MASK = !Enable;
}
BOOL WDG_GetIntStatus() {
BOOL WDG_GetITStatus() {
return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE;
}
void WDG_ClearInt() {
void WDG_ClearITPendingBit() {
WDG->INT_STA_b.STA = 1;
}
void WDG_Enable(BOOL Enable) {
void WDG_Cmd(BOOL Enable) {
WDG->CTRL_b.EN = Enable;
}

34
bsp/CME_M7/drivers/emac.c
View File

@ -205,14 +205,14 @@ static rt_err_t rt_cme_eth_init(rt_device_t dev)
RxDescChainInit();
TxDescChainInit();
ETH_EnableInt(ETH_INT_BUS_FATAL_ERROR, TRUE);
ETH_ITConfig(ETH_INT_BUS_FATAL_ERROR, TRUE);
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_EnableInt(ETH_INT_RX_STOP, TRUE);
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_ITConfig(ETH_INT_RX_STOP, TRUE);
ETH_StartRx();
ETH_EnableInt(ETH_INT_TX_COMPLETE_FRAME, TRUE);
ETH_ITConfig(ETH_INT_TX_COMPLETE_FRAME, TRUE);
ETH_StartTx();
return RT_EOK;
@ -318,8 +318,8 @@ struct pbuf *rt_cme_eth_rx(rt_device_t dev)
desc = ETH_AcquireFreeRxDesc();
if(desc == RT_NULL)
{
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_ResumeRx();
goto _exit;
}
@ -414,28 +414,28 @@ void ETH_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if (ETH_GetIntStatus(ETH_INT_TX_COMPLETE_FRAME))
if (ETH_GetITStatus(ETH_INT_TX_COMPLETE_FRAME))
{
rt_sem_release(&cme_eth_device.tx_buf_free);
ETH_ClearInt(ETH_INT_TX_COMPLETE_FRAME);
ETH_ClearITPendingBit(ETH_INT_TX_COMPLETE_FRAME);
}
if (ETH_GetIntStatus(ETH_INT_RX_STOP))
if (ETH_GetITStatus(ETH_INT_RX_STOP))
{
CME_ETH_PRINTF("ETH_INT_RX_STOP\n");
ETH_ClearInt(ETH_INT_RX_STOP);
ETH_ClearITPendingBit(ETH_INT_RX_STOP);
}
if ((ETH_GetIntStatus(ETH_INT_RX_BUF_UNAVAI)) ||
(ETH_GetIntStatus(ETH_INT_RX_COMPLETE_FRAME)))
if ((ETH_GetITStatus(ETH_INT_RX_BUF_UNAVAI)) ||
(ETH_GetITStatus(ETH_INT_RX_COMPLETE_FRAME)))
{
/* a frame has been received */
eth_device_ready(&(cme_eth_device.parent));
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, FALSE);
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, FALSE);
ETH_ClearInt(ETH_INT_RX_BUF_UNAVAI);
ETH_ClearInt(ETH_INT_RX_COMPLETE_FRAME);
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, FALSE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, FALSE);
ETH_ClearITPendingBit(ETH_INT_RX_BUF_UNAVAI);
ETH_ClearITPendingBit(ETH_INT_RX_COMPLETE_FRAME);
}
/* leave interrupt */

1527
bsp/CME_M7/project.uvopt
View File

File diff suppressed because it is too large Load Diff

309
bsp/CME_M7/project.uvproj
View File

@ -1,7 +1,10 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread</TargetName>
@ -11,31 +14,28 @@
<TargetCommonOption>
<Device>ARMCM3</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.4.1.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>CPUTYPE("Cortex-M3") CLOCK(10000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashDriverDll />
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -57,8 +57,8 @@
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -67,23 +67,21 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name />
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString />
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
@ -97,9 +95,8 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<ComprImg>1</ComprImg>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
@ -107,7 +104,7 @@
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments />
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
@ -129,7 +126,6 @@
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
@ -140,25 +136,22 @@
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
<UsePdscDebugDescription>1</UsePdscDebugDescription>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>17</TargetSelection>
<TargetSelection>15</TargetSelection>
<SimDlls>
<CpuDll />
<CpuDllArguments />
<PeripheralDll />
<PeripheralDllArguments />
<InitializationFile />
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll />
<CpuDllArguments />
<PeripheralDll />
<PeripheralDllArguments />
<InitializationFile />
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>CapitalMicro\BIN\cmagdi.dll</Driver>
</TargetDlls>
</DebugOption>
@ -171,14 +164,9 @@
<Capability>1</Capability>
<DriverSelection>4097</DriverSelection>
</Flash1>
<bUseTDR>0</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<FcArmLst>0</FcArmLst>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
@ -210,7 +198,7 @@
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName />
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -341,7 +329,7 @@
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -357,12 +345,10 @@
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<VariousControls>
<MiscControls />
<MiscControls></MiscControls>
<Define>RT_USING_ARM_LIBC</Define>
<Undefine />
<Undefine></Undefine>
<IncludePath>StdPeriph_Driver/inc;applications;.;drivers;CMSIS/CME_M7;../../components/CMSIS/Include;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif</IncludePath>
</VariousControls>
</Cads>
@ -375,12 +361,11 @@
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls />
<Define />
<Undefine />
<IncludePath />
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
@ -392,13 +377,12 @@
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x00000000</DataAddressRange>
<pXoBase />
<ScatterFile>CME_M7.sct</ScatterFile>
<IncludeLibs />
<IncludeLibsPath />
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc> --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) </Misc>
<LinkerInputFile />
<DisabledWarnings />
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
@ -411,113 +395,81 @@
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_adc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_aes.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_aes.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_can.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_can.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_ddr.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_ddr.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_dma.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_dma.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_efuse.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_efuse.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_eth.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_eth.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_flash.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_flash.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_i2c.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_misc.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_rtc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_spi.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_spi.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_tim.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_tim.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_uart.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_uart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_usb.c</FileName>
<FileType>1</FileType>
<FilePath>StdPeriph_Driver/src/cmem7_usb.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmem7_wdg.c</FileName>
<FileType>1</FileType>
@ -533,15 +485,11 @@
<FileType>1</FileType>
<FilePath>applications/application.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>led.c</FileName>
<FileType>1</FileType>
<FilePath>applications/led.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>startup.c</FileName>
<FileType>1</FileType>
@ -557,22 +505,16 @@
<FileType>1</FileType>
<FilePath>drivers/board.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>drivers/uart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>emac.c</FileName>
<FileType>1</FileType>
<FilePath>drivers/emac.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>app_phy.c</FileName>
<FileType>1</FileType>
@ -588,8 +530,6 @@
<FileType>1</FileType>
<FilePath>CMSIS/CME_M7/system_cmem7.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>startup_cmem7.s</FileName>
<FileType>2</FileType>
@ -605,85 +545,61 @@
<FileType>1</FileType>
<FilePath>../../src/clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/device.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/scheduler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>../../src/thread.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
@ -699,29 +615,21 @@
<FileType>1</FileType>
<FilePath>../../libcpu/arm/cortex-m3/cpuport.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>../../libcpu/arm/cortex-m3/context_rvds.S</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>../../libcpu/arm/common/backtrace.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>../../libcpu/arm/common/div0.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
@ -737,8 +645,6 @@
<FileType>1</FileType>
<FilePath>../../components/libc/armlibc/mem_std.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stubs.c</FileName>
<FileType>1</FileType>
@ -754,43 +660,31 @@
<FileType>1</FileType>
<FilePath>../../components/drivers/serial/serial.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/drivers/src/completion.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/drivers/src/dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/drivers/src/pipe.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>portal.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/drivers/src/portal.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/drivers/src/ringbuffer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
@ -806,99 +700,71 @@
<FileType>1</FileType>
<FilePath>../../components/finsh/shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>symbol.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/symbol.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_cmd.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/msh_cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/msh.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_compiler.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_compiler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_error.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_error.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_heap.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_heap.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_init.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_init.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_node.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_node.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_ops.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_ops.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_parser.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_parser.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_var.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_var.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_vm.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/finsh/finsh_vm.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>finsh_token.c</FileName>
<FileType>1</FileType>
@ -914,239 +780,171 @@
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/api_lib.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>api_msg.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/api_msg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>err.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/err.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>netbuf.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/netbuf.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>netdb.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/netdb.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>netifapi.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/netifapi.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>sockets.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/sockets.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>tcpip.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/api/tcpip.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>sys_arch.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/arch/sys_arch.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>def.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/def.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dhcp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/dhcp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dns.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/dns.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>init.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/init.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>memp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/memp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>netif.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/netif.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pbuf.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/pbuf.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>raw.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/raw.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stats.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/stats.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>sys.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/sys.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>tcp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/tcp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>tcp_in.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/tcp_in.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>tcp_out.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/tcp_out.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timers.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/timers.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>udp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/udp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>autoip.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>icmp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>igmp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>inet.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/inet.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>inet_chksum.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ip.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/ip.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ip_addr.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ip_frag.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>etharp.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/netif/etharp.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ethernetif.c</FileName>
<FileType>1</FileType>
<FilePath>../../components/net/lwip-1.4.1/src/netif/ethernetif.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>slipif.c</FileName>
<FileType>1</FileType>
@ -1157,4 +955,5 @@
</Groups>
</Target>
</Targets>
</Project>