commit
b25a279475
|
@ -51,9 +51,8 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
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CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_MEMHEAP is not set
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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# CONFIG_RT_USING_SMALL_MEM is not set
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CONFIG_RT_USING_SLAB=y
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CONFIG_RT_USING_HEAP=y
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#
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@ -108,9 +107,9 @@ CONFIG_FINSH_ARG_MAX=10
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#
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_WORKDIR=y
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CONFIG_DFS_FILESYSTEMS_MAX=4
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
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CONFIG_DFS_FD_MAX=16
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CONFIG_DFS_FILESYSTEMS_MAX=16
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
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CONFIG_DFS_FD_MAX=64
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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CONFIG_RT_USING_DFS_ELMFAT=y
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@ -126,7 +125,7 @@ CONFIG_RT_DFS_ELM_USE_LFN_3=y
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CONFIG_RT_DFS_ELM_USE_LFN=3
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CONFIG_RT_DFS_ELM_MAX_LFN=255
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CONFIG_RT_DFS_ELM_DRIVES=2
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CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
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CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
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# CONFIG_RT_DFS_ELM_USE_ERASE is not set
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CONFIG_RT_DFS_ELM_REENTRANT=y
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CONFIG_RT_USING_DFS_DEVFS=y
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@ -159,7 +158,11 @@ CONFIG_RT_USING_PIN=y
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CONFIG_RT_USING_SPI=y
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# CONFIG_RT_USING_QSPI is not set
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CONFIG_RT_USING_SPI_MSD=y
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# CONFIG_RT_USING_SFUD is not set
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CONFIG_RT_USING_SFUD=y
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CONFIG_RT_SFUD_USING_SFDP=y
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CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
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# CONFIG_RT_SFUD_USING_QSPI is not set
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CONFIG_RT_DEBUG_SFUD=y
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# CONFIG_RT_USING_W25QXX is not set
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# CONFIG_RT_USING_GD is not set
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# CONFIG_RT_USING_ENC28J60 is not set
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@ -8,6 +8,7 @@ board.c
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heap.c
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drv_uart.c
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drv_io_config.c
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drv_interrupt.c
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''')
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CPPPATH = [cwd]
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@ -84,6 +84,8 @@ extern int rt_hw_clint_ipi_enable(void);
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void rt_hw_board_init(void)
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{
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sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
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sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
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/* Init FPIOA */
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fpioa_init();
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/* Dmac init */
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@ -139,7 +139,7 @@ static void pin_irq(int vector, void *param)
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set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1);
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}
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if(irq_table[pin_channel 2019-03-18 ZYH first version].edge & GPIO_PE_RISING)
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if(irq_table[pin_channel].edge & GPIO_PE_RISING)
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{
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set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0);
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set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1);
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-03-19 ZYH first version
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*/
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#include <plic.h>
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void plic_irq_handle(plic_irq_t irq)
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{
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plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
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if (plic_instance[0][irq].callback)
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{
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plic_instance[0][irq].callback(
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plic_instance[0][irq].ctx);
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}
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else if (plic_instance[1][irq].callback)
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{
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plic_instance[1][irq].callback(
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plic_instance[1][irq].ctx);
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}
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}
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@ -1,3 +1,13 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-03-19 ZYH first version
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*/
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#include <rtthread.h>
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#include <fpioa.h>
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#include <drv_io_config.h>
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@ -25,7 +35,7 @@ static struct io_config
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{BSP_CAMERA_CMOS_PWDN_PIN, FUNC_CMOS_PWDN},
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{BSP_CAMERA_CMOS_XCLK_PIN, FUNC_CMOS_XCLK},
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{BSP_CAMERA_CMOS_PCLK_PIN, FUNC_CMOS_PCLK},
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{BSP_CAMERA_CMOS_PCLK_PIN, FUNC_CMOS_HREF},
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{BSP_CAMERA_CMOS_HREF_PIN, FUNC_CMOS_HREF},
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#endif
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#ifdef BSP_USING_SPI1
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@ -73,3 +83,4 @@ int io_config_init(void)
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}
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INIT_BOARD_EXPORT(io_config_init);
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@ -1,3 +1,13 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-03-19 ZYH first version
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*/
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#ifndef __DRV_IO_CONFIG_H__
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#define __DRV_IO_CONFIG_H__
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@ -19,9 +19,12 @@
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#include <sysctl.h>
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#include <gpiohs.h>
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#include <string.h>
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#include "utils.h"
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#define DRV_SPI_DEVICE(spi_bus) (struct drv_spi_bus *)(spi_bus)
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#define MAX_CLOCK (40000000UL)
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struct drv_spi_bus
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{
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struct rt_spi_bus parent;
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@ -48,6 +51,7 @@ static rt_err_t drv_spi_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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rt_err_t ret = RT_EOK;
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int freq = 0;
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struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
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struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
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RT_ASSERT(bus != RT_NULL);
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@ -60,31 +64,43 @@ static rt_err_t drv_spi_configure(struct rt_spi_device *device,
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#else
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spi_init(bus->spi_instance, configuration->mode & RT_SPI_MODE_3, SPI_FF_STANDARD, configuration->data_width, 0);
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#endif
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spi_set_clk_rate(bus->spi_instance, configuration->max_hz);
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freq = spi_set_clk_rate(bus->spi_instance, configuration->max_hz > MAX_CLOCK ? MAX_CLOCK : configuration->max_hz);
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rt_kprintf("set spi freq %d\n", freq);
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return ret;
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}
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extern void spi_receive_data_normal_dma(dmac_channel_number_t dma_send_channel_num,
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dmac_channel_number_t dma_receive_channel_num,
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spi_device_num_t spi_num, spi_chip_select_t chip_select, const void *cmd_buff,
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size_t cmd_len, void *rx_buff, size_t rx_len);
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void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
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{
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RT_ASSERT(spi_num < SPI_DEVICE_MAX);
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volatile spi_t *spi_handle = spi[spi_num];
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uint8_t tmod_offset = 0;
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switch(spi_num)
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{
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case 0:
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case 1:
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case 2:
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tmod_offset = 8;
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break;
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case 3:
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default:
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tmod_offset = 10;
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break;
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}
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set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
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}
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static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
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struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
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struct rt_spi_configuration *cfg = &device->config;
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const uint8_t * tx_buff = message->send_buf;
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uint8_t * rx_buff = message->recv_buf;
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uint32_t dummy[1024];
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size_t send_size, recv_size;
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uint32_t * tx_buff = RT_NULL;
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uint32_t * rx_buff = RT_NULL;
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int i;
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rt_ubase_t dummy = 0xFFFFFFFFU;
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send_size = message->length;
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recv_size = message->length;
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__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS_RECV);
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RT_ASSERT(bus != RT_NULL);
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@ -94,18 +110,73 @@ static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
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}
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if(message->length)
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{
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if(!tx_buff)
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spi_instance[bus->spi_instance]->dmacr = 0x3;
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spi_instance[bus->spi_instance]->ssienr = 0x01;
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sysctl_dma_select(bus->dma_send_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + bus->spi_instance * 2);
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sysctl_dma_select(bus->dma_recv_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + bus->spi_instance * 2);
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if(!message->recv_buf)
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{
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tx_buff = (uint8_t *)&dummy;
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send_size = 1;
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dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), &dummy, DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
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}
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else
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{
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rx_buff = rt_calloc(message->length * 4, 1);
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if(!rx_buff)
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{
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goto transfer_done;
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}
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dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
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DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
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}
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if(!message->send_buf)
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{
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dmac_set_single_mode(bus->dma_send_channel, &dummy, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
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}
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else
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{
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tx_buff = rt_malloc(message->length * 4);
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if(!tx_buff)
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{
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goto transfer_done;
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}
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for(i = 0; i < message->length; i++)
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{
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tx_buff[i] = ((uint8_t *)message->send_buf)[i];
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}
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dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
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}
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spi_instance[bus->spi_instance]->ser = 1U << cs->cs_index;
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dmac_wait_done(bus->dma_send_channel);
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dmac_wait_done(bus->dma_recv_channel);
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spi_instance[bus->spi_instance]->ser = 0x00;
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spi_instance[bus->spi_instance]->ssienr = 0x00;
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if(message->recv_buf)
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{
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for(i = 0; i < message->length; i++)
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{
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((uint8_t *)message->recv_buf)[i] = (uint8_t)rx_buff[i];
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}
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}
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if(!rx_buff)
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transfer_done:
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if(tx_buff)
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{
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rx_buff = (uint8_t *)&dummy;
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recv_size = 1;
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rt_free(tx_buff);
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}
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if(rx_buff)
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{
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rt_free(rx_buff);
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}
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spi_dup_send_receive_data_dma(bus->dma_send_channel, bus->dma_recv_channel, bus->spi_instance, cs->cs_index, tx_buff, send_size, rx_buff, recv_size);
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}
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if(message->cs_release)
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|
|
|
@ -49,9 +49,8 @@
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#define RT_USING_MEMPOOL
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/* RT_USING_MEMHEAP is not set */
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/* RT_USING_NOHEAP is not set */
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#define RT_USING_SMALL_MEM
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/* RT_USING_SLAB is not set */
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/* RT_USING_MEMTRACE is not set */
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/* RT_USING_SMALL_MEM is not set */
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#define RT_USING_SLAB
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#define RT_USING_HEAP
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/* Kernel Device Object */
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|
@ -101,9 +100,9 @@
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|||
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||||
#define RT_USING_DFS
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#define DFS_USING_WORKDIR
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#define DFS_FILESYSTEMS_MAX 4
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#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define DFS_FD_MAX 16
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#define DFS_FILESYSTEMS_MAX 16
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 16
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||||
#define DFS_FD_MAX 64
|
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/* RT_USING_DFS_MNTTABLE is not set */
|
||||
#define RT_USING_DFS_ELMFAT
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||||
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||||
|
@ -118,7 +117,7 @@
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|||
#define RT_DFS_ELM_USE_LFN 3
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||||
#define RT_DFS_ELM_MAX_LFN 255
|
||||
#define RT_DFS_ELM_DRIVES 2
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
|
||||
/* RT_DFS_ELM_USE_ERASE is not set */
|
||||
#define RT_DFS_ELM_REENTRANT
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||||
#define RT_USING_DFS_DEVFS
|
||||
|
@ -150,7 +149,11 @@
|
|||
#define RT_USING_SPI
|
||||
/* RT_USING_QSPI is not set */
|
||||
#define RT_USING_SPI_MSD
|
||||
/* RT_USING_SFUD is not set */
|
||||
#define RT_USING_SFUD
|
||||
#define RT_SFUD_USING_SFDP
|
||||
#define RT_SFUD_USING_FLASH_INFO_TABLE
|
||||
/* RT_SFUD_USING_QSPI is not set */
|
||||
#define RT_DEBUG_SFUD
|
||||
/* RT_USING_W25QXX is not set */
|
||||
/* RT_USING_GD is not set */
|
||||
/* RT_USING_ENC28J60 is not set */
|
||||
|
|
|
@ -230,10 +230,6 @@ uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
|
|||
/* Restore primitive IRQ threshold */
|
||||
plic->targets.target[core_id].priority_threshold = int_threshold;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("unhandled trap!\n");
|
||||
}
|
||||
|
||||
return epc;
|
||||
}
|
||||
|
@ -270,8 +266,51 @@ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
|||
rt_hw_interrupt_disable();
|
||||
|
||||
tid = rt_thread_self();
|
||||
rt_kprintf("\nException:\n");
|
||||
switch (cause)
|
||||
{
|
||||
case CAUSE_MISALIGNED_FETCH:
|
||||
rt_kprintf("Instruction address misaligned");
|
||||
break;
|
||||
case CAUSE_FAULT_FETCH:
|
||||
rt_kprintf("Instruction access fault");
|
||||
break;
|
||||
case CAUSE_ILLEGAL_INSTRUCTION:
|
||||
rt_kprintf("Illegal instruction");
|
||||
break;
|
||||
case CAUSE_BREAKPOINT:
|
||||
rt_kprintf("Breakpoint");
|
||||
break;
|
||||
case CAUSE_MISALIGNED_LOAD:
|
||||
rt_kprintf("Load address misaligned");
|
||||
break;
|
||||
case CAUSE_FAULT_LOAD:
|
||||
rt_kprintf("Load access fault");
|
||||
break;
|
||||
case CAUSE_MISALIGNED_STORE:
|
||||
rt_kprintf("Store address misaligned");
|
||||
break;
|
||||
case CAUSE_FAULT_STORE:
|
||||
rt_kprintf("Store access fault");
|
||||
break;
|
||||
case CAUSE_USER_ECALL:
|
||||
rt_kprintf("Environment call from U-mode");
|
||||
break;
|
||||
case CAUSE_SUPERVISOR_ECALL:
|
||||
rt_kprintf("Environment call from S-mode");
|
||||
break;
|
||||
case CAUSE_HYPERVISOR_ECALL:
|
||||
rt_kprintf("Environment call from H-mode");
|
||||
break;
|
||||
case CAUSE_MACHINE_ECALL:
|
||||
rt_kprintf("Environment call from M-mode");
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("Uknown exception : %08lX", cause);
|
||||
break;
|
||||
}
|
||||
rt_kprintf("\n");
|
||||
rt_kprintf("unhandled trap, epc => 0x%08x, INT[%d]\n", epc, rt_interrupt_get_nest());
|
||||
rt_kprintf("exception pc => 0x%08x\n", epc);
|
||||
rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
|
|
Loading…
Reference in New Issue