Cleanup Interrupt for F1S
Use structure to handle the registers access, which simplified the logic
This commit is contained in:
Howard Su
parent
339ebf3c16
commit
b22b7cbdfe
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@ -1,7 +1,7 @@
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/*
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* File : interrupt.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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* COPYRIGHT (C) 2017-2021, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,6 +20,7 @@
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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* 2020-03-02 Howard Su Use structure to access registers
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*/
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#include <rthw.h>
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@ -38,9 +39,6 @@ static void rt_hw_interrupt_handler(int vector, void *param)
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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}
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#define readl(addr) (*(volatile unsigned int *)(addr))
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#define writel(value,addr) (*(volatile unsigned int *)(addr) = (value))
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/**
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* This function will initialize hardware interrupt
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*/
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@ -63,20 +61,20 @@ void rt_hw_interrupt_init(void)
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/* set base_addr reg */
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INTC->base_addr_reg = 0x00000000;
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/* clear enable */
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INTC->en_reg0 = 0x00000000;
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INTC->en_reg1 = 0x00000000;
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INTC->en_reg[0] = 0x00000000;
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INTC->en_reg[1] = 0x00000000;
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/* mask interrupt */
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INTC->mask_reg0 = 0xFFFFFFFF;
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INTC->mask_reg1 = 0xFFFFFFFF;
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INTC->mask_reg[0] = 0xFFFFFFFF;
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INTC->mask_reg[1] = 0xFFFFFFFF;
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/* clear pending */
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INTC->pend_reg0 = 0x00000000;
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INTC->pend_reg1 = 0x00000000;
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INTC->pend_reg[0] = 0x00000000;
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INTC->pend_reg[1] = 0x00000000;
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/* set priority */
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INTC->resp_reg0 = 0x00000000;
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INTC->resp_reg1 = 0x00000000;
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INTC->resp_reg[0] = 0x00000000;
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INTC->resp_reg[1] = 0x00000000;
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/* close fiq interrupt */
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INTC->ff_reg0 = 0x00000000;
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INTC->ff_reg1 = 0x00000000;
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INTC->ff_reg[0] = 0x00000000;
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INTC->ff_reg[1] = 0x00000000;
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}
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/**
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@ -85,20 +83,16 @@ void rt_hw_interrupt_init(void)
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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rt_uint32_t mask_addr, data;
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int index;
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if ((vector < 0) || (vector > INTERRUPTS_MAX))
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{
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return;
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}
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mask_addr = (rt_uint32_t)(&INTC->mask_reg0);
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mask_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
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index = (vector & 0xE0) != 0;
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vector = (vector & 0x1F);
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vector &= 0x1F;
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data = readl(mask_addr);
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data |= 0x1 << vector;
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writel(data, mask_addr);
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INTC->mask_reg[index] |= 1 << vector;
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}
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/**
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@ -108,20 +102,16 @@ void rt_hw_interrupt_mask(int vector)
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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rt_uint32_t mask_addr, data;
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int index;
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if ((vector < 0) || (vector > INTERRUPTS_MAX))
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{
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return;
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}
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mask_addr = (rt_uint32_t)(&INTC->mask_reg0);
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mask_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
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index = (vector & 0xE0) != 0;
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vector = (vector & 0x1F);
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vector &= 0x1F;
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data = readl(mask_addr);
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data &= ~(0x1 << vector);
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writel(data, mask_addr);
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INTC->mask_reg[index] &= ~(1 << vector);
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}
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/**
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@ -136,7 +126,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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rt_uint32_t pend_addr, en_addr, data;
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int index;
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if ((vector < 0) || (vector > INTERRUPTS_MAX))
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{
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@ -151,19 +141,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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isr_table[vector].handler = handler;
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isr_table[vector].param = param;
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pend_addr = (rt_uint32_t)(&INTC->pend_reg0);
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en_addr = (rt_uint32_t)(&INTC->en_reg0);
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pend_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
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en_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
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index = (vector & 0xE0) != 0;
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vector = (vector & 0x1F);
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vector &= 0x1F;
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data = readl(pend_addr);
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data &= ~(0x1 << vector);
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writel(data, pend_addr);
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data = readl(en_addr);
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data |= 0x1 << vector;
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writel(data, en_addr);
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INTC->pend_reg[index] &= ~(0x1 << vector);
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INTC->en_reg[index] |= 0x1 << vector;
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return old_handler;
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}
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@ -173,7 +155,7 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
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void *param;
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int vector;
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rt_isr_handler_t isr_func;
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rt_uint32_t pend_addr, data;
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int index;
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vector = INTC->vector_reg - INTC->base_addr_reg;
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vector = vector >> 2;
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@ -184,13 +166,11 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
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/* jump to fun */
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isr_func(vector, param);
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/* clear pend bit */
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pend_addr = (rt_uint32_t)(&INTC->pend_reg0);
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pend_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0;
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vector &= 0x1F;
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data = readl(pend_addr);
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data &= ~(0x1 << vector);
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writel(data, pend_addr);
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index = (vector & 0xE0) != 0;
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vector = (vector & 0x1F);
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INTC->pend_reg[index] &= ~(0x1 << vector);
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[vector].counter ++;
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@ -1,7 +1,7 @@
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/*
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* File : interrupt.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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* COPYRIGHT (C) 2017-2021, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,6 +20,7 @@
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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* 2020-03-2 Howard Su Define same regsiters as an array
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*/
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#ifndef __INTERRUPT_H__
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#define __INTERRUPT_H__
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@ -74,34 +75,21 @@ struct tina_intc
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volatile rt_uint32_t base_addr_reg; /* 0x04 */
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volatile rt_uint32_t reserved0;
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volatile rt_uint32_t nmi_ctrl_reg; /* 0x0C */
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volatile rt_uint32_t pend_reg0; /* 0x10 */
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volatile rt_uint32_t pend_reg1; /* 0x14 */
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volatile rt_uint32_t pend_reg[2]; /* 0x10, 0x14 */
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volatile rt_uint32_t reserved1[2];
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volatile rt_uint32_t en_reg0; /* 0x20 */
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volatile rt_uint32_t en_reg1; /* 0x24 */
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volatile rt_uint32_t en_reg[2]; /* 0x20, 0x24 */
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volatile rt_uint32_t reserved2[2];
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volatile rt_uint32_t mask_reg0; /* 0x30 */
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volatile rt_uint32_t mask_reg1; /* 0x34 */
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volatile rt_uint32_t mask_reg[2]; /* 0x30, 0x34 */
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volatile rt_uint32_t reserved3[2];
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volatile rt_uint32_t resp_reg0; /* 0x40 */
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volatile rt_uint32_t resp_reg1; /* 0x44 */
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volatile rt_uint32_t resp_reg[2]; /* 0x40, 0x44 */
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volatile rt_uint32_t reserved4[2];
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volatile rt_uint32_t ff_reg0; /* 0x50 */
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volatile rt_uint32_t ff_reg1; /* 0x54 */
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volatile rt_uint32_t ff_reg[2]; /* 0x50, 0x54 */
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volatile rt_uint32_t reserved5[2];
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volatile rt_uint32_t prio_reg0; /* 0x60 */
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volatile rt_uint32_t prio_reg1; /* 0x64 */
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volatile rt_uint32_t prio_reg2; /* 0x68 */
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volatile rt_uint32_t prio_reg3; /* 0x6C */
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volatile rt_uint32_t prio_reg[4]; /* 0x60 - 0x6c */
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} ;
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typedef struct tina_intc *tina_intc_t;
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#define INTC ((tina_intc_t)INTC_BASE_ADDR)
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void rt_hw_interrupt_init(void);
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void rt_hw_interrupt_mask(int vector);
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void rt_hw_interrupt_umask(int vector);
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
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#endif /* __INTERRUPT_H__ */
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