diff --git a/bsp/lm3s/application.c b/bsp/lm3s/application.c index b574fc4d48..1453f05220 100644 --- a/bsp/lm3s/application.c +++ b/bsp/lm3s/application.c @@ -20,6 +20,22 @@ #include #include +#ifdef RT_USING_DFS +/* dfs init */ +#include +/* dfs filesystem:FAT filesystem init */ +#include +/* dfs filesystem:EFS filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +#ifdef RT_USING_LWIP +#include +#include +#endif + char thread1_stack[0x120]; struct rt_thread thread1; @@ -49,8 +65,48 @@ void thread_test() FINSH_FUNCTION_EXPORT(thread_test, test a basic thread) #endif +/* thread phase init */ +void rt_init_thread_entry(void *parameter) +{ +/* Filesystem Initialization */ +#ifdef RT_USING_DFS + { + /* init the device filesystem */ + dfs_init(); + /* init the efsl filesystam*/ + efsl_init(); + + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "efs", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } +#endif + +/* LwIP Initialization */ +#ifdef RT_USING_LWIP + { + extern void lwip_sys_init(void); + + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("TCP/IP initialized!\n"); + + ftpd_start(); + } +#endif +} + int rt_application_init() { + rt_thread_t init_thread; + + init_thread = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, 21, 20); + rt_thread_startup(init_thread); + return 0; } /*@}*/ diff --git a/bsp/lm3s/board.c b/bsp/lm3s/board.c index 87e3bf178b..da248cf64d 100644 --- a/bsp/lm3s/board.c +++ b/bsp/lm3s/board.c @@ -14,17 +14,17 @@ #include #include - -#include -#include -#include -#include -#include -#include -#include -#include -static void rt_hw_console_init(void); +#include +#include +#include +#include +#include +#include +#include +#include + +static void rt_hw_console_init(void); /** * @addtogroup LM3S @@ -47,66 +47,69 @@ void rt_hw_timer_handler(void) /* leave interrupt */ rt_interrupt_leave(); rt_hw_interrupt_thread_switch(); -} - +} + /** * This function will initial STM32 board. */ void rt_hw_board_init() -{ - /* set clock */ - SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | - SYSCTL_XTAL_6MHZ); - - /* init systick */ - SysTickDisable(); - SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); - SysTickIntEnable(); - SysTickEnable(); - - /* init console */ - rt_hw_console_init(); - - /* enable interrupt */ +{ + /* set clock */ + SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | + SYSCTL_XTAL_6MHZ); + + /* init systick */ + SysTickDisable(); + SysTickPeriodSet(SysCtlClockGet()/RT_TICK_PER_SECOND); + SysTickIntEnable(); + SysTickEnable(); + + /* enable ssio */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + + /* init console */ + rt_hw_console_init(); + + /* enable interrupt */ IntMasterEnable(); -} - -/* init console to support rt_kprintf */ -static void rt_hw_console_init() -{ - /* Enable the UART0 peripherals */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - /* Set GPIO A0 and A1 as UART pins. */ - GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); - - /* Configure the UART for 115,200, 8-N-1 operation. */ - UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, - (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | - UART_CONFIG_PAR_NONE)); -} - -/* write one character to serial, must not trigger interrupt */ -static void rt_hw_console_putc(const char c) -{ - if (c == '\n') - while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); - - while(UARTCharPutNonBlocking(UART0_BASE, c) == false); -} - -/** - * This function is used by rt_kprintf to display a string on console. - * - * @param str the displayed string - */ -void rt_hw_console_output(const char* str) -{ - while (*str) - { - rt_hw_console_putc (*str++); - } -} +} + +/* init console to support rt_kprintf */ +static void rt_hw_console_init() +{ + /* Enable the UART0 peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as UART pins. */ + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200, + (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE)); +} + +/* write one character to serial, must not trigger interrupt */ +static void rt_hw_console_putc(const char c) +{ + if (c == '\n') + while(UARTCharPutNonBlocking(UART0_BASE, '\r') == false); + + while(UARTCharPutNonBlocking(UART0_BASE, c) == false); +} + +/** + * This function is used by rt_kprintf to display a string on console. + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + rt_hw_console_putc (*str++); + } +} /*@}*/ diff --git a/bsp/lm3s/luminaryif.c b/bsp/lm3s/luminaryif.c new file mode 100644 index 0000000000..659da30f38 --- /dev/null +++ b/bsp/lm3s/luminaryif.c @@ -0,0 +1,486 @@ +//***************************************************************************** +// +// luminaryif.c - Ethernet Interface File for lwIP TCP/IP Stack +// +//***************************************************************************** + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "lwipopts.h" +#include "luminaryif.h" + +#define MAX_ADDR_LEN 6 + +struct net_device +{ + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ +}; + +static struct net_device luminaryif_dev_entry; +static struct net_device *luminaryif_dev =&luminaryif_dev_entry; +static struct rt_semaphore tx_sem; + +//***************************************************************************** +// +// Sanity Check: This module will NOT work if the following defines +// are incorrect. +// +//***************************************************************************** +#if (PBUF_LINK_HLEN != 16) +#error "Incorrect PBUF_LINK_HLEN specified!" +#endif +#if (ETH_PAD_SIZE != 2) +#error "Incorrect ETH_PAD_SIZE specified!" +#endif +#if (PBUF_POOL_BUFSIZE % 4) +#error "PBUF_POOL_BUFSIZE must be modulo 4!" +#endif + +/* RT-Thread Device Interface */ + +/* initialize the interface */ +//***************************************************************************** +// +// Low-Level initialization function for the Ethernet Controller. +// +//***************************************************************************** +rt_err_t luminaryif_init(rt_device_t dev) +{ + unsigned long ulTemp; + + // + // Disable all Ethernet Interrupts. + // + EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | + ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | + ETH_INT_RX)); + ulTemp = EthernetIntStatus(ETH_BASE, false); + EthernetIntClear(ETH_BASE, ulTemp); + + // + // Initialize the Ethernet Controller. + // + EthernetInitExpClk(ETH_BASE, SysCtlClockGet()); + + // + // Configure the Ethernet Controller for normal operation. + // - Enable TX Duplex Mode + // - Enable TX Padding + // - Enable TX CRC Generation + // + EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | + ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN)); + + // + // Enable the Ethernet Controller transmitter and receiver. + // + EthernetEnable(ETH_BASE); + + // + // Enable the Ethernet Interrupt handler. + // + IntEnable(INT_ETH); + + // + // Enable Ethernet TX and RX Packet Interrupts. + // + EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX); + + return RT_EOK; +} + +void luminaryif_isr(void) +{ + unsigned long ulTemp; + + // + // Read and Clear the interrupt. + // + ulTemp = EthernetIntStatus(ETH_BASE, false); + EthernetIntClear(ETH_BASE, ulTemp); + + // + // Check to see if an RX Interrupt has occured. + // + if(ulTemp & ETH_INT_RX) + { + // + // Indicate that a packet has been received. + // + rt_err_t result; + /* a frame has been received */ + result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent)); + RT_ASSERT(result == RT_EOK); + // + // Disable Ethernet RX Interrupt. + // + EthernetIntDisable(ETH_BASE, ETH_INT_RX); + } + if(ulTemp & ETH_INT_TX) + { + /* A frame has been transmitted. */ + rt_sem_release(&tx_sem); + } + +} + +/* control the interface */ +rt_err_t luminaryif_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, luminaryif_dev_entry.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* Open the ethernet interface */ +rt_err_t luminaryif_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +/* Close the interface */ +rt_err_t luminaryif_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* Read */ +rt_size_t luminaryif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +/* Write */ +rt_size_t luminaryif_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +//**************************************************************************** +// +// Low-Level transmit routine. Should do the actual transmission of the +// packet. The packet is contained in the pbuf that is passed to the function. +// This pbuf might be chained. +// +//**************************************************************************** +rt_err_t luminaryif_tx(rt_device_t dev, struct pbuf *p) +{ + int iBuf; + unsigned char *pucBuf; + unsigned long *pulBuf; + struct pbuf *q; + int iGather; + unsigned long ulGather; + unsigned char *pucGather; + unsigned long ulTemp; + + /* lock tx operation */ + rt_sem_take(&tx_sem, RT_WAITING_FOREVER); + + // + // Wait for space available in the TX FIFO. + // + while(!EthernetSpaceAvail(ETH_BASE)) + { + } + +// + // Fill in the first two bytes of the payload data (configured as padding + // with ETH_PAD_SIZE = 2) with the total length of the payload data + // (minus the Ethernet MAC layer header). + // + *((unsigned short *)(p->payload)) = p->tot_len - 16; + + // + // Initialize the gather register. + // + iGather = 0; + pucGather = (unsigned char *)&ulGather; + ulGather = 0; + + // + // Copy data from the pbuf(s) into the TX Fifo. + // + for(q = p; q != NULL; q = q->next) + { + // + // Intialize a char pointer and index to the pbuf payload data. + // + pucBuf = (unsigned char *)q->payload; + iBuf = 0; + + // + // If the gather buffer has leftover data from a previous pbuf + // in the chain, fill it up and write it to the Tx FIFO. + // + while((iBuf < q->len) && (iGather != 0)) + { + // + // Copy a byte from the pbuf into the gather buffer. + // + pucGather[iGather] = pucBuf[iBuf++]; + + // + // Increment the gather buffer index modulo 4. + // + iGather = ((iGather + 1) % 4); + } + + // + // If the gather index is 0 and the pbuf index is non-zero, + // we have a gather buffer to write into the Tx FIFO. + // + if((iGather == 0) && (iBuf != 0)) + { + HWREG(ETH_BASE + MAC_O_DATA) = ulGather; + ulGather = 0; + } + + // + // Copy words of pbuf data into the Tx FIFO, but don't go past + // the end of the pbuf. + // + if((iBuf % 4) != 0) + { + while((iBuf + 4) <= q->len) + { + ulTemp = (pucBuf[iBuf++] << 0); + ulTemp |= (pucBuf[iBuf++] << 8); + ulTemp |= (pucBuf[iBuf++] << 16); + ulTemp |= (pucBuf[iBuf++] << 24); + HWREG(ETH_BASE + MAC_O_DATA) = ulTemp; + } + } + else + { + // + // Initialze a long pointer into the pbuf for 32-bit access. + // + pulBuf = (unsigned long *)&pucBuf[iBuf]; + + while((iBuf + 4) <= q->len) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulBuf++; + iBuf += 4; + } + } + // + // Check if leftover data in the pbuf and save it in the gather + // buffer for the next time. + // + while(iBuf < q->len) + { + // + // Copy a byte from the pbuf into the gather buffer. + // + pucGather[iGather] = pucBuf[iBuf++]; + + // + // Increment the gather buffer index modulo 4. + // + iGather = ((iGather + 1) % 4); + } + } + + // + // Send any leftover data to the FIFO. + // + HWREG(ETH_BASE + MAC_O_DATA) = ulGather; + + // + // Wakeup the transmitter. + // + HWREG(ETH_BASE + MAC_O_TR) = MAC_TR_NEWTX; + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif + + return(ERR_OK); +} + +//***************************************************************************** +// +// Low-Level receive routine. Should allocate a pbuf and transfer the bytes +// of the incoming packet from the interface into the pbuf. +// +//***************************************************************************** +struct pbuf * luminaryif_rx(rt_device_t dev) +{ + struct pbuf *p, *q; + u16_t len; + unsigned long ulTemp; + int i; + unsigned long *ptr; + + if(!EthernetPacketAvail(ETH_BASE)) + { + return(NULL); + } + + // + // Obtain the size of the packet and put it into the "len" variable. + // Note: The length returned in the FIFO length position includes the + // two bytes for the length + the 4 bytes for the FCS. + // + ulTemp = HWREG(ETH_BASE + MAC_O_DATA); + len = ulTemp & 0xFFFF; + + // + // We allocate a pbuf chain of pbufs from the pool. + // + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + + if(p != NULL) + { + // + // Place the first word into the first pbuf location. + // + *(unsigned long *)p->payload = ulTemp; + p->payload = (char *)(p->payload) + 4; + p->len -= 4; + + // + // Process all but the last buffer in the pbuf chain. + // + q = p; + while(q != NULL) + { + // + // Setup a byte pointer into the payload section of the pbuf. + // + ptr = q->payload; + + // + // Read data from FIFO into the current pbuf + // (assume pbuf length is modulo 4) + // + for(i = 0; i < q->len; i += 4) + { + *ptr++ = HWREG(ETH_BASE + MAC_O_DATA); + } + + // + // Link in the next pbuf in the chain. + // + q = q->next; + } + + // + // Restore the first pbuf parameters to their original values. + // + p->payload = (char *)(p->payload) - 4; + p->len += 4; + +#if LINK_STATS + lwip_stats.link.recv++; +#endif + } + else + { + // + // Just read all of the remaining data from the FIFO and dump it. + // + for(i = 4; i < len; i+=4) + { + ulTemp = HWREG(ETH_BASE + MAC_O_DATA); + } + +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + } + + // + // Enable Ethernet RX Interrupt. + // + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return(p); +} + +int rt_hw_luminaryif_init(void) +{ + rt_err_t result; + unsigned long ulUser0, ulUser1; + + /* Enable and Reset the Ethernet Controller. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH); + SysCtlPeripheralReset(SYSCTL_PERIPH_ETH); + + /* + Enable Port F for Ethernet LEDs. + LED0 Bit 3 Output + LED1 Bit 2 Output + */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW); + GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, + GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); + + FlashUserSet(0x12345678, 0x12345678); + /* Configure the hardware MAC address */ + FlashUserGet(&ulUser0, &ulUser1); + if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff)) + { + rt_kprintf("Fatal error in geting MAC address\n"); + } + + /* init rt-thread device interface */ + luminaryif_dev_entry.parent.parent.init = luminaryif_init; + luminaryif_dev_entry.parent.parent.open = luminaryif_open; + luminaryif_dev_entry.parent.parent.close = luminaryif_close; + luminaryif_dev_entry.parent.parent.read = luminaryif_read; + luminaryif_dev_entry.parent.parent.write = luminaryif_write; + luminaryif_dev_entry.parent.parent.control = luminaryif_control; + luminaryif_dev_entry.parent.eth_rx = luminaryif_rx; + luminaryif_dev_entry.parent.eth_tx = luminaryif_tx; + + /* + Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC + address needed to program the hardware registers, then program the MAC + address into the Ethernet Controller registers. + */ + luminaryif_dev_entry.dev_addr[0] = ((ulUser0 >> 0) & 0xff); + luminaryif_dev_entry.dev_addr[1] = ((ulUser0 >> 8) & 0xff); + luminaryif_dev_entry.dev_addr[2] = ((ulUser0 >> 16) & 0xff); + luminaryif_dev_entry.dev_addr[3] = ((ulUser1 >> 0) & 0xff); + luminaryif_dev_entry.dev_addr[4] = ((ulUser1 >> 8) & 0xff); + luminaryif_dev_entry.dev_addr[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the hardware with it's MAC address (for filtering). */ + EthernetMACAddrSet(ETH_BASE, luminaryif_dev_entry.dev_addr); + + rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO); + + result = eth_device_init(&(luminaryif_dev->parent), "E0"); + + return RT_EOK; +} + diff --git a/bsp/lm3s/luminaryif.h b/bsp/lm3s/luminaryif.h new file mode 100644 index 0000000000..e987daea5e --- /dev/null +++ b/bsp/lm3s/luminaryif.h @@ -0,0 +1,12 @@ +//***************************************************************************** +// +// luminaryif.h - Prototypes for the Luminary Micro Ethernet interface. +// +//***************************************************************************** + +#ifndef __LUMINARYIF_H__ +#define __LUMINARYIF_H__ + +int rt_hw_luminaryif_init(void); + +#endif // __LUMINARYIF_H__ diff --git a/bsp/lm3s/project_lwip_dfs.Opt b/bsp/lm3s/project_lwip_dfs.Opt new file mode 100644 index 0000000000..5064201ddb --- /dev/null +++ b/bsp/lm3s/project_lwip_dfs.Opt @@ -0,0 +1,148 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (RT-Thread/LM3S), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Startup),1,0,0 +GRPOPT 2,(Kernel),0,0,0 +GRPOPT 3,(finsh),0,0,0 +GRPOPT 4,(LM3S),0,0,0 +GRPOPT 5,(driverlib),0,0,0 +GRPOPT 6,(Filesystem),0,0,0 +GRPOPT 7,(LwIP),1,0,0 +GRPOPT 8,(Utils),1,0,0 + +OPTFFF 1,1,1,201326592,0,0,0,0,<.\application.c> +OPTFFF 1,2,1,0,0,0,0,0,<.\board.c> +OPTFFF 1,3,1,234881024,0,132,141,0,<.\startup.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,44,0,0,0,58,0,0,0,214,2,0,0,38,1,0,0 } +OPTFFF 1,4,5,436207616,0,61,61,0,<.\rtconfig.h> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,22,0,0,0,29,0,0,0,192,2,0,0,9,1,0,0 } +OPTFFF 1,5,1,922746880,0,783,783,0,<.\sdcard.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,236,2,0,0,67,1,0,0 } +OPTFFF 1,6,1,738197504,0,1,1,0,<.\luminaryif.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,205,2,0,0,129,1,0,0 } +OPTFFF 2,7,1,0,0,0,0,0,<..\..\src\clock.c> +OPTFFF 2,8,1,0,0,0,0,0,<..\..\src\device.c> +OPTFFF 2,9,1,0,0,0,0,0,<..\..\src\idle.c> +OPTFFF 2,10,1,0,0,0,0,0,<..\..\src\ipc.c> +OPTFFF 2,11,1,0,0,0,0,0,<..\..\src\irq.c> +OPTFFF 2,12,1,0,0,0,0,0,<..\..\src\mem.c> +OPTFFF 2,13,1,0,0,0,0,0,<..\..\src\mempool.c> +OPTFFF 2,14,1,0,0,0,0,0,<..\..\src\object.c> +OPTFFF 2,15,1,0,0,0,0,0,<..\..\src\scheduler.c> +OPTFFF 2,16,1,0,0,0,0,0,<..\..\src\slab.c> +OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\thread.c> +OPTFFF 2,18,1,0,0,0,0,0,<..\..\src\timer.c> +OPTFFF 2,19,1,0,0,0,0,0,<..\..\src\kservice.c> +OPTFFF 3,20,1,0,0,0,0,0,<..\..\finsh\symbol.c> +OPTFFF 3,21,1,0,0,0,0,0,<..\..\finsh\cmd.c> +OPTFFF 3,22,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c> +OPTFFF 3,23,1,0,0,0,0,0,<..\..\finsh\finsh_error.c> +OPTFFF 3,24,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c> +OPTFFF 3,25,1,0,0,0,0,0,<..\..\finsh\finsh_init.c> +OPTFFF 3,26,1,0,0,0,0,0,<..\..\finsh\finsh_node.c> +OPTFFF 3,27,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c> +OPTFFF 3,28,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c> +OPTFFF 3,29,1,0,0,0,0,0,<..\..\finsh\finsh_token.c> +OPTFFF 3,30,1,0,0,0,0,0,<..\..\finsh\finsh_var.c> +OPTFFF 3,31,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c> +OPTFFF 3,32,1,0,0,0,0,0,<..\..\finsh\shell.c> +OPTFFF 4,33,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\cpu.c> +OPTFFF 4,34,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\interrupt.c> +OPTFFF 4,35,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\stack.c> +OPTFFF 4,36,2,0,0,0,0,0,<..\..\libcpu\arm\lm3s\context_rvds.S> +OPTFFF 4,37,2,0,0,0,0,0,<..\..\libcpu\arm\lm3s\start_rvds.S> +OPTFFF 4,38,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\serial.c> +OPTFFF 4,39,1,0,0,0,0,0,<..\..\libcpu\arm\lm3s\fault.c> +OPTFFF 4,40,2,0,0,0,0,0,<..\..\libcpu\arm\lm3s\fault_rvds.S> +OPTFFF 5,41,4,0,0,0,0,0,<.\driverlib\rvmdk\driverlib.lib> +OPTFFF 6,42,1,1,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c> +OPTFFF 6,43,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c> +OPTFFF 6,44,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c> +OPTFFF 6,45,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c> +OPTFFF 6,46,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c> +OPTFFF 6,47,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c> +OPTFFF 6,48,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c> +OPTFFF 6,49,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c> +OPTFFF 6,50,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c> +OPTFFF 6,51,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c> +OPTFFF 6,52,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c> +OPTFFF 6,53,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c> +OPTFFF 6,54,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c> +OPTFFF 6,55,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c> +OPTFFF 6,56,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c> +OPTFFF 6,57,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c> +OPTFFF 6,58,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c> +OPTFFF 7,59,1,1,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c> +OPTFFF 7,60,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c> +OPTFFF 7,61,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c> +OPTFFF 7,62,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c> +OPTFFF 7,63,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c> +OPTFFF 7,64,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c> +OPTFFF 7,65,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c> +OPTFFF 7,66,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c> +OPTFFF 7,67,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c> +OPTFFF 7,68,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c> +OPTFFF 7,69,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c> +OPTFFF 7,70,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c> +OPTFFF 7,71,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c> +OPTFFF 7,72,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c> +OPTFFF 7,73,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c> +OPTFFF 7,74,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c> +OPTFFF 7,75,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c> +OPTFFF 7,76,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c> +OPTFFF 7,77,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c> +OPTFFF 7,78,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c> +OPTFFF 7,79,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c> +OPTFFF 7,80,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c> +OPTFFF 7,81,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c> +OPTFFF 7,82,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c> +OPTFFF 7,83,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c> +OPTFFF 7,84,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c> +OPTFFF 7,85,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c> +OPTFFF 7,86,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c> +OPTFFF 7,87,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c> +OPTFFF 7,88,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c> +OPTFFF 7,89,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c> +OPTFFF 7,90,1,0,0,0,0,0,<..\..\net\lwip\src\netif\loopif.c> +OPTFFF 7,91,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c> +OPTFFF 7,92,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c> +OPTFFF 7,93,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c> +OPTFFF 7,94,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c> +OPTFFF 8,95,1,0,0,0,0,0,<..\..\net\apps\chargen.c> +OPTFFF 8,96,1,0,0,0,0,0,<..\..\net\apps\ftpd.c> +OPTFFF 8,97,1,0,0,0,0,0,<..\..\net\apps\sntp.c> +OPTFFF 8,98,1,0,0,0,0,0,<..\..\net\apps\tcpecho.c> +OPTFFF 8,99,1,486539264,0,83,87,0,<..\..\net\apps\tftp.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,22,0,0,0,29,0,0,0,161,2,0,0,71,1,0,0 } +OPTFFF 8,100,1,0,0,0,0,0,<..\..\net\apps\udpecho.c> + +ExtF 141,141,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,236,2,0,0,67,1,0,0 } +ExtF 83,91,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,170,2,0,0,236,0,0,0 } +ExtF 137,152,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,170,2,0,0,236,0,0,0 } + +TARGOPT 1, (RT-Thread/LM3S) + ADSCLK=6000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 0 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6918)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6918) + OPTDBG 49150,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)() + OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)) + OPTKEY 0,(JL2CM3)(-U -O14 -S0 -C-1 -JU1 -JI127.0.0.1 -JP0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TRE0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000) + OPTDF 0x80 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/bsp/lm3s/project_lwip_dfs.Uv2 b/bsp/lm3s/project_lwip_dfs.Uv2 new file mode 100644 index 0000000000..d0b45185e3 --- /dev/null +++ b/bsp/lm3s/project_lwip_dfs.Uv2 @@ -0,0 +1,206 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (RT-Thread/LM3S), 0x0004 // Tools: 'ARM-ADS' + +Group (Startup) +Group (Kernel) +Group (finsh) +Group (LM3S) +Group (driverlib) +Group (Filesystem) +Group (LwIP) +Group (Utils) + +File 1,1,<.\application.c> +File 1,1,<.\board.c> +File 1,1,<.\startup.c> +File 1,5,<.\rtconfig.h> +File 1,1,<.\sdcard.c> +File 1,1,<.\luminaryif.c> +File 2,1,<..\..\src\clock.c> +File 2,1,<..\..\src\device.c> +File 2,1,<..\..\src\idle.c> +File 2,1,<..\..\src\ipc.c> +File 2,1,<..\..\src\irq.c> +File 2,1,<..\..\src\mem.c> +File 2,1,<..\..\src\mempool.c> +File 2,1,<..\..\src\object.c> +File 2,1,<..\..\src\scheduler.c> +File 2,1,<..\..\src\slab.c> +File 2,1,<..\..\src\thread.c> +File 2,1,<..\..\src\timer.c> +File 2,1,<..\..\src\kservice.c> +File 3,1,<..\..\finsh\symbol.c> +File 3,1,<..\..\finsh\cmd.c> +File 3,1,<..\..\finsh\finsh_compiler.c> +File 3,1,<..\..\finsh\finsh_error.c> +File 3,1,<..\..\finsh\finsh_heap.c> +File 3,1,<..\..\finsh\finsh_init.c> +File 3,1,<..\..\finsh\finsh_node.c> +File 3,1,<..\..\finsh\finsh_ops.c> +File 3,1,<..\..\finsh\finsh_parser.c> +File 3,1,<..\..\finsh\finsh_token.c> +File 3,1,<..\..\finsh\finsh_var.c> +File 3,1,<..\..\finsh\finsh_vm.c> +File 3,1,<..\..\finsh\shell.c> +File 4,1,<..\..\libcpu\arm\lm3s\cpu.c> +File 4,1,<..\..\libcpu\arm\lm3s\interrupt.c> +File 4,1,<..\..\libcpu\arm\lm3s\stack.c> +File 4,2,<..\..\libcpu\arm\lm3s\context_rvds.S> +File 4,2,<..\..\libcpu\arm\lm3s\start_rvds.S> +File 4,1,<..\..\libcpu\arm\lm3s\serial.c> +File 4,1,<..\..\libcpu\arm\lm3s\fault.c> +File 4,2,<..\..\libcpu\arm\lm3s\fault_rvds.S> +File 5,4,<.\driverlib\rvmdk\driverlib.lib> +File 6,1,<..\..\filesystem\dfs\src\dfs_init.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_fs.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_raw.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_util.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_cache.c> +File 6,1,<..\..\filesystem\dfs\src\dfs_posix.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c> +File 6,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c> +File 7,1,<..\..\net\lwip\src\core\dhcp.c> +File 7,1,<..\..\net\lwip\src\core\dns.c> +File 7,1,<..\..\net\lwip\src\core\init.c> +File 7,1,<..\..\net\lwip\src\core\netif.c> +File 7,1,<..\..\net\lwip\src\core\pbuf.c> +File 7,1,<..\..\net\lwip\src\core\raw.c> +File 7,1,<..\..\net\lwip\src\core\stats.c> +File 7,1,<..\..\net\lwip\src\core\sys.c> +File 7,1,<..\..\net\lwip\src\core\tcp.c> +File 7,1,<..\..\net\lwip\src\core\tcp_in.c> +File 7,1,<..\..\net\lwip\src\core\tcp_out.c> +File 7,1,<..\..\net\lwip\src\core\udp.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\autoip.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\icmp.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\igmp.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\inet.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\inet_chksum.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\ip.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\ip_addr.c> +File 7,1,<..\..\net\lwip\src\core\ipv4\ip_frag.c> +File 7,1,<..\..\net\lwip\src\core\snmp\msg_in.c> +File 7,1,<..\..\net\lwip\src\core\snmp\msg_out.c> +File 7,1,<..\..\net\lwip\src\api\api_lib.c> +File 7,1,<..\..\net\lwip\src\api\api_msg.c> +File 7,1,<..\..\net\lwip\src\api\err.c> +File 7,1,<..\..\net\lwip\src\api\netbuf.c> +File 7,1,<..\..\net\lwip\src\api\netdb.c> +File 7,1,<..\..\net\lwip\src\api\netifapi.c> +File 7,1,<..\..\net\lwip\src\api\tcpip.c> +File 7,1,<..\..\net\lwip\src\netif\etharp.c> +File 7,1,<..\..\net\lwip\src\netif\ethernetif.c> +File 7,1,<..\..\net\lwip\src\netif\loopif.c> +File 7,1,<..\..\net\lwip\src\arch\sys_arch_init.c> +File 7,1,<..\..\net\lwip\src\arch\sys_arch.c> +File 7,1,<..\..\net\lwip\src\api\sockets.c> +File 7,1,<..\..\net\lwip\src\core\memp_tiny.c> +File 8,1,<..\..\net\apps\chargen.c> +File 8,1,<..\..\net\apps\ftpd.c> +File 8,1,<..\..\net\apps\sntp.c> +File 8,1,<..\..\net\apps\tcpecho.c> +File 8,1,<..\..\net\apps\tftp.c> +File 8,1,<..\..\net\apps\udpecho.c> + + +Options 1,0,0 // Target 'RT-Thread/LM3S' + Device (LM3S6918) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) + DevID (4722) + Rgf (LM3Sxxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (˙Luminary\) + OrgReg (˙Luminary\) + TgStat=16 + OutDir (.\obj\) + OutName (rtthread-lm3s) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + RVDEV () + ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } + OCMADSIROM { 1,0,0,0,0,0,0,4,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN () + ADSCUDEF () + ADSCINCD (.;.\inc;..\..\include;..\..\libcpu\arm\lm3s;..\..\finsh;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\net\lwip\src;..\..\net\lwip\src\include;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--keep __fsym_* --keep __vsym_*) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6918)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6918) + OPTDBG 49150,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()() + FLASH1 { 9,0,0,0,1,0,0,0,5,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (Segger\JL2CM3.dll) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/bsp/lm3s/rtconfig.h b/bsp/lm3s/rtconfig.h index 7e91069320..ace5102928 100644 --- a/bsp/lm3s/rtconfig.h +++ b/bsp/lm3s/rtconfig.h @@ -16,7 +16,7 @@ /* SECTION: RT_DEBUG */ /* Thread Debug*/ -#define RT_DEBUG +/* #define RT_DEBUG*/ /* #define RT_THREAD_DEBUG */ /* Using Hook*/ @@ -81,6 +81,7 @@ /* Using C++ support*/ /* #define RT_USING_CPLUSPLUS */ +#define RT_USING_DFS /* SECTION: DFS options */ /* the max number of mounted filesystem */ #define DFS_FILESYSTEMS_MAX 1 @@ -91,7 +92,7 @@ /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ -/* #define RT_USING_LWIP */ +#define RT_USING_LWIP /* Trace LwIP protocol*/ /* #define RT_LWIP_DEBUG */ @@ -108,12 +109,19 @@ /* Enable TCP protocol*/ #define RT_LWIP_TCP +/* the number of simulatenously active TCP connections*/ +#define RT_LWIP_TCP_PCB_NUM 5 + +/* TCP sender buffer space*/ +#define RT_LWIP_TCP_SND_BUF 1500 /* Enable SNMP protocol*/ /* #define RT_LWIP_SNMP */ /* Using DHCP*/ /* #define RT_LWIP_DHCP */ +#define RT_LWIP_DNS + /* ip address of target*/ #define RT_LWIP_IPADDR0 192 #define RT_LWIP_IPADDR1 168 @@ -132,4 +140,13 @@ #define RT_LWIP_MSKADDR2 255 #define RT_LWIP_MSKADDR3 0 +/* tcp thread options */ +#define RT_LWIP_TCPTHREAD_PRIORITY 22 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 + +/* ethernet if thread options */ +#define RT_LWIP_ETHTHREAD_PRIORITY 23 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #endif diff --git a/bsp/lm3s/sdcard.c b/bsp/lm3s/sdcard.c new file mode 100644 index 0000000000..7cc34f28c5 --- /dev/null +++ b/bsp/lm3s/sdcard.c @@ -0,0 +1,799 @@ +/*-----------------------------------------------------------------------*/ +/* MMC/SDC (in SPI mode) control module (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), disk_timerproc() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +/* + * This file was modified from a sample available from the FatFs + * web site. It was modified to work with a Luminary Micro + * EK-LM3S6965 evaluation board. + * + * Note that the SSI port is shared with the osram display. The code + * in this file does not attempt to share the SSI port with the osram, + * it assumes the osram is not being used. + */ + +#include "sdcard.h" +#include +#include +#include +#include +#include + + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ + +/* Peripheral definitions for EK-LM3S6965 board */ +// SSI port +#define SDC_SSI_BASE SSI0_BASE +#define SDC_SSI_SYSCTL_PERIPH SYSCTL_PERIPH_SSI0 + +// GPIO for SSI pins +#define SDC_GPIO_PORT_BASE GPIO_PORTA_BASE +#define SDC_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOA +#define SDC_SSI_CLK GPIO_PIN_2 +#define SDC_SSI_TX GPIO_PIN_5 +#define SDC_SSI_RX GPIO_PIN_4 +#define SDC_SSI_FSS GPIO_PIN_3 +#define SDC_SSI_PINS (SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK) + +// GPIO for card chip select +#define SDC_CS_GPIO_PORT_BASE GPIO_PORTD_BASE +#define SDC_CS_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOD +#define SDC_CS GPIO_PIN_0 + +// asserts the CS pin to the card +static +void SELECT (void) +{ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, 0); +} + +// de-asserts the CS pin to the card +static +void DESELECT (void) +{ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); +} + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + +static volatile +DSTATUS Stat = STA_NOINIT; /* Disk status */ + +static volatile +rt_uint8_t Timer1, Timer2; /* 100Hz decrement timer */ + +static +rt_uint8_t CardType; /* b0:MMC, b1:SDC, b2:Block addressing */ + +static +rt_uint8_t PowerFlag = 0; /* indicates if "power" is on */ + +/*-----------------------------------------------------------------------*/ +/* Transmit a byte to MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +void xmit_spi (rt_uint8_t dat) +{ + rt_uint32_t rcvdat; + + SSIDataPut(SDC_SSI_BASE, dat); /* Write the data to the tx fifo */ + + SSIDataGet(SDC_SSI_BASE, &rcvdat); /* flush data read during the write */ +} + + +/*-----------------------------------------------------------------------*/ +/* Receive a byte from MMC via SPI (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t rcvr_spi (void) +{ + rt_uint32_t rcvdat; + + SSIDataPut(SDC_SSI_BASE, 0xFF); /* write dummy data */ + + SSIDataGet(SDC_SSI_BASE, &rcvdat); /* read data frm rx fifo */ + + return (rt_uint8_t)rcvdat; +} + + +static +void rcvr_spi_m (rt_uint8_t *dst) +{ + *dst = rcvr_spi(); +} + +/*-----------------------------------------------------------------------*/ +/* Wait for card ready */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t wait_ready (void) +{ + rt_uint8_t res; + + + Timer2 = 50; /* Wait for ready in timeout of 500ms */ + rcvr_spi(); + do + res = rcvr_spi(); + while ((res != 0xFF) && Timer2); + + return res; +} + +/*-----------------------------------------------------------------------*/ +/* Send 80 or so clock transitions with CS and DI held high. This is */ +/* required after card power up to get it into SPI mode */ +/*-----------------------------------------------------------------------*/ +static +void send_initial_clock_train(void) +{ + unsigned int i; + rt_uint32_t dat; + + /* Ensure CS is held high. */ + DESELECT(); + + /* Switch the SSI TX line to a GPIO and drive it high too. */ + GPIOPinTypeGPIOOutput(SDC_GPIO_PORT_BASE, SDC_SSI_TX); + GPIOPinWrite(SDC_GPIO_PORT_BASE, SDC_SSI_TX, SDC_SSI_TX); + + /* Send 10 bytes over the SSI. This causes the clock to wiggle the */ + /* required number of times. */ + for(i = 0 ; i < 10 ; i++) + { + /* Write DUMMY data. SSIDataPut() waits until there is room in the */ + /* FIFO. */ + SSIDataPut(SDC_SSI_BASE, 0xFF); + + /* Flush data read during data write. */ + SSIDataGet(SDC_SSI_BASE, &dat); + } + + /* Revert to hardware control of the SSI TX line. */ + GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX); +} + +/*-----------------------------------------------------------------------*/ +/* Power Control (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* When the target system does not support socket power control, there */ +/* is nothing to do in these functions and chk_power always returns 1. */ + +static +void power_on (void) +{ + /* + * This doesn't really turn the power on, but initializes the + * SSI port and pins needed to talk to the card. + */ + + /* Enable the peripherals used to drive the SDC on SSI, and the CS */ + SysCtlPeripheralEnable(SDC_SSI_SYSCTL_PERIPH); + SysCtlPeripheralEnable(SDC_GPIO_SYSCTL_PERIPH); + SysCtlPeripheralEnable(SDC_CS_GPIO_SYSCTL_PERIPH); + + /* Configure the appropriate pins to be SSI instead of GPIO */ + GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_PINS); + GPIOPinTypeGPIOOutput(SDC_CS_GPIO_PORT_BASE, SDC_CS); + GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(SDC_CS_GPIO_PORT_BASE, SDC_CS, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + /* Deassert the SSI0 chip select */ + GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS); + + /* Configure the SSI0 port */ + SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, 400000, 8); + SSIEnable(SDC_SSI_BASE); + + /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */ + /* to be able to accept a native command. */ + send_initial_clock_train(); + + PowerFlag = 1; +} + +// set the SSI speed to the max setting +static +void set_max_speed(void) +{ + unsigned long i; + + /* Disable the SSI */ + SSIDisable(SDC_SSI_BASE); + + /* Set the maximum speed as half the system clock, with a max of 12.5 MHz. */ + i = SysCtlClockGet() / 2; + if(i > 12500000) + { + i = 12500000; + } + + /* Configure the SSI0 port */ + SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, i, 8); + + /* Enable the SSI */ + SSIEnable(SDC_SSI_BASE); +} + +static +void power_off (void) +{ + PowerFlag = 0; +} + +static +int chk_power(void) /* Socket power state: 0=off, 1=on */ +{ + return PowerFlag; +} + + + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from MMC */ +/*-----------------------------------------------------------------------*/ + +static +rt_bool_t rcvr_datablock ( + rt_uint8_t *buff, /* Data buffer to store received data */ + unsigned int btr /* Byte count (must be even number) */ +) +{ + rt_uint8_t token; + + + Timer1 = 10; + do { /* Wait for data packet in timeout of 100ms */ + token = rcvr_spi(); + } while ((token == 0xFF) && Timer1); + if(token != 0xFE) return RT_FALSE; /* If not valid data token, retutn with error */ + + do { /* Receive the data block into buffer */ + rcvr_spi_m(buff++); + rcvr_spi_m(buff++); + } while (btr -= 2); + rcvr_spi(); /* Discard CRC */ + rcvr_spi(); + + return RT_TRUE; /* Return with success */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to MMC */ +/*-----------------------------------------------------------------------*/ + +#if _READONLY == 0 +static +rt_bool_t xmit_datablock ( + const rt_uint8_t *buff, /* 512 byte data block to be transmitted */ + rt_uint8_t token /* Data/Stop token */ +) +{ + rt_uint8_t resp, wc; + + + if (wait_ready() != 0xFF) return RT_FALSE; + + xmit_spi(token); /* Xmit data token */ + if (token != 0xFD) { /* Is data token */ + wc = 0; + do { /* Xmit the 512 byte data block to MMC */ + xmit_spi(*buff++); + xmit_spi(*buff++); + } while (--wc); + xmit_spi(0xFF); /* CRC (Dummy) */ + xmit_spi(0xFF); + resp = rcvr_spi(); /* Reveive data response */ + if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ + return RT_FALSE; + } + + return RT_TRUE; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to MMC */ +/*-----------------------------------------------------------------------*/ + +static +rt_uint8_t send_cmd ( + rt_uint8_t cmd, /* Command byte */ + rt_uint32_t arg /* Argument */ +) +{ + rt_uint8_t n, res; + + + if (wait_ready() != 0xFF) return 0xFF; + + /* Send command packet */ + xmit_spi(cmd); /* Command */ + xmit_spi((rt_uint8_t)(arg >> 24)); /* Argument[31..24] */ + xmit_spi((rt_uint8_t)(arg >> 16)); /* Argument[23..16] */ + xmit_spi((rt_uint8_t)(arg >> 8)); /* Argument[15..8] */ + xmit_spi((rt_uint8_t)arg); /* Argument[7..0] */ + n = 0; + if (cmd == CMD0) n = 0x95; /* CRC for CMD0(0) */ + if (cmd == CMD8) n = 0x87; /* CRC for CMD8(0x1AA) */ + xmit_spi(n); + + /* Receive command response */ + if (cmd == CMD12) rcvr_spi(); /* Skip a stuff byte when stop reading */ + n = 10; /* Wait for a valid response in timeout of 10 attempts */ + do + res = rcvr_spi(); + while ((res & 0x80) && --n); + + return res; /* Return with the response value */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Initialize Disk Drive */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_initialize ( + rt_uint8_t drv /* Physical drive nmuber (0) */ +) +{ + rt_uint8_t n, ty, ocr[4]; + + + if (drv) return STA_NOINIT; /* Supports only single drive */ + if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + + power_on(); /* Force socket power on */ + send_initial_clock_train(); + + SELECT(); /* CS = L */ + ty = 0; + if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ + Timer1 = 100; /* Initialization timeout of 1000 msec */ + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDC Ver2+ */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ + do { + if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0) break; /* ACMD41 with HCS bit */ + } while (Timer1); + if (Timer1 && send_cmd(CMD58, 0) == 0) { /* Check CCS bit */ + for (n = 0; n < 4; n++) ocr[n] = rcvr_spi(); + ty = (ocr[0] & 0x40) ? 6 : 2; + } + } + } else { /* SDC Ver1 or MMC */ + ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1; /* SDC : MMC */ + do { + if (ty == 2) { + if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break; /* ACMD41 */ + } else { + if (send_cmd(CMD1, 0) == 0) break; /* CMD1 */ + } + } while (Timer1); + if (!Timer1 || send_cmd(CMD16, 512) != 0) /* Select R/W block length */ + ty = 0; + } + } + CardType = ty; + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + if (ty) { /* Initialization succeded */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + set_max_speed(); + } else { /* Initialization failed */ + power_off(); + } + + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Get Disk Status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status ( + rt_uint8_t drv /* Physical drive nmuber (0) */ +) +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_read ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + rt_uint8_t *buff, /* Pointer to the data buffer to store read data */ + rt_uint32_t sector, /* Start sector number (LBA) */ + rt_uint8_t count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + + if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ + + SELECT(); /* CS = L */ + + if (count == 1) { /* Single block read */ + if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ + && rcvr_datablock(buff, 512)) + count = 0; + } + else { /* Multiple block read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) break; + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + return count ? RES_ERROR : RES_OK; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ +/*-----------------------------------------------------------------------*/ + +#if _READONLY == 0 +DRESULT disk_write ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + const rt_uint8_t *buff, /* Pointer to the data to be written */ + rt_uint32_t sector, /* Start sector number (LBA) */ + rt_uint8_t count /* Sector count (1..255) */ +) +{ + if (drv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + + if (!(CardType & 4)) sector *= 512; /* Convert to byte address if needed */ + + SELECT(); /* CS = L */ + + if (count == 1) { /* Single block write */ + if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ + && xmit_datablock(buff, 0xFE)) + count = 0; + } + else { /* Multiple block write */ + if (CardType & 2) { + send_cmd(CMD55, 0); send_cmd(CMD23, count); /* ACMD23 */ + } + if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ + do { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + count = 1; + } + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + + return count ? RES_ERROR : RES_OK; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_ioctl ( + rt_uint8_t drv, /* Physical drive nmuber (0) */ + rt_uint8_t ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + rt_uint8_t n, csd[16], *ptr = buff; + rt_uint16_t csize; + + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (ctrl == CTRL_POWER) { + switch (*ptr) { + case 0: /* Sub control code == 0 (POWER_OFF) */ + if (chk_power()) + power_off(); /* Power off */ + res = RES_OK; + break; + case 1: /* Sub control code == 1 (POWER_ON) */ + power_on(); /* Power on */ + res = RES_OK; + break; + case 2: /* Sub control code == 2 (POWER_GET) */ + *(ptr+1) = (rt_uint8_t)chk_power(); + res = RES_OK; + break; + default : + res = RES_PARERR; + } + } + else { + if (Stat & STA_NOINIT) return RES_NOTRDY; + + SELECT(); /* CS = L */ + + switch (ctrl) { + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (rt_uint32_t) */ + if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { + if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ + csize = csd[9] + ((rt_uint16_t)csd[8] << 8) + 1; + *(rt_uint32_t*)buff = (rt_uint32_t)csize << 10; + } else { /* MMC or SDC ver 1.XX */ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((rt_uint16_t)csd[7] << 2) + ((rt_uint16_t)(csd[6] & 3) << 10) + 1; + *(rt_uint32_t*)buff = (rt_uint32_t)csize << (n - 9); + } + res = RES_OK; + } + break; + + case GET_SECTOR_SIZE : /* Get sectors on the disk (rt_uint16_t) */ + *(rt_uint16_t*)buff = 512; + res = RES_OK; + break; + + case CTRL_SYNC : /* Make sure that data has been written */ + if (wait_ready() == 0xFF) + res = RES_OK; + break; + + case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 0; n < 4; n++) + *ptr++ = rcvr_spi(); + res = RES_OK; + } + +// case MMC_GET_TYPE : /* Get card type flags (1 byte) */ +// *ptr = CardType; +// res = RES_OK; +// break; + + default: + res = RES_PARERR; + } + + DESELECT(); /* CS = H */ + rcvr_spi(); /* Idle (Release DO) */ + } + + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Device Timer Interrupt Procedure (Platform dependent) */ +/*-----------------------------------------------------------------------*/ +/* This function must be called in period of 10ms */ + +void disk_timerproc (void) +{ +// rt_uint8_t n, s; + rt_uint8_t n; + + + n = Timer1; /* 100Hz decrement timer */ + if (n) Timer1 = --n; + n = Timer2; + if (n) Timer2 = --n; + +} + +/*---------------------------------------------------------*/ +/* User Provided Timer Function for FatFs module */ +/*---------------------------------------------------------*/ +/* This is a real time clock service to be called from */ +/* FatFs module. Any valid time must be returned even if */ +/* the system does not support a real time clock. */ + +rt_uint32_t get_fattime (void) +{ + + return ((2007UL-1980) << 25) // Year = 2007 + | (6UL << 21) // Month = June + | (5UL << 16) // Day = 5 + | (11U << 11) // Hour = 11 + | (38U << 5) // Min = 38 + | (0U >> 1) // Sec = 0 + ; + +} + +/* + * RT-Thread SD Card Driver + * 20090705 Yi.Qiu + */ +#include +#include + +struct rt_device sdcard_device; +struct dfs_partition part; + +/* RT-Thread Device Driver Interface */ +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + return RT_EOK; +} + +/* set sector size to 512 */ +#define SECTOR_SIZE 512 +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + DRESULT status; + + status = disk_read(0, buffer, part.offset + pos / SECTOR_SIZE, size / SECTOR_SIZE); + if (status != RES_OK) + { + rt_kprintf("sd card read failed\n"); + return 0; + } + + return size; +} + +static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + DRESULT status; + + status = disk_write(0, buffer, part.offset + pos / SECTOR_SIZE, size / SECTOR_SIZE); + if (status != RES_OK) + { + rt_kprintf("sd card write failed\n"); + return 0; + } + + return size; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +void rt_hw_sdcard_init() +{ + if (disk_initialize(0) == RES_OK) + { + DRESULT status; + rt_uint8_t *sector; + + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } + status = disk_read(0, sector, 0, 1); + if (status == RES_OK) + { + /* get the first partition */ + if (dfs_filesystem_get_partition(&part, sector, 0) != 0) + { + /* there is no partition */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + /* release sector buffer */ + rt_free(sector); + + /* register sdcard device */ + sdcard_device.init = rt_sdcard_init; + sdcard_device.open = rt_sdcard_open; + sdcard_device.close = rt_sdcard_close; + sdcard_device.read = rt_sdcard_read; + sdcard_device.write = rt_sdcard_write; + sdcard_device.control = rt_sdcard_control; + + /* no private */ + sdcard_device.private = RT_NULL; + + rt_device_register(&sdcard_device, "sd0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + return; + } + rt_kprintf("sdcard init failed\n"); +} + diff --git a/bsp/lm3s/sdcard.h b/bsp/lm3s/sdcard.h new file mode 100644 index 0000000000..64d99e7f99 --- /dev/null +++ b/bsp/lm3s/sdcard.h @@ -0,0 +1,60 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file R0.04a (C)ChaN, 2007 +/-----------------------------------------------------------------------*/ + +#ifndef __SDCARD_H__ +#define __SDCARD_H__ + +#define _READONLY 0 /* 1: Read-only mode */ + +#include + + +/* Status of Disk Functions */ +typedef rt_uint8_t DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +DSTATUS disk_initialize (rt_uint8_t); +DSTATUS disk_status (rt_uint8_t); +DRESULT disk_read (rt_uint8_t, rt_uint8_t*, rt_uint32_t, rt_uint8_t); +#if _READONLY == 0 +DRESULT disk_write (rt_uint8_t, const rt_uint8_t*, rt_uint32_t, rt_uint8_t); +#endif +DRESULT disk_ioctl (rt_uint8_t, rt_uint8_t, void*); +void disk_timerproc (void); + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl() */ + +#define GET_SECTOR_COUNT 1 +#define GET_SECTOR_SIZE 2 +#define CTRL_SYNC 3 +#define CTRL_POWER 4 +#define CTRL_LOCK 5 +#define CTRL_EJECT 6 +#define MMC_GET_CSD 10 +#define MMC_GET_CID 11 +#define MMC_GET_OCR 12 +#define ATA_GET_REV 20 +#define ATA_GET_MODEL 21 +#define ATA_GET_SN 22 + +#endif diff --git a/bsp/lm3s/startup.c b/bsp/lm3s/startup.c index 5a27b553d6..cf2d45ac03 100644 --- a/bsp/lm3s/startup.c +++ b/bsp/lm3s/startup.c @@ -19,8 +19,8 @@ /** * @addtogroup LM3S - */ - + */ + extern void rt_hw_serial_init(void); /*@{*/ @@ -81,20 +81,26 @@ void rtthread_startup(void) rt_system_timer_init(); #ifdef RT_USING_HEAP - /* STM32F103VB has 20k SRAM, the end address of SRAM is 0x20005000 */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20005000); + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20010000); #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)0x20005000); + rt_system_heap_init(__segment_end("HEAP"), (void*)0x20010000); #else /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)0x20005000); + rt_system_heap_init((void*)&__bss_end, (void*)0x20010000); #endif #endif /* init scheduler system */ rt_system_scheduler_init(); +#ifdef RT_USING_LWIP + eth_system_device_init(); + + /* register ethernetif device */ + rt_hw_luminaryif_init(); +#endif + /* init hardware serial device */ rt_hw_serial_init(); #ifdef RT_USING_DFS