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update update stm32f40x bsp 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1775 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong 2011-10-27 02:40:15 +00:00
parent a5f688d282
commit b1531d316d
23 changed files with 941 additions and 7088 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

282
bsp/stm32f40x/Libraries/SConscript
View File

@ -1,254 +1,14 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
dsp_src = Split('''
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
''')
# The set of source files associated with this SConscript file.
src = Split("""
CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s
STM32F4xx_StdPeriph_Driver/src/misc.c
STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
@ -282,24 +42,30 @@ STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
""")
# starupt scripts for STM32F4xx
startup_scripts = 'startup_stm32f4xx.s'
# starupt scripts for each STM32 kind
# startup_scripts = {}
# startup_scripts['STM32F10X_CL'] = 'startup_stm32f10x_cl.s'
# startup_scripts['STM32F10X_HD'] = 'startup_stm32f10x_hd.s'
# startup_scripts['STM32F10X_HD_VL'] = 'startup_stm32f10x_hd_vl.s'
# startup_scripts['STM32F10X_LD'] = 'startup_stm32f10x_ld.s'
# startup_scripts['STM32F10X_LD_VL'] = 'startup_stm32f10x_ld_vl.s'
# startup_scripts['STM32F10X_MD'] = 'startup_stm32f10x_md.s'
# startup_scripts['STM32F10X_MD_VL'] = 'startup_stm32f10x_md_vl.s'
# startup_scripts['STM32F10X_XL'] = 'startup_stm32f10x_xl.s'
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/' + startup_scripts]
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/arm/' + startup_scripts]
elif rtconfig.CROSS_TOOL == 'iar':
src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/iar/' + startup_scripts]
#add for startup script
# if rtconfig.CROSS_TOOL == 'gcc':
# src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/' + startup_scripts[rtconfig.STM32_TYPE]]
# elif rtconfig.CROSS_TOOL == 'keil':
# src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/' + startup_scripts[rtconfig.STM32_TYPE]]
# elif rtconfig.CROSS_TOOL == 'iar':
# src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/' + startup_scripts[rtconfig.STM32_TYPE]]
path = [cwd + '/STM32F4xx_StdPeriph_Driver/inc',
cwd + '/CMSIS/Include',
cwd + '/CMSIS/ST/STM32F4xx/Include']
path = [cwd + '/STM32F4xx_StdPeriph_Driver/inc',
cwd + '/CMSIS/ST/STM32F4xx/Include',
cwd + '/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
src = src + dsp_src
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'ARM_MATH_CM4', 'ARM_MATH_MATRIX_CHECK', 'ARM_MATH_ROUNDING', 'ARM_MATH_BIG_ENDIAN', '__FPU_PRESENT=1']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

18
bsp/stm32f40x/SConscript
View File

@ -1,10 +1,14 @@
from building import *
# for module compiling
import os
Import('RTT_ROOT')
src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f4xx_it.c']
src_drv = ['usart.c', 'serial.c']
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
src = src_bsp + src_drv
CPPPATH = [GetCurrentDir()]
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('group')
Return('objs')

13
bsp/stm32f40x/SConstruct
View File

@ -3,10 +3,11 @@ import sys
import rtconfig
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-stm32.' + rtconfig.TARGET_EXT
TARGET = 'rtthread-stm32f4xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
@ -15,19 +16,11 @@ env = Environment(tools = ['mingw'],
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# STM32 firemare library building script
objs = objs + SConscript('Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# build program
env.Program(TARGET, objs)

96
bsp/stm32f40x/application.c
View File

@ -1,96 +0,0 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
*/
/**
* @addtogroup STM32
*/
/*@{*/
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_DFS
/* dfs init */
#include <dfs_init.h>
/* dfs filesystem:ELM filesystem init */
#include <dfs_elm.h>
/* dfs Filesystem APIs */
#include <dfs_fs.h>
#endif
#ifdef RT_USING_LWIP
#include <lwip/sys.h>
#include <lwip/api.h>
#include <netif/ethernetif.h>
#endif
void rt_init_thread_entry(void* parameter)
{
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
/* init the device filesystem */
dfs_init();
#ifdef RT_USING_DFS_ELMFAT
/* init the elm chan FatFs filesystam*/
elm_init();
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
rt_kprintf("File System initialzation failed!\n");
#endif
}
#endif
/* LwIP Initialization */
#ifdef RT_USING_LWIP
{
extern void lwip_sys_init(void);
/* register ethernetif device */
eth_system_device_init();
/* initialize eth interface */
rt_hw_stm32_eth_init();
/* re-init device driver */
rt_device_init_all();
/* init lwip system */
lwip_sys_init();
rt_kprintf("TCP/IP initialized!\n");
}
#endif
}
int rt_application_init()
{
rt_thread_t tid;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
/*@}*/

90
bsp/stm32f40x/board.c
View File

@ -1,90 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "usart.h"
/**
* @addtogroup STM32
*/
/*@{*/
/*******************************************************************************
* Function Name : NVIC_Configuration
* Description : Configures Vector Table base location.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_Configuration(void)
{
}
/*******************************************************************************
* Function Name : SysTick_Configuration
* Description : Configures the SysTick for OS tick.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SysTick_Configuration(void)
{
RCC_ClocksTypeDef rcc_clocks;
rt_uint32_t cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial STM32 board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the SysTick */
SysTick_Configuration();
rt_hw_usart_init();
#ifdef RT_USING_CONSOLE
rt_console_set_device(CONSOLE_DEVICE);
#endif
}
/*@}*/

66
bsp/stm32f40x/board.h
View File

@ -1,66 +0,0 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
*/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef __BOARD_H__
#define __BOARD_H__
#include <stm32f4xx.h>
/* board configuration */
// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
// <i>Default: 1
#define STM32_USE_SDIO 1
/* whether use board external SRAM memory */
// <e>Use external SRAM memory on the board
// <i>Enable External SRAM memory
#define STM32_EXT_SRAM 0
// <o>Begin Address of External SRAM
// <i>Default: 0x68000000
#define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */
// <o>End Address of External SRAM
// <i>Default: 0x68080000
#define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */
// </e>
// <o> Internal SRAM memory size[Kbytes] <8-128>
// <i>Default: 64
#define STM32_SRAM_SIZE 192
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
// <i>Default: 1
#define STM32_CONSOLE_USART 1
// <o> Ethernet Interface: <0=> Microchip ENC28J60
#define STM32_ETH_IF 0
void rt_hw_board_led_on(int n);
void rt_hw_board_led_off(int n);
void rt_hw_board_init(void);
#if STM32_CONSOLE_USART == 0
#define CONSOLE_DEVICE "no"
#elif STM32_CONSOLE_USART == 1
#define CONSOLE_DEVICE "uart1"
#elif STM32_CONSOLE_USART == 2
#define CONSOLE_DEVICE "uart2"
#elif STM32_CONSOLE_USART == 3
#define CONSOLE_DEVICE "uart3"
#endif
#endif
// <<< Use Configuration Wizard in Context Menu >>>

4
bsp/stm32f40x/drivers/board.h
View File

@ -16,6 +16,8 @@
#ifndef __BOARD_H__
#define __BOARD_H__
#include <stm32f4xx.h>
/* board configuration */
// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
// <i>Default: 1
@ -35,7 +37,7 @@
// <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64
#define STM32_SRAM_SIZE 64
#define STM32_SRAM_SIZE 128
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
#define RT_USING_UART2

9
bsp/stm32f40x/drivers/serial.c
View File

@ -16,9 +16,8 @@
*/
#include "serial.h"
#include "stm32f4xx.h"
//#include <stm32f10x_dma.h>
//#include <stm32f10x_usart.h>
#include <stm32f4xx_dma.h>
#include <stm32f4xx_usart.h>
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size);
@ -146,9 +145,9 @@ static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
DMA_Cmd(dma_channel, DISABLE);
/* set buffer address */
// dma_channel->CMAR = address;
dma_channel->M0AR = address;
/* set size */
// dma_channel->CNDTR = size;
dma_channel->NDTR = size;
/* enable DMA */
DMA_Cmd(dma_channel, ENABLE);

8
bsp/stm32f40x/drivers/serial.h
View File

@ -18,11 +18,10 @@
#include <rthw.h>
#include <rtthread.h>
/* STM32F10x library definitions */
#include "stm32f4xx.h"
//#include <stm32f10x.h>
/* STM32F40x library definitions */
#include <stm32f4xx.h>
#define UART_RX_BUFFER_SIZE 128
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_DMA_NODE_SIZE 4
/* data node for Tx Mode */
@ -35,7 +34,6 @@ struct stm32_serial_data_node
struct stm32_serial_dma_tx
{
/* DMA Channel */
// DMA_Channel_TypeDef* dma_channel;
DMA_Stream_TypeDef* dma_channel;
/* data list head and tail */

16
bsp/stm32f40x/drivers/usart.c
View File

@ -230,7 +230,6 @@ volatile USART_TypeDef * uart2_debug = USART2;
void rt_hw_usart_init()
{
USART_InitTypeDef USART_InitStructure;
USART_ClockInitTypeDef USART_ClockInitStructure;
RCC_Configuration();
@ -248,12 +247,7 @@ void rt_hw_usart_init()
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
USART_Init(USART1, &USART_InitStructure);
USART_ClockInit(USART1, &USART_ClockInitStructure);
/* register uart1 */
rt_hw_serial_register(&uart1_device, "uart1",
@ -271,12 +265,7 @@ void rt_hw_usart_init()
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
USART_Init(USART2, &USART_InitStructure);
USART_ClockInit(USART2, &USART_ClockInitStructure);
/* register uart2 */
rt_hw_serial_register(&uart2_device, "uart2",
@ -294,12 +283,7 @@ void rt_hw_usart_init()
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
USART_Init(USART3, &USART_InitStructure);
USART_ClockInit(USART3, &USART_ClockInitStructure);
uart3_dma_tx.dma_channel= UART3_TX_DMA;

4596
bsp/stm32f40x/project.uvopt
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File diff suppressed because it is too large Load Diff

1500
bsp/stm32f40x/project.uvproj
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File diff suppressed because it is too large Load Diff

34
bsp/stm32f40x/rtconfig.h
View File

@ -3,7 +3,7 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
@ -17,13 +17,14 @@
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_THREAD_DEBUG
#define RT_USING_OVERFLOW_CHECK
/* Using Hook */
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 1024
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
@ -59,7 +60,6 @@
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
#define RT_USING_UART1
/* SECTION: Console options */
#define RT_USING_CONSOLE
@ -74,14 +74,19 @@
/* SECTION: device filesystem */
/* #define RT_USING_DFS */
#define RT_USING_DFS_ELMFAT
#define RT_DFS_ELM_REENTRANT
//#define RT_USING_DFS_ELMFAT
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_DRIVES 1
#define RT_DFS_ELM_USE_LFN 2
/* Reentrancy (thread safe) of the FatFs module. */
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 2
/* #define RT_DFS_ELM_USE_LFN 1 */
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_USING_DFS_ROMFS
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
@ -107,7 +112,7 @@
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_IPADDR3 201
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
@ -131,4 +136,17 @@
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF 8192
/* TCP receive window. */
#define RT_LWIP_TCP_WND 8192
#define CHECKSUM_CHECK_TCP 0
#define CHECKSUM_CHECK_IP 0
#define CHECKSUM_CHECK_UDP 0
#define CHECKSUM_GEN_TCP 0
#define CHECKSUM_GEN_IP 0
#define CHECKSUM_GEN_UDP 0
#endif

16
bsp/stm32f40x/rtconfig.py
View File

@ -3,17 +3,21 @@ ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='keil'
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'E:/SourceryGCC/bin'
EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'E:/Keil'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
IAR_PATH = 'E:/Program Files/IAR Systems/Embedded Workbench 5.4 Evaluation_0'
IAR_PATH = 'E:/Program Files/IAR Systems/Embedded Workbench 6.0'
#
BUILD = 'debug'
STM32_TYPE = 'STM32F4XX'
if PLATFORM == 'gcc':
# toolchains
@ -77,7 +81,7 @@ elif PLATFORM == 'iar':
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' -D USE_STDPERIPH_DRIVER'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
@ -95,6 +99,7 @@ elif PLATFORM == 'iar':
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
@ -103,8 +108,9 @@ elif PLATFORM == 'iar':
AFLAGS += ' --cpu Cortex-M3'
AFLAGS += ' --fpu None'
LFLAGS = ' --config stm32_rom.icf'
LFLAGS += ' --semihosting'
LFLAGS = ' --config stm32f10x_flash.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = IAR_PATH + '/arm/bin/'

418
bsp/stm32f40x/serial.c
View File

@ -1,418 +0,0 @@
/*
* File : serial.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-02-05 Bernard first version
* 2009-10-25 Bernard fix rt_serial_read bug when there is no data
* in the buffer.
* 2010-03-29 Bernard cleanup code.
*/
#include "serial.h"
#include <stm32f4xx_dma.h>
#include <stm32f4xx_usart.h>
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size);
/**
* @addtogroup STM32
*/
/*@{*/
/* RT-Thread Device Interface */
static rt_err_t rt_serial_init (rt_device_t dev)
{
struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
rt_memset(uart->int_rx->rx_buffer, 0,
sizeof(uart->int_rx->rx_buffer));
uart->int_rx->read_index = 0;
uart->int_rx->save_index = 0;
}
if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
/* init data node memory pool */
rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
uart->dma_tx->data_node_mem_pool,
sizeof(uart->dma_tx->data_node_mem_pool),
sizeof(struct stm32_serial_data_node));
}
/* Enable USART */
USART_Cmd(uart->uart_device, ENABLE);
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
}
return RT_EOK;
}
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
struct stm32_serial_device* uart;
ptr = buffer;
err_code = RT_EOK;
uart = (struct stm32_serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* interrupt mode Rx */
while (size)
{
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->int_rx->read_index != uart->int_rx->save_index)
{
/* read a character */
*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
size--;
/* move to next position */
uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0;
}
else
{
/* set error code */
err_code = -RT_EEMPTY;
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
}
else
{
/* polling mode */
while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
{
while (uart->uart_device->SR & USART_FLAG_RXNE)
{
*ptr = uart->uart_device->DR & 0xff;
ptr ++;
}
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size)
{
RT_ASSERT(dma_channel != RT_NULL);
/* disable DMA */
DMA_Cmd(dma_channel, DISABLE);
/* set buffer address */
dma_channel->M0AR = address;
/* set size */
dma_channel->NDTR = size;
/* enable DMA */
DMA_Cmd(dma_channel, ENABLE);
}
static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
struct stm32_serial_device* uart;
err_code = RT_EOK;
ptr = (rt_uint8_t*)buffer;
uart = (struct stm32_serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* interrupt mode Tx, does not support */
RT_ASSERT(0);
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
/* DMA mode Tx */
/* allocate a data node */
struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
if (data_node == RT_NULL)
{
/* set error code */
err_code = -RT_ENOMEM;
}
else
{
rt_uint32_t level;
/* fill data node */
data_node->data_ptr = ptr;
data_node->data_size = size;
/* insert to data link */
data_node->next = RT_NULL;
/* disable interrupt */
level = rt_hw_interrupt_disable();
data_node->prev = uart->dma_tx->list_tail;
if (uart->dma_tx->list_tail != RT_NULL)
uart->dma_tx->list_tail->next = data_node;
uart->dma_tx->list_tail = data_node;
if (uart->dma_tx->list_head == RT_NULL)
{
/* start DMA to transmit data */
uart->dma_tx->list_head = data_node;
/* Enable DMA Channel */
rt_serial_enable_dma(uart->dma_tx->dma_channel,
(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
uart->dma_tx->list_head->data_size);
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
}
else
{
/* polling mode */
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = '\r';
}
while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = (*ptr & 0x1FF);
++ptr; --size;
}
}
else
{
/* write data directly */
while (size)
{
while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = (*ptr & 0x1FF);
++ptr; --size;
}
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
{
struct stm32_serial_device* uart;
RT_ASSERT(dev != RT_NULL);
uart = (struct stm32_serial_device*)dev->user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
USART_Cmd(uart->uart_device, DISABLE);
break;
case RT_DEVICE_CTRL_RESUME:
/* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
USART_Cmd(uart->uart_device, ENABLE);
break;
}
return RT_EOK;
}
/*
* serial register for STM32
* support STM32F103VB and STM32F103ZE
*/
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
{
RT_ASSERT(device != RT_NULL);
if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
(flag & RT_DEVICE_FLAG_INT_TX))
{
RT_ASSERT(0);
}
device->type = RT_Device_Class_Char;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_serial_init;
device->open = rt_serial_open;
device->close = rt_serial_close;
device->read = rt_serial_read;
device->write = rt_serial_write;
device->control = rt_serial_control;
device->user_data = serial;
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/* ISR for serial interrupt */
void rt_hw_serial_isr(rt_device_t device)
{
struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{
/* interrupt mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
/* save on rx buffer */
while (uart->uart_device->SR & USART_FLAG_RXNE)
{
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* save character */
uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
uart->int_rx->save_index ++;
if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->save_index = 0;
/* if the next position is read index, discard this 'read char' */
if (uart->int_rx->save_index == uart->int_rx->read_index)
{
uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
/* invoke callback */
if (device->rx_indicate != RT_NULL)
{
rt_size_t rx_length;
/* get rx length */
rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
uart->int_rx->save_index - uart->int_rx->read_index;
device->rx_indicate(device, rx_length);
}
}
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
}
}
/*
* ISR for DMA mode Tx
*/
void rt_hw_serial_dma_tx_isr(rt_device_t device)
{
rt_uint32_t level;
struct stm32_serial_data_node* data_node;
struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
/* DMA mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
/* get the first data node */
data_node = uart->dma_tx->list_head;
RT_ASSERT(data_node != RT_NULL);
/* invoke call to notify tx complete */
if (device->tx_complete != RT_NULL)
device->tx_complete(device, data_node->data_ptr);
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* remove list head */
uart->dma_tx->list_head = data_node->next;
if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
uart->dma_tx->list_tail = RT_NULL;
/* enable interrupt */
rt_hw_interrupt_enable(level);
/* release data node memory */
rt_mp_free(data_node);
if (uart->dma_tx->list_head != RT_NULL)
{
/* transmit next data node */
rt_serial_enable_dma(uart->dma_tx->dma_channel,
(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
uart->dma_tx->list_head->data_size);
}
else
{
/* no data to be transmitted, disable DMA */
DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
}
}
/*@}*/

70
bsp/stm32f40x/serial.h
View File

@ -1,70 +0,0 @@
/*
* File : serial.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first version
* 2010-03-29 Bernard remove interrupt tx and DMA rx mode.
*/
#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
/* STM32F40x library definitions */
#include <stm32f4xx.h>
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_DMA_NODE_SIZE 4
/* data node for Tx Mode */
struct stm32_serial_data_node
{
rt_uint8_t *data_ptr;
rt_size_t data_size;
struct stm32_serial_data_node *next, *prev;
};
struct stm32_serial_dma_tx
{
/* DMA Channel */
DMA_Stream_TypeDef* dma_channel;
/* data list head and tail */
struct stm32_serial_data_node *list_head, *list_tail;
/* data node memory pool */
struct rt_mempool data_node_mp;
rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
(sizeof(struct stm32_serial_data_node) + sizeof(void*))];
};
struct stm32_serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct stm32_serial_device
{
USART_TypeDef* uart_device;
/* rx structure */
struct stm32_serial_int_rx* int_rx;
/* tx structure */
struct stm32_serial_dma_tx* dma_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
void rt_hw_serial_dma_tx_isr(rt_device_t device);
#endif

147
bsp/stm32f40x/startup.c
View File

@ -1,147 +0,0 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include <stm32f4xx.h>
#include "board.h"
/**
* @addtogroup STM32
*/
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern void finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#elif __ICCARM__
#pragma section="HEAP"
#else
extern int __bss_end;
#endif
#ifdef DEBUG
/*******************************************************************************
* Function Name : assert_failed
* Description : Reports the name of the source file and the source line number
* where the assert error has occurred.
* Input : - file: pointer to the source file name
* - line: assert error line source number
* Output : None
* Return : None
*******************************************************************************/
void assert_failed(u8* file, u32 line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
}
#endif
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
#if STM32_EXT_SRAM
rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
#else
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
#else
/* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END);
#endif
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DFS
/* init sdcard driver */
#if STM32_USE_SDIO
rt_hw_sdcard_init();
#else
rt_hw_msd_init();
#endif
#endif
/* init all device */
rt_device_init_all();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device(CONSOLE_DEVICE);
#endif
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* init system setting */
SystemInit();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
/*@}*/

94
bsp/stm32f40x/stm32f4xx_conf.h
View File

@ -1,94 +0,0 @@
/**
******************************************************************************
* @file IO_Toggle/stm32f4xx_conf.h
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @brief Library configuration file.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_CONF_H
#define __STM32F4xx_CONF_H
#if defined (HSE_VALUE)
/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
#undef HSE_VALUE
#define HSE_VALUE ((uint32_t)8000000)
#endif /* HSE_VALUE */
/* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */
#include "stm32f4xx_adc.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_crc.h"
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dbgmcu.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma.h"
#include "stm32f4xx_exti.h"
#include "stm32f4xx_flash.h"
#include "stm32f4xx_fsmc.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_i2c.h"
#include "stm32f4xx_iwdg.h"
#include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_rtc.h"
#include "stm32f4xx_sdio.h"
#include "stm32f4xx_spi.h"
#include "stm32f4xx_syscfg.h"
#include "stm32f4xx_tim.h"
#include "stm32f4xx_usart.h"
#include "stm32f4xx_wwdg.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* If an external clock source is used, then the value of the following define
should be set to the value of the external clock source, else, if no external
clock is used, keep this define commented */
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* __STM32F4xx_CONF_H */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

136
bsp/stm32f40x/stm32f4xx_it.c
View File

@ -1,136 +0,0 @@
/**
******************************************************************************
* @file IO_Toggle/stm32f4xx_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_it.h"
/** @addtogroup STM32F4_Discovery_Peripheral_Examples
* @{
*/
/** @addtogroup IO_Toggle
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M4 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/******************************************************************************/
/* STM32F4xx Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles PPP interrupt request.
* @param None
* @retval None
*/
/*void PPP_IRQHandler(void)
{
}*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

54
bsp/stm32f40x/stm32f4xx_it.h
View File

@ -1,54 +0,0 @@
/**
******************************************************************************
* @file GPIO/IOToggle/stm32f4xx_it.h
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

58
bsp/stm32f40x/template.uvproj
View File

@ -7,19 +7,19 @@
<Targets>
<Target>
<TargetName>RT-Thread STM32</TargetName>
<TargetName>rt-thread_stm32f4xx</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>STM32F207VG</Device>
<Device>STM32F407VG</Device>
<Vendor>STMicroelectronics</Vendor>
<Cpu>IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")</Cpu>
<Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\ST\STM32F2xx\startup_stm32f2xx.s" ("STM32F2xx Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000)</FlashDriverDll>
<DeviceId>5118</DeviceId>
<RegisterFile>stm32f2xx.h</RegisterFile>
<StartupFile>"Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)</FlashDriverDll>
<DeviceId>6103</DeviceId>
<RegisterFile>stm32f4xx.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
@ -29,13 +29,13 @@
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\ST\STM32F2xx\STM32F2xx.sfr</SFDFile>
<SFDFile>SFD\ST\STM32F4xx\STM32F4xx.sfr</SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>ST\STM32F2xx\</RegisterFilePath>
<DBRegisterFilePath>ST\STM32F2xx\</DBRegisterFilePath>
<RegisterFilePath>ST\STM32F4xx\</RegisterFilePath>
<DBRegisterFilePath>ST\STM32F4xx\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -44,12 +44,12 @@
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\obj\</OutputDirectory>
<OutputName>rtthread-stm32</OutputName>
<OutputName>project</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\obj\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
@ -99,12 +99,12 @@
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments>-MPU</SimDllArguments>
<SimDlgDll>DARMSTM.DLL</SimDlgDll>
<SimDlgDllArguments>-pSTM32F207VG</SimDlgDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
<TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pSTM32F207VG</TargetDlgDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
@ -117,7 +117,7 @@
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
@ -136,7 +136,7 @@
<RestoreToolbox>1</RestoreToolbox>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>7</TargetSelection>
<TargetSelection>8</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
@ -150,7 +150,7 @@
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>Segger\JL2CM3.dll</Driver>
<Driver>STLink\ST-LINKIII-KEIL.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
@ -160,9 +160,9 @@
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4099</DriverSelection>
<DriverSelection>4100</DriverSelection>
</Flash1>
<Flash2>Segger\JL2CM3.dll</Flash2>
<Flash2>STLink\ST-LINKIII-KEIL.dll</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
</Utilities>
@ -195,7 +195,7 @@
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
@ -204,11 +204,11 @@
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<RvdsVP>2</RvdsVP>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
@ -323,8 +323,8 @@
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
@ -334,7 +334,7 @@
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
@ -365,7 +365,7 @@
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>

281
bsp/stm32f40x/usart.c
View File

@ -1,281 +0,0 @@
/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode
*/
#include "usart.h"
#include <serial.h>
#include <stm32f4xx.h>
#include <stm32f4xx_dma.h>
/*
* Use UART1 as console output and finsh input
* interrupt Rx and poll Tx (stream mode)
*
* Use UART2 with interrupt Rx and poll Tx
* Use UART3 with DMA Tx and interrupt Rx -- DMA channel 2
*
* USART DMA setting on STM32
* USART1 Tx --> DMA Channel 4
* USART1 Rx --> DMA Channel 5
* USART2 Tx --> DMA Channel 7
* USART2 Rx --> DMA Channel 6
* USART3 Tx --> DMA Channel 2
* USART3 Rx --> DMA Channel 3
*/
#ifdef RT_USING_UART1
struct stm32_serial_int_rx uart1_int_rx;
struct stm32_serial_device uart1 =
{
USART1,
&uart1_int_rx,
RT_NULL
};
struct rt_device uart1_device;
#endif
#ifdef RT_USING_UART6
struct stm32_serial_int_rx uart6_int_rx;
struct stm32_serial_device uart6 =
{
USART6,
&uart6_int_rx,
RT_NULL
};
struct rt_device uart6_device;
#endif
#ifdef RT_USING_UART2
struct stm32_serial_int_rx uart2_int_rx;
struct stm32_serial_device uart2 =
{
USART2,
&uart2_int_rx,
RT_NULL
};
struct rt_device uart2_device;
#endif
#ifdef RT_USING_UART3
struct stm32_serial_int_rx uart3_int_rx;
struct stm32_serial_dma_tx uart3_dma_tx;
struct stm32_serial_device uart3 =
{
USART3,
&uart3_int_rx,
&uart3_dma_tx
};
struct rt_device uart3_device;
#endif
#define USART1_DR_Base 0x40013804
#define USART2_DR_Base 0x40004404
#define USART3_DR_Base 0x40004804
/* USART1_REMAP = 0 */
#define UART1_GPIO_TX GPIO_Pin_9
#define UART1_GPIO_RX GPIO_Pin_10
#define UART1_GPIO GPIOA
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
#define UART1_TX_DMA DMA1_Channel4
#define UART1_RX_DMA DMA1_Channel5
#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL)
#define UART2_GPIO_TX GPIO_Pin_5
#define UART2_GPIO_RX GPIO_Pin_6
#define UART2_GPIO GPIOD
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#else /* for STM32F10X_HD */
/* USART2_REMAP = 0 */
#define UART2_GPIO_TX GPIO_Pin_2
#define UART2_GPIO_RX GPIO_Pin_3
#define UART2_GPIO GPIOA
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#define UART2_TX_DMA DMA1_Channel7
#define UART2_RX_DMA DMA1_Channel6
#endif
/* USART3_REMAP[1:0] = 00 */
#define UART3_GPIO_RX GPIO_Pin_11
#define UART3_GPIO_TX GPIO_Pin_10
#define UART3_GPIO GPIOB
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
#define UART3_TX_DMA DMA1_Channel2
#define UART3_RX_DMA DMA1_Channel3
/* USART6_REMAP = 0 */
#define UART6_GPIO_TX GPIO_Pin_6
#define UART6_GPIO_RX GPIO_Pin_7
#define UART6_GPIO GPIOC
#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6
//#define UART1_TX_DMA DMA1_Channel?
//#define UART1_RX_DMA DMA1_Channel?
static void RCC_Configuration(void)
{
#ifdef RT_USING_UART1
/* Enable USART1 and GPIOA clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
#endif
#ifdef RT_USING_UART6
/* Enable USART6 and GPIOC clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
#endif
}
static void GPIO_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
#ifdef RT_USING_UART1
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10;
GPIO_Init(GPIOA,&GPIO_InitStruct);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
#endif
#ifdef RT_USING_UART6
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX;
GPIO_Init(UART6_GPIO,&GPIO_InitStruct);
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6);
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6);
#endif
}
static void NVIC_Configuration(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
#ifdef RT_USING_UART1
/* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
#ifdef RT_USING_UART6
/* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
}
/*
* Init all related hardware in here
* rt_hw_serial_init() will register all supported USART device
*/
void rt_hw_usart_init()
{
USART_InitTypeDef USART_InitStructure;
RCC_Configuration();
GPIO_Configuration();
NVIC_Configuration();
/* uart init */
#ifdef RT_USING_UART1
USART_DeInit(USART1);
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART1, &USART_InitStructure);
/* register uart1 */
rt_hw_serial_register(&uart1_device, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart1);
/* enable interrupt */
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
/* Enable USART1 */
USART_Cmd(USART1, ENABLE);
USART_ClearFlag(USART1,USART_FLAG_TXE);
#endif
/* uart init */
#ifdef RT_USING_UART6
USART_DeInit(USART6);
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART6, &USART_InitStructure);
/* register uart1 */
rt_hw_serial_register(&uart6_device, "uart6",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart6);
/* enable interrupt */
USART_ITConfig(USART6, USART_IT_RXNE, ENABLE);
/* Enable USART6 */
USART_Cmd(USART6, ENABLE);
USART_ClearFlag(USART6,USART_FLAG_TXE);
#endif
}
#ifdef RT_USING_UART1
void USART1_IRQHandler()
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&uart1_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef RT_USING_UART6
void USART6_IRQHandler()
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&uart6_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif

23
bsp/stm32f40x/usart.h
View File

@ -1,23 +0,0 @@
/*
* File : usart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
*/
#ifndef __USART_H__
#define __USART_H__
#include <rthw.h>
#include <rtthread.h>
void rt_hw_usart_init(void);
#endif