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修正am335x中mmu问题
1) mmu_disable_dcache/mmu_enable_dcache等, 应使用rt_cpu_xxx相关函数,否则会跑飞. armcc并没有提供rt_cpu_xxx对应汇编代码,先删除 2) mmu_setmtt抽取为函数mmu_setmtts,并增加RT_WEAK.mmu_setmtts此处作为示例函数.实际用户板子可在bsp中重新实现该函数.可在rt_components_board_init函数前调用rt_hw_mmu_init
This commit is contained in:
liruncong
parent
e59aa648b3
commit
af1044955a
@ -14,237 +14,46 @@
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#include <rtthread.h>
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#include <rtthread.h>
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#include "am33xx.h"
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#include "am33xx.h"
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#include <mmu.h>
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#define DESC_SEC (0x2)
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extern void rt_cpu_dcache_disable(void);
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#define CB (3<<2) //cache_on, write_back
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extern void rt_hw_cpu_dcache_enable(void);
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#define CNB (2<<2) //cache_on, write_through
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extern void rt_cpu_icache_disable(void);
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#define NCB (1<<2) //cache_off,WR_BUF on
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extern void rt_hw_cpu_icache_enable(void);
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#define NCNB (0<<2) //cache_off,WR_BUF off
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extern void rt_cpu_mmu_disable(void);
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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extern void rt_cpu_mmu_enable(void);
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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extern void rt_cpu_tlb_set(register rt_uint32_t i);
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#define DOMAIN_FAULT (0x0)
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void mmu_disable_dcache()
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#ifdef __CC_ARM
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void mmu_setttbase(rt_uint32_t i)
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{
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{
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register rt_uint32_t value;
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rt_cpu_dcache_disable();
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c8, c7, 0
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}
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value = 0x55555555;
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__asm volatile
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{
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mcr p15, 0, value, c3, c0, 0
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mcr p15, 0, i, c2, c0, 0
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}
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}
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void mmu_set_domain(rt_uint32_t i)
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{
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__asm volatile
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{
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mcr p15,0, i, c3, c0, 0
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}
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}
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void mmu_enable()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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}
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void mmu_enable_dcache()
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void mmu_enable_dcache()
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{
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{
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register rt_uint32_t value;
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rt_hw_cpu_dcache_enable();
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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}
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void mmu_disable_icache()
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void mmu_disable_icache()
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{
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{
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register rt_uint32_t value;
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rt_cpu_icache_disable();
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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}
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void mmu_disable_dcache()
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void mmu_enable_icache()
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{
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{
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register rt_uint32_t value;
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rt_hw_cpu_icache_enable();
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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}
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void mmu_enable_alignfault()
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void mmu_disable()
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{
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{
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register rt_uint32_t value;
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rt_cpu_mmu_disable();
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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}
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void mmu_disable_alignfault()
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void mmu_enable()
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{
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{
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register rt_uint32_t value;
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rt_cpu_mmu_enable();
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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__asm volatile
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{
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mcr p15, 0, index, c7, c14, 2
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}
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while(ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c14, 1
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}
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ptr += 32;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c10, 1
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}
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ptr += 32;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c6, 1
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}
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ptr += 32;
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}
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}
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void mmu_invalidate_tlb()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c8, c7, 0
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}
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}
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void mmu_invalidate_icache()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c7, c5, 0
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}
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}
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#elif defined(__GNUC__)
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void mmu_setttbase(register rt_uint32_t i)
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void mmu_setttbase(register rt_uint32_t i)
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{
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{
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register rt_uint32_t value;
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register rt_uint32_t value;
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@ -259,7 +68,8 @@ void mmu_setttbase(register rt_uint32_t i)
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value = 0x55555555;
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value = 0x55555555;
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asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
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rt_cpu_tlb_set(i);
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}
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}
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void mmu_set_domain(register rt_uint32_t i)
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void mmu_set_domain(register rt_uint32_t i)
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@ -267,84 +77,6 @@ void mmu_set_domain(register rt_uint32_t i)
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asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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void mmu_enable_alignfault()
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{
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{
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register rt_uint32_t i;
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register rt_uint32_t i;
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@ -411,7 +143,6 @@ void mmu_invalidate_icache()
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{
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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}
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#endif
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/* level1 page table */
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/* level1 page table */
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static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
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static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
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@ -428,6 +159,15 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS
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}
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}
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}
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}
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/* set page table */
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RT_WEAK void mmu_setmtts(void)
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{
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mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
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mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */
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mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */
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mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */
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}
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void rt_hw_mmu_init(void)
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void rt_hw_mmu_init(void)
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{
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{
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/* disable I/D cache */
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/* disable I/D cache */
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@ -436,11 +176,7 @@ void rt_hw_mmu_init(void)
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mmu_disable();
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mmu_disable();
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mmu_invalidate_tlb();
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mmu_invalidate_tlb();
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/* set page table */
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mmu_setmtts();
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mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
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mmu_setmtt(0xC0000000, 0xC8000000-1, 0xC0000000, RW_CB); /* 128M cached DDR memory */
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mmu_setmtt(0xD0000000, 0xD8000000-1, 0xC0000000, RW_NCNB); /* 128M none-cached DDR memory */
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mmu_setmtt(0x80000000, 0x80020000-1, 0x80000000, RW_CB); /* 128k OnChip memory */
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/* set MMU table address */
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/* set MMU table address */
|
||||||
mmu_setttbase((rt_uint32_t)_page_table);
|
mmu_setttbase((rt_uint32_t)_page_table);
|
||||||
|
|||||||
51
libcpu/arm/am335x/mmu.h
Normal file
51
libcpu/arm/am335x/mmu.h
Normal file
@ -0,0 +1,51 @@
|
|||||||
|
/*
|
||||||
|
* File : mmu.h
|
||||||
|
* This file is part of RT-Thread RTOS
|
||||||
|
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along
|
||||||
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MMU_H__
|
||||||
|
#define __MMU_H__
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#define DESC_SEC (0x2)
|
||||||
|
#define CB (3<<2) //cache_on, write_back
|
||||||
|
#define CNB (2<<2) //cache_on, write_through
|
||||||
|
#define NCB (1<<2) //cache_off,WR_BUF on
|
||||||
|
#define NCNB (0<<2) //cache_off,WR_BUF off
|
||||||
|
#define AP_RW (3<<10) //supervisor=RW, user=RW
|
||||||
|
#define AP_RO (2<<10) //supervisor=RW, user=RO
|
||||||
|
|
||||||
|
#define DOMAIN_FAULT (0x0)
|
||||||
|
#define DOMAIN_CHK (0x1)
|
||||||
|
#define DOMAIN_NOTCHK (0x3)
|
||||||
|
#define DOMAIN0 (0x0<<5)
|
||||||
|
#define DOMAIN1 (0x1<<5)
|
||||||
|
|
||||||
|
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
|
||||||
|
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
|
||||||
|
|
||||||
|
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
|
||||||
|
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
|
||||||
|
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
|
||||||
|
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
|
||||||
|
|
||||||
|
void rt_hw_mmu_init(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
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Reference in New Issue
Block a user