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[Infineon]Update Infineon [mtb-hal-cat1] to V2.3.0 and [mtb-pdl-cat1] to v3.2.0

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Rbb666 2023-04-11 15:40:48 +08:00 committed by guo
parent 870bf84964
commit aeed2eebdc
1919 changed files with 366948 additions and 148274 deletions
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56
bsp/Infineon/docs/PSOC6系列BSP制作教程.md
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@ -119,14 +119,64 @@ Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_s
![](./figures/hal_config1.png)
同时下载 [TARGET_CY8CKIT-062S2-43012](https://github.com/Infineon/TARGET_CY8CKIT-062S2-43012/releases) **V3.0.0** 发行版本（需根据不同芯片型号下载），至具体 BSP 的 libs 文件夹下。
接下来需要添加板级配置文件，接下来介绍使用英飞凌官方以及非官方开发板的添加步骤：
![](./figures/hal_config4.png)
1、**英飞凌官方开发板步骤**
下载至具体 BSP 的 libs 文件夹下，例如下图：
打开 `ModusToolbox` 软件(版本需 >=V3.0.0)，点击新建项目：
![](./figures/ModusToolbox.png)
输入开发板型号信息，然后选择下一步：
![](./figures/ModusToolbox1.png)
选择 `Hello World` 模板工程，接下来点击创建该工程：
![](./figures/ModusToolbox2.png)
值得注意的是，`APP_CY8CKIT-062S2-43012` 这个 bsp 需要为 4.1.0 版本：
![](./figures/ModusToolbox2.2.png)
等待下载完成后，打开对应的 BSP 文件夹，找到 bsps 下生成的文件：
![](./figures/ModusToolbox3.png)
拷贝其中的内容到 RT-Thread 具体 BSP 的 libs文件夹下，例如下图：
![](./figures/hal_config4-1.png)
同时按照具体路径配置 `SConscript` 脚本文件。
2、**非英飞凌官方开发板步骤**
首先找到 ModusToolbox 安装路径下 `BSP Assistant` 这个软件：
![](./figures/ModusToolbox4.png)
点击 File->New 进行新建项目，按照下图选择目标芯片等：
![](./figures/ModusToolbox5.png)
点击 `Device Configurator 4.0` 后进入图形化配置界面进行外设配置：
![](./figures/ModusToolbox6.png)
引脚部分，swd 的引脚配置是必须的，保持默认即可
![](./figures/ModusToolbox7.png)
时钟相关配置，最初保持默认即可：
![](./figures/ModusToolbox8.png)
全部都配置好后，在界面中按 `ctrl+s ` 即可自动生成配置文件，然后拷贝其中的内容到 RT-Thread 具体 BSP 的 libs文件夹下，例如下图：
![](./figures/hal_config4-1.png)
同时按照具体路径配置 `SConscript` 脚本文件。
### 3.5 修改工程构建相关文件
接下来需要修改用于构建工程相关的文件。

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3
bsp/Infineon/libraries/HAL_Drivers/drv_gpio.h
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@ -14,8 +14,7 @@
#include <rthw.h>
#include <rtdevice.h>
#include "drv_common.h"
#include "cyhal_irq_psoc.h"
#include "cyhal_irq_impl.h"
#define GPIO_INTERRUPT_PRIORITY (7u)

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript
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@ -16,10 +16,10 @@ src = Split('''
mtb-hal-cat1/source/cyhal_gpio.c
mtb-hal-cat1/source/cyhal_scb_common.c
mtb-hal-cat1/source/cyhal_interconnect.c
mtb-hal-cat1/source/cyhal_utils_psoc.c
mtb-hal-cat1/source/cyhal_utils.c
mtb-hal-cat1/source/cyhal_lptimer.c
mtb-hal-cat1/source/cyhal_irq_psoc.c
mtb-hal-cat1/source/cyhal_utils_impl.c
mtb-hal-cat1/source/cyhal_irq_impl.c
mtb-pdl-cat1/drivers/source/cy_sysclk.c
mtb-pdl-cat1/drivers/source/cy_systick.c
mtb-pdl-cat1/drivers/source/cy_gpio.c

1
bsp/Infineon/libraries/IFX_PSOC6_HAL/capsense/.cyignore Normal file
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@ -0,0 +1 @@
docs

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/.gitignore → bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/.cyignore
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2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_124_bga.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_02_124_bga.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_02_128_tqfp.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_02_68_qfn.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_03_100_tqfp.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h
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@ -6,7 +6,7 @@
*
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* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_03_68_qfn.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_04_64_tqfp.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_04_68_qfn.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_04_80_tqfp.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers/cyhal_triggers_psoc6_01.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers/cyhal_triggers_psoc6_02.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers/cyhal_triggers_psoc6_03.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers/cyhal_triggers_psoc6_04.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga.c
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@ -6,7 +6,7 @@
*
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* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_128_tqfp.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1B/source/pin_packages/cyhal_cyw20829_40_qfn.c
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
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*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

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/***************************************************************************//**
* \file cyhal_xmc7200_320_bga.h
*
* \brief
* XMC7200 device GPIO HAL header for 320-BGA package
*
********************************************************************************
* \copyright
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_XMC7200_320_BGA_H_
#define _CYHAL_XMC7200_320_BGA_H_
#include "cyhal_hw_resources.h"
/**
* \addtogroup group_hal_impl_pin_package_xmc7200_320_bga XMC7200 320-BGA
* \ingroup group_hal_impl_pin_package
* \{
* Pin definitions and connections specific to the XMC7200 320-BGA package.
*/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/** Gets a pin definition from the provided port and pin numbers */
#define CYHAL_GET_GPIO(port, pin) ((((uint16_t)(port)) << 3U) + ((uint8_t)(pin)))
/** Macro that, given a gpio, will extract the pin number */
#define CYHAL_GET_PIN(pin) ((uint8_t)(((uint16_t)pin) & 0x07U))
/** Macro that, given a gpio, will extract the port number */
#define CYHAL_GET_PORT(pin) ((uint8_t)(((uint16_t)pin) >> 3U))
/** Definitions for all of the pins that are bonded out on in the 320-BGA package for the XMC7200 series. */
typedef enum {
NC = 0xFFFF, //!< No Connect/Invalid Pin
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6), //!< Port 1 Pin 6
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2
P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3
P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4
P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5
P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6), //!< Port 3 Pin 6
P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7), //!< Port 3 Pin 7
P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0
P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1
P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2
P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3
P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4
P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5), //!< Port 4 Pin 5
P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6), //!< Port 4 Pin 6
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0
P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1
P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2
P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3
P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4
P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5
P14_6 = CYHAL_GET_GPIO(CYHAL_PORT_14, 6), //!< Port 14 Pin 6
P14_7 = CYHAL_GET_GPIO(CYHAL_PORT_14, 7), //!< Port 14 Pin 7
P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0
P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1
P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2
P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3
P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0), //!< Port 16 Pin 0
P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1), //!< Port 16 Pin 1
P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2), //!< Port 16 Pin 2
P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3), //!< Port 16 Pin 3
P16_4 = CYHAL_GET_GPIO(CYHAL_PORT_16, 4), //!< Port 16 Pin 4
P16_5 = CYHAL_GET_GPIO(CYHAL_PORT_16, 5), //!< Port 16 Pin 5
P16_6 = CYHAL_GET_GPIO(CYHAL_PORT_16, 6), //!< Port 16 Pin 6
P16_7 = CYHAL_GET_GPIO(CYHAL_PORT_16, 7), //!< Port 16 Pin 7
P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0
P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1
P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2
P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3
P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4
P17_5 = CYHAL_GET_GPIO(CYHAL_PORT_17, 5), //!< Port 17 Pin 5
P17_6 = CYHAL_GET_GPIO(CYHAL_PORT_17, 6), //!< Port 17 Pin 6
P17_7 = CYHAL_GET_GPIO(CYHAL_PORT_17, 7), //!< Port 17 Pin 7
P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0
P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1
P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2
P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3
P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4
P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5
P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6
P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7
P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0
P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1
P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2
P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3
P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4
P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0
P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1
P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2
P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3
P20_4 = CYHAL_GET_GPIO(CYHAL_PORT_20, 4), //!< Port 20 Pin 4
P20_5 = CYHAL_GET_GPIO(CYHAL_PORT_20, 5), //!< Port 20 Pin 5
P20_6 = CYHAL_GET_GPIO(CYHAL_PORT_20, 6), //!< Port 20 Pin 6
P20_7 = CYHAL_GET_GPIO(CYHAL_PORT_20, 7), //!< Port 20 Pin 7
P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0
P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1
P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2
P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3
P21_4 = CYHAL_GET_GPIO(CYHAL_PORT_21, 4), //!< Port 21 Pin 4
P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5
P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6
P21_7 = CYHAL_GET_GPIO(CYHAL_PORT_21, 7), //!< Port 21 Pin 7
P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1
P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2
P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3
P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4
P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5
P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6
P22_7 = CYHAL_GET_GPIO(CYHAL_PORT_22, 7), //!< Port 22 Pin 7
P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0
P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1
P23_2 = CYHAL_GET_GPIO(CYHAL_PORT_23, 2), //!< Port 23 Pin 2
P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3
P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4
P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5
P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6
P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7
P24_0 = CYHAL_GET_GPIO(CYHAL_PORT_24, 0), //!< Port 24 Pin 0
P24_1 = CYHAL_GET_GPIO(CYHAL_PORT_24, 1), //!< Port 24 Pin 1
P24_2 = CYHAL_GET_GPIO(CYHAL_PORT_24, 2), //!< Port 24 Pin 2
P24_3 = CYHAL_GET_GPIO(CYHAL_PORT_24, 3), //!< Port 24 Pin 3
P24_4 = CYHAL_GET_GPIO(CYHAL_PORT_24, 4), //!< Port 24 Pin 4
P25_0 = CYHAL_GET_GPIO(CYHAL_PORT_25, 0), //!< Port 25 Pin 0
P25_1 = CYHAL_GET_GPIO(CYHAL_PORT_25, 1), //!< Port 25 Pin 1
P25_2 = CYHAL_GET_GPIO(CYHAL_PORT_25, 2), //!< Port 25 Pin 2
P25_3 = CYHAL_GET_GPIO(CYHAL_PORT_25, 3), //!< Port 25 Pin 3
P25_4 = CYHAL_GET_GPIO(CYHAL_PORT_25, 4), //!< Port 25 Pin 4
P25_5 = CYHAL_GET_GPIO(CYHAL_PORT_25, 5), //!< Port 25 Pin 5
P25_6 = CYHAL_GET_GPIO(CYHAL_PORT_25, 6), //!< Port 25 Pin 6
P25_7 = CYHAL_GET_GPIO(CYHAL_PORT_25, 7), //!< Port 25 Pin 7
P26_0 = CYHAL_GET_GPIO(CYHAL_PORT_26, 0), //!< Port 26 Pin 0
P26_1 = CYHAL_GET_GPIO(CYHAL_PORT_26, 1), //!< Port 26 Pin 1
P26_2 = CYHAL_GET_GPIO(CYHAL_PORT_26, 2), //!< Port 26 Pin 2
P26_3 = CYHAL_GET_GPIO(CYHAL_PORT_26, 3), //!< Port 26 Pin 3
P26_4 = CYHAL_GET_GPIO(CYHAL_PORT_26, 4), //!< Port 26 Pin 4
P26_5 = CYHAL_GET_GPIO(CYHAL_PORT_26, 5), //!< Port 26 Pin 5
P26_6 = CYHAL_GET_GPIO(CYHAL_PORT_26, 6), //!< Port 26 Pin 6
P26_7 = CYHAL_GET_GPIO(CYHAL_PORT_26, 7), //!< Port 26 Pin 7
P27_0 = CYHAL_GET_GPIO(CYHAL_PORT_27, 0), //!< Port 27 Pin 0
P27_1 = CYHAL_GET_GPIO(CYHAL_PORT_27, 1), //!< Port 27 Pin 1
P27_2 = CYHAL_GET_GPIO(CYHAL_PORT_27, 2), //!< Port 27 Pin 2
P27_3 = CYHAL_GET_GPIO(CYHAL_PORT_27, 3), //!< Port 27 Pin 3
P27_4 = CYHAL_GET_GPIO(CYHAL_PORT_27, 4), //!< Port 27 Pin 4
P27_5 = CYHAL_GET_GPIO(CYHAL_PORT_27, 5), //!< Port 27 Pin 5
P27_6 = CYHAL_GET_GPIO(CYHAL_PORT_27, 6), //!< Port 27 Pin 6
P27_7 = CYHAL_GET_GPIO(CYHAL_PORT_27, 7), //!< Port 27 Pin 7
P28_0 = CYHAL_GET_GPIO(CYHAL_PORT_28, 0), //!< Port 28 Pin 0
P28_1 = CYHAL_GET_GPIO(CYHAL_PORT_28, 1), //!< Port 28 Pin 1
P28_2 = CYHAL_GET_GPIO(CYHAL_PORT_28, 2), //!< Port 28 Pin 2
P28_3 = CYHAL_GET_GPIO(CYHAL_PORT_28, 3), //!< Port 28 Pin 3
P28_4 = CYHAL_GET_GPIO(CYHAL_PORT_28, 4), //!< Port 28 Pin 4
P28_5 = CYHAL_GET_GPIO(CYHAL_PORT_28, 5), //!< Port 28 Pin 5
P28_6 = CYHAL_GET_GPIO(CYHAL_PORT_28, 6), //!< Port 28 Pin 6
P28_7 = CYHAL_GET_GPIO(CYHAL_PORT_28, 7), //!< Port 28 Pin 7
P29_0 = CYHAL_GET_GPIO(CYHAL_PORT_29, 0), //!< Port 29 Pin 0
P29_1 = CYHAL_GET_GPIO(CYHAL_PORT_29, 1), //!< Port 29 Pin 1
P29_2 = CYHAL_GET_GPIO(CYHAL_PORT_29, 2), //!< Port 29 Pin 2
P29_3 = CYHAL_GET_GPIO(CYHAL_PORT_29, 3), //!< Port 29 Pin 3
P29_4 = CYHAL_GET_GPIO(CYHAL_PORT_29, 4), //!< Port 29 Pin 4
P29_5 = CYHAL_GET_GPIO(CYHAL_PORT_29, 5), //!< Port 29 Pin 5
P29_6 = CYHAL_GET_GPIO(CYHAL_PORT_29, 6), //!< Port 29 Pin 6
P29_7 = CYHAL_GET_GPIO(CYHAL_PORT_29, 7), //!< Port 29 Pin 7
P30_0 = CYHAL_GET_GPIO(CYHAL_PORT_30, 0), //!< Port 30 Pin 0
P30_1 = CYHAL_GET_GPIO(CYHAL_PORT_30, 1), //!< Port 30 Pin 1
P30_2 = CYHAL_GET_GPIO(CYHAL_PORT_30, 2), //!< Port 30 Pin 2
P30_3 = CYHAL_GET_GPIO(CYHAL_PORT_30, 3), //!< Port 30 Pin 3
P31_0 = CYHAL_GET_GPIO(CYHAL_PORT_31, 0), //!< Port 31 Pin 0
P31_1 = CYHAL_GET_GPIO(CYHAL_PORT_31, 1), //!< Port 31 Pin 1
P31_2 = CYHAL_GET_GPIO(CYHAL_PORT_31, 2), //!< Port 31 Pin 2
P32_0 = CYHAL_GET_GPIO(CYHAL_PORT_32, 0), //!< Port 32 Pin 0
P32_1 = CYHAL_GET_GPIO(CYHAL_PORT_32, 1), //!< Port 32 Pin 1
P32_2 = CYHAL_GET_GPIO(CYHAL_PORT_32, 2), //!< Port 32 Pin 2
P32_3 = CYHAL_GET_GPIO(CYHAL_PORT_32, 3), //!< Port 32 Pin 3
P32_4 = CYHAL_GET_GPIO(CYHAL_PORT_32, 4), //!< Port 32 Pin 4
P32_5 = CYHAL_GET_GPIO(CYHAL_PORT_32, 5), //!< Port 32 Pin 5
P32_6 = CYHAL_GET_GPIO(CYHAL_PORT_32, 6), //!< Port 32 Pin 6
P32_7 = CYHAL_GET_GPIO(CYHAL_PORT_32, 7), //!< Port 32 Pin 7
P33_0 = CYHAL_GET_GPIO(CYHAL_PORT_33, 0), //!< Port 33 Pin 0
P33_1 = CYHAL_GET_GPIO(CYHAL_PORT_33, 1), //!< Port 33 Pin 1
P33_2 = CYHAL_GET_GPIO(CYHAL_PORT_33, 2), //!< Port 33 Pin 2
P33_3 = CYHAL_GET_GPIO(CYHAL_PORT_33, 3), //!< Port 33 Pin 3
P33_4 = CYHAL_GET_GPIO(CYHAL_PORT_33, 4), //!< Port 33 Pin 4
P33_5 = CYHAL_GET_GPIO(CYHAL_PORT_33, 5), //!< Port 33 Pin 5
P33_6 = CYHAL_GET_GPIO(CYHAL_PORT_33, 6), //!< Port 33 Pin 6
P33_7 = CYHAL_GET_GPIO(CYHAL_PORT_33, 7), //!< Port 33 Pin 7
P34_0 = CYHAL_GET_GPIO(CYHAL_PORT_34, 0), //!< Port 34 Pin 0
P34_1 = CYHAL_GET_GPIO(CYHAL_PORT_34, 1), //!< Port 34 Pin 1
P34_2 = CYHAL_GET_GPIO(CYHAL_PORT_34, 2), //!< Port 34 Pin 2
P34_3 = CYHAL_GET_GPIO(CYHAL_PORT_34, 3), //!< Port 34 Pin 3
P34_4 = CYHAL_GET_GPIO(CYHAL_PORT_34, 4), //!< Port 34 Pin 4
P34_5 = CYHAL_GET_GPIO(CYHAL_PORT_34, 5), //!< Port 34 Pin 5
P34_6 = CYHAL_GET_GPIO(CYHAL_PORT_34, 6), //!< Port 34 Pin 6
P34_7 = CYHAL_GET_GPIO(CYHAL_PORT_34, 7), //!< Port 34 Pin 7
} cyhal_gpio_xmc7200_320_bga_t;
/** Create generic name for the series/package specific type. */
typedef cyhal_gpio_xmc7200_320_bga_t cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
uint8_t block_num; //!< The block number of the resource with this connection
uint8_t channel_num; //!< The channel number of the block with this connection
cyhal_gpio_t pin; //!< The GPIO pin the connection is with
en_hsiom_sel_t hsiom; //!< The HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
/** Indicates that a pin map exists for audioss_clk_i2s_if*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3];
/** Indicates that a pin map exists for audioss_mclk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_MCLK (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the audioss_mclk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3];
/** Indicates that a pin map exists for audioss_rx_sck*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3];
/** Indicates that a pin map exists for audioss_rx_sdi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3];
/** Indicates that a pin map exists for audioss_rx_ws*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3];
/** Indicates that a pin map exists for audioss_tx_sck*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3];
/** Indicates that a pin map exists for audioss_tx_sdo*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3];
/** Indicates that a pin map exists for audioss_tx_ws*/
#define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3];
/** Indicates that a pin map exists for canfd_ttcan_rx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[21];
/** Indicates that a pin map exists for canfd_ttcan_tx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[21];
/** Indicates that a pin map exists for cpuss_cal_sup_nz*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3];
/** Indicates that a pin map exists for cpuss_clk_fm_pump*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1];
/** Indicates that a pin map exists for cpuss_fault_out*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the cpuss_fault_out signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8];
/** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN)
/** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1];
/** Indicates that a pin map exists for cpuss_swj_swdio_tms*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP)
/** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1];
/** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP)
/** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1];
/** Indicates that a pin map exists for cpuss_swj_swo_tdo*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1];
/** Indicates that a pin map exists for cpuss_swj_trstn*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP)
/** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1];
/** Indicates that a pin map exists for cpuss_trace_clock*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2];
/** Indicates that a pin map exists for cpuss_trace_data*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the cpuss_trace_data signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8];
/** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[3];
/** Indicates that a pin map exists for eth_mdc*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_mdc signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[3];
/** Indicates that a pin map exists for eth_mdio*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_mdio signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[3];
/** Indicates that a pin map exists for eth_ref_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_ref_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[3];
/** Indicates that a pin map exists for eth_rx_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rx_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[3];
/** Indicates that a pin map exists for eth_rx_ctl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rx_ctl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[3];
/** Indicates that a pin map exists for eth_rx_er*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rx_er signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[2];
/** Indicates that a pin map exists for eth_rxd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rxd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[16];
/** Indicates that a pin map exists for eth_tx_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_tx_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[3];
/** Indicates that a pin map exists for eth_tx_ctl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_tx_ctl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[3];
/** Indicates that a pin map exists for eth_tx_er*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_ER (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the eth_tx_er signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[2];
/** Indicates that a pin map exists for eth_txd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_txd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[16];
/** Indicates that a pin map exists for flexray_rxda*/
#define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDA (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the flexray_rxda signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1];
/** Indicates that a pin map exists for flexray_rxdb*/
#define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDB (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the flexray_rxdb signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1];
/** Indicates that a pin map exists for flexray_txda*/
#define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDA (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the flexray_txda signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1];
/** Indicates that a pin map exists for flexray_txdb*/
#define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDB (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the flexray_txdb signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1];
/** Indicates that a pin map exists for flexray_txena_n*/
#define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENA_N (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the flexray_txena_n signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1];
/** Indicates that a pin map exists for flexray_txenb_n*/
#define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENB_N (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the flexray_txenb_n signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1];
/** Indicates that a pin map exists for lin_lin_en*/
#define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the lin_lin_en signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[39];
/** Indicates that a pin map exists for lin_lin_rx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the lin_lin_rx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[49];
/** Indicates that a pin map exists for lin_lin_tx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the lin_lin_tx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[49];
/** Indicates that a pin map exists for pass_sar_ext_mux_en*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3];
/** Indicates that a pin map exists for pass_sar_ext_mux_sel*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9];
/** Indicates that a pin map exists for pass_sarmux_pads*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG)
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[96];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[48];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW)
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[23];
/** Indicates that a pin map exists for scb_i2c_sda*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW)
/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[23];
/** Indicates that a pin map exists for scb_spi_m_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[25];
/** Indicates that a pin map exists for scb_spi_m_miso*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[24];
/** Indicates that a pin map exists for scb_spi_m_mosi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[24];
/** Indicates that a pin map exists for scb_spi_m_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[25];
/** Indicates that a pin map exists for scb_spi_m_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[21];
/** Indicates that a pin map exists for scb_spi_m_select2*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[20];
/** Indicates that a pin map exists for scb_spi_m_select3*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8];
/** Indicates that a pin map exists for scb_spi_s_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[25];
/** Indicates that a pin map exists for scb_spi_s_miso*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[24];
/** Indicates that a pin map exists for scb_spi_s_mosi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[24];
/** Indicates that a pin map exists for scb_spi_s_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[25];
/** Indicates that a pin map exists for scb_spi_s_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[21];
/** Indicates that a pin map exists for scb_spi_s_select2*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[20];
/** Indicates that a pin map exists for scb_spi_s_select3*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8];
/** Indicates that a pin map exists for scb_uart_cts*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[21];
/** Indicates that a pin map exists for scb_uart_rts*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[21];
/** Indicates that a pin map exists for scb_uart_rx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[21];
/** Indicates that a pin map exists for scb_uart_tx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[21];
/** Indicates that a pin map exists for sdhc_card_cmd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
/** Indicates that a pin map exists for sdhc_card_dat_3to0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
/** Indicates that a pin map exists for sdhc_card_dat_7to4*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[8];
/** Indicates that a pin map exists for sdhc_card_detect_n*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
/** Indicates that a pin map exists for sdhc_card_if_pwr_en*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
/** Indicates that a pin map exists for sdhc_card_mech_write_prot*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
/** Indicates that a pin map exists for sdhc_clk_card*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
/** Indicates that a pin map exists for smif_spi_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[2];
/** Indicates that a pin map exists for smif_spi_data0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[2];
/** Indicates that a pin map exists for smif_spi_data1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[2];
/** Indicates that a pin map exists for smif_spi_data2*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[2];
/** Indicates that a pin map exists for smif_spi_data3*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[2];
/** Indicates that a pin map exists for smif_spi_data4*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[2];
/** Indicates that a pin map exists for smif_spi_data5*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[2];
/** Indicates that a pin map exists for smif_spi_data6*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[2];
/** Indicates that a pin map exists for smif_spi_data7*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[2];
/** Indicates that a pin map exists for smif_spi_rwds*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_RWDS (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the smif_spi_rwds signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[2];
/** Indicates that a pin map exists for smif_spi_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[2];
/** Indicates that a pin map exists for smif_spi_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[2];
/** Indicates that a pin map exists for tcpwm_line*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tcpwm_line signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[227];
/** Indicates that a pin map exists for tcpwm_line_compl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[227];
/** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ)
/** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[446];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_impl_pin_package */
#endif /* _CYHAL_XMC7200_320_BGA_H_ */
/* [] END OF FILE */

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/include/triggers/cyhal_triggers_xmc7100.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/include/triggers/cyhal_triggers_xmc7200.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

64
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/cyhal_xmc7100_100_teqfp.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
@ -318,37 +318,37 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[37] = {
{0u, 3u, P6_3, HSIOM_SEL_GPIO},
{0u, 4u, P6_4, HSIOM_SEL_GPIO},
{0u, 5u, P6_5, HSIOM_SEL_GPIO},
{2u, 0u, P7_0, HSIOM_SEL_GPIO},
{2u, 1u, P7_1, HSIOM_SEL_GPIO},
{2u, 2u, P7_2, HSIOM_SEL_GPIO},
{2u, 3u, P7_3, HSIOM_SEL_GPIO},
{2u, 4u, P7_4, HSIOM_SEL_GPIO},
{2u, 5u, P7_5, HSIOM_SEL_GPIO},
{3u, 0u, P8_1, HSIOM_SEL_GPIO},
{3u, 1u, P8_2, HSIOM_SEL_GPIO},
{4u, 4u, P12_0, HSIOM_SEL_GPIO},
{4u, 5u, P12_1, HSIOM_SEL_GPIO},
{4u, 6u, P12_2, HSIOM_SEL_GPIO},
{4u, 7u, P12_3, HSIOM_SEL_GPIO},
{5u, 0u, P12_4, HSIOM_SEL_GPIO},
{5u, 4u, P13_0, HSIOM_SEL_GPIO},
{5u, 5u, P13_1, HSIOM_SEL_GPIO},
{5u, 6u, P13_2, HSIOM_SEL_GPIO},
{5u, 7u, P13_3, HSIOM_SEL_GPIO},
{6u, 0u, P13_4, HSIOM_SEL_GPIO},
{6u, 1u, P13_5, HSIOM_SEL_GPIO},
{6u, 2u, P13_6, HSIOM_SEL_GPIO},
{6u, 3u, P13_7, HSIOM_SEL_GPIO},
{6u, 4u, P14_0, HSIOM_SEL_GPIO},
{6u, 5u, P14_1, HSIOM_SEL_GPIO},
{8u, 0u, P18_0, HSIOM_SEL_GPIO},
{8u, 1u, P18_1, HSIOM_SEL_GPIO},
{8u, 2u, P18_2, HSIOM_SEL_GPIO},
{8u, 3u, P18_3, HSIOM_SEL_GPIO},
{8u, 4u, P18_4, HSIOM_SEL_GPIO},
{8u, 5u, P18_5, HSIOM_SEL_GPIO},
{8u, 6u, P18_6, HSIOM_SEL_GPIO},
{8u, 7u, P18_7, HSIOM_SEL_GPIO},
{0u, 16u, P7_0, HSIOM_SEL_GPIO},
{0u, 17u, P7_1, HSIOM_SEL_GPIO},
{0u, 18u, P7_2, HSIOM_SEL_GPIO},
{0u, 19u, P7_3, HSIOM_SEL_GPIO},
{0u, 20u, P7_4, HSIOM_SEL_GPIO},
{0u, 21u, P7_5, HSIOM_SEL_GPIO},
{0u, 24u, P8_1, HSIOM_SEL_GPIO},
{0u, 25u, P8_2, HSIOM_SEL_GPIO},
{1u, 4u, P12_0, HSIOM_SEL_GPIO},
{1u, 5u, P12_1, HSIOM_SEL_GPIO},
{1u, 6u, P12_2, HSIOM_SEL_GPIO},
{1u, 7u, P12_3, HSIOM_SEL_GPIO},
{1u, 8u, P12_4, HSIOM_SEL_GPIO},
{1u, 12u, P13_0, HSIOM_SEL_GPIO},
{1u, 13u, P13_1, HSIOM_SEL_GPIO},
{1u, 14u, P13_2, HSIOM_SEL_GPIO},
{1u, 15u, P13_3, HSIOM_SEL_GPIO},
{1u, 16u, P13_4, HSIOM_SEL_GPIO},
{1u, 17u, P13_5, HSIOM_SEL_GPIO},
{1u, 18u, P13_6, HSIOM_SEL_GPIO},
{1u, 19u, P13_7, HSIOM_SEL_GPIO},
{1u, 20u, P14_0, HSIOM_SEL_GPIO},
{1u, 21u, P14_1, HSIOM_SEL_GPIO},
{2u, 0u, P18_0, HSIOM_SEL_GPIO},
{2u, 1u, P18_1, HSIOM_SEL_GPIO},
{2u, 2u, P18_2, HSIOM_SEL_GPIO},
{2u, 3u, P18_3, HSIOM_SEL_GPIO},
{2u, 4u, P18_4, HSIOM_SEL_GPIO},
{2u, 5u, P18_5, HSIOM_SEL_GPIO},
{2u, 6u, P18_6, HSIOM_SEL_GPIO},
{2u, 7u, P18_7, HSIOM_SEL_GPIO},
};
/* Connections for: peri_tr_io_input */

90
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/cyhal_xmc7100_144_teqfp.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
@ -367,50 +367,50 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[52] = {
{0u, 5u, P6_5, HSIOM_SEL_GPIO},
{0u, 6u, P6_6, HSIOM_SEL_GPIO},
{0u, 7u, P6_7, HSIOM_SEL_GPIO},
{2u, 0u, P7_0, HSIOM_SEL_GPIO},
{2u, 1u, P7_1, HSIOM_SEL_GPIO},
{2u, 2u, P7_2, HSIOM_SEL_GPIO},
{2u, 3u, P7_3, HSIOM_SEL_GPIO},
{2u, 4u, P7_4, HSIOM_SEL_GPIO},
{2u, 5u, P7_5, HSIOM_SEL_GPIO},
{2u, 6u, P7_6, HSIOM_SEL_GPIO},
{2u, 7u, P7_7, HSIOM_SEL_GPIO},
{3u, 0u, P8_1, HSIOM_SEL_GPIO},
{3u, 1u, P8_2, HSIOM_SEL_GPIO},
{3u, 2u, P8_3, HSIOM_SEL_GPIO},
{3u, 4u, P9_0, HSIOM_SEL_GPIO},
{3u, 5u, P9_1, HSIOM_SEL_GPIO},
{4u, 0u, P10_4, HSIOM_SEL_GPIO},
{4u, 4u, P12_0, HSIOM_SEL_GPIO},
{4u, 5u, P12_1, HSIOM_SEL_GPIO},
{4u, 6u, P12_2, HSIOM_SEL_GPIO},
{4u, 7u, P12_3, HSIOM_SEL_GPIO},
{5u, 0u, P12_4, HSIOM_SEL_GPIO},
{5u, 1u, P12_5, HSIOM_SEL_GPIO},
{5u, 4u, P13_0, HSIOM_SEL_GPIO},
{5u, 5u, P13_1, HSIOM_SEL_GPIO},
{5u, 6u, P13_2, HSIOM_SEL_GPIO},
{5u, 7u, P13_3, HSIOM_SEL_GPIO},
{6u, 0u, P13_4, HSIOM_SEL_GPIO},
{6u, 1u, P13_5, HSIOM_SEL_GPIO},
{6u, 2u, P13_6, HSIOM_SEL_GPIO},
{6u, 3u, P13_7, HSIOM_SEL_GPIO},
{6u, 4u, P14_0, HSIOM_SEL_GPIO},
{6u, 5u, P14_1, HSIOM_SEL_GPIO},
{7u, 0u, P14_4, HSIOM_SEL_GPIO},
{7u, 1u, P14_5, HSIOM_SEL_GPIO},
{7u, 4u, P15_0, HSIOM_SEL_GPIO},
{7u, 5u, P15_1, HSIOM_SEL_GPIO},
{7u, 6u, P15_2, HSIOM_SEL_GPIO},
{7u, 7u, P15_3, HSIOM_SEL_GPIO},
{8u, 0u, P18_0, HSIOM_SEL_GPIO},
{8u, 1u, P18_1, HSIOM_SEL_GPIO},
{8u, 2u, P18_2, HSIOM_SEL_GPIO},
{8u, 3u, P18_3, HSIOM_SEL_GPIO},
{8u, 4u, P18_4, HSIOM_SEL_GPIO},
{8u, 5u, P18_5, HSIOM_SEL_GPIO},
{8u, 6u, P18_6, HSIOM_SEL_GPIO},
{8u, 7u, P18_7, HSIOM_SEL_GPIO},
{0u, 16u, P7_0, HSIOM_SEL_GPIO},
{0u, 17u, P7_1, HSIOM_SEL_GPIO},
{0u, 18u, P7_2, HSIOM_SEL_GPIO},
{0u, 19u, P7_3, HSIOM_SEL_GPIO},
{0u, 20u, P7_4, HSIOM_SEL_GPIO},
{0u, 21u, P7_5, HSIOM_SEL_GPIO},
{0u, 22u, P7_6, HSIOM_SEL_GPIO},
{0u, 23u, P7_7, HSIOM_SEL_GPIO},
{0u, 24u, P8_1, HSIOM_SEL_GPIO},
{0u, 25u, P8_2, HSIOM_SEL_GPIO},
{0u, 26u, P8_3, HSIOM_SEL_GPIO},
{0u, 28u, P9_0, HSIOM_SEL_GPIO},
{0u, 29u, P9_1, HSIOM_SEL_GPIO},
{1u, 0u, P10_4, HSIOM_SEL_GPIO},
{1u, 4u, P12_0, HSIOM_SEL_GPIO},
{1u, 5u, P12_1, HSIOM_SEL_GPIO},
{1u, 6u, P12_2, HSIOM_SEL_GPIO},
{1u, 7u, P12_3, HSIOM_SEL_GPIO},
{1u, 8u, P12_4, HSIOM_SEL_GPIO},
{1u, 9u, P12_5, HSIOM_SEL_GPIO},
{1u, 12u, P13_0, HSIOM_SEL_GPIO},
{1u, 13u, P13_1, HSIOM_SEL_GPIO},
{1u, 14u, P13_2, HSIOM_SEL_GPIO},
{1u, 15u, P13_3, HSIOM_SEL_GPIO},
{1u, 16u, P13_4, HSIOM_SEL_GPIO},
{1u, 17u, P13_5, HSIOM_SEL_GPIO},
{1u, 18u, P13_6, HSIOM_SEL_GPIO},
{1u, 19u, P13_7, HSIOM_SEL_GPIO},
{1u, 20u, P14_0, HSIOM_SEL_GPIO},
{1u, 21u, P14_1, HSIOM_SEL_GPIO},
{1u, 24u, P14_4, HSIOM_SEL_GPIO},
{1u, 25u, P14_5, HSIOM_SEL_GPIO},
{1u, 28u, P15_0, HSIOM_SEL_GPIO},
{1u, 29u, P15_1, HSIOM_SEL_GPIO},
{1u, 30u, P15_2, HSIOM_SEL_GPIO},
{1u, 31u, P15_3, HSIOM_SEL_GPIO},
{2u, 0u, P18_0, HSIOM_SEL_GPIO},
{2u, 1u, P18_1, HSIOM_SEL_GPIO},
{2u, 2u, P18_2, HSIOM_SEL_GPIO},
{2u, 3u, P18_3, HSIOM_SEL_GPIO},
{2u, 4u, P18_4, HSIOM_SEL_GPIO},
{2u, 5u, P18_5, HSIOM_SEL_GPIO},
{2u, 6u, P18_6, HSIOM_SEL_GPIO},
{2u, 7u, P18_7, HSIOM_SEL_GPIO},
};
/* Connections for: peri_tr_io_input */

114
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/cyhal_xmc7100_176_teqfp.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
@ -400,62 +400,62 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[64] = {
{0u, 5u, P6_5, HSIOM_SEL_GPIO},
{0u, 6u, P6_6, HSIOM_SEL_GPIO},
{0u, 7u, P6_7, HSIOM_SEL_GPIO},
{2u, 0u, P7_0, HSIOM_SEL_GPIO},
{2u, 1u, P7_1, HSIOM_SEL_GPIO},
{2u, 2u, P7_2, HSIOM_SEL_GPIO},
{2u, 3u, P7_3, HSIOM_SEL_GPIO},
{2u, 4u, P7_4, HSIOM_SEL_GPIO},
{2u, 5u, P7_5, HSIOM_SEL_GPIO},
{2u, 6u, P7_6, HSIOM_SEL_GPIO},
{2u, 7u, P7_7, HSIOM_SEL_GPIO},
{3u, 0u, P8_1, HSIOM_SEL_GPIO},
{3u, 1u, P8_2, HSIOM_SEL_GPIO},
{3u, 2u, P8_3, HSIOM_SEL_GPIO},
{3u, 3u, P8_4, HSIOM_SEL_GPIO},
{3u, 4u, P9_0, HSIOM_SEL_GPIO},
{3u, 5u, P9_1, HSIOM_SEL_GPIO},
{3u, 6u, P9_2, HSIOM_SEL_GPIO},
{3u, 7u, P9_3, HSIOM_SEL_GPIO},
{4u, 0u, P10_4, HSIOM_SEL_GPIO},
{4u, 1u, P10_5, HSIOM_SEL_GPIO},
{4u, 2u, P10_6, HSIOM_SEL_GPIO},
{4u, 3u, P10_7, HSIOM_SEL_GPIO},
{4u, 4u, P12_0, HSIOM_SEL_GPIO},
{4u, 5u, P12_1, HSIOM_SEL_GPIO},
{4u, 6u, P12_2, HSIOM_SEL_GPIO},
{4u, 7u, P12_3, HSIOM_SEL_GPIO},
{5u, 0u, P12_4, HSIOM_SEL_GPIO},
{5u, 1u, P12_5, HSIOM_SEL_GPIO},
{5u, 2u, P12_6, HSIOM_SEL_GPIO},
{5u, 3u, P12_7, HSIOM_SEL_GPIO},
{5u, 4u, P13_0, HSIOM_SEL_GPIO},
{5u, 5u, P13_1, HSIOM_SEL_GPIO},
{5u, 6u, P13_2, HSIOM_SEL_GPIO},
{5u, 7u, P13_3, HSIOM_SEL_GPIO},
{6u, 0u, P13_4, HSIOM_SEL_GPIO},
{6u, 1u, P13_5, HSIOM_SEL_GPIO},
{6u, 2u, P13_6, HSIOM_SEL_GPIO},
{6u, 3u, P13_7, HSIOM_SEL_GPIO},
{6u, 4u, P14_0, HSIOM_SEL_GPIO},
{6u, 5u, P14_1, HSIOM_SEL_GPIO},
{6u, 6u, P14_2, HSIOM_SEL_GPIO},
{6u, 7u, P14_3, HSIOM_SEL_GPIO},
{7u, 0u, P14_4, HSIOM_SEL_GPIO},
{7u, 1u, P14_5, HSIOM_SEL_GPIO},
{7u, 2u, P14_6, HSIOM_SEL_GPIO},
{7u, 3u, P14_7, HSIOM_SEL_GPIO},
{7u, 4u, P15_0, HSIOM_SEL_GPIO},
{7u, 5u, P15_1, HSIOM_SEL_GPIO},
{7u, 6u, P15_2, HSIOM_SEL_GPIO},
{7u, 7u, P15_3, HSIOM_SEL_GPIO},
{8u, 0u, P18_0, HSIOM_SEL_GPIO},
{8u, 1u, P18_1, HSIOM_SEL_GPIO},
{8u, 2u, P18_2, HSIOM_SEL_GPIO},
{8u, 3u, P18_3, HSIOM_SEL_GPIO},
{8u, 4u, P18_4, HSIOM_SEL_GPIO},
{8u, 5u, P18_5, HSIOM_SEL_GPIO},
{8u, 6u, P18_6, HSIOM_SEL_GPIO},
{8u, 7u, P18_7, HSIOM_SEL_GPIO},
{0u, 16u, P7_0, HSIOM_SEL_GPIO},
{0u, 17u, P7_1, HSIOM_SEL_GPIO},
{0u, 18u, P7_2, HSIOM_SEL_GPIO},
{0u, 19u, P7_3, HSIOM_SEL_GPIO},
{0u, 20u, P7_4, HSIOM_SEL_GPIO},
{0u, 21u, P7_5, HSIOM_SEL_GPIO},
{0u, 22u, P7_6, HSIOM_SEL_GPIO},
{0u, 23u, P7_7, HSIOM_SEL_GPIO},
{0u, 24u, P8_1, HSIOM_SEL_GPIO},
{0u, 25u, P8_2, HSIOM_SEL_GPIO},
{0u, 26u, P8_3, HSIOM_SEL_GPIO},
{0u, 27u, P8_4, HSIOM_SEL_GPIO},
{0u, 28u, P9_0, HSIOM_SEL_GPIO},
{0u, 29u, P9_1, HSIOM_SEL_GPIO},
{0u, 30u, P9_2, HSIOM_SEL_GPIO},
{0u, 31u, P9_3, HSIOM_SEL_GPIO},
{1u, 0u, P10_4, HSIOM_SEL_GPIO},
{1u, 1u, P10_5, HSIOM_SEL_GPIO},
{1u, 2u, P10_6, HSIOM_SEL_GPIO},
{1u, 3u, P10_7, HSIOM_SEL_GPIO},
{1u, 4u, P12_0, HSIOM_SEL_GPIO},
{1u, 5u, P12_1, HSIOM_SEL_GPIO},
{1u, 6u, P12_2, HSIOM_SEL_GPIO},
{1u, 7u, P12_3, HSIOM_SEL_GPIO},
{1u, 8u, P12_4, HSIOM_SEL_GPIO},
{1u, 9u, P12_5, HSIOM_SEL_GPIO},
{1u, 10u, P12_6, HSIOM_SEL_GPIO},
{1u, 11u, P12_7, HSIOM_SEL_GPIO},
{1u, 12u, P13_0, HSIOM_SEL_GPIO},
{1u, 13u, P13_1, HSIOM_SEL_GPIO},
{1u, 14u, P13_2, HSIOM_SEL_GPIO},
{1u, 15u, P13_3, HSIOM_SEL_GPIO},
{1u, 16u, P13_4, HSIOM_SEL_GPIO},
{1u, 17u, P13_5, HSIOM_SEL_GPIO},
{1u, 18u, P13_6, HSIOM_SEL_GPIO},
{1u, 19u, P13_7, HSIOM_SEL_GPIO},
{1u, 20u, P14_0, HSIOM_SEL_GPIO},
{1u, 21u, P14_1, HSIOM_SEL_GPIO},
{1u, 22u, P14_2, HSIOM_SEL_GPIO},
{1u, 23u, P14_3, HSIOM_SEL_GPIO},
{1u, 24u, P14_4, HSIOM_SEL_GPIO},
{1u, 25u, P14_5, HSIOM_SEL_GPIO},
{1u, 26u, P14_6, HSIOM_SEL_GPIO},
{1u, 27u, P14_7, HSIOM_SEL_GPIO},
{1u, 28u, P15_0, HSIOM_SEL_GPIO},
{1u, 29u, P15_1, HSIOM_SEL_GPIO},
{1u, 30u, P15_2, HSIOM_SEL_GPIO},
{1u, 31u, P15_3, HSIOM_SEL_GPIO},
{2u, 0u, P18_0, HSIOM_SEL_GPIO},
{2u, 1u, P18_1, HSIOM_SEL_GPIO},
{2u, 2u, P18_2, HSIOM_SEL_GPIO},
{2u, 3u, P18_3, HSIOM_SEL_GPIO},
{2u, 4u, P18_4, HSIOM_SEL_GPIO},
{2u, 5u, P18_5, HSIOM_SEL_GPIO},
{2u, 6u, P18_6, HSIOM_SEL_GPIO},
{2u, 7u, P18_7, HSIOM_SEL_GPIO},
};
/* Connections for: peri_tr_io_input */

130
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
@ -414,70 +414,70 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[72] = {
{0u, 5u, P6_5, HSIOM_SEL_GPIO},
{0u, 6u, P6_6, HSIOM_SEL_GPIO},
{0u, 7u, P6_7, HSIOM_SEL_GPIO},
{2u, 0u, P7_0, HSIOM_SEL_GPIO},
{2u, 1u, P7_1, HSIOM_SEL_GPIO},
{2u, 2u, P7_2, HSIOM_SEL_GPIO},
{2u, 3u, P7_3, HSIOM_SEL_GPIO},
{2u, 4u, P7_4, HSIOM_SEL_GPIO},
{2u, 5u, P7_5, HSIOM_SEL_GPIO},
{2u, 6u, P7_6, HSIOM_SEL_GPIO},
{2u, 7u, P7_7, HSIOM_SEL_GPIO},
{3u, 0u, P8_1, HSIOM_SEL_GPIO},
{3u, 1u, P8_2, HSIOM_SEL_GPIO},
{3u, 2u, P8_3, HSIOM_SEL_GPIO},
{3u, 3u, P8_4, HSIOM_SEL_GPIO},
{3u, 4u, P9_0, HSIOM_SEL_GPIO},
{3u, 5u, P9_1, HSIOM_SEL_GPIO},
{3u, 6u, P9_2, HSIOM_SEL_GPIO},
{3u, 7u, P9_3, HSIOM_SEL_GPIO},
{4u, 0u, P10_4, HSIOM_SEL_GPIO},
{4u, 1u, P10_5, HSIOM_SEL_GPIO},
{4u, 2u, P10_6, HSIOM_SEL_GPIO},
{4u, 3u, P10_7, HSIOM_SEL_GPIO},
{4u, 4u, P12_0, HSIOM_SEL_GPIO},
{4u, 5u, P12_1, HSIOM_SEL_GPIO},
{4u, 6u, P12_2, HSIOM_SEL_GPIO},
{4u, 7u, P12_3, HSIOM_SEL_GPIO},
{5u, 0u, P12_4, HSIOM_SEL_GPIO},
{5u, 1u, P12_5, HSIOM_SEL_GPIO},
{5u, 2u, P12_6, HSIOM_SEL_GPIO},
{5u, 3u, P12_7, HSIOM_SEL_GPIO},
{5u, 4u, P13_0, HSIOM_SEL_GPIO},
{5u, 5u, P13_1, HSIOM_SEL_GPIO},
{5u, 6u, P13_2, HSIOM_SEL_GPIO},
{5u, 7u, P13_3, HSIOM_SEL_GPIO},
{6u, 0u, P13_4, HSIOM_SEL_GPIO},
{6u, 1u, P13_5, HSIOM_SEL_GPIO},
{6u, 2u, P13_6, HSIOM_SEL_GPIO},
{6u, 3u, P13_7, HSIOM_SEL_GPIO},
{6u, 4u, P14_0, HSIOM_SEL_GPIO},
{6u, 5u, P14_1, HSIOM_SEL_GPIO},
{6u, 6u, P14_2, HSIOM_SEL_GPIO},
{6u, 7u, P14_3, HSIOM_SEL_GPIO},
{7u, 0u, P14_4, HSIOM_SEL_GPIO},
{7u, 1u, P14_5, HSIOM_SEL_GPIO},
{7u, 2u, P14_6, HSIOM_SEL_GPIO},
{7u, 3u, P14_7, HSIOM_SEL_GPIO},
{7u, 4u, P15_0, HSIOM_SEL_GPIO},
{7u, 5u, P15_1, HSIOM_SEL_GPIO},
{7u, 6u, P15_2, HSIOM_SEL_GPIO},
{7u, 7u, P15_3, HSIOM_SEL_GPIO},
{8u, 0u, P18_0, HSIOM_SEL_GPIO},
{8u, 1u, P18_1, HSIOM_SEL_GPIO},
{8u, 2u, P18_2, HSIOM_SEL_GPIO},
{8u, 3u, P18_3, HSIOM_SEL_GPIO},
{8u, 4u, P18_4, HSIOM_SEL_GPIO},
{8u, 5u, P18_5, HSIOM_SEL_GPIO},
{8u, 6u, P18_6, HSIOM_SEL_GPIO},
{8u, 7u, P18_7, HSIOM_SEL_GPIO},
{1u, 0u, P32_0, HSIOM_SEL_GPIO},
{1u, 1u, P32_1, HSIOM_SEL_GPIO},
{1u, 2u, P32_2, HSIOM_SEL_GPIO},
{1u, 3u, P32_3, HSIOM_SEL_GPIO},
{1u, 4u, P32_4, HSIOM_SEL_GPIO},
{1u, 5u, P32_5, HSIOM_SEL_GPIO},
{1u, 6u, P32_6, HSIOM_SEL_GPIO},
{1u, 7u, P32_7, HSIOM_SEL_GPIO},
{0u, 16u, P7_0, HSIOM_SEL_GPIO},
{0u, 17u, P7_1, HSIOM_SEL_GPIO},
{0u, 18u, P7_2, HSIOM_SEL_GPIO},
{0u, 19u, P7_3, HSIOM_SEL_GPIO},
{0u, 20u, P7_4, HSIOM_SEL_GPIO},
{0u, 21u, P7_5, HSIOM_SEL_GPIO},
{0u, 22u, P7_6, HSIOM_SEL_GPIO},
{0u, 23u, P7_7, HSIOM_SEL_GPIO},
{0u, 24u, P8_1, HSIOM_SEL_GPIO},
{0u, 25u, P8_2, HSIOM_SEL_GPIO},
{0u, 26u, P8_3, HSIOM_SEL_GPIO},
{0u, 27u, P8_4, HSIOM_SEL_GPIO},
{0u, 28u, P9_0, HSIOM_SEL_GPIO},
{0u, 29u, P9_1, HSIOM_SEL_GPIO},
{0u, 30u, P9_2, HSIOM_SEL_GPIO},
{0u, 31u, P9_3, HSIOM_SEL_GPIO},
{1u, 0u, P10_4, HSIOM_SEL_GPIO},
{1u, 1u, P10_5, HSIOM_SEL_GPIO},
{1u, 2u, P10_6, HSIOM_SEL_GPIO},
{1u, 3u, P10_7, HSIOM_SEL_GPIO},
{1u, 4u, P12_0, HSIOM_SEL_GPIO},
{1u, 5u, P12_1, HSIOM_SEL_GPIO},
{1u, 6u, P12_2, HSIOM_SEL_GPIO},
{1u, 7u, P12_3, HSIOM_SEL_GPIO},
{1u, 8u, P12_4, HSIOM_SEL_GPIO},
{1u, 9u, P12_5, HSIOM_SEL_GPIO},
{1u, 10u, P12_6, HSIOM_SEL_GPIO},
{1u, 11u, P12_7, HSIOM_SEL_GPIO},
{1u, 12u, P13_0, HSIOM_SEL_GPIO},
{1u, 13u, P13_1, HSIOM_SEL_GPIO},
{1u, 14u, P13_2, HSIOM_SEL_GPIO},
{1u, 15u, P13_3, HSIOM_SEL_GPIO},
{1u, 16u, P13_4, HSIOM_SEL_GPIO},
{1u, 17u, P13_5, HSIOM_SEL_GPIO},
{1u, 18u, P13_6, HSIOM_SEL_GPIO},
{1u, 19u, P13_7, HSIOM_SEL_GPIO},
{1u, 20u, P14_0, HSIOM_SEL_GPIO},
{1u, 21u, P14_1, HSIOM_SEL_GPIO},
{1u, 22u, P14_2, HSIOM_SEL_GPIO},
{1u, 23u, P14_3, HSIOM_SEL_GPIO},
{1u, 24u, P14_4, HSIOM_SEL_GPIO},
{1u, 25u, P14_5, HSIOM_SEL_GPIO},
{1u, 26u, P14_6, HSIOM_SEL_GPIO},
{1u, 27u, P14_7, HSIOM_SEL_GPIO},
{1u, 28u, P15_0, HSIOM_SEL_GPIO},
{1u, 29u, P15_1, HSIOM_SEL_GPIO},
{1u, 30u, P15_2, HSIOM_SEL_GPIO},
{1u, 31u, P15_3, HSIOM_SEL_GPIO},
{2u, 0u, P18_0, HSIOM_SEL_GPIO},
{2u, 1u, P18_1, HSIOM_SEL_GPIO},
{2u, 2u, P18_2, HSIOM_SEL_GPIO},
{2u, 3u, P18_3, HSIOM_SEL_GPIO},
{2u, 4u, P18_4, HSIOM_SEL_GPIO},
{2u, 5u, P18_5, HSIOM_SEL_GPIO},
{2u, 6u, P18_6, HSIOM_SEL_GPIO},
{2u, 7u, P18_7, HSIOM_SEL_GPIO},
{0u, 8u, P32_0, HSIOM_SEL_GPIO},
{0u, 9u, P32_1, HSIOM_SEL_GPIO},
{0u, 10u, P32_2, HSIOM_SEL_GPIO},
{0u, 11u, P32_3, HSIOM_SEL_GPIO},
{0u, 12u, P32_4, HSIOM_SEL_GPIO},
{0u, 13u, P32_5, HSIOM_SEL_GPIO},
{0u, 14u, P32_6, HSIOM_SEL_GPIO},
{0u, 15u, P32_7, HSIOM_SEL_GPIO},
};
/* Connections for: peri_tr_io_input */

148
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
@ -437,79 +437,79 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[81] = {
{0u, 5u, P6_5, HSIOM_SEL_GPIO},
{0u, 6u, P6_6, HSIOM_SEL_GPIO},
{0u, 7u, P6_7, HSIOM_SEL_GPIO},
{2u, 0u, P7_0, HSIOM_SEL_GPIO},
{2u, 1u, P7_1, HSIOM_SEL_GPIO},
{2u, 2u, P7_2, HSIOM_SEL_GPIO},
{2u, 3u, P7_3, HSIOM_SEL_GPIO},
{2u, 4u, P7_4, HSIOM_SEL_GPIO},
{2u, 5u, P7_5, HSIOM_SEL_GPIO},
{2u, 6u, P7_6, HSIOM_SEL_GPIO},
{2u, 7u, P7_7, HSIOM_SEL_GPIO},
{3u, 0u, P8_1, HSIOM_SEL_GPIO},
{3u, 1u, P8_2, HSIOM_SEL_GPIO},
{3u, 2u, P8_3, HSIOM_SEL_GPIO},
{3u, 3u, P8_4, HSIOM_SEL_GPIO},
{3u, 4u, P9_0, HSIOM_SEL_GPIO},
{3u, 5u, P9_1, HSIOM_SEL_GPIO},
{3u, 6u, P9_2, HSIOM_SEL_GPIO},
{3u, 7u, P9_3, HSIOM_SEL_GPIO},
{4u, 0u, P10_4, HSIOM_SEL_GPIO},
{4u, 1u, P10_5, HSIOM_SEL_GPIO},
{4u, 2u, P10_6, HSIOM_SEL_GPIO},
{4u, 3u, P10_7, HSIOM_SEL_GPIO},
{4u, 4u, P12_0, HSIOM_SEL_GPIO},
{4u, 5u, P12_1, HSIOM_SEL_GPIO},
{4u, 6u, P12_2, HSIOM_SEL_GPIO},
{4u, 7u, P12_3, HSIOM_SEL_GPIO},
{5u, 0u, P12_4, HSIOM_SEL_GPIO},
{5u, 1u, P12_5, HSIOM_SEL_GPIO},
{5u, 2u, P12_6, HSIOM_SEL_GPIO},
{5u, 3u, P12_7, HSIOM_SEL_GPIO},
{5u, 4u, P13_0, HSIOM_SEL_GPIO},
{5u, 5u, P13_1, HSIOM_SEL_GPIO},
{5u, 6u, P13_2, HSIOM_SEL_GPIO},
{5u, 7u, P13_3, HSIOM_SEL_GPIO},
{6u, 0u, P13_4, HSIOM_SEL_GPIO},
{6u, 1u, P13_5, HSIOM_SEL_GPIO},
{6u, 2u, P13_6, HSIOM_SEL_GPIO},
{6u, 3u, P13_7, HSIOM_SEL_GPIO},
{6u, 4u, P14_0, HSIOM_SEL_GPIO},
{6u, 5u, P14_1, HSIOM_SEL_GPIO},
{6u, 6u, P14_2, HSIOM_SEL_GPIO},
{6u, 7u, P14_3, HSIOM_SEL_GPIO},
{7u, 0u, P14_4, HSIOM_SEL_GPIO},
{7u, 1u, P14_5, HSIOM_SEL_GPIO},
{7u, 2u, P14_6, HSIOM_SEL_GPIO},
{7u, 3u, P14_7, HSIOM_SEL_GPIO},
{7u, 4u, P15_0, HSIOM_SEL_GPIO},
{7u, 5u, P15_1, HSIOM_SEL_GPIO},
{7u, 6u, P15_2, HSIOM_SEL_GPIO},
{7u, 7u, P15_3, HSIOM_SEL_GPIO},
{8u, 3u, P16_3, HSIOM_SEL_GPIO},
{9u, 0u, P17_0, HSIOM_SEL_GPIO},
{9u, 1u, P17_1, HSIOM_SEL_GPIO},
{9u, 2u, P17_2, HSIOM_SEL_GPIO},
{9u, 3u, P17_3, HSIOM_SEL_GPIO},
{9u, 4u, P17_4, HSIOM_SEL_GPIO},
{9u, 5u, P17_5, HSIOM_SEL_GPIO},
{9u, 6u, P17_6, HSIOM_SEL_GPIO},
{9u, 7u, P17_7, HSIOM_SEL_GPIO},
{10u, 0u, P18_0, HSIOM_SEL_GPIO},
{10u, 1u, P18_1, HSIOM_SEL_GPIO},
{10u, 2u, P18_2, HSIOM_SEL_GPIO},
{10u, 3u, P18_3, HSIOM_SEL_GPIO},
{10u, 4u, P18_4, HSIOM_SEL_GPIO},
{10u, 5u, P18_5, HSIOM_SEL_GPIO},
{10u, 6u, P18_6, HSIOM_SEL_GPIO},
{10u, 7u, P18_7, HSIOM_SEL_GPIO},
{11u, 0u, P19_0, HSIOM_SEL_GPIO},
{11u, 1u, P19_1, HSIOM_SEL_GPIO},
{11u, 2u, P19_2, HSIOM_SEL_GPIO},
{11u, 3u, P19_3, HSIOM_SEL_GPIO},
{11u, 4u, P19_4, HSIOM_SEL_GPIO},
{11u, 5u, P20_0, HSIOM_SEL_GPIO},
{11u, 6u, P20_1, HSIOM_SEL_GPIO},
{11u, 7u, P20_2, HSIOM_SEL_GPIO},
{0u, 16u, P7_0, HSIOM_SEL_GPIO},
{0u, 17u, P7_1, HSIOM_SEL_GPIO},
{0u, 18u, P7_2, HSIOM_SEL_GPIO},
{0u, 19u, P7_3, HSIOM_SEL_GPIO},
{0u, 20u, P7_4, HSIOM_SEL_GPIO},
{0u, 21u, P7_5, HSIOM_SEL_GPIO},
{0u, 22u, P7_6, HSIOM_SEL_GPIO},
{0u, 23u, P7_7, HSIOM_SEL_GPIO},
{0u, 24u, P8_1, HSIOM_SEL_GPIO},
{0u, 25u, P8_2, HSIOM_SEL_GPIO},
{0u, 26u, P8_3, HSIOM_SEL_GPIO},
{0u, 27u, P8_4, HSIOM_SEL_GPIO},
{0u, 28u, P9_0, HSIOM_SEL_GPIO},
{0u, 29u, P9_1, HSIOM_SEL_GPIO},
{0u, 30u, P9_2, HSIOM_SEL_GPIO},
{0u, 31u, P9_3, HSIOM_SEL_GPIO},
{1u, 0u, P10_4, HSIOM_SEL_GPIO},
{1u, 1u, P10_5, HSIOM_SEL_GPIO},
{1u, 2u, P10_6, HSIOM_SEL_GPIO},
{1u, 3u, P10_7, HSIOM_SEL_GPIO},
{1u, 4u, P12_0, HSIOM_SEL_GPIO},
{1u, 5u, P12_1, HSIOM_SEL_GPIO},
{1u, 6u, P12_2, HSIOM_SEL_GPIO},
{1u, 7u, P12_3, HSIOM_SEL_GPIO},
{1u, 8u, P12_4, HSIOM_SEL_GPIO},
{1u, 9u, P12_5, HSIOM_SEL_GPIO},
{1u, 10u, P12_6, HSIOM_SEL_GPIO},
{1u, 11u, P12_7, HSIOM_SEL_GPIO},
{1u, 12u, P13_0, HSIOM_SEL_GPIO},
{1u, 13u, P13_1, HSIOM_SEL_GPIO},
{1u, 14u, P13_2, HSIOM_SEL_GPIO},
{1u, 15u, P13_3, HSIOM_SEL_GPIO},
{1u, 16u, P13_4, HSIOM_SEL_GPIO},
{1u, 17u, P13_5, HSIOM_SEL_GPIO},
{1u, 18u, P13_6, HSIOM_SEL_GPIO},
{1u, 19u, P13_7, HSIOM_SEL_GPIO},
{1u, 20u, P14_0, HSIOM_SEL_GPIO},
{1u, 21u, P14_1, HSIOM_SEL_GPIO},
{1u, 22u, P14_2, HSIOM_SEL_GPIO},
{1u, 23u, P14_3, HSIOM_SEL_GPIO},
{1u, 24u, P14_4, HSIOM_SEL_GPIO},
{1u, 25u, P14_5, HSIOM_SEL_GPIO},
{1u, 26u, P14_6, HSIOM_SEL_GPIO},
{1u, 27u, P14_7, HSIOM_SEL_GPIO},
{1u, 28u, P15_0, HSIOM_SEL_GPIO},
{1u, 29u, P15_1, HSIOM_SEL_GPIO},
{1u, 30u, P15_2, HSIOM_SEL_GPIO},
{1u, 31u, P15_3, HSIOM_SEL_GPIO},
{2u, 3u, P16_3, HSIOM_SEL_GPIO},
{2u, 8u, P17_0, HSIOM_SEL_GPIO},
{2u, 9u, P17_1, HSIOM_SEL_GPIO},
{2u, 10u, P17_2, HSIOM_SEL_GPIO},
{2u, 11u, P17_3, HSIOM_SEL_GPIO},
{2u, 12u, P17_4, HSIOM_SEL_GPIO},
{2u, 13u, P17_5, HSIOM_SEL_GPIO},
{2u, 14u, P17_6, HSIOM_SEL_GPIO},
{2u, 15u, P17_7, HSIOM_SEL_GPIO},
{2u, 16u, P18_0, HSIOM_SEL_GPIO},
{2u, 17u, P18_1, HSIOM_SEL_GPIO},
{2u, 18u, P18_2, HSIOM_SEL_GPIO},
{2u, 19u, P18_3, HSIOM_SEL_GPIO},
{2u, 20u, P18_4, HSIOM_SEL_GPIO},
{2u, 21u, P18_5, HSIOM_SEL_GPIO},
{2u, 22u, P18_6, HSIOM_SEL_GPIO},
{2u, 23u, P18_7, HSIOM_SEL_GPIO},
{2u, 24u, P19_0, HSIOM_SEL_GPIO},
{2u, 25u, P19_1, HSIOM_SEL_GPIO},
{2u, 26u, P19_2, HSIOM_SEL_GPIO},
{2u, 27u, P19_3, HSIOM_SEL_GPIO},
{2u, 28u, P19_4, HSIOM_SEL_GPIO},
{2u, 29u, P20_0, HSIOM_SEL_GPIO},
{2u, 30u, P20_1, HSIOM_SEL_GPIO},
{2u, 31u, P20_2, HSIOM_SEL_GPIO},
};
/* Connections for: peri_tr_io_input */

178
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/cyhal_xmc7200_272_bga.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
@ -493,94 +493,94 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[96] = {
{0u, 5u, P6_5, HSIOM_SEL_GPIO},
{0u, 6u, P6_6, HSIOM_SEL_GPIO},
{0u, 7u, P6_7, HSIOM_SEL_GPIO},
{2u, 0u, P7_0, HSIOM_SEL_GPIO},
{2u, 1u, P7_1, HSIOM_SEL_GPIO},
{2u, 2u, P7_2, HSIOM_SEL_GPIO},
{2u, 3u, P7_3, HSIOM_SEL_GPIO},
{2u, 4u, P7_4, HSIOM_SEL_GPIO},
{2u, 5u, P7_5, HSIOM_SEL_GPIO},
{2u, 6u, P7_6, HSIOM_SEL_GPIO},
{2u, 7u, P7_7, HSIOM_SEL_GPIO},
{3u, 0u, P8_1, HSIOM_SEL_GPIO},
{3u, 1u, P8_2, HSIOM_SEL_GPIO},
{3u, 2u, P8_3, HSIOM_SEL_GPIO},
{3u, 3u, P8_4, HSIOM_SEL_GPIO},
{3u, 4u, P9_0, HSIOM_SEL_GPIO},
{3u, 5u, P9_1, HSIOM_SEL_GPIO},
{3u, 6u, P9_2, HSIOM_SEL_GPIO},
{3u, 7u, P9_3, HSIOM_SEL_GPIO},
{4u, 0u, P10_4, HSIOM_SEL_GPIO},
{4u, 1u, P10_5, HSIOM_SEL_GPIO},
{4u, 2u, P10_6, HSIOM_SEL_GPIO},
{4u, 3u, P10_7, HSIOM_SEL_GPIO},
{4u, 4u, P12_0, HSIOM_SEL_GPIO},
{4u, 5u, P12_1, HSIOM_SEL_GPIO},
{4u, 6u, P12_2, HSIOM_SEL_GPIO},
{4u, 7u, P12_3, HSIOM_SEL_GPIO},
{5u, 0u, P12_4, HSIOM_SEL_GPIO},
{5u, 1u, P12_5, HSIOM_SEL_GPIO},
{5u, 2u, P12_6, HSIOM_SEL_GPIO},
{5u, 3u, P12_7, HSIOM_SEL_GPIO},
{5u, 4u, P13_0, HSIOM_SEL_GPIO},
{5u, 5u, P13_1, HSIOM_SEL_GPIO},
{5u, 6u, P13_2, HSIOM_SEL_GPIO},
{5u, 7u, P13_3, HSIOM_SEL_GPIO},
{6u, 0u, P13_4, HSIOM_SEL_GPIO},
{6u, 1u, P13_5, HSIOM_SEL_GPIO},
{6u, 2u, P13_6, HSIOM_SEL_GPIO},
{6u, 3u, P13_7, HSIOM_SEL_GPIO},
{6u, 4u, P14_0, HSIOM_SEL_GPIO},
{6u, 5u, P14_1, HSIOM_SEL_GPIO},
{6u, 6u, P14_2, HSIOM_SEL_GPIO},
{6u, 7u, P14_3, HSIOM_SEL_GPIO},
{7u, 0u, P14_4, HSIOM_SEL_GPIO},
{7u, 1u, P14_5, HSIOM_SEL_GPIO},
{7u, 2u, P14_6, HSIOM_SEL_GPIO},
{7u, 3u, P14_7, HSIOM_SEL_GPIO},
{7u, 4u, P15_0, HSIOM_SEL_GPIO},
{7u, 5u, P15_1, HSIOM_SEL_GPIO},
{7u, 6u, P15_2, HSIOM_SEL_GPIO},
{7u, 7u, P15_3, HSIOM_SEL_GPIO},
{8u, 0u, P16_0, HSIOM_SEL_GPIO},
{8u, 1u, P16_1, HSIOM_SEL_GPIO},
{8u, 2u, P16_2, HSIOM_SEL_GPIO},
{8u, 3u, P16_3, HSIOM_SEL_GPIO},
{8u, 4u, P16_4, HSIOM_SEL_GPIO},
{8u, 5u, P16_5, HSIOM_SEL_GPIO},
{8u, 6u, P16_6, HSIOM_SEL_GPIO},
{8u, 7u, P16_7, HSIOM_SEL_GPIO},
{9u, 0u, P17_0, HSIOM_SEL_GPIO},
{9u, 1u, P17_1, HSIOM_SEL_GPIO},
{9u, 2u, P17_2, HSIOM_SEL_GPIO},
{9u, 3u, P17_3, HSIOM_SEL_GPIO},
{9u, 4u, P17_4, HSIOM_SEL_GPIO},
{9u, 5u, P17_5, HSIOM_SEL_GPIO},
{9u, 6u, P17_6, HSIOM_SEL_GPIO},
{9u, 7u, P17_7, HSIOM_SEL_GPIO},
{10u, 0u, P18_0, HSIOM_SEL_GPIO},
{10u, 1u, P18_1, HSIOM_SEL_GPIO},
{10u, 2u, P18_2, HSIOM_SEL_GPIO},
{10u, 3u, P18_3, HSIOM_SEL_GPIO},
{10u, 4u, P18_4, HSIOM_SEL_GPIO},
{10u, 5u, P18_5, HSIOM_SEL_GPIO},
{10u, 6u, P18_6, HSIOM_SEL_GPIO},
{10u, 7u, P18_7, HSIOM_SEL_GPIO},
{11u, 0u, P19_0, HSIOM_SEL_GPIO},
{11u, 1u, P19_1, HSIOM_SEL_GPIO},
{11u, 2u, P19_2, HSIOM_SEL_GPIO},
{11u, 3u, P19_3, HSIOM_SEL_GPIO},
{11u, 4u, P19_4, HSIOM_SEL_GPIO},
{11u, 5u, P20_0, HSIOM_SEL_GPIO},
{11u, 6u, P20_1, HSIOM_SEL_GPIO},
{11u, 7u, P20_2, HSIOM_SEL_GPIO},
{1u, 0u, P32_0, HSIOM_SEL_GPIO},
{1u, 1u, P32_1, HSIOM_SEL_GPIO},
{1u, 2u, P32_2, HSIOM_SEL_GPIO},
{1u, 3u, P32_3, HSIOM_SEL_GPIO},
{1u, 4u, P32_4, HSIOM_SEL_GPIO},
{1u, 5u, P32_5, HSIOM_SEL_GPIO},
{1u, 6u, P32_6, HSIOM_SEL_GPIO},
{1u, 7u, P32_7, HSIOM_SEL_GPIO},
{0u, 16u, P7_0, HSIOM_SEL_GPIO},
{0u, 17u, P7_1, HSIOM_SEL_GPIO},
{0u, 18u, P7_2, HSIOM_SEL_GPIO},
{0u, 19u, P7_3, HSIOM_SEL_GPIO},
{0u, 20u, P7_4, HSIOM_SEL_GPIO},
{0u, 21u, P7_5, HSIOM_SEL_GPIO},
{0u, 22u, P7_6, HSIOM_SEL_GPIO},
{0u, 23u, P7_7, HSIOM_SEL_GPIO},
{0u, 24u, P8_1, HSIOM_SEL_GPIO},
{0u, 25u, P8_2, HSIOM_SEL_GPIO},
{0u, 26u, P8_3, HSIOM_SEL_GPIO},
{0u, 27u, P8_4, HSIOM_SEL_GPIO},
{0u, 28u, P9_0, HSIOM_SEL_GPIO},
{0u, 29u, P9_1, HSIOM_SEL_GPIO},
{0u, 30u, P9_2, HSIOM_SEL_GPIO},
{0u, 31u, P9_3, HSIOM_SEL_GPIO},
{1u, 0u, P10_4, HSIOM_SEL_GPIO},
{1u, 1u, P10_5, HSIOM_SEL_GPIO},
{1u, 2u, P10_6, HSIOM_SEL_GPIO},
{1u, 3u, P10_7, HSIOM_SEL_GPIO},
{1u, 4u, P12_0, HSIOM_SEL_GPIO},
{1u, 5u, P12_1, HSIOM_SEL_GPIO},
{1u, 6u, P12_2, HSIOM_SEL_GPIO},
{1u, 7u, P12_3, HSIOM_SEL_GPIO},
{1u, 8u, P12_4, HSIOM_SEL_GPIO},
{1u, 9u, P12_5, HSIOM_SEL_GPIO},
{1u, 10u, P12_6, HSIOM_SEL_GPIO},
{1u, 11u, P12_7, HSIOM_SEL_GPIO},
{1u, 12u, P13_0, HSIOM_SEL_GPIO},
{1u, 13u, P13_1, HSIOM_SEL_GPIO},
{1u, 14u, P13_2, HSIOM_SEL_GPIO},
{1u, 15u, P13_3, HSIOM_SEL_GPIO},
{1u, 16u, P13_4, HSIOM_SEL_GPIO},
{1u, 17u, P13_5, HSIOM_SEL_GPIO},
{1u, 18u, P13_6, HSIOM_SEL_GPIO},
{1u, 19u, P13_7, HSIOM_SEL_GPIO},
{1u, 20u, P14_0, HSIOM_SEL_GPIO},
{1u, 21u, P14_1, HSIOM_SEL_GPIO},
{1u, 22u, P14_2, HSIOM_SEL_GPIO},
{1u, 23u, P14_3, HSIOM_SEL_GPIO},
{1u, 24u, P14_4, HSIOM_SEL_GPIO},
{1u, 25u, P14_5, HSIOM_SEL_GPIO},
{1u, 26u, P14_6, HSIOM_SEL_GPIO},
{1u, 27u, P14_7, HSIOM_SEL_GPIO},
{1u, 28u, P15_0, HSIOM_SEL_GPIO},
{1u, 29u, P15_1, HSIOM_SEL_GPIO},
{1u, 30u, P15_2, HSIOM_SEL_GPIO},
{1u, 31u, P15_3, HSIOM_SEL_GPIO},
{2u, 0u, P16_0, HSIOM_SEL_GPIO},
{2u, 1u, P16_1, HSIOM_SEL_GPIO},
{2u, 2u, P16_2, HSIOM_SEL_GPIO},
{2u, 3u, P16_3, HSIOM_SEL_GPIO},
{2u, 4u, P16_4, HSIOM_SEL_GPIO},
{2u, 5u, P16_5, HSIOM_SEL_GPIO},
{2u, 6u, P16_6, HSIOM_SEL_GPIO},
{2u, 7u, P16_7, HSIOM_SEL_GPIO},
{2u, 8u, P17_0, HSIOM_SEL_GPIO},
{2u, 9u, P17_1, HSIOM_SEL_GPIO},
{2u, 10u, P17_2, HSIOM_SEL_GPIO},
{2u, 11u, P17_3, HSIOM_SEL_GPIO},
{2u, 12u, P17_4, HSIOM_SEL_GPIO},
{2u, 13u, P17_5, HSIOM_SEL_GPIO},
{2u, 14u, P17_6, HSIOM_SEL_GPIO},
{2u, 15u, P17_7, HSIOM_SEL_GPIO},
{2u, 16u, P18_0, HSIOM_SEL_GPIO},
{2u, 17u, P18_1, HSIOM_SEL_GPIO},
{2u, 18u, P18_2, HSIOM_SEL_GPIO},
{2u, 19u, P18_3, HSIOM_SEL_GPIO},
{2u, 20u, P18_4, HSIOM_SEL_GPIO},
{2u, 21u, P18_5, HSIOM_SEL_GPIO},
{2u, 22u, P18_6, HSIOM_SEL_GPIO},
{2u, 23u, P18_7, HSIOM_SEL_GPIO},
{2u, 24u, P19_0, HSIOM_SEL_GPIO},
{2u, 25u, P19_1, HSIOM_SEL_GPIO},
{2u, 26u, P19_2, HSIOM_SEL_GPIO},
{2u, 27u, P19_3, HSIOM_SEL_GPIO},
{2u, 28u, P19_4, HSIOM_SEL_GPIO},
{2u, 29u, P20_0, HSIOM_SEL_GPIO},
{2u, 30u, P20_1, HSIOM_SEL_GPIO},
{2u, 31u, P20_2, HSIOM_SEL_GPIO},
{0u, 8u, P32_0, HSIOM_SEL_GPIO},
{0u, 9u, P32_1, HSIOM_SEL_GPIO},
{0u, 10u, P32_2, HSIOM_SEL_GPIO},
{0u, 11u, P32_3, HSIOM_SEL_GPIO},
{0u, 12u, P32_4, HSIOM_SEL_GPIO},
{0u, 13u, P32_5, HSIOM_SEL_GPIO},
{0u, 14u, P32_6, HSIOM_SEL_GPIO},
{0u, 15u, P32_7, HSIOM_SEL_GPIO},
};
/* Connections for: peri_tr_io_input */

2224
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/cyhal_xmc7200_320_bga.c Normal file
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File diff suppressed because it is too large Load Diff

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/triggers/cyhal_triggers_xmc7100.c
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C/source/triggers/cyhal_triggers_xmc7200.c
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0

538
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1D/include/pin_packages/cyhal_explorer_144_lqfp.h
View File

@ -1,538 +0,0 @@
/***************************************************************************//**
* \file cyhal_explorer_144_lqfp.h
*
* \brief
* Explorer device GPIO HAL header for 144-LQFP package
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_EXPLORER_144_LQFP_H_
#define _CYHAL_EXPLORER_144_LQFP_H_
#include "cyhal_hw_resources.h"
/**
* \addtogroup group_hal_impl_pin_package_explorer_144_lqfp Explorer 144-LQFP
* \ingroup group_hal_impl_pin_package
* \{
* Pin definitions and connections specific to the Explorer 144-LQFP package.
*/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/** Gets a pin definition from the provided port and pin numbers */
#define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin)))
/** Macro that, given a gpio, will extract the pin number */
#define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U))
/** Macro that, given a gpio, will extract the port number */
#define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U))
/** Definitions for all of the pins that are bonded out on in the 144-LQFP package for the Explorer series. */
typedef enum {
NC = 0xFF, //!< No Connect/Invalid Pin
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6), //!< Port 1 Pin 6
P1_7 = CYHAL_GET_GPIO(CYHAL_PORT_1, 7), //!< Port 1 Pin 7
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0
P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1
P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2
P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3
P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4
P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5), //!< Port 4 Pin 5
P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6), //!< Port 4 Pin 6
P4_7 = CYHAL_GET_GPIO(CYHAL_PORT_4, 7), //!< Port 4 Pin 7
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7
P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1
P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2
P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3
P15_4 = CYHAL_GET_GPIO(CYHAL_PORT_15, 4), //!< Port 15 Pin 4
P15_5 = CYHAL_GET_GPIO(CYHAL_PORT_15, 5), //!< Port 15 Pin 5
P15_6 = CYHAL_GET_GPIO(CYHAL_PORT_15, 6), //!< Port 15 Pin 6
P15_7 = CYHAL_GET_GPIO(CYHAL_PORT_15, 7), //!< Port 15 Pin 7
P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0), //!< Port 16 Pin 0
P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1), //!< Port 16 Pin 1
P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2), //!< Port 16 Pin 2
P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3), //!< Port 16 Pin 3
P16_4 = CYHAL_GET_GPIO(CYHAL_PORT_16, 4), //!< Port 16 Pin 4
P16_5 = CYHAL_GET_GPIO(CYHAL_PORT_16, 5), //!< Port 16 Pin 5
P16_6 = CYHAL_GET_GPIO(CYHAL_PORT_16, 6), //!< Port 16 Pin 6
P16_7 = CYHAL_GET_GPIO(CYHAL_PORT_16, 7), //!< Port 16 Pin 7
P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0
P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1
P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2
P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0
P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1
P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0
P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1
P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0
P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1
P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2
P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0
P24_0 = CYHAL_GET_GPIO(CYHAL_PORT_24, 0), //!< Port 24 Pin 0
} cyhal_gpio_explorer_144_lqfp_t;
/** Create generic name for the series/package specific type. */
typedef cyhal_gpio_explorer_144_lqfp_t cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
uint8_t block_num; //!< The block number of the resource with this connection
uint8_t channel_num; //!< The channel number of the block with this connection
cyhal_gpio_t pin; //!< The GPIO pin the connection is with
en_hsiom_sel_t hsiom; //!< The HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
/** Indicates that a pin map exists for canfd_ttcan_rx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[2];
/** Indicates that a pin map exists for canfd_ttcan_tx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[2];
/** Indicates that a pin map exists for debug600_clk_swj_swclk_tclk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN)
/** List of valid pin to peripheral connections for the debug600_clk_swj_swclk_tclk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1];
/** Indicates that a pin map exists for debug600_rst_swj_trstn*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_RST_SWJ_TRSTN (CY_GPIO_DM_PULLDOWN)
/** List of valid pin to peripheral connections for the debug600_rst_swj_trstn signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1];
/** Indicates that a pin map exists for debug600_swj_swdio_tms*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP)
/** List of valid pin to peripheral connections for the debug600_swj_swdio_tms signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1];
/** Indicates that a pin map exists for debug600_swj_swdoe_tdi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP)
/** List of valid pin to peripheral connections for the debug600_swj_swdoe_tdi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1];
/** Indicates that a pin map exists for debug600_swj_swo_tdo*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the debug600_swj_swo_tdo signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1];
/** Indicates that a pin map exists for debug600_trace_clock*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the debug600_trace_clock signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[2];
/** Indicates that a pin map exists for debug600_trace_data*/
#define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the debug600_trace_data signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[8];
/** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1];
/** Indicates that a pin map exists for eth_mdc*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_mdc signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1];
/** Indicates that a pin map exists for eth_mdio*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_mdio signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1];
/** Indicates that a pin map exists for eth_ref_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_ref_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1];
/** Indicates that a pin map exists for eth_rx_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rx_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1];
/** Indicates that a pin map exists for eth_rx_ctl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rx_ctl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1];
/** Indicates that a pin map exists for eth_rx_er*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rx_er signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1];
/** Indicates that a pin map exists for eth_rxd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the eth_rxd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[2];
/** Indicates that a pin map exists for eth_tx_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_tx_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1];
/** Indicates that a pin map exists for eth_tx_ctl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_tx_ctl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1];
/** Indicates that a pin map exists for eth_txd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the eth_txd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4];
/** Indicates that a pin map exists for gfxss_dbi_csx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_DBI_CSX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_dbi_csx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_csx[1];
/** Indicates that a pin map exists for gfxss_dbi_d*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_DBI_D (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_dbi_d signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_d[8];
/** Indicates that a pin map exists for gfxss_dbi_dcx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_DBI_DCX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_dbi_dcx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_dcx[1];
/** Indicates that a pin map exists for gfxss_dbi_e*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_DBI_E (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_dbi_e signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_e[1];
/** Indicates that a pin map exists for gfxss_dbi_wrx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_DBI_WRX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_dbi_wrx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_wrx[1];
/** Indicates that a pin map exists for gfxss_spi_csx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_SPI_CSX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_spi_csx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_csx[1];
/** Indicates that a pin map exists for gfxss_spi_dcx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_SPI_DCX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_spi_dcx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_dcx[1];
/** Indicates that a pin map exists for gfxss_spi_dout*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_SPI_DOUT (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_spi_dout signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_dout[1];
/** Indicates that a pin map exists for gfxss_spi_scl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_GFXSS_SPI_SCL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the gfxss_spi_scl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_scl[1];
/** Indicates that a pin map exists for i3c_i3c_scl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_I3C_I3C_SCL (CY_GPIO_DM_OD_DRIVESLOW)
/** List of valid pin to peripheral connections for the i3c_i3c_scl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_i3c_i3c_scl[1];
/** Indicates that a pin map exists for i3c_i3c_sda*/
#define CYHAL_PIN_MAP_DRIVE_MODE_I3C_I3C_SDA (CY_GPIO_DM_OD_DRIVESLOW)
/** List of valid pin to peripheral connections for the i3c_i3c_sda signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_i3c_i3c_sda[1];
/** Indicates that a pin map exists for lpcomp_inn_comp*/
#define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG)
/** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2];
/** Indicates that a pin map exists for lpcomp_inp_comp*/
#define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG)
/** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
/** Indicates that a pin map exists for m0seccpuss_clk_m0sec_swd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_M0SECCPUSS_CLK_M0SEC_SWD (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the m0seccpuss_clk_m0sec_swd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_m0seccpuss_clk_m0sec_swd[1];
/** Indicates that a pin map exists for m0seccpuss_m0sec_swd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_M0SECCPUSS_M0SEC_SWD (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the m0seccpuss_m0sec_swd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_m0seccpuss_m0sec_swd[1];
/** Indicates that a pin map exists for pass_sarmux_pads*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG)
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
/** Indicates that a pin map exists for pdm_pdm_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the pdm_pdm_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[5];
/** Indicates that a pin map exists for pdm_pdm_data*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PDM_PDM_DATA (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the pdm_pdm_data signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[6];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW)
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[8];
/** Indicates that a pin map exists for scb_i2c_sda*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW)
/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10];
/** Indicates that a pin map exists for scb_spi_m_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8];
/** Indicates that a pin map exists for scb_spi_m_miso*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11];
/** Indicates that a pin map exists for scb_spi_m_mosi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11];
/** Indicates that a pin map exists for scb_spi_m_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10];
/** Indicates that a pin map exists for scb_spi_m_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
/** Indicates that a pin map exists for scb_spi_s_clk*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8];
/** Indicates that a pin map exists for scb_spi_s_miso*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11];
/** Indicates that a pin map exists for scb_spi_s_mosi*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11];
/** Indicates that a pin map exists for scb_spi_s_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10];
/** Indicates that a pin map exists for scb_spi_s_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
/** Indicates that a pin map exists for scb_uart_cts*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_uart_cts signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
/** Indicates that a pin map exists for scb_uart_rts*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9];
/** Indicates that a pin map exists for scb_uart_rx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[7];
/** Indicates that a pin map exists for scb_uart_tx*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the scb_uart_tx signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9];
/** Indicates that a pin map exists for sdhc_card_cmd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
/** Indicates that a pin map exists for sdhc_card_dat_3to0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
/** Indicates that a pin map exists for sdhc_card_dat_7to4*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[3];
/** Indicates that a pin map exists for sdhc_card_detect_n*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
/** Indicates that a pin map exists for sdhc_card_emmc_reset_n*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_EMMC_RESET_N (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
/** Indicates that a pin map exists for sdhc_card_if_pwr_en*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
/** Indicates that a pin map exists for sdhc_card_mech_write_prot*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
/** Indicates that a pin map exists for sdhc_clk_card*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG)
/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
/** Indicates that a pin map exists for sdhc_io_volt_sel*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_IO_VOLT_SEL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
/** Indicates that a pin map exists for sdhc_led_ctrl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_LED_CTRL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
/** Indicates that a pin map exists for smif_smif0_spi_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF0_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif0_spi_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select0[1];
/** Indicates that a pin map exists for smif_smif0_spi_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF0_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif0_spi_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select1[1];
/** Indicates that a pin map exists for smif_smif0_spi_select2*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF0_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif0_spi_select2 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select2[1];
/** Indicates that a pin map exists for smif_smif0_spi_select3*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF0_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif0_spi_select3 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select3[1];
/** Indicates that a pin map exists for smif_smif1_spi_select0*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF1_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif1_spi_select0 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select0[1];
/** Indicates that a pin map exists for smif_smif1_spi_select1*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF1_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif1_spi_select1 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select1[1];
/** Indicates that a pin map exists for smif_smif1_spi_select2*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF1_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif1_spi_select2 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select2[1];
/** Indicates that a pin map exists for smif_smif1_spi_select3*/
#define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SMIF1_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the smif_smif1_spi_select3 signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select3[1];
/** Indicates that a pin map exists for tcpwm_line*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tcpwm_line signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98];
/** Indicates that a pin map exists for tcpwm_line_compl*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[94];
/** Indicates that a pin map exists for tdm_tdm_rx_fsync*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_rx_fsync signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[2];
/** Indicates that a pin map exists for tdm_tdm_rx_mck*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_MCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_rx_mck signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1];
/** Indicates that a pin map exists for tdm_tdm_rx_sck*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_rx_sck signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1];
/** Indicates that a pin map exists for tdm_tdm_rx_sd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_RX_SD (CY_GPIO_EXT_DM_HIGHZ)
/** List of valid pin to peripheral connections for the tdm_tdm_rx_sd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[2];
/** Indicates that a pin map exists for tdm_tdm_tx_fsync*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_FSYNC (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_tx_fsync signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[2];
/** Indicates that a pin map exists for tdm_tdm_tx_mck*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_MCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_tx_mck signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[2];
/** Indicates that a pin map exists for tdm_tdm_tx_sck*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_tx_sck signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[2];
/** Indicates that a pin map exists for tdm_tdm_tx_sd*/
#define CYHAL_PIN_MAP_DRIVE_MODE_TDM_TDM_TX_SD (CY_GPIO_DM_STRONG_IN_OFF)
/** List of valid pin to peripheral connections for the tdm_tdm_tx_sd signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[2];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_impl_pin_package */
#endif /* _CYHAL_EXPLORER_144_LQFP_H_ */
/* [] END OF FILE */

650
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1D/include/triggers/cyhal_triggers_explorer.h
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@ -1,650 +0,0 @@
/***************************************************************************//**
* \file cyhal_triggers_explorer.h
*
* \brief
* Explorer family HAL triggers header
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_TRIGGERS_EXPLORER_H_
#define _CYHAL_TRIGGERS_EXPLORER_H_
/**
* \addtogroup group_hal_impl_triggers_explorer EXPLORER
* \ingroup group_hal_impl_triggers
* \{
* Trigger connections for explorer
*/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/** \cond INTERNAL */
/** @brief Name of each input trigger. */
typedef enum
{
_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0 = 0, //!< canfd.tr_dbg_dma_req[0]
_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1 = 1, //!< canfd.tr_dbg_dma_req[1]
_CYHAL_TRIGGER_CANFD_TR_FIFO00 = 2, //!< canfd.tr_fifo0[0]
_CYHAL_TRIGGER_CANFD_TR_FIFO01 = 3, //!< canfd.tr_fifo0[1]
_CYHAL_TRIGGER_CANFD_TR_FIFO10 = 4, //!< canfd.tr_fifo1[0]
_CYHAL_TRIGGER_CANFD_TR_FIFO11 = 5, //!< canfd.tr_fifo1[1]
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0 = 6, //!< canfd.tr_tmp_rtp_out[0]
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1 = 7, //!< canfd.tr_tmp_rtp_out[1]
_CYHAL_TRIGGER_I3C_TR_RX_REQ = 8, //!< i3c.tr_rx_req
_CYHAL_TRIGGER_I3C_TR_TX_REQ = 9, //!< i3c.tr_tx_req
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0 = 10, //!< ioss.peri_tr_io_input_in[0]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1 = 11, //!< ioss.peri_tr_io_input_in[1]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2 = 12, //!< ioss.peri_tr_io_input_in[2]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3 = 13, //!< ioss.peri_tr_io_input_in[3]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4 = 14, //!< ioss.peri_tr_io_input_in[4]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5 = 15, //!< ioss.peri_tr_io_input_in[5]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6 = 16, //!< ioss.peri_tr_io_input_in[6]
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7 = 17, //!< ioss.peri_tr_io_input_in[7]
_CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 18, //!< lpcomp.dsi_comp0
_CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 19, //!< lpcomp.dsi_comp1
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0 = 20, //!< m33syscpuss.cti_tr_out[0]
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1 = 21, //!< m33syscpuss.cti_tr_out[1]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0 = 22, //!< m33syscpuss.dw0_tr_out[0]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1 = 23, //!< m33syscpuss.dw0_tr_out[1]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2 = 24, //!< m33syscpuss.dw0_tr_out[2]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3 = 25, //!< m33syscpuss.dw0_tr_out[3]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4 = 26, //!< m33syscpuss.dw0_tr_out[4]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5 = 27, //!< m33syscpuss.dw0_tr_out[5]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6 = 28, //!< m33syscpuss.dw0_tr_out[6]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7 = 29, //!< m33syscpuss.dw0_tr_out[7]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8 = 30, //!< m33syscpuss.dw0_tr_out[8]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9 = 31, //!< m33syscpuss.dw0_tr_out[9]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10 = 32, //!< m33syscpuss.dw0_tr_out[10]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11 = 33, //!< m33syscpuss.dw0_tr_out[11]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12 = 34, //!< m33syscpuss.dw0_tr_out[12]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13 = 35, //!< m33syscpuss.dw0_tr_out[13]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14 = 36, //!< m33syscpuss.dw0_tr_out[14]
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15 = 37, //!< m33syscpuss.dw0_tr_out[15]
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO = 38, //!< m33syscpuss.zero
_CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE = 39, //!< mxnnlite.tr_mxnnlite
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0 = 40, //!< pass.tr_lppass_out[0]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1 = 41, //!< pass.tr_lppass_out[1]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2 = 42, //!< pass.tr_lppass_out[2]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3 = 43, //!< pass.tr_lppass_out[3]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4 = 44, //!< pass.tr_lppass_out[4]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5 = 45, //!< pass.tr_lppass_out[5]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6 = 46, //!< pass.tr_lppass_out[6]
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7 = 47, //!< pass.tr_lppass_out[7]
_CYHAL_TRIGGER_PDM_TR_RX_REQ0 = 48, //!< pdm.tr_rx_req[0]
_CYHAL_TRIGGER_PDM_TR_RX_REQ1 = 49, //!< pdm.tr_rx_req[1]
_CYHAL_TRIGGER_PDM_TR_RX_REQ2 = 50, //!< pdm.tr_rx_req[2]
_CYHAL_TRIGGER_PDM_TR_RX_REQ3 = 51, //!< pdm.tr_rx_req[3]
_CYHAL_TRIGGER_PDM_TR_RX_REQ4 = 52, //!< pdm.tr_rx_req[4]
_CYHAL_TRIGGER_PDM_TR_RX_REQ5 = 53, //!< pdm.tr_rx_req[5]
_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 54, //!< scb[0].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 55, //!< scb[1].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 56, //!< scb[2].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 57, //!< scb[3].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 58, //!< scb[4].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 59, //!< scb[5].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 60, //!< scb[6].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 61, //!< scb[7].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 62, //!< scb[8].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = 63, //!< scb[9].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = 64, //!< scb[10].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = 65, //!< scb[11].tr_i2c_scl_filtered
_CYHAL_TRIGGER_SCB0_TR_RX_REQ = 66, //!< scb[0].tr_rx_req
_CYHAL_TRIGGER_SCB1_TR_RX_REQ = 67, //!< scb[1].tr_rx_req
_CYHAL_TRIGGER_SCB2_TR_RX_REQ = 68, //!< scb[2].tr_rx_req
_CYHAL_TRIGGER_SCB3_TR_RX_REQ = 69, //!< scb[3].tr_rx_req
_CYHAL_TRIGGER_SCB4_TR_RX_REQ = 70, //!< scb[4].tr_rx_req
_CYHAL_TRIGGER_SCB5_TR_RX_REQ = 71, //!< scb[5].tr_rx_req
_CYHAL_TRIGGER_SCB6_TR_RX_REQ = 72, //!< scb[6].tr_rx_req
_CYHAL_TRIGGER_SCB7_TR_RX_REQ = 73, //!< scb[7].tr_rx_req
_CYHAL_TRIGGER_SCB8_TR_RX_REQ = 74, //!< scb[8].tr_rx_req
_CYHAL_TRIGGER_SCB9_TR_RX_REQ = 75, //!< scb[9].tr_rx_req
_CYHAL_TRIGGER_SCB10_TR_RX_REQ = 76, //!< scb[10].tr_rx_req
_CYHAL_TRIGGER_SCB11_TR_RX_REQ = 77, //!< scb[11].tr_rx_req
_CYHAL_TRIGGER_SCB0_TR_TX_REQ = 78, //!< scb[0].tr_tx_req
_CYHAL_TRIGGER_SCB1_TR_TX_REQ = 79, //!< scb[1].tr_tx_req
_CYHAL_TRIGGER_SCB2_TR_TX_REQ = 80, //!< scb[2].tr_tx_req
_CYHAL_TRIGGER_SCB3_TR_TX_REQ = 81, //!< scb[3].tr_tx_req
_CYHAL_TRIGGER_SCB4_TR_TX_REQ = 82, //!< scb[4].tr_tx_req
_CYHAL_TRIGGER_SCB5_TR_TX_REQ = 83, //!< scb[5].tr_tx_req
_CYHAL_TRIGGER_SCB6_TR_TX_REQ = 84, //!< scb[6].tr_tx_req
_CYHAL_TRIGGER_SCB7_TR_TX_REQ = 85, //!< scb[7].tr_tx_req
_CYHAL_TRIGGER_SCB8_TR_TX_REQ = 86, //!< scb[8].tr_tx_req
_CYHAL_TRIGGER_SCB9_TR_TX_REQ = 87, //!< scb[9].tr_tx_req
_CYHAL_TRIGGER_SCB10_TR_TX_REQ = 88, //!< scb[10].tr_tx_req
_CYHAL_TRIGGER_SCB11_TR_TX_REQ = 89, //!< scb[11].tr_tx_req
_CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 90, //!< tcpwm[0].tr_out0[0]
_CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 91, //!< tcpwm[0].tr_out0[1]
_CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 92, //!< tcpwm[0].tr_out0[2]
_CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 93, //!< tcpwm[0].tr_out0[3]
_CYHAL_TRIGGER_TCPWM0_TR_OUT04 = 94, //!< tcpwm[0].tr_out0[4]
_CYHAL_TRIGGER_TCPWM0_TR_OUT05 = 95, //!< tcpwm[0].tr_out0[5]
_CYHAL_TRIGGER_TCPWM0_TR_OUT06 = 96, //!< tcpwm[0].tr_out0[6]
_CYHAL_TRIGGER_TCPWM0_TR_OUT07 = 97, //!< tcpwm[0].tr_out0[7]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 98, //!< tcpwm[0].tr_out0[256]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 99, //!< tcpwm[0].tr_out0[257]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 100, //!< tcpwm[0].tr_out0[258]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 101, //!< tcpwm[0].tr_out0[259]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 102, //!< tcpwm[0].tr_out0[260]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 103, //!< tcpwm[0].tr_out0[261]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 104, //!< tcpwm[0].tr_out0[262]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 105, //!< tcpwm[0].tr_out0[263]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0264 = 106, //!< tcpwm[0].tr_out0[264]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0265 = 107, //!< tcpwm[0].tr_out0[265]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0266 = 108, //!< tcpwm[0].tr_out0[266]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0267 = 109, //!< tcpwm[0].tr_out0[267]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0268 = 110, //!< tcpwm[0].tr_out0[268]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0269 = 111, //!< tcpwm[0].tr_out0[269]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0270 = 112, //!< tcpwm[0].tr_out0[270]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0271 = 113, //!< tcpwm[0].tr_out0[271]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0272 = 114, //!< tcpwm[0].tr_out0[272]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0273 = 115, //!< tcpwm[0].tr_out0[273]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0274 = 116, //!< tcpwm[0].tr_out0[274]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0275 = 117, //!< tcpwm[0].tr_out0[275]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0276 = 118, //!< tcpwm[0].tr_out0[276]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0277 = 119, //!< tcpwm[0].tr_out0[277]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0278 = 120, //!< tcpwm[0].tr_out0[278]
_CYHAL_TRIGGER_TCPWM0_TR_OUT0279 = 121, //!< tcpwm[0].tr_out0[279]
_CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 122, //!< tcpwm[0].tr_out1[0]
_CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 123, //!< tcpwm[0].tr_out1[1]
_CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 124, //!< tcpwm[0].tr_out1[2]
_CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 125, //!< tcpwm[0].tr_out1[3]
_CYHAL_TRIGGER_TCPWM0_TR_OUT14 = 126, //!< tcpwm[0].tr_out1[4]
_CYHAL_TRIGGER_TCPWM0_TR_OUT15 = 127, //!< tcpwm[0].tr_out1[5]
_CYHAL_TRIGGER_TCPWM0_TR_OUT16 = 128, //!< tcpwm[0].tr_out1[6]
_CYHAL_TRIGGER_TCPWM0_TR_OUT17 = 129, //!< tcpwm[0].tr_out1[7]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 130, //!< tcpwm[0].tr_out1[256]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 131, //!< tcpwm[0].tr_out1[257]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 132, //!< tcpwm[0].tr_out1[258]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 133, //!< tcpwm[0].tr_out1[259]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 134, //!< tcpwm[0].tr_out1[260]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 135, //!< tcpwm[0].tr_out1[261]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 136, //!< tcpwm[0].tr_out1[262]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 137, //!< tcpwm[0].tr_out1[263]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1264 = 138, //!< tcpwm[0].tr_out1[264]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1265 = 139, //!< tcpwm[0].tr_out1[265]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1266 = 140, //!< tcpwm[0].tr_out1[266]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1267 = 141, //!< tcpwm[0].tr_out1[267]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1268 = 142, //!< tcpwm[0].tr_out1[268]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1269 = 143, //!< tcpwm[0].tr_out1[269]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1270 = 144, //!< tcpwm[0].tr_out1[270]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1271 = 145, //!< tcpwm[0].tr_out1[271]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1272 = 146, //!< tcpwm[0].tr_out1[272]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1273 = 147, //!< tcpwm[0].tr_out1[273]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1274 = 148, //!< tcpwm[0].tr_out1[274]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1275 = 149, //!< tcpwm[0].tr_out1[275]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1276 = 150, //!< tcpwm[0].tr_out1[276]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1277 = 151, //!< tcpwm[0].tr_out1[277]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1278 = 152, //!< tcpwm[0].tr_out1[278]
_CYHAL_TRIGGER_TCPWM0_TR_OUT1279 = 153, //!< tcpwm[0].tr_out1[279]
_CYHAL_TRIGGER_TDM_TR_RX_REQ0 = 154, //!< tdm.tr_rx_req[0]
_CYHAL_TRIGGER_TDM_TR_RX_REQ1 = 155, //!< tdm.tr_rx_req[1]
_CYHAL_TRIGGER_TDM_TR_TX_REQ0 = 156, //!< tdm.tr_tx_req[0]
_CYHAL_TRIGGER_TDM_TR_TX_REQ1 = 157, //!< tdm.tr_tx_req[1]
} _cyhal_trigger_source_explorer_t;
/** Typedef for internal device family specific trigger source to generic trigger source */
typedef _cyhal_trigger_source_explorer_t cyhal_internal_source_t;
/** @brief Get a public source signal type (cyhal_trigger_source_explorer_t) given an internal source signal and signal type */
#define _CYHAL_TRIGGER_CREATE_SOURCE(src, type) ((src) << 1 | (type))
/** @brief Get an internal source signal (_cyhal_trigger_source_explorer_t) given a public source signal. */
#define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src) ((cyhal_internal_source_t)((src) >> 1))
/** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */
#define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src) ((cyhal_signal_type_t)((src) & 1))
/** \endcond */
/** @brief Name of each input trigger. */
typedef enum
{
CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_dbg_dma_req[0]
CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_dbg_dma_req[1]
CYHAL_TRIGGER_CANFD_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo0[0]
CYHAL_TRIGGER_CANFD_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo0[1]
CYHAL_TRIGGER_CANFD_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo1[0]
CYHAL_TRIGGER_CANFD_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo1[1]
CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd.tr_tmp_rtp_out[0]
CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd.tr_tmp_rtp_out[1]
CYHAL_TRIGGER_I3C_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_I3C_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< i3c.tr_rx_req
CYHAL_TRIGGER_I3C_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_I3C_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< i3c.tr_tx_req
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[0]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[0]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[1]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[1]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[2]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[2]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[3]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[3]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[4]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[4]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[5]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[5]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[6]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[6]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[7]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[7]
CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp0
CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp1
CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.cti_tr_out[0]
CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.cti_tr_out[1]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[0]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[1]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[2]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[3]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[4]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[5]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[6]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[7]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[8]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[9]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[10]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[11]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[12]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[13]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[14]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[15]
CYHAL_TRIGGER_M33SYSCPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.zero
CYHAL_TRIGGER_M33SYSCPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< m33syscpuss.zero
CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE, CYHAL_SIGNAL_TYPE_LEVEL), //!< mxnnlite.tr_mxnnlite
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[0]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[0]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[1]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[1]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[2]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[2]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[3]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[3]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[4]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[4]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[5]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[5]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[6]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[6]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[7]
CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[7]
CYHAL_TRIGGER_PDM_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[0]
CYHAL_TRIGGER_PDM_TR_RX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[1]
CYHAL_TRIGGER_PDM_TR_RX_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[2]
CYHAL_TRIGGER_PDM_TR_RX_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[3]
CYHAL_TRIGGER_PDM_TR_RX_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[4]
CYHAL_TRIGGER_PDM_TR_RX_REQ5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[5]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req
CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req
CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req
CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req
CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_rx_req
CYHAL_TRIGGER_SCB9_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_rx_req
CYHAL_TRIGGER_SCB10_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_rx_req
CYHAL_TRIGGER_SCB11_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req
CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req
CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req
CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req
CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_tx_req
CYHAL_TRIGGER_SCB9_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_tx_req
CYHAL_TRIGGER_SCB10_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_tx_req
CYHAL_TRIGGER_SCB11_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2]
CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2]
CYHAL_TRIGGER_TCPWM0_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[3]
CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[3]
CYHAL_TRIGGER_TCPWM0_TR_OUT04_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[4]
CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[4]
CYHAL_TRIGGER_TCPWM0_TR_OUT05_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[5]
CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[5]
CYHAL_TRIGGER_TCPWM0_TR_OUT06_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[6]
CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[6]
CYHAL_TRIGGER_TCPWM0_TR_OUT07_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[7]
CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[7]
CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[263]
CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[263]
CYHAL_TRIGGER_TCPWM0_TR_OUT0264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[264]
CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[264]
CYHAL_TRIGGER_TCPWM0_TR_OUT0265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[265]
CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[265]
CYHAL_TRIGGER_TCPWM0_TR_OUT0266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[266]
CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[266]
CYHAL_TRIGGER_TCPWM0_TR_OUT0267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[267]
CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[267]
CYHAL_TRIGGER_TCPWM0_TR_OUT0268_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0268, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[268]
CYHAL_TRIGGER_TCPWM0_TR_OUT0268_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0268, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[268]
CYHAL_TRIGGER_TCPWM0_TR_OUT0269_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0269, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[269]
CYHAL_TRIGGER_TCPWM0_TR_OUT0269_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0269, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[269]
CYHAL_TRIGGER_TCPWM0_TR_OUT0270_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0270, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[270]
CYHAL_TRIGGER_TCPWM0_TR_OUT0270_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0270, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[270]
CYHAL_TRIGGER_TCPWM0_TR_OUT0271_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0271, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[271]
CYHAL_TRIGGER_TCPWM0_TR_OUT0271_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0271, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[271]
CYHAL_TRIGGER_TCPWM0_TR_OUT0272_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0272, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[272]
CYHAL_TRIGGER_TCPWM0_TR_OUT0272_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0272, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[272]
CYHAL_TRIGGER_TCPWM0_TR_OUT0273_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0273, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[273]
CYHAL_TRIGGER_TCPWM0_TR_OUT0273_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0273, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[273]
CYHAL_TRIGGER_TCPWM0_TR_OUT0274_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0274, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[274]
CYHAL_TRIGGER_TCPWM0_TR_OUT0274_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0274, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[274]
CYHAL_TRIGGER_TCPWM0_TR_OUT0275_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0275, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[275]
CYHAL_TRIGGER_TCPWM0_TR_OUT0275_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0275, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[275]
CYHAL_TRIGGER_TCPWM0_TR_OUT0276_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0276, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[276]
CYHAL_TRIGGER_TCPWM0_TR_OUT0276_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0276, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[276]
CYHAL_TRIGGER_TCPWM0_TR_OUT0277_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0277, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[277]
CYHAL_TRIGGER_TCPWM0_TR_OUT0277_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0277, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[277]
CYHAL_TRIGGER_TCPWM0_TR_OUT0278_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0278, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[278]
CYHAL_TRIGGER_TCPWM0_TR_OUT0278_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0278, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[278]
CYHAL_TRIGGER_TCPWM0_TR_OUT0279_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0279, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[279]
CYHAL_TRIGGER_TCPWM0_TR_OUT0279_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0279, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[279]
CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2]
CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2]
CYHAL_TRIGGER_TCPWM0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[3]
CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[3]
CYHAL_TRIGGER_TCPWM0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[4]
CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[4]
CYHAL_TRIGGER_TCPWM0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[5]
CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[5]
CYHAL_TRIGGER_TCPWM0_TR_OUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[6]
CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[6]
CYHAL_TRIGGER_TCPWM0_TR_OUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[7]
CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[7]
CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[263]
CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[263]
CYHAL_TRIGGER_TCPWM0_TR_OUT1264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[264]
CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[264]
CYHAL_TRIGGER_TCPWM0_TR_OUT1265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[265]
CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[265]
CYHAL_TRIGGER_TCPWM0_TR_OUT1266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[266]
CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[266]
CYHAL_TRIGGER_TCPWM0_TR_OUT1267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[267]
CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[267]
CYHAL_TRIGGER_TCPWM0_TR_OUT1268_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1268, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[268]
CYHAL_TRIGGER_TCPWM0_TR_OUT1268_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1268, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[268]
CYHAL_TRIGGER_TCPWM0_TR_OUT1269_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1269, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[269]
CYHAL_TRIGGER_TCPWM0_TR_OUT1269_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1269, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[269]
CYHAL_TRIGGER_TCPWM0_TR_OUT1270_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1270, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[270]
CYHAL_TRIGGER_TCPWM0_TR_OUT1270_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1270, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[270]
CYHAL_TRIGGER_TCPWM0_TR_OUT1271_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1271, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[271]
CYHAL_TRIGGER_TCPWM0_TR_OUT1271_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1271, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[271]
CYHAL_TRIGGER_TCPWM0_TR_OUT1272_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1272, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[272]
CYHAL_TRIGGER_TCPWM0_TR_OUT1272_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1272, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[272]
CYHAL_TRIGGER_TCPWM0_TR_OUT1273_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1273, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[273]
CYHAL_TRIGGER_TCPWM0_TR_OUT1273_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1273, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[273]
CYHAL_TRIGGER_TCPWM0_TR_OUT1274_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1274, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[274]
CYHAL_TRIGGER_TCPWM0_TR_OUT1274_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1274, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[274]
CYHAL_TRIGGER_TCPWM0_TR_OUT1275_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1275, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[275]
CYHAL_TRIGGER_TCPWM0_TR_OUT1275_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1275, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[275]
CYHAL_TRIGGER_TCPWM0_TR_OUT1276_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1276, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[276]
CYHAL_TRIGGER_TCPWM0_TR_OUT1276_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1276, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[276]
CYHAL_TRIGGER_TCPWM0_TR_OUT1277_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1277, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[277]
CYHAL_TRIGGER_TCPWM0_TR_OUT1277_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1277, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[277]
CYHAL_TRIGGER_TCPWM0_TR_OUT1278_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1278, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[278]
CYHAL_TRIGGER_TCPWM0_TR_OUT1278_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1278, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[278]
CYHAL_TRIGGER_TCPWM0_TR_OUT1279_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1279, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[279]
CYHAL_TRIGGER_TCPWM0_TR_OUT1279_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1279, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[279]
CYHAL_TRIGGER_TDM_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_rx_req[0]
CYHAL_TRIGGER_TDM_TR_RX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_RX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_rx_req[1]
CYHAL_TRIGGER_TDM_TR_TX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_TX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_tx_req[0]
CYHAL_TRIGGER_TDM_TR_TX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_TX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_tx_req[1]
} cyhal_trigger_source_explorer_t;
/** Typedef from device family specific trigger source to generic trigger source */
typedef cyhal_trigger_source_explorer_t cyhal_source_t;
/** Deprecated defines for signals that can be either level or edge. */
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_M33SYSCPUSS_ZERO (CYHAL_TRIGGER_M33SYSCPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT03 (CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT04 (CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT05 (CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT06 (CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT07 (CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0259 (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0260 (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0261 (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0262 (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0263 (CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0264 (CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0265 (CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0266 (CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0267 (CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0268 (CYHAL_TRIGGER_TCPWM0_TR_OUT0268_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0269 (CYHAL_TRIGGER_TCPWM0_TR_OUT0269_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0270 (CYHAL_TRIGGER_TCPWM0_TR_OUT0270_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0271 (CYHAL_TRIGGER_TCPWM0_TR_OUT0271_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0272 (CYHAL_TRIGGER_TCPWM0_TR_OUT0272_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0273 (CYHAL_TRIGGER_TCPWM0_TR_OUT0273_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0274 (CYHAL_TRIGGER_TCPWM0_TR_OUT0274_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0275 (CYHAL_TRIGGER_TCPWM0_TR_OUT0275_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0276 (CYHAL_TRIGGER_TCPWM0_TR_OUT0276_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0277 (CYHAL_TRIGGER_TCPWM0_TR_OUT0277_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0278 (CYHAL_TRIGGER_TCPWM0_TR_OUT0278_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0279 (CYHAL_TRIGGER_TCPWM0_TR_OUT0279_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT13 (CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT14 (CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT15 (CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT16 (CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT17 (CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1259 (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1260 (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1261 (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1262 (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1263 (CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1264 (CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1265 (CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1266 (CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1267 (CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1268 (CYHAL_TRIGGER_TCPWM0_TR_OUT1268_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1269 (CYHAL_TRIGGER_TCPWM0_TR_OUT1269_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1270 (CYHAL_TRIGGER_TCPWM0_TR_OUT1270_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1271 (CYHAL_TRIGGER_TCPWM0_TR_OUT1271_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1272 (CYHAL_TRIGGER_TCPWM0_TR_OUT1272_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1273 (CYHAL_TRIGGER_TCPWM0_TR_OUT1273_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1274 (CYHAL_TRIGGER_TCPWM0_TR_OUT1274_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1275 (CYHAL_TRIGGER_TCPWM0_TR_OUT1275_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1276 (CYHAL_TRIGGER_TCPWM0_TR_OUT1276_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1277 (CYHAL_TRIGGER_TCPWM0_TR_OUT1277_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1278 (CYHAL_TRIGGER_TCPWM0_TR_OUT1278_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1279 (CYHAL_TRIGGER_TCPWM0_TR_OUT1279_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
/** @brief Name of each output trigger. */
typedef enum
{
CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 = 0, //!< TCPWM0_20_31 Trigger multiplexer - canfd.tr_dbg_dma_ack[0]
CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK1 = 1, //!< TCPWM0_20_31 Trigger multiplexer - canfd.tr_dbg_dma_ack[1]
CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 = 2, //!< CAN TT Sync - canfd.tr_evt_swt_in[0]
CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN1 = 3, //!< CAN TT Sync - canfd.tr_evt_swt_in[1]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 = 4, //!< Debug Reduction #1 - ioss.peri_tr_io_output_out[0]
CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 = 5, //!< Debug Reduction #1 - ioss.peri_tr_io_output_out[1]
CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - m33syscpuss.cti_tr_in[0]
CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - m33syscpuss.cti_tr_in[1]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN0 = 8, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[0]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN1 = 9, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[1]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN2 = 10, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[2]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN3 = 11, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[3]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN4 = 12, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[4]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN5 = 13, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[5]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN6 = 14, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[6]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN7 = 15, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[7]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN8 = 16, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[8]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN9 = 17, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[9]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN10 = 18, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[10]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN11 = 19, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[11]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN12 = 20, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[12]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN13 = 21, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[13]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN14 = 22, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[14]
CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN15 = 23, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[15]
CYHAL_TRIGGER_PASS_TR_LPPASS_IN0 = 24, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[0]
CYHAL_TRIGGER_PASS_TR_LPPASS_IN1 = 25, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[1]
CYHAL_TRIGGER_PASS_TR_LPPASS_IN2 = 26, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[2]
CYHAL_TRIGGER_PASS_TR_LPPASS_IN3 = 27, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[3]
CYHAL_TRIGGER_PDM_TR_ACTIVATE0 = 28, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[0]
CYHAL_TRIGGER_PDM_TR_ACTIVATE1 = 29, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[1]
CYHAL_TRIGGER_PDM_TR_ACTIVATE2 = 30, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[2]
CYHAL_TRIGGER_PDM_TR_ACTIVATE3 = 31, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[3]
CYHAL_TRIGGER_PDM_TR_ACTIVATE4 = 32, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[4]
CYHAL_TRIGGER_PDM_TR_ACTIVATE5 = 33, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[5]
CYHAL_TRIGGER_PDM_TR_DBG_FREEZE = 34, //!< PERI Freeze trigger multiplexer - pdm.tr_dbg_freeze
CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 35, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 36, //!< PERI Freeze trigger multiplexer - srss.tr_debug_freeze_mcwdt[0]
CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 = 37, //!< PERI Freeze trigger multiplexer - srss.tr_debug_freeze_mcwdt[1]
CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT = 38, //!< PERI Freeze trigger multiplexer - srss.tr_debug_freeze_wdt
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 39, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[0]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 40, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[1]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 41, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[2]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 42, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[3]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 43, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[4]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 44, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[5]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 45, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[6]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 46, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[7]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 47, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[8]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 48, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[9]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 49, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[10]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 50, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[11]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 51, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[12]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 52, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[13]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 53, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[14]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 54, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[15]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 55, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[16]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 56, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[17]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 57, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[18]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 58, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[19]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 59, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[20]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 60, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[21]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 61, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[22]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 62, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[23]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 63, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[24]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 64, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[25]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 65, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[26]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 = 66, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[27]
CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 67, //!< PERI Freeze trigger multiplexer - tcpwm[0].tr_debug_freeze
CYHAL_TRIGGER_TDM_TR_DBG_FREEZE = 68, //!< PERI Freeze trigger multiplexer - tdm.tr_dbg_freeze
} cyhal_trigger_dest_explorer_t;
/** Typedef from device family specific trigger dest to generic trigger dest */
typedef cyhal_trigger_dest_explorer_t cyhal_dest_t;
/** \cond INTERNAL */
/** Table of number of inputs to each mux. */
extern const uint16_t cyhal_sources_per_mux[7];
/** Table indicating whether mux is 1to1. */
extern const bool cyhal_is_mux_1to1[7];
/** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
extern const _cyhal_trigger_source_explorer_t* cyhal_mux_to_sources [7];
/** Maps each cyhal_destination_t to a mux index.
* If bit 8 of the mux index is set, this denotes that the trigger is a
* one to one trigger.
*/
extern const uint8_t cyhal_dest_to_mux[69];
/* Maps each cyhal_destination_t to a specific output in its mux */
extern const uint8_t cyhal_mux_dest_index[69];
/** \endcond */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_impl_triggers_explorer */
#endif /* _CYHAL_TRIGGERS_EXPLORER_H_ */
/* [] END OF FILE */

851
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1D/source/pin_packages/cyhal_explorer_144_lqfp.c
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@ -1,851 +0,0 @@
/***************************************************************************//**
* \file cyhal_explorer_144_lqfp.c
*
* \brief
* Explorer device GPIO HAL header for 144-LQFP package
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_EXPLORER_144_LQFP_H_)
#include "pin_packages/cyhal_explorer_144_lqfp.h"
/* Pin connections */
/* Connections for: canfd_ttcan_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[2] = {
{0u, 0u, P16_4, P16_4_CANFD_TTCAN_RX0},
{0u, 1u, P16_6, P16_6_CANFD_TTCAN_RX1},
};
/* Connections for: canfd_ttcan_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[2] = {
{0u, 0u, P16_5, P16_5_CANFD_TTCAN_TX0},
{0u, 1u, P16_7, P16_7_CANFD_TTCAN_TX1},
};
/* Connections for: debug600_clk_swj_swclk_tclk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1] = {
{0u, 0u, P7_6, P7_6_DEBUG600_CLK_SWJ_SWCLK_TCLK},
};
/* Connections for: debug600_rst_swj_trstn */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1] = {
{0u, 0u, P7_0, P7_0_DEBUG600_RST_SWJ_TRSTN},
};
/* Connections for: debug600_swj_swdio_tms */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1] = {
{0u, 0u, P7_5, P7_5_DEBUG600_SWJ_SWDIO_TMS},
};
/* Connections for: debug600_swj_swdoe_tdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1] = {
{0u, 0u, P7_2, P7_2_DEBUG600_SWJ_SWDOE_TDI},
};
/* Connections for: debug600_swj_swo_tdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1] = {
{0u, 0u, P7_1, P7_1_DEBUG600_SWJ_SWO_TDO},
};
/* Connections for: debug600_trace_clock */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[2] = {
{0u, 0u, P12_4, P12_4_DEBUG600_TRACE_CLOCK},
{0u, 0u, P24_0, P24_0_DEBUG600_TRACE_CLOCK},
};
/* Connections for: debug600_trace_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[8] = {
{0u, 0u, P4_4, P4_4_DEBUG600_TRACE_DATA0},
{0u, 1u, P4_5, P4_5_DEBUG600_TRACE_DATA1},
{0u, 2u, P4_6, P4_6_DEBUG600_TRACE_DATA2},
{0u, 3u, P4_7, P4_7_DEBUG600_TRACE_DATA3},
{0u, 0u, P12_0, P12_0_DEBUG600_TRACE_DATA0},
{0u, 1u, P12_1, P12_1_DEBUG600_TRACE_DATA1},
{0u, 2u, P12_2, P12_2_DEBUG600_TRACE_DATA2},
{0u, 3u, P12_3, P12_3_DEBUG600_TRACE_DATA3},
};
/* Connections for: eth_eth_tsu_timer_cmp_val */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1] = {
{0u, 0u, P13_1, P13_1_ETH_ETH_TSU_TIMER_CMP_VAL},
};
/* Connections for: eth_mdc */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1] = {
{0u, 0u, P13_2, P13_2_ETH_MDC},
};
/* Connections for: eth_mdio */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1] = {
{0u, 0u, P13_3, P13_3_ETH_MDIO},
};
/* Connections for: eth_ref_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1] = {
{0u, 0u, P13_4, P13_4_ETH_REF_CLK},
};
/* Connections for: eth_rx_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: eth_rx_ctl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1] = {
{0u, 0u, P13_5, P13_5_ETH_RX_CTL},
};
/* Connections for: eth_rx_er */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1] = {
{0u, 0u, P13_0, P13_0_ETH_RX_ER},
};
/* Connections for: eth_rxd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[2] = {
{0u, 0u, P13_6, P13_6_ETH_RXD0},
{0u, 1u, P13_7, P13_7_ETH_RXD1},
};
/* Connections for: eth_tx_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: eth_tx_ctl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1] = {
{0u, 0u, P12_4, P12_4_ETH_TX_CTL},
};
/* Connections for: eth_txd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4] = {
{0u, 2u, P12_0, P12_0_ETH_TXD2},
{0u, 3u, P12_1, P12_1_ETH_TXD3},
{0u, 0u, P12_2, P12_2_ETH_TXD0},
{0u, 1u, P12_3, P12_3_ETH_TXD1},
};
/* Connections for: gfxss_dbi_csx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_csx[1] = {
{0u, 0u, P16_0, P16_0_GFXSS_DBI_CSX},
};
/* Connections for: gfxss_dbi_d */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_d[8] = {
{0u, 0u, P16_3, P16_3_GFXSS_DBI_D0},
{0u, 1u, P16_4, P16_4_GFXSS_DBI_D1},
{0u, 2u, P16_5, P16_5_GFXSS_DBI_D2},
{0u, 3u, P16_6, P16_6_GFXSS_DBI_D3},
{0u, 4u, P16_7, P16_7_GFXSS_DBI_D4},
{0u, 5u, P17_0, P17_0_GFXSS_DBI_D5},
{0u, 6u, P17_1, P17_1_GFXSS_DBI_D6},
{0u, 7u, P17_2, P17_2_GFXSS_DBI_D7},
};
/* Connections for: gfxss_dbi_dcx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_dcx[1] = {
{0u, 0u, P16_2, P16_2_GFXSS_DBI_DCX},
};
/* Connections for: gfxss_dbi_e */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_e[1] = {
{0u, 0u, P16_1, P16_1_GFXSS_DBI_E},
};
/* Connections for: gfxss_dbi_wrx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_dbi_wrx[1] = {
{0u, 0u, P16_1, P16_1_GFXSS_DBI_WRX},
};
/* Connections for: gfxss_spi_csx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_csx[1] = {
{0u, 0u, P16_0, P16_0_GFXSS_SPI_CSX},
};
/* Connections for: gfxss_spi_dcx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_dcx[1] = {
{0u, 0u, P16_3, P16_3_GFXSS_SPI_DCX},
};
/* Connections for: gfxss_spi_dout */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_dout[1] = {
{0u, 0u, P16_2, P16_2_GFXSS_SPI_DOUT},
};
/* Connections for: gfxss_spi_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_gfxss_spi_scl[1] = {
{0u, 0u, P16_1, P16_1_GFXSS_SPI_SCL},
};
/* Connections for: i3c_i3c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_i3c_i3c_scl[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: i3c_i3c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_i3c_i3c_sda[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: lpcomp_inn_comp */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2] = {
{0u, 0u, P12_1, HSIOM_SEL_GPIO},
{0u, 1u, P12_3, HSIOM_SEL_GPIO},
};
/* Connections for: lpcomp_inp_comp */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2] = {
{0u, 0u, P12_0, HSIOM_SEL_GPIO},
{0u, 1u, P12_2, HSIOM_SEL_GPIO},
};
/* Connections for: m0seccpuss_clk_m0sec_swd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_m0seccpuss_clk_m0sec_swd[1] = {
{0u, 0u, P8_1, P8_1_M0SECCPUSS_CLK_M0SEC_SWD},
};
/* Connections for: m0seccpuss_m0sec_swd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_m0seccpuss_m0sec_swd[1] = {
{0u, 0u, P8_0, P8_0_M0SECCPUSS_M0SEC_SWD},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7] = {
{0u, 1u, P15_1, HSIOM_SEL_GPIO},
{0u, 2u, P15_2, HSIOM_SEL_GPIO},
{0u, 3u, P15_3, HSIOM_SEL_GPIO},
{0u, 4u, P15_4, HSIOM_SEL_GPIO},
{0u, 5u, P15_5, HSIOM_SEL_GPIO},
{0u, 6u, P15_6, HSIOM_SEL_GPIO},
{0u, 7u, P15_7, HSIOM_SEL_GPIO},
};
/* Connections for: pdm_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[5] = {
{0u, 0u, P7_1, P7_1_PDM_PDM_CLK0},
{0u, 1u, P7_3, P7_3_PDM_PDM_CLK1},
{0u, 2u, P7_5, P7_5_PDM_PDM_CLK2},
{0u, 4u, P8_1, P8_1_PDM_PDM_CLK4},
{0u, 5u, P8_3, P8_3_PDM_PDM_CLK5},
};
/* Connections for: pdm_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[6] = {
{0u, 0u, P7_0, P7_0_PDM_PDM_DATA0},
{0u, 1u, P7_2, P7_2_PDM_PDM_DATA1},
{0u, 2u, P7_4, P7_4_PDM_PDM_DATA2},
{0u, 3u, P7_6, P7_6_PDM_PDM_DATA3},
{0u, 4u, P8_0, P8_0_PDM_PDM_DATA4},
{0u, 5u, P8_2, P8_2_PDM_PDM_DATA5},
};
/* Connections for: peri_tr_io_input */
/* The actual channel_num has no value to how the connection works. However, the HAL driver needs
to know the index of the input or output trigger line. Store that in the channel_num field
instead. */
const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8] = {
{0u, 0u, P6_0, P6_0_PERI0_TR_IO_INPUT0},
{0u, 1u, P6_1, P6_1_PERI0_TR_IO_INPUT1},
{0u, 2u, P6_2, P6_2_PERI0_TR_IO_INPUT2},
{0u, 3u, P6_3, P6_3_PERI0_TR_IO_INPUT3},
{0u, 4u, P6_4, P6_4_PERI0_TR_IO_INPUT4},
{0u, 5u, P6_5, P6_5_PERI0_TR_IO_INPUT5},
{0u, 6u, P6_6, P6_6_PERI0_TR_IO_INPUT6},
{0u, 7u, P6_7, P6_7_PERI0_TR_IO_INPUT7},
};
/* Connections for: peri_tr_io_output */
/* The actual channel_num has no value to how the connection works. However, the HAL driver needs
to know the index of the input or output trigger line. Store that in the channel_num field
instead. */
const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = {
{0u, 0u, P7_0, P7_0_PERI0_TR_IO_OUTPUT0},
{0u, 1u, P7_1, P7_1_PERI0_TR_IO_OUTPUT1},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[8] = {
{0u, 0u, P6_0, P6_0_SCB0_I2C_SCL},
{1u, 0u, P7_0, P7_0_SCB1_I2C_SCL},
{2u, 0u, P8_0, P8_0_SCB2_I2C_SCL},
{5u, 0u, P11_0, P11_0_SCB5_I2C_SCL},
{6u, 0u, P12_0, P12_0_SCB6_I2C_SCL},
{7u, 0u, P13_0, P13_0_SCB7_I2C_SCL},
{10u, 0u, P16_0, P16_0_SCB10_I2C_SCL},
{11u, 0u, P17_0, P17_0_SCB11_I2C_SCL},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10] = {
{0u, 0u, P6_1, P6_1_SCB0_I2C_SDA},
{1u, 0u, P7_1, P7_1_SCB1_I2C_SDA},
{2u, 0u, P8_1, P8_1_SCB2_I2C_SDA},
{3u, 0u, P9_1, P9_1_SCB3_I2C_SDA},
{5u, 0u, P11_1, P11_1_SCB5_I2C_SDA},
{6u, 0u, P12_1, P12_1_SCB6_I2C_SDA},
{7u, 0u, P13_1, P13_1_SCB7_I2C_SDA},
{9u, 0u, P15_1, P15_1_SCB9_I2C_SDA},
{10u, 0u, P16_1, P16_1_SCB10_I2C_SDA},
{11u, 0u, P17_1, P17_1_SCB11_I2C_SDA},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8] = {
{0u, 0u, P6_0, P6_0_SCB0_SPI_CLK},
{1u, 0u, P7_0, P7_0_SCB1_SPI_CLK},
{2u, 0u, P8_0, P8_0_SCB2_SPI_CLK},
{5u, 0u, P11_0, P11_0_SCB5_SPI_CLK},
{6u, 0u, P12_0, P12_0_SCB6_SPI_CLK},
{7u, 0u, P13_0, P13_0_SCB7_SPI_CLK},
{10u, 0u, P16_0, P16_0_SCB10_SPI_CLK},
{11u, 0u, P17_0, P17_0_SCB11_SPI_CLK},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11] = {
{0u, 0u, P6_2, P6_2_SCB0_SPI_MISO},
{1u, 0u, P7_2, P7_2_SCB1_SPI_MISO},
{2u, 0u, P8_2, P8_2_SCB2_SPI_MISO},
{3u, 0u, P9_2, P9_2_SCB3_SPI_MISO},
{4u, 0u, P10_3, P10_3_SCB4_SPI_MISO},
{5u, 0u, P11_2, P11_2_SCB5_SPI_MISO},
{6u, 0u, P12_2, P12_2_SCB6_SPI_MISO},
{7u, 0u, P13_2, P13_2_SCB7_SPI_MISO},
{9u, 0u, P15_2, P15_2_SCB9_SPI_MISO},
{10u, 0u, P16_2, P16_2_SCB10_SPI_MISO},
{11u, 0u, P17_2, P17_2_SCB11_SPI_MISO},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11] = {
{0u, 0u, P6_1, P6_1_SCB0_SPI_MOSI},
{1u, 0u, P7_1, P7_1_SCB1_SPI_MOSI},
{2u, 0u, P8_1, P8_1_SCB2_SPI_MOSI},
{3u, 0u, P9_1, P9_1_SCB3_SPI_MOSI},
{4u, 0u, P10_2, P10_2_SCB4_SPI_MOSI},
{5u, 0u, P11_1, P11_1_SCB5_SPI_MOSI},
{6u, 0u, P12_1, P12_1_SCB6_SPI_MOSI},
{7u, 0u, P13_1, P13_1_SCB7_SPI_MOSI},
{9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI},
{10u, 0u, P16_1, P16_1_SCB10_SPI_MOSI},
{11u, 0u, P17_1, P17_1_SCB11_SPI_MOSI},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10] = {
{0u, 0u, P6_3, P6_3_SCB0_SPI_SELECT0},
{1u, 0u, P7_3, P7_3_SCB1_SPI_SELECT0},
{2u, 0u, P8_3, P8_3_SCB2_SPI_SELECT0},
{3u, 0u, P9_3, P9_3_SCB3_SPI_SELECT0},
{4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT0},
{5u, 0u, P11_3, P11_3_SCB5_SPI_SELECT0},
{6u, 0u, P12_3, P12_3_SCB6_SPI_SELECT0},
{7u, 0u, P13_3, P13_3_SCB7_SPI_SELECT0},
{9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0},
{10u, 0u, P16_3, P16_3_SCB10_SPI_SELECT0},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9] = {
{0u, 0u, P6_4, P6_4_SCB0_SPI_SELECT1},
{1u, 0u, P7_4, P7_4_SCB1_SPI_SELECT1},
{2u, 0u, P8_4, P8_4_SCB2_SPI_SELECT1},
{4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT1},
{5u, 0u, P11_4, P11_4_SCB5_SPI_SELECT1},
{6u, 0u, P12_4, P12_4_SCB6_SPI_SELECT1},
{7u, 0u, P13_4, P13_4_SCB7_SPI_SELECT1},
{9u, 0u, P15_4, P15_4_SCB9_SPI_SELECT1},
{10u, 0u, P16_4, P16_4_SCB10_SPI_SELECT1},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8] = {
{0u, 0u, P6_0, P6_0_SCB0_SPI_CLK},
{1u, 0u, P7_0, P7_0_SCB1_SPI_CLK},
{2u, 0u, P8_0, P8_0_SCB2_SPI_CLK},
{5u, 0u, P11_0, P11_0_SCB5_SPI_CLK},
{6u, 0u, P12_0, P12_0_SCB6_SPI_CLK},
{7u, 0u, P13_0, P13_0_SCB7_SPI_CLK},
{10u, 0u, P16_0, P16_0_SCB10_SPI_CLK},
{11u, 0u, P17_0, P17_0_SCB11_SPI_CLK},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11] = {
{0u, 0u, P6_2, P6_2_SCB0_SPI_MISO},
{1u, 0u, P7_2, P7_2_SCB1_SPI_MISO},
{2u, 0u, P8_2, P8_2_SCB2_SPI_MISO},
{3u, 0u, P9_2, P9_2_SCB3_SPI_MISO},
{4u, 0u, P10_3, P10_3_SCB4_SPI_MISO},
{5u, 0u, P11_2, P11_2_SCB5_SPI_MISO},
{6u, 0u, P12_2, P12_2_SCB6_SPI_MISO},
{7u, 0u, P13_2, P13_2_SCB7_SPI_MISO},
{9u, 0u, P15_2, P15_2_SCB9_SPI_MISO},
{10u, 0u, P16_2, P16_2_SCB10_SPI_MISO},
{11u, 0u, P17_2, P17_2_SCB11_SPI_MISO},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11] = {
{0u, 0u, P6_1, P6_1_SCB0_SPI_MOSI},
{1u, 0u, P7_1, P7_1_SCB1_SPI_MOSI},
{2u, 0u, P8_1, P8_1_SCB2_SPI_MOSI},
{3u, 0u, P9_1, P9_1_SCB3_SPI_MOSI},
{4u, 0u, P10_2, P10_2_SCB4_SPI_MOSI},
{5u, 0u, P11_1, P11_1_SCB5_SPI_MOSI},
{6u, 0u, P12_1, P12_1_SCB6_SPI_MOSI},
{7u, 0u, P13_1, P13_1_SCB7_SPI_MOSI},
{9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI},
{10u, 0u, P16_1, P16_1_SCB10_SPI_MOSI},
{11u, 0u, P17_1, P17_1_SCB11_SPI_MOSI},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10] = {
{0u, 0u, P6_3, P6_3_SCB0_SPI_SELECT0},
{1u, 0u, P7_3, P7_3_SCB1_SPI_SELECT0},
{2u, 0u, P8_3, P8_3_SCB2_SPI_SELECT0},
{3u, 0u, P9_3, P9_3_SCB3_SPI_SELECT0},
{4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT0},
{5u, 0u, P11_3, P11_3_SCB5_SPI_SELECT0},
{6u, 0u, P12_3, P12_3_SCB6_SPI_SELECT0},
{7u, 0u, P13_3, P13_3_SCB7_SPI_SELECT0},
{9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0},
{10u, 0u, P16_3, P16_3_SCB10_SPI_SELECT0},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9] = {
{0u, 0u, P6_4, P6_4_SCB0_SPI_SELECT1},
{1u, 0u, P7_4, P7_4_SCB1_SPI_SELECT1},
{2u, 0u, P8_4, P8_4_SCB2_SPI_SELECT1},
{4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT1},
{5u, 0u, P11_4, P11_4_SCB5_SPI_SELECT1},
{6u, 0u, P12_4, P12_4_SCB6_SPI_SELECT1},
{7u, 0u, P13_4, P13_4_SCB7_SPI_SELECT1},
{9u, 0u, P15_4, P15_4_SCB9_SPI_SELECT1},
{10u, 0u, P16_4, P16_4_SCB10_SPI_SELECT1},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10] = {
{1u, 0u, P7_2, P7_2_SCB1_UART_CTS},
{2u, 0u, P8_2, P8_2_SCB2_UART_CTS},
{3u, 0u, P9_2, P9_2_SCB3_UART_CTS},
{4u, 0u, P10_2, P10_2_SCB4_UART_CTS},
{5u, 0u, P11_2, P11_2_SCB5_UART_CTS},
{6u, 0u, P12_2, P12_2_SCB6_UART_CTS},
{7u, 0u, P13_2, P13_2_SCB7_UART_CTS},
{9u, 0u, P15_2, P15_2_SCB9_UART_CTS},
{10u, 0u, P16_2, P16_2_SCB10_UART_CTS},
{11u, 0u, P17_2, P17_2_SCB11_UART_CTS},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9] = {
{1u, 0u, P7_3, P7_3_SCB1_UART_RTS},
{2u, 0u, P8_3, P8_3_SCB2_UART_RTS},
{3u, 0u, P9_3, P9_3_SCB3_UART_RTS},
{4u, 0u, P10_3, P10_3_SCB4_UART_RTS},
{5u, 0u, P11_3, P11_3_SCB5_UART_RTS},
{6u, 0u, P12_3, P12_3_SCB6_UART_RTS},
{7u, 0u, P13_3, P13_3_SCB7_UART_RTS},
{9u, 0u, P15_3, P15_3_SCB9_UART_RTS},
{10u, 0u, P16_3, P16_3_SCB10_UART_RTS},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[7] = {
{1u, 0u, P7_0, P7_0_SCB1_UART_RX},
{2u, 0u, P8_0, P8_0_SCB2_UART_RX},
{5u, 0u, P11_0, P11_0_SCB5_UART_RX},
{6u, 0u, P12_0, P12_0_SCB6_UART_RX},
{7u, 0u, P13_0, P13_0_SCB7_UART_RX},
{10u, 0u, P16_0, P16_0_SCB10_UART_RX},
{11u, 0u, P17_0, P17_0_SCB11_UART_RX},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9] = {
{1u, 0u, P7_1, P7_1_SCB1_UART_TX},
{2u, 0u, P8_1, P8_1_SCB2_UART_TX},
{3u, 0u, P9_1, P9_1_SCB3_UART_TX},
{5u, 0u, P11_1, P11_1_SCB5_UART_TX},
{6u, 0u, P12_1, P12_1_SCB6_UART_TX},
{7u, 0u, P13_1, P13_1_SCB7_UART_TX},
{9u, 0u, P15_1, P15_1_SCB9_UART_TX},
{10u, 0u, P16_1, P16_1_SCB10_UART_TX},
{11u, 0u, P17_1, P17_1_SCB11_UART_TX},
};
/* Connections for: sdhc_card_cmd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2] = {
{0u, 0u, P6_0, P6_0_SDHC0_CARD_CMD},
{1u, 0u, P8_0, P8_0_SDHC1_CARD_CMD},
};
/* Connections for: sdhc_card_dat_3to0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8] = {
{0u, 0u, P6_2, P6_2_SDHC0_CARD_DAT_3TO00},
{0u, 1u, P6_3, P6_3_SDHC0_CARD_DAT_3TO01},
{0u, 2u, P6_4, P6_4_SDHC0_CARD_DAT_3TO02},
{0u, 3u, P6_5, P6_5_SDHC0_CARD_DAT_3TO03},
{1u, 0u, P8_2, P8_2_SDHC1_CARD_DAT_3TO00},
{1u, 1u, P8_3, P8_3_SDHC1_CARD_DAT_3TO01},
{1u, 2u, P8_4, P8_4_SDHC1_CARD_DAT_3TO02},
{1u, 3u, P8_5, P8_5_SDHC1_CARD_DAT_3TO03},
};
/* Connections for: sdhc_card_dat_7to4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[3] = {
{1u, 0u, P8_6, P8_6_SDHC1_CARD_DAT_7TO40},
{1u, 1u, P8_7, P8_7_SDHC1_CARD_DAT_7TO41},
{1u, 3u, P9_1, P9_1_SDHC1_CARD_DAT_7TO43},
};
/* Connections for: sdhc_card_detect_n */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2] = {
{0u, 0u, P6_6, P6_6_SDHC0_CARD_DETECT_N},
{1u, 0u, P9_3, P9_3_SDHC1_CARD_DETECT_N},
};
/* Connections for: sdhc_card_emmc_reset_n */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1] = {
{1u, 0u, P9_2, P9_2_SDHC1_CARD_EMMC_RESET_N},
};
/* Connections for: sdhc_card_if_pwr_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2] = {
{0u, 0u, P7_1, P7_1_SDHC0_CARD_IF_PWR_EN},
{1u, 0u, P10_2, P10_2_SDHC1_CARD_IF_PWR_EN},
};
/* Connections for: sdhc_card_mech_write_prot */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1] = {
{0u, 0u, P6_7, P6_7_SDHC0_CARD_MECH_WRITE_PROT},
};
/* Connections for: sdhc_clk_card */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2] = {
{0u, 0u, P6_1, P6_1_SDHC0_CLK_CARD},
{1u, 0u, P8_1, P8_1_SDHC1_CLK_CARD},
};
/* Connections for: sdhc_io_volt_sel */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2] = {
{0u, 0u, P7_0, P7_0_SDHC0_IO_VOLT_SEL},
{1u, 0u, P10_3, P10_3_SDHC1_IO_VOLT_SEL},
};
/* Connections for: sdhc_led_ctrl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: smif_smif0_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select0[1] = {
{0u, 0u, P0_2, P0_2_SMIF_SMIF0_SPIHB_SELECT0},
};
/* Connections for: smif_smif0_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select1[1] = {
{0u, 0u, P7_0, P7_0_SMIF_SMIF0_SPIHB_SELECT1},
};
/* Connections for: smif_smif0_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select2[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: smif_smif0_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif0_spi_select3[1] = {
{0u, 0u, NC, HSIOM_SEL_GPIO},
};
/* Connections for: smif_smif1_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select0[1] = {
{0u, 0u, P24_0, P24_0_SMIF_SMIF1_SPIHB_SELECT0},
};
/* Connections for: smif_smif1_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select1[1] = {
{0u, 0u, P6_6, P6_6_SMIF_SMIF1_SPIHB_SELECT1},
};
/* Connections for: smif_smif1_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select2[1] = {
{0u, 0u, P6_7, P6_7_SMIF_SMIF1_SPIHB_SELECT2},
};
/* Connections for: smif_smif1_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_smif1_spi_select3[1] = {
{0u, 0u, P7_1, P7_1_SMIF_SMIF1_SPIHB_SELECT3},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98] = {
{0u, 5u, P0_2, P0_2_TCPWM0_LINE5},
{1u, 5u, P0_2, P0_2_TCPWM0_LINE261},
{0u, 1u, P1_0, P1_0_TCPWM0_LINE1},
{1u, 1u, P1_0, P1_0_TCPWM0_LINE257},
{0u, 2u, P1_2, P1_2_TCPWM0_LINE2},
{1u, 2u, P1_2, P1_2_TCPWM0_LINE258},
{0u, 3u, P1_4, P1_4_TCPWM0_LINE3},
{1u, 3u, P1_4, P1_4_TCPWM0_LINE259},
{0u, 4u, P1_6, P1_6_TCPWM0_LINE4},
{1u, 4u, P1_6, P1_6_TCPWM0_LINE260},
{0u, 7u, P4_1, P4_1_TCPWM0_LINE7},
{1u, 7u, P4_1, P4_1_TCPWM0_LINE263},
{0u, 0u, P4_3, P4_3_TCPWM0_LINE0},
{1u, 8u, P4_3, P4_3_TCPWM0_LINE264},
{0u, 1u, P4_5, P4_5_TCPWM0_LINE1},
{1u, 9u, P4_5, P4_5_TCPWM0_LINE265},
{0u, 2u, P4_7, P4_7_TCPWM0_LINE2},
{1u, 10u, P4_7, P4_7_TCPWM0_LINE266},
{0u, 3u, P6_0, P6_0_TCPWM0_LINE3},
{1u, 11u, P6_0, P6_0_TCPWM0_LINE267},
{0u, 4u, P6_2, P6_2_TCPWM0_LINE4},
{1u, 12u, P6_2, P6_2_TCPWM0_LINE268},
{0u, 5u, P6_4, P6_4_TCPWM0_LINE5},
{1u, 13u, P6_4, P6_4_TCPWM0_LINE269},
{0u, 6u, P6_6, P6_6_TCPWM0_LINE6},
{1u, 14u, P6_6, P6_6_TCPWM0_LINE270},
{0u, 7u, P7_0, P7_0_TCPWM0_LINE7},
{1u, 15u, P7_0, P7_0_TCPWM0_LINE271},
{0u, 0u, P7_2, P7_2_TCPWM0_LINE0},
{1u, 16u, P7_2, P7_2_TCPWM0_LINE272},
{0u, 1u, P7_4, P7_4_TCPWM0_LINE1},
{1u, 17u, P7_4, P7_4_TCPWM0_LINE273},
{0u, 2u, P7_6, P7_6_TCPWM0_LINE2},
{1u, 18u, P7_6, P7_6_TCPWM0_LINE274},
{0u, 3u, P8_0, P8_0_TCPWM0_LINE3},
{1u, 19u, P8_0, P8_0_TCPWM0_LINE275},
{0u, 4u, P8_2, P8_2_TCPWM0_LINE4},
{1u, 20u, P8_2, P8_2_TCPWM0_LINE276},
{0u, 5u, P8_4, P8_4_TCPWM0_LINE5},
{1u, 21u, P8_4, P8_4_TCPWM0_LINE277},
{0u, 6u, P8_6, P8_6_TCPWM0_LINE6},
{1u, 22u, P8_6, P8_6_TCPWM0_LINE278},
{0u, 0u, P9_2, P9_2_TCPWM0_LINE0},
{1u, 0u, P9_2, P9_2_TCPWM0_LINE256},
{0u, 2u, P10_2, P10_2_TCPWM0_LINE2},
{1u, 2u, P10_2, P10_2_TCPWM0_LINE258},
{0u, 3u, P10_4, P10_4_TCPWM0_LINE3},
{1u, 3u, P10_4, P10_4_TCPWM0_LINE259},
{0u, 4u, P10_6, P10_6_TCPWM0_LINE4},
{1u, 4u, P10_6, P10_6_TCPWM0_LINE260},
{0u, 5u, P11_0, P11_0_TCPWM0_LINE5},
{1u, 5u, P11_0, P11_0_TCPWM0_LINE261},
{0u, 6u, P11_2, P11_2_TCPWM0_LINE6},
{1u, 6u, P11_2, P11_2_TCPWM0_LINE262},
{0u, 7u, P11_4, P11_4_TCPWM0_LINE7},
{1u, 7u, P11_4, P11_4_TCPWM0_LINE263},
{0u, 0u, P11_6, P11_6_TCPWM0_LINE0},
{1u, 8u, P11_6, P11_6_TCPWM0_LINE264},
{0u, 1u, P12_0, P12_0_TCPWM0_LINE1},
{1u, 9u, P12_0, P12_0_TCPWM0_LINE265},
{0u, 2u, P12_2, P12_2_TCPWM0_LINE2},
{1u, 10u, P12_2, P12_2_TCPWM0_LINE266},
{0u, 3u, P12_4, P12_4_TCPWM0_LINE3},
{1u, 11u, P12_4, P12_4_TCPWM0_LINE267},
{0u, 4u, P13_0, P13_0_TCPWM0_LINE4},
{1u, 12u, P13_0, P13_0_TCPWM0_LINE268},
{0u, 5u, P13_2, P13_2_TCPWM0_LINE5},
{1u, 13u, P13_2, P13_2_TCPWM0_LINE269},
{0u, 6u, P13_4, P13_4_TCPWM0_LINE6},
{1u, 14u, P13_4, P13_4_TCPWM0_LINE270},
{0u, 7u, P13_6, P13_6_TCPWM0_LINE7},
{1u, 15u, P13_6, P13_6_TCPWM0_LINE271},
{0u, 5u, P15_2, P15_2_TCPWM0_LINE5},
{1u, 21u, P15_2, P15_2_TCPWM0_LINE277},
{0u, 6u, P15_4, P15_4_TCPWM0_LINE6},
{1u, 22u, P15_4, P15_4_TCPWM0_LINE278},
{0u, 7u, P15_6, P15_6_TCPWM0_LINE7},
{1u, 23u, P15_6, P15_6_TCPWM0_LINE279},
{0u, 0u, P16_0, P16_0_TCPWM0_LINE0},
{1u, 0u, P16_0, P16_0_TCPWM0_LINE256},
{0u, 1u, P16_2, P16_2_TCPWM0_LINE1},
{1u, 1u, P16_2, P16_2_TCPWM0_LINE257},
{0u, 2u, P16_4, P16_4_TCPWM0_LINE2},
{1u, 2u, P16_4, P16_4_TCPWM0_LINE258},
{0u, 3u, P16_6, P16_6_TCPWM0_LINE3},
{1u, 3u, P16_6, P16_6_TCPWM0_LINE259},
{0u, 4u, P17_0, P17_0_TCPWM0_LINE4},
{1u, 4u, P17_0, P17_0_TCPWM0_LINE260},
{0u, 5u, P17_2, P17_2_TCPWM0_LINE5},
{1u, 5u, P17_2, P17_2_TCPWM0_LINE261},
{0u, 0u, P18_0, P18_0_TCPWM0_LINE0},
{1u, 8u, P18_0, P18_0_TCPWM0_LINE264},
{0u, 1u, P19_0, P19_0_TCPWM0_LINE1},
{1u, 9u, P19_0, P19_0_TCPWM0_LINE265},
{0u, 2u, P20_0, P20_0_TCPWM0_LINE2},
{1u, 10u, P20_0, P20_0_TCPWM0_LINE266},
{0u, 3u, P20_2, P20_2_TCPWM0_LINE3},
{1u, 11u, P20_2, P20_2_TCPWM0_LINE267},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[94] = {
{0u, 1u, P1_1, P1_1_TCPWM0_LINE_COMPL1},
{1u, 1u, P1_1, P1_1_TCPWM0_LINE_COMPL257},
{0u, 2u, P1_3, P1_3_TCPWM0_LINE_COMPL2},
{1u, 2u, P1_3, P1_3_TCPWM0_LINE_COMPL258},
{0u, 3u, P1_5, P1_5_TCPWM0_LINE_COMPL3},
{1u, 3u, P1_5, P1_5_TCPWM0_LINE_COMPL259},
{0u, 4u, P1_7, P1_7_TCPWM0_LINE_COMPL4},
{1u, 4u, P1_7, P1_7_TCPWM0_LINE_COMPL260},
{0u, 6u, P4_0, P4_0_TCPWM0_LINE_COMPL6},
{1u, 6u, P4_0, P4_0_TCPWM0_LINE_COMPL262},
{0u, 7u, P4_2, P4_2_TCPWM0_LINE_COMPL7},
{1u, 7u, P4_2, P4_2_TCPWM0_LINE_COMPL263},
{0u, 0u, P4_4, P4_4_TCPWM0_LINE_COMPL0},
{1u, 8u, P4_4, P4_4_TCPWM0_LINE_COMPL264},
{0u, 1u, P4_6, P4_6_TCPWM0_LINE_COMPL1},
{1u, 9u, P4_6, P4_6_TCPWM0_LINE_COMPL265},
{0u, 3u, P6_1, P6_1_TCPWM0_LINE_COMPL3},
{1u, 11u, P6_1, P6_1_TCPWM0_LINE_COMPL267},
{0u, 4u, P6_3, P6_3_TCPWM0_LINE_COMPL4},
{1u, 12u, P6_3, P6_3_TCPWM0_LINE_COMPL268},
{0u, 5u, P6_5, P6_5_TCPWM0_LINE_COMPL5},
{1u, 13u, P6_5, P6_5_TCPWM0_LINE_COMPL269},
{0u, 6u, P6_7, P6_7_TCPWM0_LINE_COMPL6},
{1u, 14u, P6_7, P6_7_TCPWM0_LINE_COMPL270},
{0u, 7u, P7_1, P7_1_TCPWM0_LINE_COMPL7},
{1u, 15u, P7_1, P7_1_TCPWM0_LINE_COMPL271},
{0u, 0u, P7_3, P7_3_TCPWM0_LINE_COMPL0},
{1u, 16u, P7_3, P7_3_TCPWM0_LINE_COMPL272},
{0u, 1u, P7_5, P7_5_TCPWM0_LINE_COMPL1},
{1u, 17u, P7_5, P7_5_TCPWM0_LINE_COMPL273},
{0u, 3u, P8_1, P8_1_TCPWM0_LINE_COMPL3},
{1u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL275},
{0u, 4u, P8_3, P8_3_TCPWM0_LINE_COMPL4},
{1u, 20u, P8_3, P8_3_TCPWM0_LINE_COMPL276},
{0u, 5u, P8_5, P8_5_TCPWM0_LINE_COMPL5},
{1u, 21u, P8_5, P8_5_TCPWM0_LINE_COMPL277},
{0u, 6u, P8_7, P8_7_TCPWM0_LINE_COMPL6},
{1u, 22u, P8_7, P8_7_TCPWM0_LINE_COMPL278},
{0u, 7u, P9_1, P9_1_TCPWM0_LINE_COMPL7},
{1u, 23u, P9_1, P9_1_TCPWM0_LINE_COMPL279},
{0u, 0u, P9_3, P9_3_TCPWM0_LINE_COMPL0},
{1u, 0u, P9_3, P9_3_TCPWM0_LINE_COMPL256},
{0u, 2u, P10_3, P10_3_TCPWM0_LINE_COMPL2},
{1u, 2u, P10_3, P10_3_TCPWM0_LINE_COMPL258},
{0u, 3u, P10_5, P10_5_TCPWM0_LINE_COMPL3},
{1u, 3u, P10_5, P10_5_TCPWM0_LINE_COMPL259},
{0u, 4u, P10_7, P10_7_TCPWM0_LINE_COMPL4},
{1u, 4u, P10_7, P10_7_TCPWM0_LINE_COMPL260},
{0u, 5u, P11_1, P11_1_TCPWM0_LINE_COMPL5},
{1u, 5u, P11_1, P11_1_TCPWM0_LINE_COMPL261},
{0u, 6u, P11_3, P11_3_TCPWM0_LINE_COMPL6},
{1u, 6u, P11_3, P11_3_TCPWM0_LINE_COMPL262},
{0u, 7u, P11_5, P11_5_TCPWM0_LINE_COMPL7},
{1u, 7u, P11_5, P11_5_TCPWM0_LINE_COMPL263},
{0u, 0u, P11_7, P11_7_TCPWM0_LINE_COMPL0},
{1u, 8u, P11_7, P11_7_TCPWM0_LINE_COMPL264},
{0u, 1u, P12_1, P12_1_TCPWM0_LINE_COMPL1},
{1u, 9u, P12_1, P12_1_TCPWM0_LINE_COMPL265},
{0u, 2u, P12_3, P12_3_TCPWM0_LINE_COMPL2},
{1u, 10u, P12_3, P12_3_TCPWM0_LINE_COMPL266},
{0u, 4u, P13_1, P13_1_TCPWM0_LINE_COMPL4},
{1u, 12u, P13_1, P13_1_TCPWM0_LINE_COMPL268},
{0u, 5u, P13_3, P13_3_TCPWM0_LINE_COMPL5},
{1u, 13u, P13_3, P13_3_TCPWM0_LINE_COMPL269},
{0u, 6u, P13_5, P13_5_TCPWM0_LINE_COMPL6},
{1u, 14u, P13_5, P13_5_TCPWM0_LINE_COMPL270},
{0u, 7u, P13_7, P13_7_TCPWM0_LINE_COMPL7},
{1u, 15u, P13_7, P13_7_TCPWM0_LINE_COMPL271},
{0u, 4u, P15_1, P15_1_TCPWM0_LINE_COMPL4},
{1u, 20u, P15_1, P15_1_TCPWM0_LINE_COMPL276},
{0u, 5u, P15_3, P15_3_TCPWM0_LINE_COMPL5},
{1u, 21u, P15_3, P15_3_TCPWM0_LINE_COMPL277},
{0u, 6u, P15_5, P15_5_TCPWM0_LINE_COMPL6},
{1u, 22u, P15_5, P15_5_TCPWM0_LINE_COMPL278},
{0u, 7u, P15_7, P15_7_TCPWM0_LINE_COMPL7},
{1u, 23u, P15_7, P15_7_TCPWM0_LINE_COMPL279},
{0u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL0},
{1u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL256},
{0u, 1u, P16_3, P16_3_TCPWM0_LINE_COMPL1},
{1u, 1u, P16_3, P16_3_TCPWM0_LINE_COMPL257},
{0u, 2u, P16_5, P16_5_TCPWM0_LINE_COMPL2},
{1u, 2u, P16_5, P16_5_TCPWM0_LINE_COMPL258},
{0u, 3u, P16_7, P16_7_TCPWM0_LINE_COMPL3},
{1u, 3u, P16_7, P16_7_TCPWM0_LINE_COMPL259},
{0u, 4u, P17_1, P17_1_TCPWM0_LINE_COMPL4},
{1u, 4u, P17_1, P17_1_TCPWM0_LINE_COMPL260},
{0u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL0},
{1u, 8u, P18_1, P18_1_TCPWM0_LINE_COMPL264},
{0u, 1u, P19_1, P19_1_TCPWM0_LINE_COMPL1},
{1u, 9u, P19_1, P19_1_TCPWM0_LINE_COMPL265},
{0u, 2u, P20_1, P20_1_TCPWM0_LINE_COMPL2},
{1u, 10u, P20_1, P20_1_TCPWM0_LINE_COMPL266},
{0u, 2u, P24_0, P24_0_TCPWM0_LINE_COMPL2},
{1u, 10u, P24_0, P24_0_TCPWM0_LINE_COMPL266},
};
/* Connections for: tdm_tdm_rx_fsync */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[2] = {
{0u, 0u, P10_2, P10_2_TDM_TDM_RX_FSYNC0},
{0u, 1u, P11_2, P11_2_TDM_TDM_RX_FSYNC1},
};
/* Connections for: tdm_tdm_rx_mck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1] = {
{0u, 1u, P11_0, P11_0_TDM_TDM_RX_MCK1},
};
/* Connections for: tdm_tdm_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1] = {
{0u, 1u, P11_1, P11_1_TDM_TDM_RX_SCK1},
};
/* Connections for: tdm_tdm_rx_sd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[2] = {
{0u, 0u, P10_3, P10_3_TDM_TDM_RX_SD0},
{0u, 1u, P11_3, P11_3_TDM_TDM_RX_SD1},
};
/* Connections for: tdm_tdm_tx_fsync */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[2] = {
{0u, 0u, P10_6, P10_6_TDM_TDM_TX_FSYNC0},
{0u, 1u, P11_6, P11_6_TDM_TDM_TX_FSYNC1},
};
/* Connections for: tdm_tdm_tx_mck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[2] = {
{0u, 0u, P10_4, P10_4_TDM_TDM_TX_MCK0},
{0u, 1u, P11_4, P11_4_TDM_TDM_TX_MCK1},
};
/* Connections for: tdm_tdm_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[2] = {
{0u, 0u, P10_5, P10_5_TDM_TDM_TX_SCK0},
{0u, 1u, P11_5, P11_5_TDM_TDM_TX_SCK1},
};
/* Connections for: tdm_tdm_tx_sd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[2] = {
{0u, 0u, P10_7, P10_7_TDM_TDM_TX_SD0},
{0u, 1u, P11_7, P11_7_TDM_TDM_TX_SD1},
};
#endif

463
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1D/source/triggers/cyhal_triggers_explorer.c
View File

@ -1,463 +0,0 @@
/***************************************************************************//**
* \file cyhal_triggers_explorer.c
*
* \brief
* Explorer family HAL triggers header
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#ifdef CY_DEVICE_EXPLORER
#include "triggers/cyhal_triggers_explorer.h"
const uint16_t cyhal_sources_per_mux[7] =
{
62, 3, 21, 73, 3, 65, 8,
};
const bool cyhal_is_mux_1to1[7] =
{
false, false, false, false, false, false, true,
};
const _cyhal_trigger_source_explorer_t cyhal_mux0_sources[62] =
{
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6,
_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7,
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0,
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1,
_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
_CYHAL_TRIGGER_TDM_TR_TX_REQ0,
_CYHAL_TRIGGER_TDM_TR_RX_REQ0,
_CYHAL_TRIGGER_TDM_TR_TX_REQ1,
_CYHAL_TRIGGER_TDM_TR_RX_REQ1,
_CYHAL_TRIGGER_PDM_TR_RX_REQ0,
_CYHAL_TRIGGER_PDM_TR_RX_REQ1,
_CYHAL_TRIGGER_PDM_TR_RX_REQ2,
_CYHAL_TRIGGER_PDM_TR_RX_REQ3,
_CYHAL_TRIGGER_PDM_TR_RX_REQ4,
_CYHAL_TRIGGER_PDM_TR_RX_REQ5,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6,
_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7,
_CYHAL_TRIGGER_I3C_TR_TX_REQ,
_CYHAL_TRIGGER_I3C_TR_RX_REQ,
_CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE,
};
const _cyhal_trigger_source_explorer_t cyhal_mux1_sources[3] =
{
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
};
const _cyhal_trigger_source_explorer_t cyhal_mux2_sources[21] =
{
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0,
_CYHAL_TRIGGER_CANFD_TR_FIFO00,
_CYHAL_TRIGGER_CANFD_TR_FIFO10,
_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1,
_CYHAL_TRIGGER_CANFD_TR_FIFO01,
_CYHAL_TRIGGER_CANFD_TR_FIFO11,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
_CYHAL_TRIGGER_LPCOMP_DSI_COMP0,
_CYHAL_TRIGGER_LPCOMP_DSI_COMP1,
_CYHAL_TRIGGER_TDM_TR_TX_REQ0,
_CYHAL_TRIGGER_TDM_TR_RX_REQ0,
_CYHAL_TRIGGER_TDM_TR_TX_REQ1,
_CYHAL_TRIGGER_TDM_TR_RX_REQ1,
_CYHAL_TRIGGER_PDM_TR_RX_REQ0,
_CYHAL_TRIGGER_PDM_TR_RX_REQ1,
_CYHAL_TRIGGER_PDM_TR_RX_REQ2,
_CYHAL_TRIGGER_PDM_TR_RX_REQ3,
_CYHAL_TRIGGER_PDM_TR_RX_REQ4,
_CYHAL_TRIGGER_PDM_TR_RX_REQ5,
};
const _cyhal_trigger_source_explorer_t cyhal_mux3_sources[73] =
{
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14,
_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15,
_CYHAL_TRIGGER_SCB0_TR_TX_REQ,
_CYHAL_TRIGGER_SCB1_TR_TX_REQ,
_CYHAL_TRIGGER_SCB2_TR_TX_REQ,
_CYHAL_TRIGGER_SCB3_TR_TX_REQ,
_CYHAL_TRIGGER_SCB4_TR_TX_REQ,
_CYHAL_TRIGGER_SCB5_TR_TX_REQ,
_CYHAL_TRIGGER_SCB6_TR_TX_REQ,
_CYHAL_TRIGGER_SCB7_TR_TX_REQ,
_CYHAL_TRIGGER_SCB8_TR_TX_REQ,
_CYHAL_TRIGGER_SCB9_TR_TX_REQ,
_CYHAL_TRIGGER_SCB10_TR_TX_REQ,
_CYHAL_TRIGGER_SCB11_TR_TX_REQ,
_CYHAL_TRIGGER_SCB0_TR_RX_REQ,
_CYHAL_TRIGGER_SCB1_TR_RX_REQ,
_CYHAL_TRIGGER_SCB2_TR_RX_REQ,
_CYHAL_TRIGGER_SCB3_TR_RX_REQ,
_CYHAL_TRIGGER_SCB4_TR_RX_REQ,
_CYHAL_TRIGGER_SCB5_TR_RX_REQ,
_CYHAL_TRIGGER_SCB6_TR_RX_REQ,
_CYHAL_TRIGGER_SCB7_TR_RX_REQ,
_CYHAL_TRIGGER_SCB8_TR_RX_REQ,
_CYHAL_TRIGGER_SCB9_TR_RX_REQ,
_CYHAL_TRIGGER_SCB10_TR_RX_REQ,
_CYHAL_TRIGGER_SCB11_TR_RX_REQ,
_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED,
_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0,
_CYHAL_TRIGGER_CANFD_TR_FIFO00,
_CYHAL_TRIGGER_CANFD_TR_FIFO10,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0,
_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1,
_CYHAL_TRIGGER_CANFD_TR_FIFO01,
_CYHAL_TRIGGER_CANFD_TR_FIFO11,
_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1,
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0,
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1,
_CYHAL_TRIGGER_TDM_TR_TX_REQ0,
_CYHAL_TRIGGER_TDM_TR_RX_REQ0,
_CYHAL_TRIGGER_TDM_TR_TX_REQ1,
_CYHAL_TRIGGER_TDM_TR_RX_REQ1,
_CYHAL_TRIGGER_PDM_TR_RX_REQ0,
_CYHAL_TRIGGER_PDM_TR_RX_REQ1,
_CYHAL_TRIGGER_PDM_TR_RX_REQ2,
_CYHAL_TRIGGER_PDM_TR_RX_REQ3,
_CYHAL_TRIGGER_PDM_TR_RX_REQ4,
_CYHAL_TRIGGER_PDM_TR_RX_REQ5,
};
const _cyhal_trigger_source_explorer_t cyhal_mux4_sources[3] =
{
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0,
_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1,
};
const _cyhal_trigger_source_explorer_t cyhal_mux5_sources[65] =
{
_CYHAL_TRIGGER_M33SYSCPUSS_ZERO,
_CYHAL_TRIGGER_TCPWM0_TR_OUT00,
_CYHAL_TRIGGER_TCPWM0_TR_OUT10,
_CYHAL_TRIGGER_TCPWM0_TR_OUT01,
_CYHAL_TRIGGER_TCPWM0_TR_OUT11,
_CYHAL_TRIGGER_TCPWM0_TR_OUT02,
_CYHAL_TRIGGER_TCPWM0_TR_OUT12,
_CYHAL_TRIGGER_TCPWM0_TR_OUT03,
_CYHAL_TRIGGER_TCPWM0_TR_OUT13,
_CYHAL_TRIGGER_TCPWM0_TR_OUT04,
_CYHAL_TRIGGER_TCPWM0_TR_OUT14,
_CYHAL_TRIGGER_TCPWM0_TR_OUT05,
_CYHAL_TRIGGER_TCPWM0_TR_OUT15,
_CYHAL_TRIGGER_TCPWM0_TR_OUT06,
_CYHAL_TRIGGER_TCPWM0_TR_OUT16,
_CYHAL_TRIGGER_TCPWM0_TR_OUT07,
_CYHAL_TRIGGER_TCPWM0_TR_OUT17,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0256,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1256,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0257,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1257,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0258,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1258,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0259,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1259,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0260,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1260,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0261,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1261,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0262,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1262,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0263,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1263,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0264,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1264,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0265,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1265,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0266,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1266,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0267,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1267,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0268,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1268,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0269,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1269,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0270,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1270,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0271,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1271,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0272,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1272,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0273,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1273,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0274,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1274,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0275,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1275,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0276,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1276,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0277,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1277,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0278,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1278,
_CYHAL_TRIGGER_TCPWM0_TR_OUT0279,
_CYHAL_TRIGGER_TCPWM0_TR_OUT1279,
};
const _cyhal_trigger_source_explorer_t cyhal_mux6_sources[8] =
{
_CYHAL_TRIGGER_SCB0_TR_TX_REQ,
_CYHAL_TRIGGER_SCB0_TR_RX_REQ,
_CYHAL_TRIGGER_SCB1_TR_TX_REQ,
_CYHAL_TRIGGER_SCB1_TR_RX_REQ,
_CYHAL_TRIGGER_SCB2_TR_TX_REQ,
_CYHAL_TRIGGER_SCB2_TR_RX_REQ,
_CYHAL_TRIGGER_SCB3_TR_TX_REQ,
_CYHAL_TRIGGER_SCB3_TR_RX_REQ,
};
const _cyhal_trigger_source_explorer_t* cyhal_mux_to_sources[7] =
{
cyhal_mux0_sources,
cyhal_mux1_sources,
cyhal_mux2_sources,
cyhal_mux3_sources,
cyhal_mux4_sources,
cyhal_mux5_sources,
cyhal_mux6_sources,
};
const uint8_t cyhal_dest_to_mux[69] =
{
2, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 */
2, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK1 */
1, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 */
1, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN1 */
3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */
3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN0 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN1 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN0 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN1 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN2 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN3 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN4 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN5 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN6 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN7 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN8 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN9 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN10 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN11 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN12 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN13 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN14 */
128, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN15 */
0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN0 */
0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN1 */
0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN2 */
0, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN3 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE2 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE3 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE4 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE5 */
4, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */
4, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */
4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */
4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 */
4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */
4, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */
4, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */
};
const uint8_t cyhal_mux_dest_index[69] =
{
28, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 */
29, /* CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK1 */
0, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 */
1, /* CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN1 */
0, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */
1, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */
8, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN0 */
9, /* CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN1 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN0 */
1, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN1 */
2, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN2 */
3, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN3 */
4, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN4 */
5, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN5 */
6, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN6 */
7, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN7 */
0, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN8 */
1, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN9 */
2, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN10 */
3, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN11 */
4, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN12 */
5, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN13 */
6, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN14 */
7, /* CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN15 */
10, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN0 */
11, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN1 */
12, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN2 */
13, /* CYHAL_TRIGGER_PASS_TR_LPPASS_IN3 */
0, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */
1, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */
2, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE2 */
3, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE3 */
4, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE4 */
5, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE5 */
3, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */
0, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */
4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */
5, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 */
6, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT */
0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */
1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */
2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */
3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */
4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */
5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */
6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */
7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */
8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */
9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */
10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */
11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */
12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */
13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */
14, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */
15, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */
16, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */
17, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */
18, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */
19, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */
20, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */
21, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */
22, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */
23, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */
24, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */
25, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */
26, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */
27, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */
1, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */
2, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */
};
#endif /* CY_DEVICE_EXPLORER */

232
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/EULA
View File

@ -1,55 +1,211 @@
CYPRESS END USER LICENSE AGREEMENT
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PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
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b. (i) if provided in Source Code form, to copy, modify, and compile the
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10. Restricted Rights. The Software is commercial computer software as that term is described in 48 C.F.R. 252.227-7014(a)(1). If the Software is being acquired by or on behalf of the U.S. Government or by a U.S. Government prime contractor or subcontractor (at any tier), then the Government's rights in Software shall be only those set forth in this Agreement.
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installed on a device that includes the Cypress hardware product
that the Driver is intended to enable; and
11. Personal Information. You agree that information you provide through your registration on Cypress IoT Community Forum or other Cypress websites, including contact information or other personal information, may be collected and used by Cypress consistent with its Data Privacy Policy (www.cypress.com/privacy-policy), as updated or revised from time to time, and may be provided to its third party sales representatives, distributors and other entities conducting sales activities for Cypress for sales-related and other business purposes.
d. (i) if provided in Source Code form, to copy, modify, and compile the
Host Application Source Code to create one or more Host
Applications to program, control, or communicate with a Cypress
hardware product, and
(ii) to distribute Host Applications, in binary code form only, only
when installed on a device that includes a Cypress hardware product
that the Host Application is intended to program, control, or
communicate with; and
12. General. This Agreement will bind and inure to the benefit of each party's successors and assigns, provided that you may not assign or transfer this Agreement, in whole or in part, without Cypress' written consent. This Agreement shall be governed by and construed in accordance with the laws of the State of California, United States of America, as if performed wholly within the state and without giving effect to the principles of conflict of law. The parties consent to personal and exclusive jurisdiction of and venue in, the state and federal courts within Santa Clara County, California; provided however, that nothing in this Agreement will limit Cypress' right to bring legal action in any venue in order to protect or enforce its intellectual property rights. No failure of either party to exercise or enforce any of its rights under this Agreement will act as a waiver of such rights. If any portion of this Agreement is found to be void or unenforceable, the remaining provisions of this Agreement shall remain in full force and effect. This Agreement is the complete and exclusive agreement between the parties with respect to the subject matter hereof, superseding and replacing any and all prior agreements, communications, and understandings (both written and oral) regarding such subject matter. Any notice to Cypress will be deemed effective when actually received and must be sent to Cypress Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San Jose, CA 95134 USA.
e. to freely distribute any inf File.
Any distribution of Software permitted under this Agreement must be made
pursuant to your standard end user license agreement used for your proprietary
(closed source) software products, such end user license agreement to include,
at a minimum, provisions limiting your licensors' liability and prohibiting
reverse engineering of the Software, consistent with such provisions in this
Agreement.
3. Free and Open Source Software. Portions of the Software may be licensed
under free and/or open source licenses such as the GNU General Public License
or other licenses from third parties ("Third Party Software"). Third Party
Software is subject to the applicable license agreement and not this
Agreement. If you are entitled to receive the source code from Cypress for
any Third Party Software included with the Software, either the source code
will be included with the Software or you may obtain the source code at no
charge from
<https://www.infineon.com/cms/en/design-support/software/free-and-open-source-software-foss/>.
The applicable license terms will accompany each source code package. To
review the license terms applicable to any Third Party Software for which
Cypress is not required to provide you with source code, please see the
Software's installation directory on your computer.
4. Proprietary Rights; Ownership. The Software, including all intellectual
property rights therein, is and will remain the sole and exclusive property of
Cypress or its suppliers. Cypress retains ownership of the Source Code and
any compiled version thereof. Subject to Cypress' ownership of the underlying
Software (including Source Code), you retain ownership of any modifications
you make to the Source Code. You agree not to remove any Cypress copyright or
other notices from the Source Code and any modifications thereof. You agree
to keep the Source Code confidential. Any reproduction, modification,
translation, compilation, or representation of the Source Code except as
permitted in Section 2 ("License") is prohibited without the express written
permission of Cypress. Except as otherwise expressly provided in this
Agreement, you may not:
(i) modify, adapt, or create derivative works based upon the Software;
(ii) copy the Software;
(iii) except and only to the extent explicitly permitted by applicable
law despite this limitation, decompile, translate, reverse engineer,
disassemble or otherwise reduce the Software to human-readable form;
or
(iv) use the Software or any sample code other than for the Purpose.
You hereby covenant that you will not assert any claim that the Software, or
derivative works thereof created by or for Cypress, infringe any intellectual
property right owned or controlled by you
5. No Support. Cypress may, but is not required to, provide technical support
for the Software.
6. Term and Termination. This Agreement is effective until terminated, and
either party may terminate this Agreement at any time with or without cause.
This Agreement and your license rights under this Agreement will terminate
immediately without notice from Cypress if you fail to comply with any
provision of this Agreement. Upon termination, you must destroy all copies of
Software in your possession or control. The following paragraphs shall
survive any termination of this Agreement: "Free and Open Source Software,"
"Proprietary Rights; Ownership," "Compliance With Law," "Disclaimer,"
"Limitation of Liability," and "General."
7. Compliance With Law. Each party agrees to comply with all applicable laws,
rules and regulations in connection with its activities under this Agreement.
Without limiting the foregoing, the Software may be subject to export control
laws and regulations of the United States and other countries. You agree to
comply strictly with all such laws and regulations and acknowledge that you
have the responsibility to obtain licenses to export, re-export, or import the
Software.
8. Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS
MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THE
SOFTWARE, INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress
reserves the right to make changes to the Software without notice. Cypress
does not assume any liability arising out of the application or use of
Software or any product or circuit described in the Software. It is the
responsibility of the user of the Software to properly design, program, and
test the functionality and safety of any application made of the Software and
any resulting product. Cypress does not authorize its Software or products
for use in any products where a malfunction or failure of the Software or
Cypress product may reasonably be expected to result in significant property
damage, injury or death ("High Risk Product"). If you include any Software or
Cypress product in a High Risk Product, you assume all risk of such use and
agree to indemnify Cypress and its suppliers against all liability. No
computing device can be absolutely secure. Therefore, despite security
measures implemented in Cypress hardware or software products, Cypress does
not assume any liability arising out of any security breach, such as
unauthorized access to or use of a Cypress product.
9. Limitation of Liability. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE
LAW, IN NO EVENT WILL CYPRESS OR ITS SUPPLIERS, RESELLERS, OR DISTRIBUTORS BE
LIABLE FOR ANY LOST REVENUE, PROFIT, OR DATA, OR FOR SPECIAL, INDIRECT,
CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGES HOWEVER CAUSED AND REGARDLESS
OF THE THEORY OF LIABILITY, ARISING OUT OF OR RELATED TO THE USE OF OR
INABILITY TO USE THE SOFTWARE EVEN IF CYPRESS OR ITS SUPPLIERS, RESELLERS, OR
DISTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO
EVENT SHALL CYPRESS' OR ITS SUPPLIERS', RESELLERS', OR DISTRIBUTORS' TOTAL
LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE), OR
OTHERWISE, EXCEED THE GREATER OF US$500 OR THE PRICE PAID BY YOU FOR THE
SOFTWARE. THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED
WARRANTY FAILS OF ITS ESSENTIAL PURPOSE. BECAUSE SOME STATES OR JURISDICTIONS
DO NOT ALLOW LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES,
ALL OR PORTIONS OF THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
10. Restricted Rights. The Software is commercial computer software as that
term is described in 48 C.F.R. 252.227-7014(a)(1). If the Software is being
acquired by or on behalf of the U.S. Government or by a U.S. Government prime
contractor or subcontractor (at any tier), then the Government's rights in
Software shall be only those set forth in this Agreement.
11. Personal Information. You agree that information you provide through your
registration on Cypress IoT Community Forum or other Cypress websites,
including contact information or other personal information, may be collected
and used by Cypress consistent with its Data Privacy Policy
(https://www.infineon.com/cms/en/about-infineon/privacy-policy/), as updated
or revised from time to time, and may be provided to its third party sales
representatives, distributors and other entities conducting sales activities
for Cypress for sales-related and other business purposes.
12. General. This Agreement will bind and inure to the benefit of each
party's successors and assigns, provided that you may not assign or transfer
this Agreement, in whole or in part, without Cypress' written consent. This
Agreement shall be governed by and construed in accordance with the laws of
the State of California, United States of America, as if performed wholly
within the state and without giving effect to the principles of conflict of
law. The parties consent to personal and exclusive jurisdiction of and venue
in, the state and federal courts within Santa Clara County, California;
provided however, that nothing in this Agreement will limit Cypress' right to
bring legal action in any venue in order to protect or enforce its
intellectual property rights. No failure of either party to exercise or
enforce any of its rights under this Agreement will act as a waiver of such
rights. If any portion of this Agreement is found to be void or
unenforceable, the remaining provisions of this Agreement shall remain in full
force and effect. This Agreement is the complete and exclusive agreement
between the parties with respect to the subject matter hereof, superseding and
replacing any and all prior agreements, communications, and understandings
(both written and oral) regarding such subject matter. Any notice to Cypress
will be deemed effective when actually received and must be sent to Cypress
Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San
Jose, CA 95134 USA.

28
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/RELEASE.md
View File

@ -1,7 +1,7 @@
# CAT1 (PSoC™ 6) Hardware Abstraction Layer (HAL) Release Notes
The CAT1 Hardware Abstraction Layer (HAL) provides an implementation of the Hardware Abstraction Layer for the PSoC™ 6 family of chips. This API provides convenience methods for initializing and manipulating different hardware peripherals. Depending on the specific chip being used, not all features may be supported.
# CAT1 Hardware Abstraction Layer (HAL) Release Notes
The CAT1 Hardware Abstraction Layer (HAL) provides an implementation of the Hardware Abstraction Layer for the PSoC™ 6 and XMC7000/T2G-B-H families of chips. This API provides convenience methods for initializing and manipulating different hardware peripherals. Depending on the specific chip being used, not all features may be supported.
This library is only supported on the Cortex-M4. It is not compatible with the Cortex-M0+. Any peripherals used by the Cortex-M0+ must be configured using the PDL and reserved on the Cortex-M4 by calling cyhal_hwmgr_reserve(). This ensures the HAL is aware the resource is in use and does not overuse it.
On devices which contain multiple cores, this library is supported on all cores. If HAL is used on multiple cores at the same time, the application is responsible for ensuring that each peripheral is only used on one core at a given time. This can be achieved by calling cyhal_hwmgr_reserve() on the core(s) where a particular resource is not expected to be used. This ensures the HAL is aware the resource is in use and does not use it in a conflicting manner.
### What's Included?
This release of the CAT1 HAL includes support for the following drivers:
@ -15,8 +15,11 @@ This release of the CAT1 HAL includes support for the following drivers:
* Flash
* GPIO
* Hardware Manager
* KeyScan
* I2C
* I2S
* Interconnect
* IPC
* LowPower Timer (LPTimer)
* OpAmp
* PDM/PCM
@ -37,6 +40,17 @@ This release of the CAT1 HAL includes support for the following drivers:
* WDT
### What Changed?
#### v2.3.0
* Add new SPI APIs
* Fix incorrect base address calculation on some devices in SCB-based drivers (UART, SPI, I2C, EZI2C).
* Extend documentation on pins and triggers to cover additional devices.
#### v2.2.0
* Production support for CAT1C devices
* Improve interrupt handling when running on on CM0+ core
* Add new I2C slave APIs
* Add driver for inter-processor communication (IPC)
* Add new function `cyhal_system_reset_device`
NOTE: This version requires udb-sdio-whd 1.2.0 or later
#### v2.1.0
* Pre-production support for CAT1B devices
* Fixed a few bugs in various drivers
@ -160,10 +174,10 @@ This version of the CAT1 Hardware Abstraction Layer was validated for compatibil
| Software and Tools | Version |
| :--- | :----: |
| ModusToolbox™ Software Environment | 2.4.0 |
| ModusToolbox™ Software Environment | 3.0.0 |
| GCC Compiler | 10.3.1 |
| IAR Compiler | 8.4 |
| ARM Compiler | 6.11 |
| IAR Compiler | 9.30.1 |
| ARM Compiler | 6.16 |
Minimum required ModusToolbox™ Software Environment: v2.0
@ -175,4 +189,4 @@ Use the following links for more information, as needed:
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
---
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021.
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal.h
View File

@ -21,7 +21,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@ -116,6 +116,8 @@
*/
/** Macro specifying whether the I2S driver is available for the current device \def CYHAL_DRIVER_AVAILABLE_I2S
*/
/** Macro specifying whether the IPC driver is available for the current device \def CYHAL_DRIVER_AVAILABLE_IPC
*/
/** Macro specifying whether the TX functionality is available on the I2S driver for the current device \def CYHAL_DRIVER_AVAILABLE_I2S_TX
*/
/** Macro specifying whether the RX functionality is available on the I2S driver for the current device \def CYHAL_DRIVER_AVAILABLE_I2S_RX

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_adc.h
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_clock.h
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_comp.h
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@ -8,7 +8,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_crc.h
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_dac.h
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

8
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_dma.h
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@ -243,9 +243,9 @@ typedef enum
* stringent address and data alignment requirements. */
typedef struct
{
uint32_t src_addr; //!< Source address
uint32_t src_addr; //!< Source address. Some devices can apply special requirements for user data arrays. Please refer to implementation-specific documentation to see whether any limitations exist for used device.
int16_t src_increment; //!< Source address auto increment amount in multiples of transfer_width
uint32_t dst_addr; //!< Destination address
uint32_t dst_addr; //!< Destination address. Some devices can apply special requirements for user data arrays. Please refer to implementation-specific documentation to see whether any limitations exist for used device.
int16_t dst_increment; //!< Destination address auto increment amount in multiples of transfer_width
uint8_t transfer_width; //!< Transfer width in bits. Valid values are: 8, 16, or 32
uint32_t length; //!< Number of elements to be transferred in total
@ -279,7 +279,7 @@ typedef struct
* @param[out] obj Pointer to a DMA object. The caller must allocate the memory
* for this object but the init function will initialize its contents.
* @param[in] src An optional source signal to connect to the DMA
* @param[in] dest An optional destination singal to drive from the DMA
* @param[in] dest An optional destination signal to drive from the DMA
* @param[out] dest_source An optional pointer to user-allocated source signal object which
* will be initialized by enable_output. If \p dest is non-null, this must also be non-null.
* \p dest_source should be passed to (dis)connect_digital functions to (dis)connect the

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_ezi2c.h
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

2
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_flash.h
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0

50
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_general_types.h
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@ -74,30 +74,32 @@ enum cyhal_rslt_module_chip
CYHAL_RSLT_MODULE_GPIO = (0x09), //!< An error occurred in GPIO module
CYHAL_RSLT_MODULE_I2C = (0x0A), //!< An error occurred in I2C module
CYHAL_RSLT_MODULE_I2S = (0x0B), //!< An error occurred in I2S module
CYHAL_RSLT_MODULE_INTERCONNECT = (0x0C), //!< An error occurred in Interconnect module
CYHAL_RSLT_MODULE_HWMGR = (0x0D), //!< An error occurred in hardware management module
CYHAL_RSLT_MODULE_KEYSCAN = (0x0E), //!< An error occurred in KeyScan module
CYHAL_RSLT_MODULE_LPTIMER = (0x0F), //!< An error occured in LPTimer module
CYHAL_RSLT_MODULE_OPAMP = (0x10), //!< An error occurred in OpAmp module
CYHAL_RSLT_MODULE_PDMPCM = (0x11), //!< An error occurred in PDM/PCM module
CYHAL_RSLT_MODULE_PWM = (0x12), //!< An error occurred in PWM module
CYHAL_RSLT_MODULE_QSPI = (0x13), //!< An error occurred in QSPI module
CYHAL_RSLT_MODULE_QUADDEC = (0x14), //!< An error occurred in Quadrature Decoder module
CYHAL_RSLT_MODULE_RTC = (0x15), //!< An error occurred in RTC module
CYHAL_RSLT_MODULE_SDHC = (0x16), //!< An error occurred in SDHC module
CYHAL_RSLT_MODULE_SDIO = (0x17), //!< An error occurred in SDIO module
CYHAL_RSLT_MODULE_SPI = (0x18), //!< An error occurred in SPI module
CYHAL_RSLT_MODULE_SYSPM = (0x19), //!< An error occurred in SysPM module
CYHAL_RSLT_MODULE_SYSTEM = (0x1A), //!< An error occurred in System module
CYHAL_RSLT_MODULE_TDM = (0x1B), //!< An error occurred in Timer module
CYHAL_RSLT_MODULE_TIMER = (0x1C), //!< An error occurred in Timer module
CYHAL_RSLT_MODULE_TRNG = (0x1D), //!< An error occurred in RNG module
CYHAL_RSLT_MODULE_UART = (0x1E), //!< An error occurred in UART module
CYHAL_RSLT_MODULE_USB = (0x1F), //!< An error occurred in USB module
CYHAL_RSLT_MODULE_WDT = (0x20), //!< An error occurred in WDT module
CYHAL_RSLT_MODULE_IPC = (0x0C), //!< An error occurred in IPC module
CYHAL_RSLT_MODULE_INTERCONNECT = (0x0D), //!< An error occurred in Interconnect module
CYHAL_RSLT_MODULE_HWMGR = (0x0E), //!< An error occurred in hardware management module
CYHAL_RSLT_MODULE_KEYSCAN = (0x0F), //!< An error occurred in KeyScan module
CYHAL_RSLT_MODULE_LPTIMER = (0x10), //!< An error occured in LPTimer module
CYHAL_RSLT_MODULE_OPAMP = (0x11), //!< An error occurred in OpAmp module
CYHAL_RSLT_MODULE_PDMPCM = (0x12), //!< An error occurred in PDM/PCM module
CYHAL_RSLT_MODULE_PWM = (0x13), //!< An error occurred in PWM module
CYHAL_RSLT_MODULE_QSPI = (0x14), //!< An error occurred in QSPI module
CYHAL_RSLT_MODULE_QUADDEC = (0x15), //!< An error occurred in Quadrature Decoder module
CYHAL_RSLT_MODULE_RTC = (0x16), //!< An error occurred in RTC module
CYHAL_RSLT_MODULE_SDHC = (0x17), //!< An error occurred in SDHC module
CYHAL_RSLT_MODULE_SDIO = (0x18), //!< An error occurred in SDIO module
CYHAL_RSLT_MODULE_SPI = (0x19), //!< An error occurred in SPI module
CYHAL_RSLT_MODULE_SYSPM = (0x1A), //!< An error occurred in SysPM module
CYHAL_RSLT_MODULE_SYSTEM = (0x1B), //!< An error occurred in System module
CYHAL_RSLT_MODULE_TDM = (0x1C), //!< An error occurred in Timer module
CYHAL_RSLT_MODULE_TIMER = (0x1D), //!< An error occurred in Timer module
CYHAL_RSLT_MODULE_TRNG = (0x1E), //!< An error occurred in RNG module
CYHAL_RSLT_MODULE_UART = (0x1F), //!< An error occurred in UART module
CYHAL_RSLT_MODULE_USB = (0x20), //!< An error occurred in USB module
CYHAL_RSLT_MODULE_WDT = (0x21), //!< An error occurred in WDT module
// Implementation specific section
CYHAL_RSLT_MODULE_IMPL_TCPWM = (0x21), //!< An error occurred in TCPWM module (TCPWM based drivers are: Timer, PWM, Quadrature Decoder)
CYHAL_RSLT_MODULE_IMPL_SCB = (0x22), //!< An error occurred in SCB module (SCB based drivers are: I2C, SPI, UART)
CYHAL_RSLT_MODULE_IMPL_TCPWM = (0x22), //!< An error occurred in TCPWM module (TCPWM based drivers are: Timer, PWM, Quadrature Decoder)
CYHAL_RSLT_MODULE_IMPL_SCB = (0x23), //!< An error occurred in SCB module (SCB based drivers are: I2C, SPI, UART)
CYHAL_RSLT_MODULE_T2TIMER = (0x24), //!< An error occurred in T2Timer module
};
/**

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