modify format
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1844 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
nongli1031@gmail.com
parent
08f25161d9
commit
ae73bd59bc
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@ -20,7 +20,7 @@
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int rt_application_init()
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{
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return 0;
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return 0;
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}
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/*@}*/
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@ -11,7 +11,7 @@
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* Date Author Notes
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* 2006-08-23 Bernard first implementation
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*
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* 2011-12-17 nl1031 for MacroBlaze
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* 2011-12-17 nl1031 for MicroBlaze
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*
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*/
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@ -39,17 +39,15 @@
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#define RS232_DEVICE_ID XPAR_USB_UART_DEVICE_ID
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#ifdef RT_USING_UART1
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#define USB_UART_BASE ((struct uartport *)XPAR_USB_UART_BASEADDR)
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#define USB_UART_BASE ((struct uartport *)XPAR_USB_UART_BASEADDR)
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#endif
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/* Global Variables: */
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XTmrCtr timer; /* The instance of the timer */
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XGpio gpio_output; /* The driver instance for GPIO Device configured as O/P */
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XUartLite uart_lite; /* Instance of the UartLite device */
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XIntc int_ctl; /* The instance of the Interrupt Controller */
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static rt_uint32_t led_data;
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XTmrCtr timer; /* The instance of the timer */
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XGpio gpio_output; /* The driver instance for GPIO Device configured as O/P */
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XUartLite uart_lite; /* Instance of the UartLite device */
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XIntc int_ctl; /* The instance of the Interrupt Controller */
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static rt_uint32_t led_data;
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static void rt_hw_board_led_init(void);
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@ -58,22 +56,22 @@ static void rt_hw_board_led_init(void);
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*/
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static void rt_hw_board_led_init()
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{
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rt_uint32_t status;
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led_data = 0;
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status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID);
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if (status != XST_SUCCESS)
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{
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return;
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}
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rt_uint32_t status;
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led_data = 0;
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status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID);
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if (status != XST_SUCCESS)
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{
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return;
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}
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/*
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* Set the direction for all signals to be outputs
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*/
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XGpio_SetDataDirection(&gpio_output, 1, 0x0);
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/*
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* Set the GPIO outputs to high
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*/
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XGpio_DiscreteWrite(&gpio_output, 1, 3);
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/*
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* Set the direction for all signals to be outputs
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*/
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XGpio_SetDataDirection(&gpio_output, 1, 0x0);
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/*
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* Set the GPIO outputs to high
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*/
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XGpio_DiscreteWrite(&gpio_output, 1, 3);
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}
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/**
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@ -83,8 +81,8 @@ static void rt_hw_board_led_init()
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*/
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void rt_hw_board_led_on(rt_uint32_t led)
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{
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led_data |= led;
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XGpio_DiscreteWrite(&gpio_output, 1, led_data);
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led_data |= led;
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XGpio_DiscreteWrite(&gpio_output, 1, led_data);
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}
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/**
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@ -94,23 +92,21 @@ void rt_hw_board_led_on(rt_uint32_t led)
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*/
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void rt_hw_board_led_off(rt_uint32_t led)
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{
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led_data &= ~led;
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XGpio_DiscreteWrite(&gpio_output, 1, led_data);
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led_data &= ~led;
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XGpio_DiscreteWrite(&gpio_output, 1, led_data);
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}
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void rt_hw_led_flash(void)
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{
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rt_uint32_t i;
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rt_uint32_t i;
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rt_hw_board_led_off(1);
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for (i = 0; i < 20000; i ++);
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rt_hw_board_led_off(1);
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for (i = 0; i < 20000; i++) ;
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rt_hw_board_led_on(1);
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for (i = 0; i < 20000; i ++);
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rt_hw_board_led_on(1);
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for (i = 0; i < 20000; i++) ;
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}
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#ifdef RT_USING_CONSOLE
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/*
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@ -124,109 +120,107 @@ void rt_hw_led_flash(void)
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*/
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void rt_hw_console_output(const char* str)
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{
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while (*str)
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{
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while (*str)
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{
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/* Transmit Character */
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XUartLite_SendByte(STDOUT_BASEADDRESS, *str);
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if (*str == '\n')
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XUartLite_SendByte(STDOUT_BASEADDRESS, '\r');
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str++;
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}
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/* Transmit Character */
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XUartLite_SendByte(STDOUT_BASEADDRESS, *str);
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if (*str == '\n')
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XUartLite_SendByte(STDOUT_BASEADDRESS, '\r');
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str++;
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}
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}
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static void rt_hw_console_init()
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{
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rt_uint32_t status;
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rt_uint32_t status;
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/*
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* Initialize the UartLite driver so that it is ready to use.
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*/
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status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
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if (status != XST_SUCCESS)
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{
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return;
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}
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/*
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* Initialize the UartLite driver so that it is ready to use.
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*/
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status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
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if (status != XST_SUCCESS)
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{
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return;
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}
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}
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#endif
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void rt_hw_timer_handler(void)
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{
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rt_uint32_t csr;
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csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET);
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/*
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* Check if timer expired and interrupt occured
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*/
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if (csr & XTC_CSR_INT_OCCURED_MASK)
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{
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rt_tick_increase();
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK);
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}
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rt_uint32_t csr;
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csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET);
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/*
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* Check if timer expired and interrupt occured
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*/
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if (csr & XTC_CSR_INT_OCCURED_MASK)
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{
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rt_tick_increase();
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK);
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}
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}
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/*
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*********************************************************************************************************
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* rt_intc_init()
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*
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* Description: This function intializes the interrupt controller by registering the appropriate handler
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* functions and enabling interrupts.
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*
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* Arguments : None
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*
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* Returns : None
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*********************************************************************************************************
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*/
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*********************************************************************************************************
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* rt_intc_init()
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*
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* Description: This function intializes the interrupt controller by registering the appropriate handler
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* functions and enabling interrupts.
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*
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* Arguments : None
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*
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* Returns : None
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*********************************************************************************************************
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*/
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void rt_intc_init (void)
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void rt_intc_init(void)
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{
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XStatus status;
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XStatus status;
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XIntc_MasterDisable(XPAR_INTC_0_BASEADDR);
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status = XIntc_Initialize(&int_ctl, XPAR_INTC_0_DEVICE_ID);
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/* install interrupt handler */
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rt_hw_interrupt_install(XPAR_INTC_0_TMRCTR_0_VEC_ID, (rt_isr_handler_t)rt_hw_timer_handler, RT_NULL);
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rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID);
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/* install interrupt handler */
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rt_hw_interrupt_install(XPAR_INTC_0_TMRCTR_0_VEC_ID, (rt_isr_handler_t) rt_hw_timer_handler, RT_NULL);
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XIntc_Start(&int_ctl, XIN_REAL_MODE);
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rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID);
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XIntc_Start(&int_ctl, XIN_REAL_MODE);
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}
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void rt_tmr_init (void)
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void rt_tmr_init(void)
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{
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rt_uint32_t ctl;
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XStatus status;
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rt_uint32_t ctl;
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XStatus status;
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status = XTmrCtr_Initialize(&timer, XPAR_AXI_TIMER_0_DEVICE_ID);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV);
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status = XTmrCtr_Initialize(&timer,XPAR_AXI_TIMER_0_DEVICE_ID);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV);
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ctl = XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK;
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl);
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XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl);
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}
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/**
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* This function will initial SPARTAN 6 LX9 board.
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*/
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void rt_hw_board_init()
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{
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/* init hardware console */
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rt_hw_console_init();
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/* init hardware console */
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rt_hw_console_init();
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/* init led */
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rt_hw_board_led_init();
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/* init led */
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rt_hw_board_led_init();
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/* init intc */
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/* init intc */
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rt_intc_init();
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/* timer init */
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rt_tmr_init();
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}
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@ -13,7 +13,6 @@
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#define __BOARD_H__
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#define MCK 50000000
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void rt_hw_board_led_on(rt_uint32_t);
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void rt_hw_board_led_off(rt_uint32_t);
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@ -16,7 +16,6 @@
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/* Tick per Second*/
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#define RT_TICK_PER_SECOND 100
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/* SECTION: RT_DEBUG */
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/* Thread Debug*/
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/* #define RT_THREAD_DEBUG */
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@ -89,7 +88,6 @@
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#define FINSH_THREAD_STACK_SIZE 8192
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#define RT_USING_TC
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/* SECTION: a runtime libc library */
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/* a runtime libc library*/
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/* #define RT_USING_NEWLIB */
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@ -16,7 +16,6 @@
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#include <rthw.h>
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#include <rtthread.h>
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//#include <AT91SAM7S.h>
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#include "board.h"
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#ifdef RT_USING_FINSH
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@ -26,7 +25,6 @@ extern void finsh_system_init(void);
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extern void rt_hw_led_flash(void);
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/*@{*/
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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@ -38,7 +36,7 @@ extern unsigned char __bss_end;
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#endif
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extern void rt_hw_interrupt_init(void);
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extern int rt_application_init(void);
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extern int rt_application_init(void);
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#ifdef RT_USING_DEVICE
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extern rt_err_t rt_hw_serial_init(void);
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#endif
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@ -48,73 +46,73 @@ extern rt_err_t rt_hw_serial_init(void);
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*/
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void rtthread_startup(void)
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{
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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/* init board */
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rt_hw_board_init();
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/* init board */
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rt_hw_board_init();
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rt_show_version();
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rt_show_version();
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/* init tick */
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rt_system_tick_init();
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/* init tick */
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rt_system_tick_init();
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/* init kernel object */
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rt_system_object_init();
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/* init kernel object */
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rt_system_object_init();
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/* init timer system */
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rt_system_timer_init();
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/* init timer system */
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rt_system_timer_init();
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#ifdef RT_USING_HEAP
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#ifdef __CC_ARM
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rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
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rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
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#elif __ICCARM__
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rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
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#else
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rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000));
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rt_system_heap_init((void*) &__bss_end, (void*) (&__bss_end + 0x4000));
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#endif
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#endif
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/* init scheduler system */
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rt_system_scheduler_init();
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/* init scheduler system */
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rt_system_scheduler_init();
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#ifdef RT_USING_HOOK /* if the hook is used */
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/* set idle thread hook */
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rt_thread_idle_sethook(rt_hw_led_flash);
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/* set idle thread hook */
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rt_thread_idle_sethook(rt_hw_led_flash);
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#endif
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//#ifdef RT_USING_DEVICE
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/* init hardware serial device */
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rt_hw_serial_init();
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/* init all device */
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rt_device_init_all();
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//#endif
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#ifdef RT_USING_DEVICE
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/* init hardware serial device */
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rt_hw_serial_init();
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/* init all device */
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rt_device_init_all();
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#endif
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/* init application */
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rt_application_init();
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/* init application */
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rt_application_init();
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#ifdef RT_USING_FINSH
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/* init finsh */
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finsh_system_init();
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finsh_set_device("uart1");
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/* init finsh */
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finsh_system_init();
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finsh_set_device("uart1");
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#endif
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/* init idle thread */
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rt_thread_idle_init();
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/* init idle thread */
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rt_thread_idle_init();
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/* start scheduler */
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rt_system_scheduler_start();
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/* start scheduler */
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rt_system_scheduler_start();
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/* never reach here */
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return ;
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/* never reach here */
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return;
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}
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int main (void)
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int main(void)
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{
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/* invoke rtthread_startup */
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rtthread_startup();
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/* invoke rtthread_startup */
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rtthread_startup();
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return 0;
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return 0;
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}
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/*@}*/
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@ -13,7 +13,7 @@
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*
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*/
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#include "microbalze.inc"
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#include "microblaze.inc"
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.text
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.globl rt_interrupt_enter
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|
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@ -22,23 +22,23 @@
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typedef volatile rt_uint32_t REG32;
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struct rt_mb_uart_lite_hw
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{
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REG32 Rx_FIFO; // Receiver Holding Register
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REG32 Tx_FIFO; // Transmitter Holding Register
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REG32 STAT_REG; // Channel Status Register
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REG32 CTRL_REG; // Control Register
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REG32 Rx_FIFO; // Receiver Holding Register
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REG32 Tx_FIFO; // Transmitter Holding Register
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REG32 STAT_REG; // Channel Status Register
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REG32 CTRL_REG; // Control Register
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};
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struct rt_mb_uart_lite
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{
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struct rt_device parent;
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struct rt_device parent;
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|
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struct rt_mb_uart_lite_hw* hw_base;
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rt_uint16_t peripheral_id;
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rt_uint32_t baudrate;
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struct rt_mb_uart_lite_hw* hw_base;
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rt_uint16_t peripheral_id;
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rt_uint32_t baudrate;
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/* reception field */
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rt_uint16_t save_index, read_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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/* reception field */
|
||||
rt_uint16_t save_index, read_index;
|
||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||
};
|
||||
#ifdef RT_USING_UART1
|
||||
struct rt_mb_uart_lite serial1;
|
||||
|
|
@ -46,265 +46,263 @@ struct rt_mb_uart_lite serial1;
|
|||
|
||||
static void rt_hw_serial_isr(void)
|
||||
{
|
||||
unsigned int status;
|
||||
rt_base_t level;
|
||||
struct rt_device* device;
|
||||
struct rt_mb_uart_lite* serial = RT_NULL;
|
||||
unsigned int status;
|
||||
rt_base_t level;
|
||||
struct rt_device* device;
|
||||
struct rt_mb_uart_lite* serial = RT_NULL;
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
/* serial 1 */
|
||||
serial = &serial1;
|
||||
/* serial 1 */
|
||||
serial = &serial1;
|
||||
#endif
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
/* get generic device object */
|
||||
device = (rt_device_t)serial;
|
||||
/* get generic device object */
|
||||
device = (rt_device_t) serial;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
/* get uart status register */
|
||||
status = serial->hw_base->STAT_REG;
|
||||
while (status & XUL_SR_RX_FIFO_VALID_DATA)
|
||||
{
|
||||
/* get received character */
|
||||
serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO;
|
||||
/* get uart status register */
|
||||
status = serial->hw_base->STAT_REG;
|
||||
while (status & XUL_SR_RX_FIFO_VALID_DATA)
|
||||
{
|
||||
/* get received character */
|
||||
serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO;
|
||||
|
||||
/* move to next position */
|
||||
serial->save_index ++;
|
||||
if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
serial->save_index = 0;
|
||||
/* move to next position */
|
||||
serial->save_index++;
|
||||
if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
serial->save_index = 0;
|
||||
|
||||
/* if the next position is read index, discard this 'read char' */
|
||||
if (serial->save_index == serial->read_index)
|
||||
{
|
||||
serial->read_index ++;
|
||||
if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
serial->read_index = 0;
|
||||
}
|
||||
status = serial->hw_base->STAT_REG;
|
||||
}
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
/* if the next position is read index, discard this 'read char' */
|
||||
if (serial->save_index == serial->read_index)
|
||||
{
|
||||
serial->read_index++;
|
||||
if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
serial->read_index = 0;
|
||||
}
|
||||
status = serial->hw_base->STAT_REG;
|
||||
}
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
/* indicate to upper layer application */
|
||||
if (device->rx_indicate != RT_NULL)
|
||||
device->rx_indicate(device, 1);
|
||||
/* indicate to upper layer application */
|
||||
if (device->rx_indicate != RT_NULL)
|
||||
device->rx_indicate(device, 1);
|
||||
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_init (rt_device_t dev)
|
||||
static rt_err_t rt_serial_init(rt_device_t dev)
|
||||
{
|
||||
struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev;
|
||||
struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
RT_ASSERT(serial->peripheral_id != XPAR_INTC_0_UARTLITE_1_VEC_ID);
|
||||
RT_ASSERT(serial->peripheral_id != XPAR_INTC_0_UARTLITE_1_VEC_ID);
|
||||
|
||||
// serial->hw_base->CTRL_REG = XUL_CR_FIFO_RX_RESET | /* Reset Receiver */
|
||||
// XUL_CR_FIFO_TX_RESET; /* Reset Transmitter */
|
||||
/* reset rx index */
|
||||
serial->save_index = 0;
|
||||
serial->read_index = 0;
|
||||
|
||||
/* reset rx index */
|
||||
serial->save_index = 0;
|
||||
serial->read_index = 0;
|
||||
/* reset rx buffer */
|
||||
rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
|
||||
|
||||
/* reset rx buffer */
|
||||
rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*) dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* enable UART rx interrupt */
|
||||
serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* enable UART rx interrupt */
|
||||
serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */
|
||||
|
||||
/* install UART handler */
|
||||
rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL);
|
||||
rt_hw_interrupt_umask(serial->peripheral_id);
|
||||
}
|
||||
/* install UART handler */
|
||||
rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t) rt_hw_serial_isr, RT_NULL);
|
||||
rt_hw_interrupt_umask(serial->peripheral_id);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_close(rt_device_t dev)
|
||||
{
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*) dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* disable interrupt */
|
||||
serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */
|
||||
}
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* disable interrupt */
|
||||
serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*) dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (serial->read_index != serial->save_index)
|
||||
{
|
||||
*ptr = serial->rx_buffer[serial->read_index];
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (serial->read_index != serial->save_index)
|
||||
{
|
||||
*ptr = serial->rx_buffer[serial->read_index];
|
||||
|
||||
serial->read_index ++;
|
||||
if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
serial->read_index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
serial->read_index++;
|
||||
if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
serial->read_index = 0;
|
||||
} else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
ptr ++; size --;
|
||||
}
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
|
||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||
}
|
||||
else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
|
||||
{
|
||||
/* not support right now */
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* poll mode */
|
||||
while (size)
|
||||
{
|
||||
/* Wait for Full Rx Buffer */
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA));
|
||||
return (rt_uint32_t) ptr - (rt_uint32_t) buffer;
|
||||
} else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
|
||||
{
|
||||
/* not support right now */
|
||||
RT_ASSERT(0);
|
||||
} else
|
||||
{
|
||||
/* poll mode */
|
||||
while (size)
|
||||
{
|
||||
/* Wait for Full Rx Buffer */
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA))
|
||||
;
|
||||
|
||||
/* Read Character */
|
||||
*ptr = serial->hw_base->Rx_FIFO;
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
/* Read Character */
|
||||
*ptr = serial->hw_base->Rx_FIFO;
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
|
||||
return (rt_size_t)ptr - (rt_size_t)buffer;
|
||||
}
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*) dev;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
|
||||
{
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* it's a stream mode device */
|
||||
while (size)
|
||||
{
|
||||
/* stream mode */
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
|
||||
serial->hw_base->Tx_FIFO = '\r';
|
||||
}
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
|
||||
{
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* it's a stream mode device */
|
||||
while (size)
|
||||
{
|
||||
/* stream mode */
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY))
|
||||
;
|
||||
serial->hw_base->Tx_FIFO = '\r';
|
||||
}
|
||||
|
||||
/* Wait for Empty Tx Buffer */
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
|
||||
/* Wait for Empty Tx Buffer */
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)) ;
|
||||
|
||||
/* Transmit Character */
|
||||
serial->hw_base->Tx_FIFO = *ptr;
|
||||
ptr ++; size --;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* Wait for Empty Tx Buffer */
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
|
||||
/* Transmit Character */
|
||||
serial->hw_base->Tx_FIFO = *ptr;
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* Wait for Empty Tx Buffer */
|
||||
while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY))
|
||||
;
|
||||
|
||||
/* Transmit Character */
|
||||
serial->hw_base->Tx_FIFO = *ptr;
|
||||
ptr ++; size --;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Transmit Character */
|
||||
serial->hw_base->Tx_FIFO = *ptr;
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t)ptr - (rt_size_t)buffer;
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t rt_hw_serial_init()
|
||||
{
|
||||
rt_device_t device;
|
||||
rt_device_t device;
|
||||
|
||||
#ifndef RT_USING_CONSOLE
|
||||
int Status;
|
||||
int Status;
|
||||
|
||||
/*
|
||||
* Initialize the UartLite driver so that it is ready to use.
|
||||
*/
|
||||
Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
/*
|
||||
* Initialize the UartLite driver so that it is ready to use.
|
||||
*/
|
||||
Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
device = (rt_device_t) &serial1;
|
||||
device = (rt_device_t) &serial1;
|
||||
|
||||
/* init serial device private data */
|
||||
serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR;
|
||||
serial1.peripheral_id = XPAR_INTC_0_UARTLITE_1_VEC_ID;
|
||||
serial1.baudrate = 9600;
|
||||
/* init serial device private data */
|
||||
serial1.hw_base = (struct rt_mb_uart_lite_hw*) XPAR_USB_UART_BASEADDR;
|
||||
serial1.peripheral_id = XPAR_INTC_0_UARTLITE_1_VEC_ID;
|
||||
serial1.baudrate = 9600;
|
||||
|
||||
/* set device virtual interface */
|
||||
device->init = rt_serial_init;
|
||||
device->open = rt_serial_open;
|
||||
device->close = rt_serial_close;
|
||||
device->read = rt_serial_read;
|
||||
device->write = rt_serial_write;
|
||||
device->control = rt_serial_control;
|
||||
/* set device virtual interface */
|
||||
device->init = rt_serial_init;
|
||||
device->open = rt_serial_open;
|
||||
device->close = rt_serial_close;
|
||||
device->read = rt_serial_read;
|
||||
device->write = rt_serial_write;
|
||||
device->control = rt_serial_control;
|
||||
|
||||
/* register uart1 on device subsystem */
|
||||
rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
||||
/* register uart1 on device subsystem */
|
||||
rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
||||
#endif
|
||||
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,8 @@
|
|||
*
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
extern void *_SDA_BASE_;
|
||||
extern void *_SDA2_BASE_;
|
||||
|
||||
|
||||
extern void *_SDA_BASE_;
|
||||
extern void *_SDA2_BASE_;
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
|
|
@ -28,44 +26,43 @@ extern void *_SDA2_BASE_;
|
|||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
unsigned long *stk;
|
||||
unsigned long *stk;
|
||||
|
||||
stk = (unsigned long *)stack_addr;
|
||||
stk--;
|
||||
stk--;
|
||||
*stk-- = 0; /* r31 */
|
||||
*stk-- = 0; /* r30 */
|
||||
*stk-- = 0; /* r29 */
|
||||
*stk-- = 0; /* r28 */
|
||||
*stk-- = 0; /* r27 */
|
||||
*stk-- = 0; /* r26 */
|
||||
*stk-- = 0; /* r25 */
|
||||
*stk-- = 0; /* r24 */
|
||||
*stk-- = 0; /* r23 */
|
||||
*stk-- = 0; /* r22 */
|
||||
*stk-- = 0; /* r21 */
|
||||
*stk-- = 0; /* r20 */
|
||||
*stk-- = 0; /* r19 */
|
||||
*stk-- = 0; /* r18 */
|
||||
*stk-- = 0; /* r17 */
|
||||
*stk-- = (unsigned long)texit; /* r15 = task return address*/
|
||||
*stk-- = (unsigned long)tentry; /* r14 = entry address*/
|
||||
*stk-- = (unsigned long)&_SDA_BASE_; /* r13 */
|
||||
*stk-- = 0; /* r12 */
|
||||
*stk-- = 0; /* r11 */
|
||||
*stk-- = 0; /* r10 */
|
||||
*stk-- = 0; /* r09 */
|
||||
*stk-- = 0; /* r08 */
|
||||
*stk-- = 0; /* r07 */
|
||||
*stk-- = 0; /* r06 */
|
||||
*stk-- = (unsigned long) parameter; /* r05 */
|
||||
*stk-- = 0; /* r04 */
|
||||
*stk-- = 0; /* r03 */
|
||||
*stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */
|
||||
*stk = 2; /* enable interrupt */
|
||||
return (rt_uint8_t *)stk;
|
||||
stk = (unsigned long *) stack_addr;
|
||||
stk--;
|
||||
stk--;
|
||||
*stk-- = 0; /* r31 */
|
||||
*stk-- = 0; /* r30 */
|
||||
*stk-- = 0; /* r29 */
|
||||
*stk-- = 0; /* r28 */
|
||||
*stk-- = 0; /* r27 */
|
||||
*stk-- = 0; /* r26 */
|
||||
*stk-- = 0; /* r25 */
|
||||
*stk-- = 0; /* r24 */
|
||||
*stk-- = 0; /* r23 */
|
||||
*stk-- = 0; /* r22 */
|
||||
*stk-- = 0; /* r21 */
|
||||
*stk-- = 0; /* r20 */
|
||||
*stk-- = 0; /* r19 */
|
||||
*stk-- = 0; /* r18 */
|
||||
*stk-- = 0; /* r17 */
|
||||
*stk-- = (unsigned long) texit; /* r15 = task return address*/
|
||||
*stk-- = (unsigned long) tentry; /* r14 = entry address*/
|
||||
*stk-- = (unsigned long) &_SDA_BASE_; /* r13 */
|
||||
*stk-- = 0; /* r12 */
|
||||
*stk-- = 0; /* r11 */
|
||||
*stk-- = 0; /* r10 */
|
||||
*stk-- = 0; /* r09 */
|
||||
*stk-- = 0; /* r08 */
|
||||
*stk-- = 0; /* r07 */
|
||||
*stk-- = 0; /* r06 */
|
||||
*stk-- = (unsigned long) parameter; /* r05 */
|
||||
*stk-- = 0; /* r04 */
|
||||
*stk-- = 0; /* r03 */
|
||||
*stk-- = (unsigned long) &_SDA2_BASE_; /* r02 */
|
||||
*stk = 2; /* enable interrupt */
|
||||
return (rt_uint8_t *) stk;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,20 +20,17 @@
|
|||
#include "xintc_i.h"
|
||||
#include "xintc_l.h"
|
||||
|
||||
|
||||
#define MAX_HANDLERS XPAR_INTC_MAX_NUM_INTR_INPUTS
|
||||
extern XIntc int_ctl; /* The instance of the Interrupt Controller */
|
||||
|
||||
|
||||
extern rt_uint32_t rt_interrupt_nest;
|
||||
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
|
||||
void rt_hw_interrupt_handler(int vector)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -41,24 +38,22 @@ void rt_hw_interrupt_handler(int vector)
|
|||
*/
|
||||
void rt_hw_interrupt_init()
|
||||
{
|
||||
rt_base_t index;
|
||||
|
||||
XIntc_Config *CfgPtr;
|
||||
rt_base_t index;
|
||||
|
||||
XIntc_Config *CfgPtr;
|
||||
|
||||
CfgPtr = &XIntc_ConfigTable[0];
|
||||
|
||||
for (index = 0; index < MAX_HANDLERS; index++)
|
||||
{
|
||||
CfgPtr->HandlerTable[index].Handler = (XInterruptHandler) rt_hw_interrupt_handler;
|
||||
}
|
||||
|
||||
for (index = 0; index < MAX_HANDLERS; index ++)
|
||||
{
|
||||
CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler;
|
||||
}
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -67,8 +62,8 @@ void rt_hw_interrupt_init()
|
|||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
/* disable interrupt */
|
||||
XIntc_Disable(&int_ctl,vector);
|
||||
/* disable interrupt */
|
||||
XIntc_Disable(&int_ctl, vector);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -77,7 +72,7 @@ void rt_hw_interrupt_mask(int vector)
|
|||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
XIntc_Enable(&int_ctl,vector);
|
||||
XIntc_Enable(&int_ctl, vector);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -88,124 +83,123 @@ void rt_hw_interrupt_umask(int vector)
|
|||
*/
|
||||
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
|
||||
{
|
||||
XIntc_Config *CfgPtr;
|
||||
XIntc_Config *CfgPtr;
|
||||
|
||||
CfgPtr = &XIntc_ConfigTable[0];
|
||||
|
||||
if(vector >= 0 && vector < MAX_HANDLERS)
|
||||
{
|
||||
if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler;
|
||||
if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler;
|
||||
}
|
||||
if (vector >= 0 && vector < MAX_HANDLERS)
|
||||
{
|
||||
if (*old_handler != RT_NULL)
|
||||
*old_handler = (rt_isr_handler_t) CfgPtr->HandlerTable[vector].Handler;
|
||||
if (new_handler != RT_NULL)
|
||||
CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler) new_handler;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/** copy from XIntc_DeviceInterruptHandler in xintc_l.c nl1031
|
||||
*
|
||||
* This function is the primary interrupt handler for the driver. It must be
|
||||
* connected to the interrupt source such that is called when an interrupt of
|
||||
* the interrupt controller is active. It will resolve which interrupts are
|
||||
* active and enabled and call the appropriate interrupt handler. It uses
|
||||
* the AckBeforeService flag in the configuration data to determine when to
|
||||
* acknowledge the interrupt. Highest priority interrupts are serviced first.
|
||||
* The driver can be configured to service only the highest priority interrupt
|
||||
* or all pending interrupts using the {XIntc_SetOptions()} function or
|
||||
* the {XIntc_SetIntrSrvOption()} function.
|
||||
*
|
||||
* This function assumes that an interrupt vector table has been previously
|
||||
* initialized. It does not verify that entries in the table are valid before
|
||||
* calling an interrupt handler.
|
||||
*
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* The constant XPAR_INTC_MAX_NUM_INTR_INPUTS must be setup for this to compile.
|
||||
* Interrupt IDs range from 0 - 31 and correspond to the interrupt input signals
|
||||
* for the interrupt controller. XPAR_INTC_MAX_NUM_INTR_INPUTS specifies the
|
||||
* highest numbered interrupt input signal that is used.
|
||||
*
|
||||
******************************************************************************/
|
||||
*
|
||||
* This function is the primary interrupt handler for the driver. It must be
|
||||
* connected to the interrupt source such that is called when an interrupt of
|
||||
* the interrupt controller is active. It will resolve which interrupts are
|
||||
* active and enabled and call the appropriate interrupt handler. It uses
|
||||
* the AckBeforeService flag in the configuration data to determine when to
|
||||
* acknowledge the interrupt. Highest priority interrupts are serviced first.
|
||||
* The driver can be configured to service only the highest priority interrupt
|
||||
* or all pending interrupts using the {XIntc_SetOptions()} function or
|
||||
* the {XIntc_SetIntrSrvOption()} function.
|
||||
*
|
||||
* This function assumes that an interrupt vector table has been previously
|
||||
* initialized. It does not verify that entries in the table are valid before
|
||||
* calling an interrupt handler.
|
||||
*
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* The constant XPAR_INTC_MAX_NUM_INTR_INPUTS must be setup for this to compile.
|
||||
* Interrupt IDs range from 0 - 31 and correspond to the interrupt input signals
|
||||
* for the interrupt controller. XPAR_INTC_MAX_NUM_INTR_INPUTS specifies the
|
||||
* highest numbered interrupt input signal that is used.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
void rt_hw_trap_irq(void )
|
||||
void rt_hw_trap_irq(void)
|
||||
{
|
||||
u32 intr_status;
|
||||
u32 intr_mask = 1;
|
||||
int intr_number;
|
||||
volatile u32 reg; /* used as bit bucket */
|
||||
XIntc_Config *cfg_ptr;
|
||||
u32 intr_status;
|
||||
u32 intr_mask = 1;
|
||||
int intr_number;
|
||||
volatile u32 reg; /* used as bit bucket */
|
||||
XIntc_Config *cfg_ptr;
|
||||
|
||||
/* Get the configuration data using the device ID */
|
||||
cfg_ptr = &XIntc_ConfigTable[0];
|
||||
|
||||
/* Get the configuration data using the device ID */
|
||||
cfg_ptr = &XIntc_ConfigTable[0];
|
||||
/* Get the interrupts that are waiting to be serviced */
|
||||
intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR);
|
||||
|
||||
/* Get the interrupts that are waiting to be serviced */
|
||||
intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR);
|
||||
/* Service each interrupt that is active and enabled by checking each
|
||||
* bit in the register from LSB to MSB which corresponds to an interrupt
|
||||
* intput signal
|
||||
*/
|
||||
for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++)
|
||||
{
|
||||
if (intr_status & 1)
|
||||
{
|
||||
XIntc_VectorTableEntry *table_ptr;
|
||||
|
||||
/* Service each interrupt that is active and enabled by checking each
|
||||
* bit in the register from LSB to MSB which corresponds to an interrupt
|
||||
* intput signal
|
||||
*/
|
||||
for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++)
|
||||
{
|
||||
if (intr_status & 1)
|
||||
{
|
||||
XIntc_VectorTableEntry *table_ptr;
|
||||
/* If the interrupt has been setup to acknowledge it
|
||||
* before servicing the interrupt, then ack it
|
||||
*/
|
||||
if (cfg_ptr->AckBeforeService & intr_mask)
|
||||
{
|
||||
XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
|
||||
}
|
||||
|
||||
/* If the interrupt has been setup to acknowledge it
|
||||
* before servicing the interrupt, then ack it
|
||||
*/
|
||||
if (cfg_ptr->AckBeforeService & intr_mask)
|
||||
{
|
||||
XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
|
||||
}
|
||||
/* The interrupt is active and enabled, call the
|
||||
* interrupt handler that was setup with the specified
|
||||
* parameter
|
||||
*/
|
||||
table_ptr = &(cfg_ptr->HandlerTable[intr_number]);
|
||||
table_ptr->Handler(table_ptr->CallBackRef);
|
||||
|
||||
/* The interrupt is active and enabled, call the
|
||||
* interrupt handler that was setup with the specified
|
||||
* parameter
|
||||
*/
|
||||
table_ptr = &(cfg_ptr->HandlerTable[intr_number]);
|
||||
table_ptr->Handler(table_ptr->CallBackRef);
|
||||
/* If the interrupt has been setup to acknowledge it
|
||||
* after it has been serviced then ack it
|
||||
*/
|
||||
if ((cfg_ptr->AckBeforeService & intr_mask) == 0)
|
||||
{
|
||||
XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
|
||||
}
|
||||
|
||||
/* If the interrupt has been setup to acknowledge it
|
||||
* after it has been serviced then ack it
|
||||
*/
|
||||
if ((cfg_ptr->AckBeforeService & intr_mask) == 0)
|
||||
{
|
||||
XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
|
||||
}
|
||||
/*
|
||||
* Read the ISR again to handle architectures with posted write
|
||||
* bus access issues.
|
||||
*/
|
||||
reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress);
|
||||
|
||||
/*
|
||||
* Read the ISR again to handle architectures with posted write
|
||||
* bus access issues.
|
||||
*/
|
||||
reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress);
|
||||
/*
|
||||
* If only the highest priority interrupt is to be
|
||||
* serviced, exit loop and return after servicing
|
||||
* the interrupt
|
||||
*/
|
||||
if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION)
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If only the highest priority interrupt is to be
|
||||
* serviced, exit loop and return after servicing
|
||||
* the interrupt
|
||||
*/
|
||||
if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION)
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
/* Move to the next interrupt to check */
|
||||
intr_mask <<= 1;
|
||||
intr_status >>= 1;
|
||||
|
||||
/* Move to the next interrupt to check */
|
||||
intr_mask <<= 1;
|
||||
intr_status >>= 1;
|
||||
|
||||
/* If there are no other bits set indicating that all interrupts
|
||||
* have been serviced, then exit the loop
|
||||
*/
|
||||
if (intr_status == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* If there are no other bits set indicating that all interrupts
|
||||
* have been serviced, then exit the loop
|
||||
*/
|
||||
if (intr_status == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue