AT32UC3B: Rewire _intx for updated exceptions file from Microchip (#8182)
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@ -1,54 +1,48 @@
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/* This file is part of the ATMEL AVR32-UC3-SoftwareFramework-1.6.0 Release */
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/*This file is prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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/**
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* \file
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*
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* \brief Exception and interrupt vectors.
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* \brief Exception and interrupt vectors mapping for the INTC Software Driver.
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*
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* This file maps all events supported by an AVR32.
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* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* - Compiler: GNU GCC for AVR32
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* - Supported devices: All AVR32 devices with an INTC module can be used.
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* - AppNote:
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* \asf_license_start
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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******************************************************************************/
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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an Atmel
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* AVR product.
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#if !__AVR32_UC__ && !__AVR32_AP__
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#error Implementation of the AVR32 architecture not supported by the INTC driver.
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#error Implementation for the AVR32 architecture only.
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#endif
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@ -59,227 +53,204 @@
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//! \verbatim
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.section .exception, "ax", @progbits
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.section .exception, "ax", @progbits
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// Start of Exception Vector Table.
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// EVBA must be aligned with a power of two strictly greater than the EVBA-
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// relative offset of the last vector.
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.balign 0x200
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/*
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* EVBA must be aligned with a power of two strictly greater than the
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* EVBA-relative offset of the last vector.
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*/
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.balign 0x200
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// Export symbol.
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.global _evba
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.type _evba, @function
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// Export symbol.
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.global _evba
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.type _evba, @function
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_evba:
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.org 0x000
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// Unrecoverable Exception.
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.org 0x000
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// Unrecoverable Exception.
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_handle_Unrecoverable_Exception:
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rjmp $
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rjmp $
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.org 0x004
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// TLB Multiple Hit.
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.org 0x004
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// TLB Multiple Hit.
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_handle_TLB_Multiple_Hit:
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rjmp $
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rjmp $
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.org 0x008
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// Bus Error Data Fetch.
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.org 0x008
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// Bus Error Data Fetch.
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_handle_Bus_Error_Data_Fetch:
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rjmp $
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rjmp $
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.org 0x00C
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// Bus Error Instruction Fetch.
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.org 0x00C
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// Bus Error Instruction Fetch.
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_handle_Bus_Error_Instruction_Fetch:
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rjmp $
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rjmp $
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.org 0x010
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// NMI.
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.org 0x010
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// NMI.
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_handle_NMI:
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rjmp $
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rjmp $
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.org 0x014
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// Instruction Address.
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.org 0x014
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// Instruction Address.
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_handle_Instruction_Address:
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rjmp $
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rjmp $
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.org 0x018
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// ITLB Protection.
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.org 0x018
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// ITLB Protection.
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_handle_ITLB_Protection:
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rjmp $
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rjmp $
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.org 0x01C
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// Breakpoint.
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.org 0x01C
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// Breakpoint.
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_handle_Breakpoint:
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rjmp $
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rjmp $
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.org 0x020
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// Illegal Opcode.
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.org 0x020
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// Illegal Opcode.
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_handle_Illegal_Opcode:
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rjmp $
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rjmp $
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.org 0x024
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// Unimplemented Instruction.
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.org 0x024
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// Unimplemented Instruction.
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_handle_Unimplemented_Instruction:
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rjmp $
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rjmp $
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.org 0x028
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// Privilege Violation.
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.org 0x028
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// Privilege Violation.
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_handle_Privilege_Violation:
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rjmp $
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rjmp $
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.org 0x02C
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// Floating-Point: UNUSED IN AVR32UC and AVR32AP.
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.org 0x02C
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// Floating-Point: UNUSED IN AVR32UC and AVR32AP.
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_handle_Floating_Point:
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rjmp $
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rjmp $
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.org 0x030
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// Coprocessor Absent: UNUSED IN AVR32UC.
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.org 0x030
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// Coprocessor Absent: UNUSED IN AVR32UC.
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_handle_Coprocessor_Absent:
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rjmp $
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rjmp $
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.org 0x034
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// Data Address (Read).
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.org 0x034
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// Data Address (Read).
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_handle_Data_Address_Read:
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rjmp $
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rjmp $
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.org 0x038
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// Data Address (Write).
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.org 0x038
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// Data Address (Write).
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_handle_Data_Address_Write:
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rjmp $
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rjmp $
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.org 0x03C
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// DTLB Protection (Read).
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.org 0x03C
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// DTLB Protection (Read).
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_handle_DTLB_Protection_Read:
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rjmp $
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rjmp $
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.org 0x040
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// DTLB Protection (Write).
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.org 0x040
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// DTLB Protection (Write).
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_handle_DTLB_Protection_Write:
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rjmp $
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rjmp $
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.org 0x044
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// DTLB Modified: UNUSED IN AVR32UC.
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.org 0x044
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// DTLB Modified: UNUSED IN AVR32UC.
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_handle_DTLB_Modified:
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rjmp $
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rjmp $
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.org 0x050
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// ITLB Miss.
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.org 0x050
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// ITLB Miss.
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_handle_ITLB_Miss:
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rjmp $
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rjmp $
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.org 0x060
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// DTLB Miss (Read).
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.org 0x060
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// DTLB Miss (Read).
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_handle_DTLB_Miss_Read:
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rjmp $
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rjmp $
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.org 0x070
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// DTLB Miss (Write).
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.org 0x070
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// DTLB Miss (Write).
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_handle_DTLB_Miss_Write:
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rjmp $
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rjmp $
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.org 0x100
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// Supervisor Call.
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.org 0x100
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// Supervisor Call.
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_handle_Supervisor_Call:
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rjmp $
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rjmp $
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// Interrupt support.
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// The interrupt controller must provide the offset address relative to EVBA.
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// Important note:
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// All interrupts call a C function named _get_interrupt_handler.
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// This function will read group and interrupt line number to then return in
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// R12 a pointer to a user-provided interrupt handler.
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/*
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* Interrupt support.
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* The interrupt controller must provide the offset address relative to EVBA.
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* Important note:
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* All interrupts call a C function named _get_interrupt_handler.
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* This function will read group and interrupt line number to then return in
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*R12 a pointer to a user-provided interrupt handler.
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*/
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.balign 4
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_int0:
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mov r12, 0 // Pass the int_level parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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breq _spint0 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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call rt_interrupt_enter
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icall r12
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call rt_interrupt_leave
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ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
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lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
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ld.w r11, r12[0]
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cp.w r11, 0
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brne _spint0
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lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
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ld.w r11, r12[0]
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cp.w r11, 1
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breq rt_hw_context_switch_interrupt_do
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_spint0:
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csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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_int1:
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mov r12, 1 // Pass the int_level parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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breq _spint1 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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call rt_interrupt_enter
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icall r12
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call rt_interrupt_leave
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ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
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lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
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ld.w r11, r12[0]
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cp.w r11, 0
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brne _spint1
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lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
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ld.w r11, r12[0]
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cp.w r11, 1
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breq rt_hw_context_switch_interrupt_do
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_spint1:
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csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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_int2:
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mov r12, 2 // Pass the int_level parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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breq _spint2 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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call rt_interrupt_enter
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icall r12
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call rt_interrupt_leave
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ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
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lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
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ld.w r11, r12[0]
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cp.w r11, 0
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brne _spint2
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lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
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ld.w r11, r12[0]
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cp.w r11, 1
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breq rt_hw_context_switch_interrupt_do
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_spint2:
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csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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_int3:
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mov r12, 3 // Pass the int_level parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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breq _spint3 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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call rt_interrupt_enter
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icall r12
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call rt_interrupt_leave
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ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
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lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
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ld.w r11, r12[0]
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cp.w r11, 0
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brne _spint3
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lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
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ld.w r11, r12[0]
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cp.w r11, 1
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breq rt_hw_context_switch_interrupt_do
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_spint3:
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csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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.balign 4
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.irp priority, 0, 1, 2, 3
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.global _int\priority
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.type _int\priority, @function
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_int\priority:
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#if __AVR32_UC__
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/*
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* R8-R12, LR, PC and SR are automatically pushed onto the system stack
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* by the CPU upon interrupt entry. No other register is saved by
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* hardware.
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*/
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#elif __AVR32_AP__
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/*
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* PC and SR are automatically saved in respectively RAR_INTx and
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* RSR_INTx by the CPU upon interrupt entry. No other register is saved
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* by hardware.
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*/
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pushm r8-r12, lr
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#endif
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mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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breq _spint\priority // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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call rt_interrupt_enter
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icall r12
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call rt_interrupt_leave
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ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
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lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
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ld.w r11, r12[0]
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cp.w r11, 0
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brne _spint\priority
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lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
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ld.w r11, r12[0]
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cp.w r11, 1
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breq rt_hw_context_switch_interrupt_do
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_spint\priority:
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csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
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#if __AVR32_UC__
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/*
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* If this was not a spurious interrupt (R12 != NULL), jump to the
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* handler.
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*/
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/* movne pc, r12 */
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#elif __AVR32_AP__
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// If this was a spurious interrupt (R12 == NULL), branch.
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breq spint\priority
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/*
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* Push the pointer to the interrupt handler onto the system stack since
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* no register may be altered.
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*/
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st.w --sp, r12
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popm r8-r12, lr, pc // Restore registers and jump to the handler.
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spint\priority:
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popm r8-r12, lr
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#endif
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/*
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* If this was a spurious interrupt (R12 == NULL), return from event
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* handler.
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*/
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rete
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.endr
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rt_hw_context_switch_interrupt_do:
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mov r11, 0
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@ -292,24 +263,22 @@ rt_hw_context_switch_interrupt_do:
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st.w r12[0], sp /* Store old thread SP */
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ld.w sp, r11[0] /* Load new thread SP */
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ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */
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rete /* RETE pops R8-R12, LR, PC, SR automatically */
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rete /* RETE pops R8-R12, LR, PC, SR automatically */
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// Constant data area.
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.balign 4
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.balign 4
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// Values to store in the interrupt priority registers for the various interrupt priority levels.
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// The interrupt priority registers contain the interrupt priority level and
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// the EVBA-relative interrupt vector offset.
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.global ipr_val
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.type ipr_val, @object
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// Values to store in the interrupt priority registers for the various interrupt priority levels.
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// The interrupt priority registers contain the interrupt priority level and
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// the EVBA-relative interrupt vector offset.
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.global ipr_val
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.type ipr_val, @object
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ipr_val:
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.word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
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(AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
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(AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
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(AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
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//! \endverbatim
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//! @}
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Reference in New Issue