diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 2abe335cf5..da65c8e884 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -19,4 +19,24 @@ menu "General Drivers Configuration" default 30 endif + menuconfig BSP_USING_I2C + bool "Using HW I2C" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default n + + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + + config I2C_IRQ_BASE + int + default 32 + endif endmenu diff --git a/bsp/cvitek/c906_little/board/tick.c b/bsp/cvitek/c906_little/board/tick.c old mode 100755 new mode 100644 index e2b9fb40a6..a371256136 --- a/bsp/cvitek/c906_little/board/tick.c +++ b/bsp/cvitek/c906_little/board/tick.c @@ -61,3 +61,21 @@ int rt_hw_tick_init(void) return 0; } + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + unsigned long start_time; + unsigned long end_time; + unsigned long run_time; + + start_time = get_ticks(); + end_time = start_time + us * (TIMER_CLK_FREQ / 1000000); + do{ + run_time = get_ticks(); + } while(run_time < end_time); +} diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index 1993774cba..27c24ff764 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -12,6 +12,9 @@ if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'): if GetDepend('BSP_USING_CV1800B'): src += ['drv_gpio.c'] +if GetDepend('BSP_USING_I2C'): + src += ['drv_hw_i2c.c'] + CPPDEFINES += ['-DCONFIG_64BIT'] group = DefineGroup('drivers', src, depend = [''], CPPDEFINES = CPPDEFINES, CPPPATH = CPPPATH) diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c new file mode 100644 index 0000000000..1cbb47dc2a --- /dev/null +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + *2024-02-14 ShichengChu first version + */ +#include "drv_hw_i2c.h" +#include +#include + +#ifdef RT_USING_I2C + +#define DBG_TAG "drv.i2c" +#define DBG_LVL DBG_INFO +#include + +#define false 0 +#define true 1 +struct _i2c_bus +{ + struct rt_i2c_bus_device parent; + uint8_t i2c_id; + char *device_name; +}; + +static struct _i2c_bus _i2c_obj[] = +{ +#ifdef BSP_USING_I2C0 + { + .i2c_id = I2C0, + .device_name = "i2c0", + }, +#endif /* BSP_USING_I2C0 */ +#ifdef BSP_USING_I2C1 + { + .i2c_id = I2C1, + .device_name = "i2c1", + }, +#endif /* BSP_USING_I2C1 */ +}; + +static struct i2c_regs *get_i2c_base(uint8_t i2c_id) +{ + struct i2c_regs *i2c_base = NULL; + + switch (i2c_id) { + case I2C0: + i2c_base = (struct i2c_regs *)I2C0_BASE; + break; + case I2C1: + i2c_base = (struct i2c_regs *)I2C1_BASE; + break; + case I2C2: + i2c_base = (struct i2c_regs *)I2C2_BASE; + break; + case I2C3: + i2c_base = (struct i2c_regs *)I2C3_BASE; + break; + case I2C4: + i2c_base = (struct i2c_regs *)I2C4_BASE; + break; + } + + return i2c_base; +} + +static uint32_t get_i2c_intr(uint8_t i2c_id) +{ + uint32_t i2c_intr = 0; + + switch (i2c_id) { + case I2C0: + i2c_intr = I2C0_IRQ; + break; + case I2C1: + i2c_intr = I2C1_IRQ; + break; + case I2C2: + i2c_intr = I2C2_IRQ; + break; + case I2C3: + i2c_intr = I2C3_IRQ; + break; + case I2C4: + i2c_intr = I2C4_IRQ; + break; + } + + return i2c_intr; +} + +void i2c_write_cmd_data(struct i2c_regs *i2c, uint16_t value) +{ + mmio_write_32((uintptr_t)&i2c->ic_cmd_data, value); +} + +static void i2c_enable(struct i2c_regs *i2c, uint8_t enable) +{ + uint32_t ena = enable ? IC_ENABLE : 0; + int timeout = 100; + + do { + mmio_write_32((uintptr_t)&i2c->ic_enable, ena); + if ((mmio_read_32((uintptr_t)&i2c->ic_enable_status) & IC_ENABLE) == ena) + return; + + /* + * Wait 10 times the signaling period of the highest I2C + * transfer supported by the driver (for 400KHz this is + * 25us) as described in the DesignWare I2C databook. + */ + rt_hw_us_delay(25); + } while (timeout--); + + LOG_I("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); +} + +static void i2c_disable(struct i2c_regs *i2c) +{ + int timeout = 100; + + do { + mmio_write_32((uintptr_t)&i2c->ic_enable, 0x0); + if ((mmio_read_32((uintptr_t)&i2c->ic_enable_status) & IC_ENABLE) == 0x0) + return; + + /* + * Wait 10 times the signaling period of the highest I2C + * transfer supported by the driver (for 400KHz this is + * 25us) as described in the DesignWare I2C databook. + */ + rt_hw_us_delay(25); + } while (timeout--); + + LOG_I("timeout in disabling I2C adapter\n"); +} + +/* + * i2c_flush_rxfifo - Flushes the i2c RX FIFO + * + * Flushes the i2c RX FIFO + */ +static void i2c_flush_rxfifo(struct i2c_regs *i2c) +{ + while (mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_RFNE) + mmio_read_32((uintptr_t)&i2c->ic_cmd_data); +} + +/* + * i2c_wait_for_bb - Waits for bus busy + * + * Waits for bus busy + */ +static int i2c_wait_for_bb(struct i2c_regs *i2c) +{ + uint16_t timeout = 0; + + while ((mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_MA) || + !(mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_TFE)) { + + /* Evaluate timeout */ + rt_hw_us_delay(5); + timeout++; + if (timeout > 200) /* exceed 1 ms */ + return 1; + } + + return 0; +} + +/* + * i2c_setaddress - Sets the target slave address + * @i2c_addr: target i2c address + * + * Sets the target slave address. + */ +static void i2c_setaddress(struct i2c_regs *i2c, uint16_t i2c_addr) +{ + /* Disable i2c */ + i2c_enable(i2c, false); + mmio_write_32((uintptr_t)&i2c->ic_tar, i2c_addr); + /* Enable i2c */ + i2c_enable(i2c, true); +} + + +static int i2c_xfer_init(struct i2c_regs *i2c, uint16_t chip, uint16_t addr, uint16_t alen) +{ + if (i2c_wait_for_bb(i2c)) + return 1; + + i2c_setaddress(i2c, chip); + + while (alen) { + alen--; + /* high byte address going out first */ + i2c_write_cmd_data(i2c, (addr >> (alen * 8)) & 0xff); // TODO + //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, (addr >> (alen * 8)) & 0xff); + } + return 0; +} + +static int i2c_xfer_finish(struct i2c_regs *i2c) +{ + uint16_t timeout = 0; + while (1) { + if ((mmio_read_32((uintptr_t)&i2c->ic_raw_intr_stat) & IC_STOP_DET)) { + mmio_read_32((uintptr_t)&i2c->ic_clr_stop_det); + break; + } else { + timeout++; + rt_hw_us_delay(5); + if (timeout > I2C_STOPDET_TO * 100) { + LOG_I("%s, tiemout\n", __func__); + break; + } + } + } + + if (i2c_wait_for_bb(i2c)) + return 1; + + i2c_flush_rxfifo(i2c); + + return 0; +} + +/* + * i2c_read - Read from i2c memory + * @chip: target i2c address + * @addr: address to read from + * @alen: + * @buffer: buffer for read data + * @len: no of bytes to be read + * + * Read from i2c memory. + */ +static int hal_i2c_read(uint8_t i2c_id, uint8_t dev, uint16_t addr, uint16_t alen, uint8_t *buffer, uint16_t len) +{ + unsigned int active = 0; + unsigned int time_count = 0; + struct i2c_regs *i2c; + int ret = 0; + + i2c = get_i2c_base(i2c_id); + + i2c_enable(i2c, true); + + if (i2c_xfer_init(i2c, dev, addr, alen)) + return 1; + + while (len) { + if (!active) { + /* + * Avoid writing to ic_cmd_data multiple times + * in case this loop spins too quickly and the + * ic_status RFNE bit isn't set after the first + * write. Subsequent writes to ic_cmd_data can + * trigger spurious i2c transfer. + */ + i2c_write_cmd_data(i2c, (dev <<1) | BIT_I2C_CMD_DATA_READ_BIT | BIT_I2C_CMD_DATA_STOP_BIT); + //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, (dev <<1) | BIT_I2C_CMD_DATA_READ_BIT | BIT_I2C_CMD_DATA_STOP_BIT); + active = 1; + } + + if (mmio_read_32((uintptr_t)&i2c->ic_raw_intr_stat) & BIT_I2C_INT_RX_FULL) { + *buffer++ = (uint8_t)mmio_read_32((uintptr_t)&i2c->ic_cmd_data); + len--; + time_count = 0; + active = 0; + } + else { + rt_hw_us_delay(5); + time_count++; + if (time_count >= I2C_BYTE_TO * 100) + return 1; + } + } + + ret = i2c_xfer_finish(i2c); + i2c_disable(i2c); + + return ret; +} + +/* + * i2c_write - Write to i2c memory + * @chip: target i2c address + * @addr: address to read from + * @alen: + * @buffer: buffer for read data + * @len: no of bytes to be read + * + * Write to i2c memory. + */ + +static int hal_i2c_write(uint8_t i2c_id, uint8_t dev, uint16_t addr, uint16_t alen, uint8_t *buffer, uint16_t len) +{ + struct i2c_regs *i2c; + int ret = 0; + i2c = get_i2c_base(i2c_id); + + i2c_enable(i2c, true); + + if (i2c_xfer_init(i2c, dev, addr, alen)) + return 1; + + while (len) { + if (i2c->ic_status & IC_STATUS_TFNF) { + if (--len == 0) { + i2c_write_cmd_data(i2c, *buffer | IC_STOP); + //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, *buffer | IC_STOP); + } else { + i2c_write_cmd_data(i2c, *buffer); + //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, *buffer); + } + buffer++; + } else + LOG_I("len=%d, ic status is not TFNF\n", len); + } + ret = i2c_xfer_finish(i2c); + i2c_disable(i2c); + return ret; +} + +/* + * hal_i2c_set_bus_speed - Set the i2c speed + * @speed: required i2c speed + * + * Set the i2c speed. + */ +static void i2c_set_bus_speed(struct i2c_regs *i2c, unsigned int speed) +{ + unsigned int cntl; + unsigned int hcnt, lcnt; + int i2c_spd; + + if (speed > I2C_FAST_SPEED) + i2c_spd = IC_SPEED_MODE_MAX; + else if ((speed <= I2C_FAST_SPEED) && (speed > I2C_STANDARD_SPEED)) + i2c_spd = IC_SPEED_MODE_FAST; + else + i2c_spd = IC_SPEED_MODE_STANDARD; + + /* to set speed cltr must be disabled */ + i2c_enable(i2c, false); + + cntl = (mmio_read_32((uintptr_t)&i2c->ic_con) & (~IC_CON_SPD_MSK)); + + switch (i2c_spd) { + case IC_SPEED_MODE_MAX: + cntl |= IC_CON_SPD_HS; + //hcnt = (u16)(((IC_CLK * MIN_HS100pF_SCL_HIGHTIME) / 1000) - 8); + /* 7 = 6+1 == MIN LEN +IC_FS_SPKLEN */ + //lcnt = (u16)(((IC_CLK * MIN_HS100pF_SCL_LOWTIME) / 1000) - 1); + hcnt = 6; + lcnt = 8; + + mmio_write_32((uintptr_t)&i2c->ic_hs_scl_hcnt, hcnt); + mmio_write_32((uintptr_t)&i2c->ic_hs_scl_lcnt, lcnt); + break; + + case IC_SPEED_MODE_STANDARD: + cntl |= IC_CON_SPD_SS; + + hcnt = (uint16_t)(((IC_CLK * MIN_SS_SCL_HIGHTIME) / 1000) - 7); + lcnt = (uint16_t)(((IC_CLK * MIN_SS_SCL_LOWTIME) / 1000) - 1); + + mmio_write_32((uintptr_t)&i2c->ic_ss_scl_hcnt, hcnt); + mmio_write_32((uintptr_t)&i2c->ic_ss_scl_lcnt, lcnt); + break; + + case IC_SPEED_MODE_FAST: + default: + cntl |= IC_CON_SPD_FS; + hcnt = (uint16_t)(((IC_CLK * MIN_FS_SCL_HIGHTIME) / 1000) - 7); + lcnt = (uint16_t)(((IC_CLK * MIN_FS_SCL_LOWTIME) / 1000) - 1); + + mmio_write_32((uintptr_t)&i2c->ic_fs_scl_hcnt, hcnt); + mmio_write_32((uintptr_t)&i2c->ic_fs_scl_lcnt, lcnt); + break; + } + + mmio_write_32((uintptr_t)&i2c->ic_con, cntl); + + /* Enable back i2c now speed set */ + i2c_enable(i2c, true); +} + +/* + * __hal_i2c_init - Init function + * @speed: required i2c speed + * @slaveaddr: slave address for the device + * + * Initialization function. + */ +static void hal_i2c_init(uint8_t i2c_id) +{ + struct i2c_regs *i2c; + uint32_t i2c_intr; + + LOG_I("%s, i2c-%d\n", __func__, i2c_id); + /* Disable i2c */ + //Need to acquire lock here + + i2c = get_i2c_base(i2c_id); + i2c_intr = get_i2c_intr(i2c_id); + + // request_irq(i2c_intr, i2c_dw_isr, 0, "IC2_INTR int", &dw_i2c[i2c_id]); + + i2c_enable(i2c, false); + mmio_write_32((uintptr_t)&i2c->ic_con, (IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM | IC_CON_RE)); + mmio_write_32((uintptr_t)&i2c->ic_rx_tl, IC_RX_TL); + mmio_write_32((uintptr_t)&i2c->ic_tx_tl, IC_TX_TL); + mmio_write_32((uintptr_t)&i2c->ic_intr_mask, 0x0); + i2c_set_bus_speed(i2c, I2C_SPEED); + //mmio_write_32((uintptr_t)&i2c->ic_sar, slaveaddr); + /* Enable i2c */ + i2c_enable(i2c, false); + + //Need to release lock here +} + +static rt_ssize_t _master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_ssize_t ret = -RT_ERROR; + + struct _i2c_bus *i2c = (struct _i2c_bus *)bus; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_RD) + { + hal_i2c_read(i2c->i2c_id, msg->addr, RT_NULL, 1, msg->buf, msg->len); + } + else + { + hal_i2c_write(i2c->i2c_id, msg->addr, RT_NULL, 1, msg->buf, msg->len); + } + } + + return ret; +} + +static void rt_hw_i2c_isr(int irqno, void *param) +{ + uint32_t stat, enabled; + struct i2c_regs *i2c = (struct i2c_regs *)param; + + enabled = mmio_read_32((uintptr_t)&i2c->ic_enable); + stat = mmio_read_32((uintptr_t)&i2c->ic_intr_stat); + + LOG_I("i2c interrupt stat: 0x%08x", stat); +} + +static const struct rt_i2c_bus_device_ops i2c_ops = +{ + .master_xfer = _master_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = RT_NULL +}; + +int rt_hw_i2c_init(void) +{ + int result = RT_EOK; + +#ifdef BSP_USING_I2C0 + PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); + PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); +#endif /* BSP_USING_I2C0 */ +#ifdef BSP_USING_I2C1 + PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); + PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); +#endif /* BSP_USING_I2C1 */ + + for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++) + { + hal_i2c_init(_i2c_obj->i2c_id); + + _i2c_obj[i].parent.ops = &i2c_ops; + + /* register i2c device */ + if (rt_i2c_bus_device_register(&_i2c_obj[i].parent, _i2c_obj[i].device_name) == RT_EOK) + { + LOG_D("%s init success", _i2c_obj[i].device_name); + } + else + { + LOG_E("%s register failed", _i2c_obj[i].device_name); + result = -RT_ERROR; + } + + uint32_t irqno = get_i2c_intr(_i2c_obj[i].i2c_id); + struct i2c_regs *_i2c = get_i2c_base(_i2c_obj[i].i2c_id); + rt_hw_interrupt_install(irqno, rt_hw_i2c_isr, _i2c, _i2c_obj[i].device_name); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/cvitek/drivers/drv_hw_i2c.h b/bsp/cvitek/drivers/drv_hw_i2c.h new file mode 100644 index 0000000000..095550263b --- /dev/null +++ b/bsp/cvitek/drivers/drv_hw_i2c.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + *2024-02-14 ShichengChu first version + */ +#ifndef __DRV_HW_I2C_H__ +#define __DRV_HW_I2C_H__ + +#include +#include "rtdevice.h" +#include + +#include "pinctrl.h" +#include "mmio.h" + +#define I2C0 0x0 +#define I2C1 0x1 +#define I2C2 0x2 +#define I2C3 0x3 +#define I2C4 0x4 + +#define I2C0_BASE 0x4000000 +#define I2C1_BASE 0x4010000 +#define I2C2_BASE 0x4020000 +#define I2C3_BASE 0x4030000 +#define I2C4_BASE 0x4040000 + +#define BIT_I2C_CMD_DATA_READ_BIT (0x01 << 8) +#define BIT_I2C_CMD_DATA_STOP_BIT (0x01 << 9) + +/* bit definition */ +#define BIT_I2C_CON_MASTER_MODE (0x01 << 0) +#define BIT_I2C_CON_STANDARD_SPEED (0x01 << 1) +#define BIT_I2C_CON_FULL_SPEED (0x02 << 1) +#define BIT_I2C_CON_HIGH_SPEED (0x03 << 1) +#define BIT_I2C_CON_10B_ADDR_SLAVE (0x01 << 3) +#define BIT_I2C_CON_10B_ADDR_MASTER (0x01 << 4) +#define BIT_I2C_CON_RESTART_EN (0x01 << 5) +#define BIT_I2C_CON_SLAVE_DIS (0x01 << 6) + +#define BIT_I2C_TAR_10B_ADDR_MASTER (0x01 << 12) + +#define BIT_I2C_INT_RX_UNDER (0x01 << 0) +#define BIT_I2C_INT_RX_OVER (0x01 << 1) +#define BIT_I2C_INT_RX_FULL (0x01 << 2) +#define BIT_I2C_INT_TX_OVER (0x01 << 3) +#define BIT_I2C_INT_TX_EMPTY (0x01 << 4) +#define BIT_I2C_INT_RD_REQ (0x01 << 5) +#define BIT_I2C_INT_TX_ABRT (0x01 << 6) +#define BIT_I2C_INT_RX_DONE (0x01 << 7) +#define BIT_I2C_INT_ACTIVITY (0x01 << 8) +#define BIT_I2C_INT_STOP_DET (0x01 << 9) +#define BIT_I2C_INT_START_DET (0x01 << 10) +#define BIT_I2C_INT_GEN_ALL (0x01 << 11) +#define I2C_INTR_MASTER_MASK (BIT_I2C_INT_TX_ABRT | \ + BIT_I2C_INT_STOP_DET | \ + BIT_I2C_INT_RX_FULL | \ + BIT_I2C_INT_TX_EMPTY) + +#define BIT_I2C_INT_RX_UNDER_MASK (0x01 << 0) +#define BIT_I2C_INT_RX_OVER_MASK (0x01 << 1) +#define BIT_I2C_INT_RX_FULL_MASK (0x01 << 2) +#define BIT_I2C_INT_TX_OVER_MASK (0x01 << 3) +#define BIT_I2C_INT_TX_EMPTY_MASK (0x01 << 4) +#define BIT_I2C_INT_RD_REQ_MASK (0x01 << 5) +#define BIT_I2C_INT_TX_ABRT_MASK (0x01 << 6) +#define BIT_I2C_INT_RX_DONE_MASK (0x01 << 7) +#define BIT_I2C_INT_ACTIVITY_MASK (0x01 << 8) +#define BIT_I2C_INT_STOP_DET_MASK (0x01 << 9) +#define BIT_I2C_INT_START_DET_MASK (0x01 << 10) +#define BIT_I2C_INT_GEN_ALL_MASK (0x01 << 11) + +#define BIT_I2C_INT_RX_UNDER_RAW (0x01 << 0) +#define BIT_I2C_INT_RX_OVER_RAW (0x01 << 1) +#define BIT_I2C_INT_RX_FULL_RAW (0x01 << 2) +#define BIT_I2C_INT_TX_OVER_RAW (0x01 << 3) +#define BIT_I2C_INT_TX_EMPTY_RAW (0x01 << 4) +#define BIT_I2C_INT_RD_REQ_RAW (0x01 << 5) +#define BIT_I2C_INT_TX_ABRT_RAW (0x01 << 6) +#define BIT_I2C_INT_RX_DONE_RAW (0x01 << 7) +#define BIT_I2C_INT_ACTIVITY_RAW (0x01 << 8) +#define BIT_I2C_INT_STOP_DET_RAW (0x01 << 9) +#define BIT_I2C_INT_START_DET_RAW (0x01 << 10) +#define BIT_I2C_INT_GEN_ALL_RAW (0x01 << 11) + +#define BIT_I2C_DMA_CR_TDMAE (0x01 << 1) +#define BIT_I2C_DMA_CR_RDMAE (0x01 << 0) + +struct i2c_regs { + volatile uint32_t ic_con; /* 0x00 */ + volatile uint32_t ic_tar; /* 0x04 */ + volatile uint32_t ic_sar; /* 0x08 */ + volatile uint32_t ic_hs_maddr; /* 0x0c */ + volatile uint32_t ic_cmd_data; /* 0x10 */ + volatile uint32_t ic_ss_scl_hcnt; /* 0x14 */ + volatile uint32_t ic_ss_scl_lcnt; /* 0x18 */ + volatile uint32_t ic_fs_scl_hcnt; /* 0x1c */ + volatile uint32_t ic_fs_scl_lcnt; /* 0x20 */ + volatile uint32_t ic_hs_scl_hcnt; /* 0x24 */ + volatile uint32_t ic_hs_scl_lcnt; /* 0x28 */ + volatile uint32_t ic_intr_stat; /* 0x2c */ + volatile uint32_t ic_intr_mask; /* 0x30 */ + volatile uint32_t ic_raw_intr_stat; /* 0x34 */ + volatile uint32_t ic_rx_tl; /* 0x38 */ + volatile uint32_t ic_tx_tl; /* 0x3c */ + volatile uint32_t ic_clr_intr; /* 0x40 */ + volatile uint32_t ic_clr_rx_under; /* 0x44 */ + volatile uint32_t ic_clr_rx_over; /* 0x48 */ + volatile uint32_t ic_clr_tx_over; /* 0x4c */ + volatile uint32_t ic_clr_rd_req; /* 0x50 */ + volatile uint32_t ic_clr_tx_abrt; /* 0x54 */ + volatile uint32_t ic_clr_rx_done; /* 0x58 */ + volatile uint32_t ic_clr_activity; /* 0x5c */ + volatile uint32_t ic_clr_stop_det; /* 0x60 */ + volatile uint32_t ic_clr_start_det; /* 0x64 */ + volatile uint32_t ic_clr_gen_call; /* 0x68 */ + volatile uint32_t ic_enable; /* 0x6c */ + volatile uint32_t ic_status; /* 0x70 */ + volatile uint32_t ic_txflr; /* 0x74 */ + volatile uint32_t ic_rxflr; /* 0x78 */ + volatile uint32_t ic_sda_hold; /* 0x7c */ + volatile uint32_t ic_tx_abrt_source; /* 0x80 */ + volatile uint32_t ic_slv_dat_nack_only; /* 0x84 */ + volatile uint32_t ic_dma_cr; /* 0x88 */ + volatile uint32_t ic_dma_tdlr; /* 0x8c */ + volatile uint32_t ic_dma_rdlr; /* 0x90 */ + volatile uint32_t ic_sda_setup; /* 0x94 */ + volatile uint32_t ic_ack_general_call; /* 0x98 */ + volatile uint32_t ic_enable_status; /* 0x9c */ + volatile uint32_t ic_fs_spklen; /* 0xa0 */ + volatile uint32_t ic_hs_spklen; /* 0xa4 */ +}; + +#if !defined(IC_CLK) +#define IC_CLK 100 +#endif + +#define NANO_TO_MICRO 1000 + +/* High and low times in different speed modes (in ns) */ +#define MIN_SS_SCL_HIGHTIME 4000 +#define MIN_SS_SCL_LOWTIME 4700 +#define MIN_FS_SCL_HIGHTIME 600 +#define MIN_FS_SCL_LOWTIME 1300 +#define MIN_HS100pF_SCL_HIGHTIME 60 +#define MIN_HS100pF_SCL_LOWTIME 120 +#define MIN_HS400pF_SCL_HIGHTIME 160 +#define MIN_HS400pF_SCL_LOWTIME 320 + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +/* Worst case timeout for 1 byte is kept as 2ms */ +#define I2C_BYTE_TO (CONFIG_SYS_HZ/500) + +#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500) +#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16) + +/* i2c control register definitions */ +#define IC_CON_SD 0x0040 +#define IC_CON_RE 0x0020 +#define IC_CON_10BITADDRMASTER 0x0010 +#define IC_CON_10BITADDR_SLAVE 0x0008 +#define IC_CON_SPD_MSK 0x0006 +#define IC_CON_SPD_SS 0x0002 +#define IC_CON_SPD_FS 0x0004 +#define IC_CON_SPD_HS 0x0006 +#define IC_CON_MM 0x0001 + +/* i2c data buffer and command register definitions */ +#define IC_CMD 0x0100 +#define IC_STOP 0x0200 + +/* i2c interrupt status register definitions */ +#define IC_GEN_CALL 0x0800 +#define IC_START_DET 0x0400 +#define IC_STOP_DET 0x0200 +#define IC_ACTIVITY 0x0100 +#define IC_RX_DONE 0x0080 +#define IC_TX_ABRT 0x0040 +#define IC_RD_REQ 0x0020 +#define IC_TX_EMPTY 0x0010 +#define IC_TX_OVER 0x0008 +#define IC_RX_FULL 0x0004 +#define IC_RX_OVER 0x0002 +#define IC_RX_UNDER 0x0001 + +/* fifo threshold register definitions */ +#define IC_TL0 0x00 +#define IC_TL1 0x01 +#define IC_TL2 0x02 +#define IC_TL3 0x03 +#define IC_TL4 0x04 +#define IC_TL5 0x05 +#define IC_TL6 0x06 +#define IC_TL7 0x07 +#define IC_RX_TL IC_TL0 +#define IC_TX_TL IC_TL0 + +/* i2c enable register definitions */ +#define IC_ENABLE 0x0001 + +/* i2c status register definitions */ +#define IC_STATUS_SA 0x0040 +#define IC_STATUS_MA 0x0020 +#define IC_STATUS_RFF 0x0010 +#define IC_STATUS_RFNE 0x0008 +#define IC_STATUS_TFE 0x0004 +#define IC_STATUS_TFNF 0x0002 +#define IC_STATUS_ACT 0x0001 + +/* Speed Selection */ +#define IC_SPEED_MODE_STANDARD 1 +#define IC_SPEED_MODE_FAST 2 +#define IC_SPEED_MODE_MAX 3 + +#define I2C_MAX_SPEED 3400000 +#define I2C_FAST_SPEED 400000 +#define I2C_STANDARD_SPEED 100000 + +#define I2C_SPEED I2C_FAST_SPEED + +#define I2C0_IRQ (I2C_IRQ_BASE + 0) +#define I2C1_IRQ (I2C_IRQ_BASE + 1) +#define I2C2_IRQ (I2C_IRQ_BASE + 2) +#define I2C3_IRQ (I2C_IRQ_BASE + 3) +#define I2C4_IRQ (I2C_IRQ_BASE + 4) + +int rt_hw_i2c_init(void); + +#endif /* __DRV_HW_I2C_H__ */