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[DeviceDriver][SPI] Cleanup the at45db/gd25q/w25q/sst25v SPI flash driver. Please using SFUD instead of them.

This commit is contained in:
armink 2019-05-29 13:53:27 +08:00
parent f9a7b47955
commit ab700d54aa
13 changed files with 5 additions and 2011 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
components/drivers/Kconfig
View File

@ -212,6 +212,9 @@ config RT_USING_SPI
config RT_USING_SFUD config RT_USING_SFUD
bool "Using Serial Flash Universal Driver" bool "Using Serial Flash Universal Driver"
default n default n
help
An using JEDEC's SFDP standard serial (SPI) flash universal driver library
if RT_USING_SFUD if RT_USING_SFUD
config RT_SFUD_USING_SFDP config RT_SFUD_USING_SFDP
bool "Using auto probe flash JEDEC SFDP parameter" bool "Using auto probe flash JEDEC SFDP parameter"
@ -231,14 +234,6 @@ config RT_USING_SPI
default n default n
endif endif
config RT_USING_W25QXX
bool "Using W25QXX SPI NorFlash"
default n
config RT_USING_GD
bool "Using GD SPI NorFlash"
default n
config RT_USING_ENC28J60 config RT_USING_ENC28J60
bool "Using ENC28J60 SPI Ethernet network interface" bool "Using ENC28J60 SPI Ethernet network interface"
select RT_USING_LWIP select RT_USING_LWIP

15
components/drivers/spi/SConscript
View File

@ -14,24 +14,9 @@ src_device = []
if GetDepend('RT_USING_SPI_WIFI'): if GetDepend('RT_USING_SPI_WIFI'):
src_device += ['spi_wifi_rw009.c'] src_device += ['spi_wifi_rw009.c']
if GetDepend('RT_USING_W25QXX'):
src_device += ['spi_flash_w25qxx.c']
if GetDepend('RT_USING_W25QXX_MTD'):
src_device += ['spi_flash_w25qxx_mtd.c']
if GetDepend('RT_USING_ENC28J60'): if GetDepend('RT_USING_ENC28J60'):
src_device += ['enc28j60.c'] src_device += ['enc28j60.c']
if GetDepend('RT_USING_AT45DBXX'):
src_device += ['spi_flash_at45dbxx.c']
if GetDepend('RT_USING_SST25VFXX'):
src_device += ['spi_flash_sst25vfxx.c']
if GetDepend('RT_USING_GD'):
src_device += ['spi_flash_gd.c']
if GetDepend('RT_USING_SPI_MSD'): if GetDepend('RT_USING_SPI_MSD'):
src_device += ['spi_msd.c'] src_device += ['spi_msd.c']

10
components/drivers/spi/device_driver_list.txt
View File

@ -5,11 +5,5 @@ http://www.rt-thread.com/
enc28j60.c/enc28j60.h enc28j60.c/enc28j60.h
http://www.microchip.com/ http://www.microchip.com/
spi_flash_at45dbxx.c/spi_flash_at45dbxx.h spi_flash_sfud: Serial Flash Universal Driver
http://www.atmel.com/ https://github.com/armink/SFUD
spi_flash_sst25vfxx.c/spi_flash_sst25vfxx.h
http://www.microchip.com/
spi_flash_w25qxx.c/spi_flash_w25qxx.h
http://www.winbond.com/

433
components/drivers/spi/spi_flash_at45dbxx.c
View File

@ -1,433 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
*/
#include <stdint.h>
#include "spi_flash_at45dbxx.h"
#define FLASH_DEBUG
#define DMA_BUFFER_SIZE 512
#ifdef FLASH_DEBUG
#define FLASH_TRACE rt_kprintf
#else
#define FLASH_TRACE(...)
#endif /**< #ifdef FLASH_DEBUG */
/* JEDEC Manufacturer’s ID */
#define MF_ID (0x1F) /* atmel */
#define DENSITY_CODE_011D (0x02) /* AT45DB011D Density Code : 00010 = 1-Mbit */
#define DENSITY_CODE_021D (0x03) /* AT45DB021D Density Code : 00011 = 2-Mbit */
#define DENSITY_CODE_041D (0x04) /* AT45DB041D Density Code : 00100 = 4-Mbit */
#define DENSITY_CODE_081D (0x05) /* AT45DB081D Density Code : 00101 = 8-Mbit */
#define DENSITY_CODE_161D (0x06) /* AT45DB161D Density Code : 00110 = 16-Mbit */
#define DENSITY_CODE_321D (0x07) /* AT45DB321D Density Code : 00111 = 32-Mbit */
#define DENSITY_CODE_642D (0x08) /* AT45DB642D Density Code : 01000 = 64-Mbit */
struct JEDEC_ID
{
uint8_t manufacturer_id; /* Manufacturer ID */
uint8_t density_code:5; /* Density Code */
uint8_t family_code:3; /* Family Code */
uint8_t version_code:5; /* Product Version Code */
uint8_t mlc_code:3; /* MLC Code */
uint8_t byte_count; /* Byte Count */
};
#define AT45DB_BUFFER_1_WRITE 0x84
#define AT45DB_BUFFER_2_WRITE 0x87
#define AT45DB_BUFFER_1_READ 0xD4
#define AT45DB_BUFFER_2_READ 0xD6
#define AT45DB_B1_TO_MM_PAGE_PROG_WITH_ERASE 0x83
#define AT45DB_B2_TO_MM_PAGE_PROG_WITH_ERASE 0x86
#define AT45DB_MM_PAGE_TO_B1_XFER 0x53
#define AT45DB_MM_PAGE_TO_B2_XFER 0x55
#define AT45DB_PAGE_ERASE 0x81
#define AT45DB_SECTOR_ERASE 0x7C
#define AT45DB_READ_STATE_REGISTER 0xD7
#define AT45DB_MM_PAGE_READ 0xD2
#define AT45DB_MM_PAGE_PROG_THRU_BUFFER1 0x82
#define AT45DB_CMD_JEDEC_ID 0x9F
static struct spi_flash_at45dbxx spi_flash_at45dbxx;
/*****************************************************************************/
/*Status Register Format: */
/* ------------------------------------------------------------------------- */
/* | bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | */
/* |--------|--------|--------|--------|--------|--------|--------|--------| */
/* |RDY/BUSY| COMP | device density | X | X | */
/* ------------------------------------------------------------------------- */
/* 0:busy | | AT45DB041:0111 | protect|page size */
/* 1:ready | | AT45DB161:1011 | */
/* --------------------------------------------------------------------------*/
/*****************************************************************************/
static uint8_t AT45DB_StatusRegisterRead(void)
{
return rt_spi_sendrecv8(spi_flash_at45dbxx.rt_spi_device, AT45DB_READ_STATE_REGISTER);
}
static void wait_busy(void)
{
uint16_t i = 0;
while (i++ < 10000)
{
if (AT45DB_StatusRegisterRead() & 0x80)
{
return;
}
}
FLASH_TRACE("\r\nSPI_FLASH timeout!!!\r\n");
}
/* RT-Thread Device Driver Interface */
static rt_err_t AT45DB_flash_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t AT45DB_flash_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t AT45DB_flash_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t AT45DB_flash_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = 512;
geometry->sector_count = 4096;
geometry->block_size = 4096; /* block erase: 4k */
}
return RT_EOK;
}
static rt_size_t AT45DB_flash_read_page_256(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
uint32_t index, nr;
uint8_t * read_buffer = buffer;
uint32_t page = pos;
nr = size;
for (index = 0; index < nr; index++)
{
uint8_t send_buffer[8];
uint32_t i;
for(i=0; i<sizeof(send_buffer); i++)
{
send_buffer[i] = 0;
}
send_buffer[0] = AT45DB_MM_PAGE_READ;
send_buffer[1] = (uint8_t)(page >> 7);
send_buffer[2] = (uint8_t)(page << 1);
rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, send_buffer, 8, read_buffer, 256);
read_buffer += 256;
page++;
}
return size;
}
static rt_size_t AT45DB_flash_read_page_512(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
uint32_t index, nr;
uint8_t * read_buffer = buffer;
uint32_t page = pos;
nr = size;
for (index = 0; index < nr; index++)
{
uint8_t send_buffer[8];
uint32_t i;
for(i=0; i<sizeof(send_buffer); i++)
{
send_buffer[i] = 0;
}
send_buffer[0] = AT45DB_MM_PAGE_READ;
send_buffer[1] = (uint8_t)(page >> 6);
send_buffer[2] = (uint8_t)(page << 2);
rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, send_buffer, 8, read_buffer, 512);
read_buffer += 512;
page++;
}
return size;
}
static rt_size_t AT45DB_flash_read_page_1024(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
uint32_t index, nr;
uint8_t * read_buffer = buffer;
uint32_t page = pos;
nr = size;
for (index = 0; index < nr; index++)
{
uint8_t send_buffer[8];
uint32_t i;
for(i=0; i<sizeof(send_buffer); i++)
{
send_buffer[i] = 0;
}
send_buffer[0] = AT45DB_MM_PAGE_READ;
send_buffer[1] = (uint8_t)(page >> 5);
send_buffer[2] = (uint8_t)(page << 3);
rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, send_buffer, 8, read_buffer, 1024);
read_buffer += 1024;
page++;
}
return size;
}
static rt_size_t AT45DB_flash_write_page_256(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint32_t index, nr;
const uint8_t * write_buffer = buffer;
uint32_t page = pos;
nr = size;
for (index = 0; index < nr; index++)
{
uint8_t send_buffer[4];
send_buffer[0] = AT45DB_MM_PAGE_PROG_THRU_BUFFER1;
send_buffer[1] = (uint8_t) (page >> 7);
send_buffer[2] = (uint8_t) (page << 1);
send_buffer[3] = 0;
rt_spi_send_then_send(spi_flash_at45dbxx.rt_spi_device, send_buffer, 4, write_buffer, 256);
write_buffer += 256;
page++;
wait_busy();
}
return size;
}
static rt_size_t AT45DB_flash_write_page_512(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint32_t index, nr;
const uint8_t * write_buffer = buffer;
uint32_t page = pos;
nr = size;
for (index = 0; index < nr; index++)
{
uint8_t send_buffer[4];
send_buffer[0] = AT45DB_MM_PAGE_PROG_THRU_BUFFER1;
send_buffer[1] = (uint8_t) (page >> 6);
send_buffer[2] = (uint8_t) (page << 2);
send_buffer[3] = 0;
rt_spi_send_then_send(spi_flash_at45dbxx.rt_spi_device, send_buffer, 4, write_buffer, 512);
write_buffer += 512;
page++;
wait_busy();
}
return size;
}
static rt_size_t AT45DB_flash_write_page_1024(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint32_t index, nr;
const uint8_t * write_buffer = buffer;
uint32_t page = pos;
nr = size;
for (index = 0; index < nr; index++)
{
uint8_t send_buffer[4];
send_buffer[0] = AT45DB_MM_PAGE_PROG_THRU_BUFFER1;
send_buffer[1] = (uint8_t) (page >> 5);
send_buffer[2] = (uint8_t) (page << 3);
send_buffer[3] = 0;
rt_spi_send_then_send(spi_flash_at45dbxx.rt_spi_device, send_buffer, 4, write_buffer, 1024);
write_buffer += 1024;
page++;
wait_busy();
}
return size;
}
rt_err_t at45dbxx_init(const char * flash_device_name, const char * spi_device_name)
{
struct rt_spi_device * rt_spi_device;
struct JEDEC_ID * JEDEC_ID;
rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
if(rt_spi_device == RT_NULL)
{
FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
return -RT_ENOSYS;
}
spi_flash_at45dbxx.rt_spi_device = rt_spi_device;
/* config spi */
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 and 3 */
cfg.max_hz = 66000000; /* Atmel RapidS Serial Interface: 66MHz Maximum Clock Frequency */
rt_spi_configure(spi_flash_at45dbxx.rt_spi_device, &cfg);
}
/* read JEDEC ID */
{
uint8_t cmd;
uint8_t id_recv[6];
JEDEC_ID = (struct JEDEC_ID *)id_recv;
cmd = AT45DB_CMD_JEDEC_ID;
rt_spi_send_then_recv(spi_flash_at45dbxx.rt_spi_device, &cmd, 1, id_recv, 6);
/**< 1FH = Atmel */
/**< 001 = Atmel DataFlash */
if(JEDEC_ID->manufacturer_id != 0x1F || JEDEC_ID->family_code != 0x01)
{
FLASH_TRACE("Manufacturer’s ID or Memory Type error!\r\n");
FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
return -RT_ENOSYS;
}
if(JEDEC_ID->density_code == DENSITY_CODE_011D)
{
/**< AT45DB011D Density Code : 00010 = 1-Mbit */
FLASH_TRACE("AT45DB011D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
spi_flash_at45dbxx.geometry.sector_count = 512; /* 1-Mbit / 8 / 256 = 512 */
spi_flash_at45dbxx.geometry.block_size = 1024*2; /* Block Erase (2-Kbytes) */
}
else if(JEDEC_ID->density_code == DENSITY_CODE_021D)
{
/**< AT45DB021D Density Code : 00011 = 2-Mbit */
FLASH_TRACE("AT45DB021D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
spi_flash_at45dbxx.geometry.sector_count = 512*2; /* 2-Mbit / 8 / 256 = 1024 */
spi_flash_at45dbxx.geometry.block_size = 1024*2; /* Block Erase (2-Kbytes) */
}
else if(JEDEC_ID->density_code == DENSITY_CODE_041D)
{
/**< AT45DB041D Density Code : 00100 = 4-Mbit */
FLASH_TRACE("AT45DB041D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
spi_flash_at45dbxx.geometry.sector_count = 512*4; /* 4-Mbit / 8 / 256 = 2048 */
spi_flash_at45dbxx.geometry.block_size = 1024*2; /* Block Erase (2-Kbytes) */
}
else if(JEDEC_ID->density_code == DENSITY_CODE_081D)
{
/**< AT45DB081D Density Code : 00101 = 8-Mbit */
FLASH_TRACE("AT45DB081D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 256; /* Page Erase (256 Bytes) */
spi_flash_at45dbxx.geometry.sector_count = 512*8; /* 8-Mbit / 8 / 256 = 4096 */
spi_flash_at45dbxx.geometry.block_size = 1024*2; /* Block Erase (2-Kbytes) */
}
else if(JEDEC_ID->density_code == DENSITY_CODE_161D)
{
/**< AT45DB161D Density Code : 00110 = 16-Mbit */
FLASH_TRACE("AT45DB161D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 512; /* Page Erase (512 Bytes) */
spi_flash_at45dbxx.geometry.sector_count = 256*16; /* 16-Mbit / 8 / 512 = 4096 */
spi_flash_at45dbxx.geometry.block_size = 1024*4; /* Block Erase (4-Kbytes) */
}
else if(JEDEC_ID->density_code == DENSITY_CODE_321D)
{
/**< AT45DB321D Density Code : 00111 = 32-Mbit */
FLASH_TRACE("AT45DB321D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 512; /* Page Erase (512 Bytes) */
spi_flash_at45dbxx.geometry.sector_count = 256*32; /* 32-Mbit / 8 / 512 = 8192 */
spi_flash_at45dbxx.geometry.block_size = 1024*4; /* Block Erase (4-Kbytes) */
}
else if(JEDEC_ID->density_code == DENSITY_CODE_642D)
{
/**< AT45DB642D Density Code : 01000 = 64-Mbit */
FLASH_TRACE("AT45DB642D detection\r\n");
spi_flash_at45dbxx.geometry.bytes_per_sector = 1024; /* Page Erase (1 Kbyte) */
spi_flash_at45dbxx.geometry.sector_count = 128*64; /* 64-Mbit / 8 / 1024 = 8192 */
spi_flash_at45dbxx.geometry.block_size = 1024*8; /* Block Erase (8 Kbytes) */
}
else
{
FLASH_TRACE("Memory Capacity error!\r\n");
return -RT_ENOSYS;
}
}
/* register device */
spi_flash_at45dbxx.flash_device.type = RT_Device_Class_Block;
spi_flash_at45dbxx.flash_device.init = AT45DB_flash_init;
spi_flash_at45dbxx.flash_device.open = AT45DB_flash_open;
spi_flash_at45dbxx.flash_device.close = AT45DB_flash_close;
spi_flash_at45dbxx.flash_device.control = AT45DB_flash_control;
if(JEDEC_ID->density_code == DENSITY_CODE_642D)
{
spi_flash_at45dbxx.flash_device.read = AT45DB_flash_read_page_1024;
spi_flash_at45dbxx.flash_device.write = AT45DB_flash_write_page_1024;
}
else if(JEDEC_ID->density_code == DENSITY_CODE_161D
|| JEDEC_ID->density_code == DENSITY_CODE_321D )
{
spi_flash_at45dbxx.flash_device.read = AT45DB_flash_read_page_512;
spi_flash_at45dbxx.flash_device.write = AT45DB_flash_write_page_512;
}
else
{
spi_flash_at45dbxx.flash_device.read = AT45DB_flash_read_page_256;
spi_flash_at45dbxx.flash_device.write = AT45DB_flash_write_page_256;
}
/* no private */
spi_flash_at45dbxx.flash_device.user_data = RT_NULL;
rt_device_register(&spi_flash_at45dbxx.flash_device, flash_device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
return RT_EOK;
}

27
components/drivers/spi/spi_flash_at45dbxx.h
View File

@ -1,27 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
*/
#ifndef SPI_FLASH_AT45DBXX_H_INCLUDED
#define SPI_FLASH_AT45DBXX_H_INCLUDED
#include <rtthread.h>
#include <drivers/spi.h>
struct spi_flash_at45dbxx
{
struct rt_device flash_device;
struct rt_device_blk_geometry geometry;
struct rt_spi_device * rt_spi_device;
};
extern rt_err_t at45dbxx_init(const char * flash_device_name, const char * spi_device_name);
#endif // SPI_FLASH_AT45DBXX_H_INCLUDED

347
components/drivers/spi/spi_flash_gd.c
View File

@ -1,347 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-10-11 fullhan copy from winbond flash
*/
#include <stdint.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "spi_flash.h"
#include "spi_flash_gd.h"
#define FLASH_DEBUG
#ifdef FLASH_DEBUG
#define FLASH_TRACE rt_kprintf
#else
#define FLASH_TRACE(...)
#endif /* #ifdef FLASH_DEBUG */
#define PAGE_SIZE 4096
/* JEDEC Manufacturer's ID */
#define MF_ID (0xC8)
/* JEDEC Device ID: Memory type and Capacity */
#define MTC_GD25Q128 (0x4018)
/* command list */
#define CMD_WRSR (0x01) /* Write Status Register */
#define CMD_PP (0x02) /* Page Program */
#define CMD_READ (0x03) /* Read Data */
#define CMD_WRDI (0x04) /* Write Disable */
#define CMD_RDSR1 (0x05) /* Read Status Register-1 */
#define CMD_WREN (0x06) /* Write Enable */
#define CMD_FAST_READ (0x0B) /* Fast Read */
#define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
#define CMD_RDSR2 (0x35) /* Read Status Register-2 */
#define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
#define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
#define CMD_ERASE_full (0xC7) /* Chip Erase */
#define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
#define DUMMY (0xFF)
static struct spi_flash_device spi_flash_device;
static void flash_lock(struct spi_flash_device * flash_device)
{
rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
}
static void flash_unlock(struct spi_flash_device * flash_device)
{
rt_mutex_release(&flash_device->lock);
}
static uint8_t w25qxx_read_status(void)
{
return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
}
static void w25qxx_wait_busy(void)
{
while( w25qxx_read_status() & (0x01));
}
/** \brief read [size] byte from [offset] to [buffer]
*
* \param offset uint32_t unit : byte
* \param buffer uint8_t*
* \param size uint32_t unit : byte
* \return uint32_t byte for read
*
*/
static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
{
uint8_t send_buffer[4];
send_buffer[0] = CMD_WRDI;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_READ;
send_buffer[1] = (uint8_t)(offset>>16);
send_buffer[2] = (uint8_t)(offset>>8);
send_buffer[3] = (uint8_t)(offset);
rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
send_buffer, 4,
buffer, size);
return size;
}
/** \brief write N page on [page]
*
* \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
* \param buffer const uint8_t*
* \return uint32_t
*
*/
static uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
{
uint32_t index;
uint8_t send_buffer[4];
RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_ERASE_4K;
send_buffer[1] = (page_addr >> 16);
send_buffer[2] = (page_addr >> 8);
send_buffer[3] = (page_addr);
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
w25qxx_wait_busy(); // wait erase done.
for(index=0; index < (PAGE_SIZE / 256); index++)
{
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_PP;
send_buffer[1] = (uint8_t)(page_addr >> 16);
send_buffer[2] = (uint8_t)(page_addr >> 8);
send_buffer[3] = (uint8_t)(page_addr);
rt_spi_send_then_send(spi_flash_device.rt_spi_device,
send_buffer,
4,
buffer,
256);
buffer += 256;
page_addr += 256;
w25qxx_wait_busy();
}
send_buffer[0] = CMD_WRDI;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
return PAGE_SIZE;
}
/* RT-Thread device interface */
static rt_err_t w25qxx_flash_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
{
uint8_t send_buffer[3];
flash_lock((struct spi_flash_device *)dev);
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_WRSR;
send_buffer[1] = 0;
send_buffer[2] = 0;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
w25qxx_wait_busy();
flash_unlock((struct spi_flash_device *)dev);
return RT_EOK;
}
static rt_err_t w25qxx_flash_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t w25qxx_flash_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
geometry->sector_count = spi_flash_device.geometry.sector_count;
geometry->block_size = spi_flash_device.geometry.block_size;
}
return RT_EOK;
}
static rt_size_t w25qxx_flash_read(rt_device_t dev,
rt_off_t pos,
void* buffer,
rt_size_t size)
{
flash_lock((struct spi_flash_device *)dev);
w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
buffer,
size*spi_flash_device.geometry.bytes_per_sector);
flash_unlock((struct spi_flash_device *)dev);
return size;
}
static rt_size_t w25qxx_flash_write(rt_device_t dev,
rt_off_t pos,
const void* buffer,
rt_size_t size)
{
rt_size_t i = 0;
rt_size_t block = size;
const uint8_t * ptr = buffer;
flash_lock((struct spi_flash_device *)dev);
while(block--)
{
w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
ptr);
ptr += PAGE_SIZE;
i++;
}
flash_unlock((struct spi_flash_device *)dev);
return size;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops gd_device_ops =
{
w25qxx_flash_init,
w25qxx_flash_open,
w25qxx_flash_close,
w25qxx_flash_read,
w25qxx_flash_write,
w25qxx_flash_control
};
#endif
rt_err_t gd_init(const char * flash_device_name, const char * spi_device_name)
{
struct rt_spi_device * rt_spi_device;
/* initialize mutex */
if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
{
rt_kprintf("init sd lock mutex failed\n");
return -RT_ENOSYS;
}
rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
if(rt_spi_device == RT_NULL)
{
FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
return -RT_ENOSYS;
}
spi_flash_device.rt_spi_device = rt_spi_device;
/* config spi */
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
cfg.max_hz = 50 * 1000 * 1000; /* 50M */
rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
}
/* init flash */
{
rt_uint8_t cmd;
rt_uint8_t id_recv[3];
uint16_t memory_type_capacity;
flash_lock(&spi_flash_device);
cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
cmd = CMD_WRDI;
rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
/* read flash id */
cmd = CMD_JEDEC_ID;
rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
flash_unlock(&spi_flash_device);
if(id_recv[0] != MF_ID)
{
FLASH_TRACE("Manufacturers ID error!\r\n");
FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
return -RT_ENOSYS;
}
spi_flash_device.geometry.bytes_per_sector = 4096;
spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
/* get memory type and capacity */
memory_type_capacity = id_recv[1];
memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
if(memory_type_capacity == MTC_GD25Q128)
{
FLASH_TRACE("GD128 detection\r\n");
spi_flash_device.geometry.sector_count = 4096;
}
else
{
FLASH_TRACE("Memory Capacity error!\r\n");
return -RT_ENOSYS;
}
}
/* register device */
spi_flash_device.flash_device.type = RT_Device_Class_Block;
#ifdef RT_USING_DEVICE_OPS
spi_flash_device.flash_device.ops = &gd_device_ops;
#else
spi_flash_device.flash_device.init = w25qxx_flash_init;
spi_flash_device.flash_device.open = w25qxx_flash_open;
spi_flash_device.flash_device.close = w25qxx_flash_close;
spi_flash_device.flash_device.read = w25qxx_flash_read;
spi_flash_device.flash_device.write = w25qxx_flash_write;
spi_flash_device.flash_device.control = w25qxx_flash_control;
#endif
/* no private */
spi_flash_device.flash_device.user_data = RT_NULL;
rt_device_register(&spi_flash_device.flash_device, flash_device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
return RT_EOK;
}

18
components/drivers/spi/spi_flash_gd.h
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@ -1,18 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-10-11 fullhan copy from winbond flash
*/
#ifndef SPI_FLASH_GD_H_
#define SPI_FLASH_GD_H_
#include <rtthread.h>
extern rt_err_t gd_init(const char * flash_device_name, const char * spi_device_name);
#endif /* SPI_FLASH_GD_H_ */

358
components/drivers/spi/spi_flash_sst25vfxx.c
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@ -1,358 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
*/
#include <stdint.h>
#include "spi_flash_sst25vfxx.h"
#define FLASH_DEBUG
#ifdef FLASH_DEBUG
#define FLASH_TRACE rt_kprintf
#else
#define FLASH_TRACE(...)
#endif /* #ifdef FLASH_DEBUG */
/* JEDEC Manufacturer’s ID */
#define MF_ID (0xBF)
/* JEDEC Device ID : Memory Type */
#define MT_ID (0x25)
/* JEDEC Device ID: Memory Capacity */
#define MC_ID_SST25VF020B (0x8C) /* 2Mbit */
#define MC_ID_SST25VF040B (0x8D) /* 4Mbit */
#define MC_ID_SST25VF080B (0x8E) /* 8Mbit */
#define MC_ID_SST25VF016B (0x41) /* 16Mbit */
#define MC_ID_SST25VF032B (0x4A) /* 32Mbit */
#define MC_ID_SST25VF064C (0x4B) /* 64Mbit */
/* command list */
#define CMD_RDSR (0x05)
#define CMD_WRSR (0x01)
#define CMD_EWSR (0x50)
#define CMD_WRDI (0x04)
#define CMD_WREN (0x06)
#define CMD_READ (0x03)
#define CMD_FAST_READ (0x0B)
#define CMD_BP (0x02)
#define CMD_AAIP (0xAD)
#define CMD_ERASE_4K (0x20)
#define CMD_ERASE_32K (0x52)
#define CMD_ERASE_64K (0xD8)
#define CMD_ERASE_full (0xC7)
#define CMD_JEDEC_ID (0x9F)
#define CMD_EBSY (0x70)
#define CMD_DBSY (0x80)
#define DUMMY (0xFF)
static struct spi_flash_sst25vfxx spi_flash_sst25vfxx;
static uint8_t sst25vfxx_read_status(struct spi_flash_sst25vfxx * spi_flash)
{
return rt_spi_sendrecv8(spi_flash->rt_spi_device, CMD_RDSR);
}
static void sst25vfxx_wait_busy(struct spi_flash_sst25vfxx * spi_flash)
{
while( sst25vfxx_read_status(spi_flash) & (0x01));
}
/** \brief write N page on [page]
*
* \param page uint32_t unit : byte (4096 * N,1 page = 4096byte)
* \param buffer const uint8_t*
* \param size uint32_t unit : byte ( 4096*N )
* \return uint32_t
*
*/
static uint32_t sst25vfxx_page_write(struct spi_flash_sst25vfxx * spi_flash, uint32_t page, const uint8_t * buffer, uint32_t size)
{
uint32_t index;
uint32_t need_wirte = size;
uint8_t send_buffer[6];
page &= ~0xFFF; // page size = 4096byte
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_ERASE_4K;
send_buffer[1] = (page >> 16);
send_buffer[2] = (page >> 8);
send_buffer[3] = (page);
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 4);
sst25vfxx_wait_busy(spi_flash); // wait erase done.
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_AAIP;
send_buffer[1] = (uint8_t)(page >> 16);
send_buffer[2] = (uint8_t)(page >> 8);
send_buffer[3] = (uint8_t)(page);
send_buffer[4] = *buffer++;
send_buffer[5] = *buffer++;
need_wirte -= 2;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 6);
sst25vfxx_wait_busy(spi_flash);
for(index=0; index < need_wirte/2; index++)
{
send_buffer[0] = CMD_AAIP;
send_buffer[1] = *buffer++;
send_buffer[2] = *buffer++;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 3);
sst25vfxx_wait_busy(spi_flash);
}
send_buffer[0] = CMD_WRDI;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
return size;
}
/* RT-Thread device interface */
static rt_err_t sst25vfxx_flash_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t sst25vfxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
{
rt_err_t result;
uint8_t send_buffer[2];
struct spi_flash_sst25vfxx * spi_flash = (struct spi_flash_sst25vfxx *)dev;
/* lock spi flash */
result = rt_mutex_take(&(spi_flash->lock), RT_WAITING_FOREVER);
if(result != RT_EOK)
{
return result;
}
send_buffer[0] = CMD_DBSY;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_EWSR;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_WRSR;
send_buffer[1] = 0;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 2);
/* release lock */
rt_mutex_release(&(spi_flash->lock));
return RT_EOK;
}
static rt_err_t sst25vfxx_flash_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t sst25vfxx_flash_control(rt_device_t dev, int cmd, void *args)
{
struct spi_flash_sst25vfxx * spi_flash;
spi_flash = (struct spi_flash_sst25vfxx *)dev;
RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = spi_flash->geometry.bytes_per_sector;
geometry->sector_count = spi_flash->geometry.sector_count;
geometry->block_size = spi_flash->geometry.block_size;
}
return RT_EOK;
}
static rt_size_t sst25vfxx_flash_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_err_t result;
uint8_t send_buffer[4];
struct spi_flash_sst25vfxx * spi_flash = (struct spi_flash_sst25vfxx *)dev;
uint32_t offset = pos * spi_flash->geometry.bytes_per_sector;
/* lock spi flash */
result = rt_mutex_take(&(spi_flash->lock), RT_WAITING_FOREVER);
if(result != RT_EOK)
{
return 0;
}
send_buffer[0] = CMD_WRDI;
rt_spi_send(spi_flash->rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_READ;
send_buffer[1] = (uint8_t)(offset>>16);
send_buffer[2] = (uint8_t)(offset>>8);
send_buffer[3] = (uint8_t)(offset);
rt_spi_send_then_recv(spi_flash->rt_spi_device, send_buffer, 4, buffer, size * spi_flash->geometry.bytes_per_sector);
/* release lock */
rt_mutex_release(&(spi_flash->lock));
return size;
}
static rt_size_t sst25vfxx_flash_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
uint32_t i;
rt_err_t result;
const uint8_t * write_buffer = buffer;
struct spi_flash_sst25vfxx * spi_flash = (struct spi_flash_sst25vfxx *)dev;
/* lock spi flash */
result = rt_mutex_take(&(spi_flash->lock), RT_WAITING_FOREVER);
if(result != RT_EOK)
{
return 0;
}
for(i=0; i<size; i++)
{
sst25vfxx_page_write(spi_flash,
(pos + i) * spi_flash->geometry.bytes_per_sector,
write_buffer,
spi_flash->geometry.bytes_per_sector);
write_buffer += spi_flash->geometry.bytes_per_sector;
}
/* release lock */
rt_mutex_release(&(spi_flash->lock));
return size;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops sst25vfxx_device_ops =
{
sst25vfxx_flash_init,
sst25vfxx_flash_open,
sst25vfxx_flash_close,
sst25vfxx_flash_read,
sst25vfxx_flash_write,
sst25vfxx_flash_control
};
#endif
rt_err_t sst25vfxx_init(const char * flash_device_name, const char * spi_device_name)
{
struct rt_spi_device * rt_spi_device;
struct spi_flash_sst25vfxx * spi_flash = &spi_flash_sst25vfxx;
rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
if(rt_spi_device == RT_NULL)
{
FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
return -RT_ENOSYS;
}
spi_flash->rt_spi_device = rt_spi_device;
/* config spi */
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
cfg.max_hz = 50000000; /* 50M */
rt_spi_configure(spi_flash->rt_spi_device, &cfg);
}
/* init flash */
{
rt_uint8_t cmd;
rt_uint8_t id_recv[3];
cmd = CMD_WRDI;
rt_spi_send(spi_flash->rt_spi_device, &cmd, 1);
/* read flash id */
cmd = CMD_JEDEC_ID;
rt_spi_send_then_recv(spi_flash->rt_spi_device, &cmd, 1, id_recv, 3);
if(id_recv[0] != MF_ID || id_recv[1] != MT_ID)
{
FLASH_TRACE("Manufacturer’s ID or Memory Type error!\r\n");
FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
return -RT_ENOSYS;
}
spi_flash->geometry.bytes_per_sector = 4096;
spi_flash->geometry.block_size = 4096; /* block erase: 4k */
if(id_recv[2] == MC_ID_SST25VF020B)
{
FLASH_TRACE("SST25VF020B detection\r\n");
spi_flash->geometry.sector_count = 64;
}
else if(id_recv[2] == MC_ID_SST25VF040B)
{
FLASH_TRACE("SST25VF040B detection\r\n");
spi_flash->geometry.sector_count = 128;
}
else if(id_recv[2] == MC_ID_SST25VF080B)
{
FLASH_TRACE("SST25VF080B detection\r\n");
spi_flash->geometry.sector_count = 256;
}
else if(id_recv[2] == MC_ID_SST25VF016B)
{
FLASH_TRACE("SST25VF016B detection\r\n");
spi_flash->geometry.sector_count = 512;
}
else if(id_recv[2] == MC_ID_SST25VF032B)
{
FLASH_TRACE("SST25VF032B detection\r\n");
spi_flash->geometry.sector_count = 1024;
}
else if(id_recv[2] == MC_ID_SST25VF064C)
{
FLASH_TRACE("SST25VF064C detection\r\n");
spi_flash->geometry.sector_count = 2048;
}
else
{
FLASH_TRACE("Memory Capacity error!\r\n");
return -RT_ENOSYS;
}
}
/* initialize mutex lock */
rt_mutex_init(&spi_flash->lock, flash_device_name, RT_IPC_FLAG_PRIO);
/* register device */
spi_flash->flash_device.type = RT_Device_Class_Block;
#ifdef RT_USING_DEVICE_OPS
spi_flash->flash_device.ops = &sst25vfxx_device_ops;
#else
spi_flash->flash_device.init = sst25vfxx_flash_init;
spi_flash->flash_device.open = sst25vfxx_flash_open;
spi_flash->flash_device.close = sst25vfxx_flash_close;
spi_flash->flash_device.read = sst25vfxx_flash_read;
spi_flash->flash_device.write = sst25vfxx_flash_write;
spi_flash->flash_device.control = sst25vfxx_flash_control;
#endif
/* no private */
spi_flash->flash_device.user_data = RT_NULL;
rt_device_register(&spi_flash->flash_device, flash_device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
return RT_EOK;
}

28
components/drivers/spi/spi_flash_sst25vfxx.h
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@ -1,28 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
*/
#ifndef SPI_FLASH_SST25VFXX_H_INCLUDED
#define SPI_FLASH_SST25VFXX_H_INCLUDED
#include <rtthread.h>
#include <drivers/spi.h>
struct spi_flash_sst25vfxx
{
struct rt_device flash_device;
struct rt_device_blk_geometry geometry;
struct rt_spi_device * rt_spi_device;
struct rt_mutex lock;
};
extern rt_err_t sst25vfxx_init(const char * flash_device_name, const char * spi_device_name);
#endif // SPI_FLASH_SST25VFXX_H_INCLUDED

393
components/drivers/spi/spi_flash_w25qxx.c
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@ -1,393 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
* 2012-05-06 aozima can page write.
* 2012-08-23 aozima add flash lock.
* 2012-08-24 aozima fixed write status register BUG.
*/
#include <stdint.h>
#include <rtdevice.h>
#include "spi_flash.h"
#include "spi_flash_w25qxx.h"
#define FLASH_DEBUG
#ifdef FLASH_DEBUG
#define FLASH_TRACE rt_kprintf
#else
#define FLASH_TRACE(...)
#endif /* #ifdef FLASH_DEBUG */
#define PAGE_SIZE 4096
/* JEDEC Manufacturer ID */
#define MF_ID (0xEF)
/* JEDEC Device ID: Memory type and Capacity */
#define MTC_W25Q80_BV (0x4014) /* W25Q80BV */
#define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */
#define MTC_W25Q16_DW (0x6015) /* W25Q16DW */
#define MTC_W25Q32_BV (0x4016) /* W25Q32BV */
#define MTC_W25Q32_DW (0x6016) /* W25Q32DW */
#define MTC_W25Q64_BV_CV (0x4017) /* W25Q64BV W25Q64CV */
#define MTC_W25Q64_DW (0x4017) /* W25Q64DW */
#define MTC_W25Q128_BV (0x4018) /* W25Q128BV */
#define MTC_W25Q256_FV (TBD) /* W25Q256FV */
/* command list */
#define CMD_WRSR (0x01) /* Write Status Register */
#define CMD_PP (0x02) /* Page Program */
#define CMD_READ (0x03) /* Read Data */
#define CMD_WRDI (0x04) /* Write Disable */
#define CMD_RDSR1 (0x05) /* Read Status Register-1 */
#define CMD_WREN (0x06) /* Write Enable */
#define CMD_FAST_READ (0x0B) /* Fast Read */
#define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
#define CMD_RDSR2 (0x35) /* Read Status Register-2 */
#define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
#define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
#define CMD_ERASE_full (0xC7) /* Chip Erase */
#define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
#define DUMMY (0xFF)
static struct spi_flash_device spi_flash_device;
static void flash_lock(struct spi_flash_device * flash_device)
{
rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
}
static void flash_unlock(struct spi_flash_device * flash_device)
{
rt_mutex_release(&flash_device->lock);
}
static uint8_t w25qxx_read_status(void)
{
return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
}
static void w25qxx_wait_busy(void)
{
while( w25qxx_read_status() & (0x01));
}
/** \brief read [size] byte from [offset] to [buffer]
*
* \param offset uint32_t unit : byte
* \param buffer uint8_t*
* \param size uint32_t unit : byte
* \return uint32_t byte for read
*
*/
static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
{
uint8_t send_buffer[4];
send_buffer[0] = CMD_WRDI;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_READ;
send_buffer[1] = (uint8_t)(offset>>16);
send_buffer[2] = (uint8_t)(offset>>8);
send_buffer[3] = (uint8_t)(offset);
rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
send_buffer, 4,
buffer, size);
return size;
}
/** \brief write N page on [page]
*
* \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
* \param buffer const uint8_t*
* \return uint32_t
*
*/
uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
{
uint32_t index;
uint8_t send_buffer[4];
RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_ERASE_4K;
send_buffer[1] = (page_addr >> 16);
send_buffer[2] = (page_addr >> 8);
send_buffer[3] = (page_addr);
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
w25qxx_wait_busy(); // wait erase done.
for(index=0; index < (PAGE_SIZE / 256); index++)
{
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_PP;
send_buffer[1] = (uint8_t)(page_addr >> 16);
send_buffer[2] = (uint8_t)(page_addr >> 8);
send_buffer[3] = (uint8_t)(page_addr);
rt_spi_send_then_send(spi_flash_device.rt_spi_device,
send_buffer,
4,
buffer,
256);
buffer += 256;
page_addr += 256;
w25qxx_wait_busy();
}
send_buffer[0] = CMD_WRDI;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
return PAGE_SIZE;
}
/* RT-Thread device interface */
static rt_err_t w25qxx_flash_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
{
uint8_t send_buffer[3];
flash_lock((struct spi_flash_device *)dev);
send_buffer[0] = CMD_WREN;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_WRSR;
send_buffer[1] = 0;
send_buffer[2] = 0;
rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
w25qxx_wait_busy();
flash_unlock((struct spi_flash_device *)dev);
return RT_EOK;
}
static rt_err_t w25qxx_flash_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t w25qxx_flash_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
geometry->sector_count = spi_flash_device.geometry.sector_count;
geometry->block_size = spi_flash_device.geometry.block_size;
}
return RT_EOK;
}
static rt_size_t w25qxx_flash_read(rt_device_t dev,
rt_off_t pos,
void* buffer,
rt_size_t size)
{
flash_lock((struct spi_flash_device *)dev);
w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
buffer,
size*spi_flash_device.geometry.bytes_per_sector);
flash_unlock((struct spi_flash_device *)dev);
return size;
}
static rt_size_t w25qxx_flash_write(rt_device_t dev,
rt_off_t pos,
const void* buffer,
rt_size_t size)
{
rt_size_t i = 0;
rt_size_t block = size;
const uint8_t * ptr = buffer;
flash_lock((struct spi_flash_device *)dev);
while(block--)
{
w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
ptr);
ptr += PAGE_SIZE;
i++;
}
flash_unlock((struct spi_flash_device *)dev);
return size;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops w25qxx_device_ops =
{
w25qxx_flash_init,
w25qxx_flash_open,
w25qxx_flash_close,
w25qxx_flash_read,
w25qxx_flash_write,
w25qxx_flash_control
};
#endif
rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_name)
{
struct rt_spi_device * rt_spi_device;
/* initialize mutex */
if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
{
rt_kprintf("init sd lock mutex failed\n");
return -RT_ENOSYS;
}
rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
if(rt_spi_device == RT_NULL)
{
FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
return -RT_ENOSYS;
}
spi_flash_device.rt_spi_device = rt_spi_device;
/* config spi */
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
cfg.max_hz = 50 * 1000 * 1000; /* 50M */
rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
}
/* init flash */
{
rt_uint8_t cmd;
rt_uint8_t id_recv[3];
uint16_t memory_type_capacity;
flash_lock(&spi_flash_device);
cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
cmd = CMD_WRDI;
rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
/* read flash id */
cmd = CMD_JEDEC_ID;
rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
flash_unlock(&spi_flash_device);
if(id_recv[0] != MF_ID)
{
FLASH_TRACE("Manufacturers ID error!\r\n");
FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
return -RT_ENOSYS;
}
spi_flash_device.geometry.bytes_per_sector = 4096;
spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
/* get memory type and capacity */
memory_type_capacity = id_recv[1];
memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
if(memory_type_capacity == MTC_W25Q128_BV)
{
FLASH_TRACE("W25Q128BV detection\r\n");
spi_flash_device.geometry.sector_count = 4096;
}
else if(memory_type_capacity == MTC_W25Q64_BV_CV)
{
FLASH_TRACE("W25Q64BV or W25Q64CV detection\r\n");
spi_flash_device.geometry.sector_count = 2048;
}
else if(memory_type_capacity == MTC_W25Q64_DW)
{
FLASH_TRACE("W25Q64DW detection\r\n");
spi_flash_device.geometry.sector_count = 2048;
}
else if(memory_type_capacity == MTC_W25Q32_BV)
{
FLASH_TRACE("W25Q32BV detection\r\n");
spi_flash_device.geometry.sector_count = 1024;
}
else if(memory_type_capacity == MTC_W25Q32_DW)
{
FLASH_TRACE("W25Q32DW detection\r\n");
spi_flash_device.geometry.sector_count = 1024;
}
else if(memory_type_capacity == MTC_W25Q16_BV_CL_CV)
{
FLASH_TRACE("W25Q16BV or W25Q16CL or W25Q16CV detection\r\n");
spi_flash_device.geometry.sector_count = 512;
}
else if(memory_type_capacity == MTC_W25Q16_DW)
{
FLASH_TRACE("W25Q16DW detection\r\n");
spi_flash_device.geometry.sector_count = 512;
}
else if(memory_type_capacity == MTC_W25Q80_BV)
{
FLASH_TRACE("W25Q80BV detection\r\n");
spi_flash_device.geometry.sector_count = 256;
}
else
{
FLASH_TRACE("Memory Capacity error!\r\n");
return -RT_ENOSYS;
}
}
/* register device */
spi_flash_device.flash_device.type = RT_Device_Class_Block;
#ifdef RT_USING_DEVICE_OPS
spi_flash_device.flash_device.ops = &w25qxx_device_ops;
#else
spi_flash_device.flash_device.init = w25qxx_flash_init;
spi_flash_device.flash_device.open = w25qxx_flash_open;
spi_flash_device.flash_device.close = w25qxx_flash_close;
spi_flash_device.flash_device.read = w25qxx_flash_read;
spi_flash_device.flash_device.write = w25qxx_flash_write;
spi_flash_device.flash_device.control = w25qxx_flash_control;
#endif
/* no private */
spi_flash_device.flash_device.user_data = RT_NULL;
rt_device_register(&spi_flash_device.flash_device, flash_device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
return RT_EOK;
}

20
components/drivers/spi/spi_flash_w25qxx.h
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@ -1,20 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
* 2012-08-23 aozima add flash lock.
*/
#ifndef SPI_FLASH_W25QXX_H_INCLUDED
#define SPI_FLASH_W25QXX_H_INCLUDED
#include <rtthread.h>
extern rt_err_t w25qxx_init(const char * flash_device_name,
const char * spi_device_name);
#endif // SPI_FLASH_W25QXX_H_INCLUDED

336
components/drivers/spi/spi_flash_w25qxx_mtd.c
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@ -1,336 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "spi_flash.h"
#include "spi_flash_w25qxx_mtd.h"
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#define FLASH_DEBUG
#ifdef FLASH_DEBUG
#define FLASH_TRACE printf
#else
#define FLASH_TRACE(...)
#endif /* #ifdef FLASH_DEBUG */
/* JEDEC Manufacturer’s ID */
#define MF_ID (0xEF)
/* JEDEC Device ID: Memory type and Capacity */
#define MTC_W25Q80_BV (0x4014) /* W25Q80BV */
#define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */
#define MTC_W25Q16_DW (0x6015) /* W25Q16DW */
#define MTC_W25Q32_BV (0x4016) /* W25Q32BV */
#define MTC_W25Q32_DW (0x6016) /* W25Q32DW */
#define MTC_W25Q64_BV_CV (0x4017) /* W25Q64BV W25Q64CV */
#define MTC_W25Q64_DW (0x4017) /* W25Q64DW */
#define MTC_W25Q128_BV (0x4018) /* W25Q128BV */
#define MTC_W25Q256_FV (TBD) /* W25Q256FV */
#define MTC_W25X80 (0x3014)
/* command list */
#define CMD_WRSR (0x01) /* Write Status Register */
#define CMD_PP (0x02) /* Page Program */
#define CMD_READ (0x03) /* Read Data */
#define CMD_WRDI (0x04) /* Write Disable */
#define CMD_RDSR1 (0x05) /* Read Status Register-1 */
#define CMD_WREN (0x06) /* Write Enable */
#define CMD_FAST_READ (0x0B) /* Fast Read */
#define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
#define CMD_RDSR2 (0x35) /* Read Status Register-2 */
#define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
#define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
#define CMD_ERASE_full (0xC7) /* Chip Erase */
#define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
#define CMD_MANU_ID (0x90)
#define DUMMY (0xFF)
#define FLASH_ERASE_CMD CMD_ERASE_4K
#define FLASH_BLOCK_SIZE 4096
#define FLASH_PAGE_SIZE 256
static void w25qxx_lock(struct rt_mtd_nor_device *device)
{
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
rt_mutex_take(&mtd->lock, RT_WAITING_FOREVER);
}
static void w25qxx_unlock(struct rt_mtd_nor_device *device)
{
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
rt_mutex_release(&mtd->lock);
}
static rt_uint8_t w25qxx_read_status(struct rt_mtd_nor_device *device)
{
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
return rt_spi_sendrecv8(mtd->rt_spi_device, CMD_RDSR1);
}
static void w25qxx_wait_busy(struct rt_mtd_nor_device *device)
{
while( w25qxx_read_status(device) & (0x01));
}
static rt_err_t w25qxx_read_id(struct rt_mtd_nor_device *device)
{
rt_uint8_t cmd;
rt_uint8_t id_recv[3];
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
w25qxx_lock(device);
cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
rt_spi_send(mtd->rt_spi_device, &cmd, 1);
cmd = CMD_WRDI;
rt_spi_send(mtd->rt_spi_device, &cmd, 1);
/* read flash id */
cmd = CMD_JEDEC_ID;
rt_spi_send_then_recv(mtd->rt_spi_device, &cmd, 1, id_recv, 3);
w25qxx_unlock(device);
return (rt_uint32_t)(id_recv[0] << 16) | (id_recv[1] << 8) | id_recv[2];
}
static rt_size_t w25qxx_read(struct rt_mtd_nor_device *device, rt_off_t offset, rt_uint8_t *buffer, rt_size_t length)
{
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
rt_uint8_t send_buffer[4];
if((offset + length) > device->block_end * FLASH_BLOCK_SIZE)
return 0;
w25qxx_lock(device);
send_buffer[0] = CMD_WRDI;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
send_buffer[0] = CMD_READ;
send_buffer[1] = (rt_uint8_t)(offset>>16);
send_buffer[2] = (rt_uint8_t)(offset>>8);
send_buffer[3] = (rt_uint8_t)(offset);
rt_spi_send_then_recv(mtd->rt_spi_device,
send_buffer, 4,
buffer, length);
w25qxx_unlock(device);
return length;
}
static rt_size_t w25qxx_write(struct rt_mtd_nor_device *device, rt_off_t offset, const rt_uint8_t *buffer, rt_size_t length)
{
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
rt_uint8_t send_buffer[4];
rt_uint8_t *write_ptr ;
rt_size_t write_size,write_total;
if((offset + length) > device->block_end * FLASH_BLOCK_SIZE)
return 0;
w25qxx_lock(device);
send_buffer[0] = CMD_WREN;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
w25qxx_wait_busy(device); // wait erase done.
write_size = 0;
write_total = 0;
write_ptr = (rt_uint8_t *)buffer;
while(write_total < length)
{
send_buffer[0] = CMD_WREN;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
//write first page...
send_buffer[0] = CMD_PP;
send_buffer[1] = (rt_uint8_t)(offset >> 16);
send_buffer[2] = (rt_uint8_t)(offset >> 8);
send_buffer[3] = (rt_uint8_t)(offset);
//address % FLASH_PAGE_SIZE + length
if(((offset & (FLASH_PAGE_SIZE - 1)) + (length - write_total)) > FLASH_PAGE_SIZE)
{
write_size = FLASH_PAGE_SIZE - (offset & (FLASH_PAGE_SIZE - 1));
}
else
{
write_size = (length - write_total);
}
rt_spi_send_then_send(mtd->rt_spi_device,
send_buffer, 4,
write_ptr + write_total, write_size);
w25qxx_wait_busy(device);
offset += write_size;
write_total += write_size;
}
send_buffer[0] = CMD_WRDI;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
w25qxx_unlock(device);
return length;
}
static rt_err_t w25qxx_erase_block(struct rt_mtd_nor_device *device, rt_off_t offset, rt_uint32_t length)
{
struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device;
rt_uint8_t send_buffer[4];
rt_uint32_t erase_size = 0;
//offset must be ALIGN_DOWN to BLOCKSIZE
if(offset != RT_ALIGN_DOWN(offset,FLASH_BLOCK_SIZE))
return 0;
if((offset + length) > device->block_end * FLASH_BLOCK_SIZE)
return 0;
/* check length must align to block size */
if(length % device->block_size != 0)
{
rt_kprintf("param length = %d ,error\n",length);
return 0;
}
w25qxx_lock(device);
send_buffer[0] = CMD_WREN;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
w25qxx_wait_busy(device); // wait erase done.
while (erase_size < length)
{
send_buffer[0] = CMD_ERASE_4K;
send_buffer[1] = (rt_uint8_t) (offset >> 16);
send_buffer[2] = (rt_uint8_t) (offset >> 8);
send_buffer[3] = (rt_uint8_t) (offset);
rt_spi_send(mtd->rt_spi_device, send_buffer, 4);
w25qxx_wait_busy(device); // wait erase done.
erase_size += 4096;
offset += 4096;
}
send_buffer[0] = CMD_WRDI;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
w25qxx_unlock(device);
return RT_EOK;
}
const static struct rt_mtd_nor_driver_ops w25qxx_mtd_ops =
{
w25qxx_read_id,
w25qxx_read,
w25qxx_write,
w25qxx_erase_block,
};
rt_err_t w25qxx_mtd_init(const char *mtd_name,const char * spi_device_name)
{
rt_err_t result = RT_EOK;
rt_uint32_t id;
rt_uint8_t send_buffer[3];
struct rt_spi_device* rt_spi_device;
struct spi_flash_mtd* mtd = (struct spi_flash_mtd *)rt_malloc(sizeof(struct spi_flash_mtd));
RT_ASSERT(mtd != RT_NULL);
/* initialize mutex */
if (rt_mutex_init(&mtd->lock, mtd_name, RT_IPC_FLAG_FIFO) != RT_EOK)
{
FLASH_TRACE("init mtd lock mutex failed\n");
result = -RT_ENOSYS;
goto _error_exit;
}
rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
if(rt_spi_device == RT_NULL)
{
FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
result = -RT_ENOSYS;
goto _error_exit;
}
mtd->rt_spi_device = rt_spi_device;
/* config spi */
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
cfg.max_hz = 20 * 1000 * 1000; /* 20 */
rt_spi_configure(rt_spi_device, &cfg);
}
/* Init Flash device */
{
w25qxx_lock(&mtd->mtd_device);
send_buffer[0] = CMD_WREN;
rt_spi_send(mtd->rt_spi_device, send_buffer, 1);
w25qxx_wait_busy(&mtd->mtd_device);
send_buffer[0] = CMD_WRSR;
send_buffer[1] = 0;
send_buffer[2] = 0;
rt_spi_send(mtd->rt_spi_device, send_buffer, 3);
w25qxx_wait_busy(&mtd->mtd_device);
w25qxx_unlock(&mtd->mtd_device);
}
id = w25qxx_read_id(&mtd->mtd_device);
mtd->mtd_device.block_size = 4096;
mtd->mtd_device.block_start = 0;
switch(id & 0xFFFF)
{
case MTC_W25Q80_BV: /* W25Q80BV */
mtd->mtd_device.block_end = 256;
break;
case MTC_W25Q16_BV_CL_CV: /* W25Q16BV W25Q16CL W25Q16CV */
case MTC_W25Q16_DW: /* W25Q16DW */
mtd->mtd_device.block_end = 512;
break;
case MTC_W25Q32_BV: /* W25Q32BV */
case MTC_W25Q32_DW: /* W25Q32DW */
mtd->mtd_device.block_end = 1024;
break;
case MTC_W25Q64_BV_CV: /* W25Q64BV W25Q64CV */
mtd->mtd_device.block_end = 2048;
break;
case MTC_W25Q128_BV: /* W25Q128BV */
mtd->mtd_device.block_end = 4086;
break;
}
mtd->mtd_device.ops = &w25qxx_mtd_ops;
rt_mtd_nor_register_device(mtd_name,&mtd->mtd_device);
return RT_EOK;
_error_exit:
if(mtd != RT_NULL)
rt_free(mtd);
return result;
}

20
components/drivers/spi/spi_flash_w25qxx_mtd.h
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@ -1,20 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-12-16 aozima the first version
* 2012-08-23 aozima add flash lock.
* 2017-02-11 urey add mtd fucntion
*/
#ifndef SPI_FLASH_W25QXX_H_INCLUDED
#define SPI_FLASH_W25QXX_H_INCLUDED
#include <rtthread.h>
extern rt_err_t w25qxx_mtd_init(const char *mtd_name,const char * spi_device_name);
#endif // SPI_FLASH_W25QXX_H_INCLUDED