gpio: add gd32h7xx support

This commit is contained in:
wirano 2024-07-24 16:45:22 +08:00 committed by Rbb666
parent 36dd0b74c8
commit ab2e98aacf
2 changed files with 18 additions and 10 deletions

View File

@ -257,7 +257,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
const struct pin_index *index = RT_NULL;
rt_uint32_t pin_mode = 0;
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
rt_uint32_t pin_pupd = 0, pin_odpp = 0;
#endif
@ -269,7 +269,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
/* GPIO Periph clock enable */
rcu_periph_clock_enable(index->clk);
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
pin_mode = GPIO_MODE_OUTPUT;
#else
pin_mode = GPIO_MODE_OUT_PP;
@ -279,7 +279,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{
case PIN_MODE_OUTPUT:
/* output setting */
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
pin_mode = GPIO_MODE_OUTPUT;
pin_pupd = GPIO_PUPD_NONE;
pin_odpp = GPIO_OTYPE_PP;
@ -289,7 +289,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
break;
case PIN_MODE_OUTPUT_OD:
/* output setting: od. */
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
pin_mode = GPIO_MODE_OUTPUT;
pin_pupd = GPIO_PUPD_NONE;
pin_odpp = GPIO_OTYPE_OD;
@ -299,7 +299,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
break;
case PIN_MODE_INPUT:
/* input setting: not pull. */
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
pin_mode = GPIO_MODE_INPUT;
pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN;
#else
@ -308,7 +308,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
break;
case PIN_MODE_INPUT_PULLUP:
/* input setting: pull up. */
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
pin_mode = GPIO_MODE_INPUT;
pin_pupd = GPIO_PUPD_PULLUP;
#else
@ -317,7 +317,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
break;
case PIN_MODE_INPUT_PULLDOWN:
/* input setting: pull down. */
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
pin_mode = GPIO_MODE_INPUT;
pin_pupd = GPIO_PUPD_PULLDOWN;
#else
@ -334,6 +334,12 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{
gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_50MHZ, index->pin);
}
#elif defined SOC_SERIES_GD32H7xx
gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin);
if(pin_mode == GPIO_MODE_OUTPUT)
{
gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_60MHZ, index->pin);
}
#else
gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
#endif
@ -547,7 +553,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
return -RT_EINVAL;
}
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
rcu_periph_clock_enable(RCU_SYSCFG);
#else
rcu_periph_clock_enable(RCU_AF);
@ -557,7 +563,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
nvic_irq_enable(irqmap->irqno, 5U, 0U);
/* connect EXTI line to GPIO pin */
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
syscfg_exti_line_config(index->port_src, index->pin_src);
#else
gpio_exti_source_select(index->port_src, index->pin_src);

View File

@ -27,11 +27,13 @@ extern "C" {
#include "gd32f30x_gpio.h"
#elif defined SOC_SERIES_GD32F4xx
#include "gd32f4xx_gpio.h"
#elif defined SOC_SERIES_GD32H7xx
#include "gd32h7xx_gpio.h"
#endif
#define __GD32_PORT(port) GPIO##port
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
GPIO##port, GPIO_PIN_##pin, \
EXTI_SOURCE_GPIO##port, \