diff --git a/bsp/lpc54114-lite/README.md b/bsp/lpc54114-lite/README.md index 7247a6f08c..1b0652401b 100644 --- a/bsp/lpc54114-lite/README.md +++ b/bsp/lpc54114-lite/README.md @@ -41,8 +41,8 @@ LPC54114-Lite 开发板的更多详细信息请参考万利电子 [开发板用 | SPI Flash | 支持 |- | | SPI TF 卡 | 支持 |- | | I2C 温度传感器
(PCT2075DP) | 支持 |- | -| I2S 音频输入 / 输出接口
(WM8904) | 暂不支持 |- | -| PDM 数字麦克风
(SPH0641LM4H) | 暂不支持 |- | +| I2S 音频输入 / 输出接口
(WM8904) | 支持 |仅支持解码 | +| PDM 数字麦克风
(SPH0641LM4H) | 支持 |- | |**片上外设** |**支持情况**|**备注** | | GPIO | 支持 | PIO0_0 ... PIO1_31 ---> PIN: 0, 1...63 | | UART | 支持 | UART0 | diff --git a/bsp/lpc54114-lite/drivers/Kconfig b/bsp/lpc54114-lite/drivers/Kconfig index e616638663..0f8a701d58 100644 --- a/bsp/lpc54114-lite/drivers/Kconfig +++ b/bsp/lpc54114-lite/drivers/Kconfig @@ -35,4 +35,19 @@ menu "LPC54110 Bsp Config" select BSP_USING_SPI2 default y + config BSP_USING_AUDIO + bool "Enable Audio(WM8904&SPH0641LU4H)" + select RT_USING_AUDIO + default n + + if BSP_USING_AUDIO + config BSP_USING_AUDIO_REPLAY + bool "Enable WM8904(only replay)" + select BSP_USING_I2C4 + default y + + config BSP_USING_AUDIO_RECORD + bool "Enable SPH0641LU4H" + default y + endif endmenu diff --git a/bsp/lpc54114-lite/drivers/SConscript b/bsp/lpc54114-lite/drivers/SConscript index 1bdfeedc1c..9888f8fd95 100644 --- a/bsp/lpc54114-lite/drivers/SConscript +++ b/bsp/lpc54114-lite/drivers/SConscript @@ -29,6 +29,16 @@ if GetDepend('BSP_USING_SDCARD'): if GetDepend('BSP_USING_SPIFLASH'): src = src + ['drv_spi_flash.c'] +if GetDepend('BSP_USING_AUDIO_REPLAY'): + src = src + ['audio/drv_sound.c'] + src = src + ['audio/fsl_wm8904.c'] + +if GetDepend('BSP_USING_AUDIO_RECORD'): + src = src + ['audio/drv_mic.c'] + +if GetDepend('BSP_USING_AUDIO_REPLAY') or GetDepend('BSP_USING_AUDIO_RECORD'): + CPPPATH += [cwd+'audio'] + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.c b/bsp/lpc54114-lite/drivers/audio/drv_mic.c new file mode 100644 index 0000000000..d8219b504d --- /dev/null +++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-17 LiWeiHao First implementation + */ + +#include "drv_mic.h" +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_dmic.h" +#include "fsl_dma.h" +#include "fsl_dmic_dma.h" + +struct mic_device +{ + dma_handle_t dma_handle; + dmic_dma_handle_t dmic_dma_handle; + struct rt_audio_device audio; + struct rt_audio_configure config; + rt_uint8_t *rx_fifo; +}; + +#define DMAREQ_DMIC0 16U +#define DMAREQ_DMIC1 17U +#define DMAREQ_CHANNEL DMAREQ_DMIC0 +#define DMIC_CHANNEL kDMIC_Channel0 +#define DMIC_CHANNEL_ENABLE DMIC_CHANEN_EN_CH0(1) +#define FIFO_DEPTH 15U + +#define RX_DMA_FIFO_SIZE (2048) + +struct mic_device mic_dev; + +void dmic_dma_transfer_callback(DMIC_Type *base, + dmic_dma_handle_t *handle, + status_t status, + void *userData) +{ + struct mic_device *mic_dev = (struct mic_device *)userData; + rt_audio_rx_done(&mic_dev->audio, &mic_dev->rx_fifo[0], RX_DMA_FIFO_SIZE); + dmic_transfer_t dmic_transfer; + dmic_transfer.data = (uint16_t *)&mic_dev->rx_fifo[0]; + dmic_transfer.dataSize = RX_DMA_FIFO_SIZE / 2; + DMIC_TransferReceiveDMA(DMIC0, &mic_dev->dmic_dma_handle, &dmic_transfer, kDMIC_Channel0); +} + +rt_err_t mic_device_init(struct rt_audio_device *audio) +{ + dmic_channel_config_t dmic_channel_cfg; + + CLOCK_EnableClock(kCLOCK_Iocon); + CLOCK_EnableClock(kCLOCK_InputMux); + CLOCK_EnableClock(kCLOCK_Gpio0); + + IOCON_PinMuxSet(IOCON, 1, 16, IOCON_FUNC1 | IOCON_DIGITAL_EN); + IOCON_PinMuxSet(IOCON, 1, 15, IOCON_FUNC1 | IOCON_DIGITAL_EN); + + CLOCK_AttachClk(kFRO12M_to_DMIC); + CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 14, false); + + dmic_channel_cfg.divhfclk = kDMIC_PdmDiv1; + dmic_channel_cfg.osr = 25U; + dmic_channel_cfg.gainshft = 2U; + dmic_channel_cfg.preac2coef = kDMIC_CompValueZero; + dmic_channel_cfg.preac4coef = kDMIC_CompValueZero; + dmic_channel_cfg.dc_cut_level = kDMIC_DcCut155; + dmic_channel_cfg.post_dc_gain_reduce = 1; + dmic_channel_cfg.saturate16bit = 1U; + dmic_channel_cfg.sample_rate = kDMIC_PhyFullSpeed; + DMIC_Init(DMIC0); + + DMIC_ConfigIO(DMIC0, kDMIC_PdmDual); + DMIC_Use2fs(DMIC0, true); + DMIC_SetOperationMode(DMIC0, kDMIC_OperationModeDma); + DMIC_ConfigChannel(DMIC0, DMIC_CHANNEL, kDMIC_Left, &dmic_channel_cfg); + + DMIC_FifoChannel(DMIC0, DMIC_CHANNEL, FIFO_DEPTH, true, true); + + DMIC_EnableChannnel(DMIC0, DMIC_CHANNEL_ENABLE); + + DMA_EnableChannel(DMA0, DMAREQ_CHANNEL); + + /* Request dma channels from DMA manager. */ + DMA_CreateHandle(&mic_dev.dma_handle, DMA0, DMAREQ_CHANNEL); + + /* Create DMIC DMA handle. */ + DMIC_TransferCreateHandleDMA(DMIC0, + &mic_dev.dmic_dma_handle, + dmic_dma_transfer_callback, + (void *)&mic_dev, + &mic_dev.dma_handle); + return RT_EOK; +} + +rt_err_t mic_device_start(struct rt_audio_device *audio, int stream) +{ + struct mic_device *mic_dev = (struct mic_device *)audio->parent.user_data; + if (stream == AUDIO_STREAM_RECORD) + { + dmic_transfer_t dmic_transfer; + dmic_transfer.data = (uint16_t *)&mic_dev->rx_fifo[0]; + dmic_transfer.dataSize = RX_DMA_FIFO_SIZE / 2; + DMIC_TransferReceiveDMA(DMIC0, &mic_dev->dmic_dma_handle, &dmic_transfer, kDMIC_Channel0); + } + return RT_EOK; +} + +rt_err_t mic_device_stop(struct rt_audio_device *audio, int stream) +{ + struct mic_device *mic_dev = (struct mic_device *)audio->parent.user_data; + if (stream == AUDIO_STREAM_RECORD) + { + DMIC_TransferAbortReceiveDMA(DMIC0, &mic_dev->dmic_dma_handle); + } + return RT_EOK; +} + +rt_err_t mic_device_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + return RT_EOK; +} + +rt_err_t mic_device_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + return RT_EOK; +} + +static struct rt_audio_ops _mic_audio_ops = +{ + .getcaps = mic_device_getcaps, + .configure = mic_device_configure, + .init = mic_device_init, + .start = mic_device_start, + .stop = mic_device_stop, + .transmit = RT_NULL, + .buffer_info = RT_NULL, +}; + +int rt_hw_mic_init(void) +{ + struct rt_audio_device *audio = &mic_dev.audio; + /* mic default */ + mic_dev.rx_fifo = rt_calloc(1, RX_DMA_FIFO_SIZE); + if (mic_dev.rx_fifo == RT_NULL) + { + return -RT_ENOMEM; + } + + mic_dev.config.channels = 1; + mic_dev.config.samplerate = 16000; + mic_dev.config.samplebits = 16; + + /* register mic device */ + audio->ops = &_mic_audio_ops; + rt_audio_register(audio, "mic0", RT_DEVICE_FLAG_RDONLY, (void *)&mic_dev); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_mic_init); \ No newline at end of file diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.h b/bsp/lpc54114-lite/drivers/audio/drv_mic.h new file mode 100644 index 0000000000..1ce777d87d --- /dev/null +++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-17 LiWeiHao First implementation + */ + +#ifndef __DRV_MIC_H__ +#define __DRV_MIC_H__ + +#include +#include + +#endif diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.c b/bsp/lpc54114-lite/drivers/audio/drv_sound.c new file mode 100644 index 0000000000..b6cf0ca2f0 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-17 LiWeiHao First implementation + */ + +#include "drv_sound.h" +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_dma.h" +#include "fsl_i2s.h" +#include "fsl_i2s_dma.h" +#include "fsl_wm8904.h" +#include "fsl_i2c.h" + +#define TX_FIFO_SIZE (4096) + +#define I2S_TX I2S1 +#define I2S_RX I2S0 + +#define I2S_DMA_TX 15 +#define I2S_DMA_RX 12 + +#ifndef CODEC_I2C_NAME + #define CODEC_I2C_NAME "i2c4" +#endif + +struct sound_device +{ + wm8904_handle_t wm8904_handle; + dma_handle_t tx_dma_handle; + i2s_dma_handle_t tx_i2s_dma_handle; + struct rt_audio_device audio; + struct rt_audio_configure replay_config; + rt_uint8_t volume; + rt_uint8_t *tx_fifo; +}; + +const pll_setup_t pll_setup = +{ + .syspllctrl = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELP(0x1FU) | SYSCON_SYSPLLCTRL_SELI(0x8U), + .syspllndec = SYSCON_SYSPLLNDEC_NDEC(0x2DU), + .syspllpdec = SYSCON_SYSPLLPDEC_PDEC(0x42U), + .syspllssctrl = {SYSCON_SYSPLLSSCTRL0_MDEC(0x34D3U) | SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK, 0x00000000U}, + .pllRate = 24576000U, /* 16 bits * 2 channels * 44.1 kHz * 16 */ + .flags = PLL_SETUPFLAG_WAITLOCK +}; + +static struct sound_device snd_dev; + +void i2s_tx_transfer_callback(I2S_Type *base, + i2s_dma_handle_t *handle, + status_t completionStatus, + void *userData) +{ + struct sound_device *snd_dev = (struct sound_device *)userData; + rt_audio_tx_complete(&snd_dev->audio); +} + +static rt_err_t lpc_audio_init(struct rt_audio_device *audio) +{ + i2s_config_t tx_i2s_config; + wm8904_config_t wm8904_config; + + CLOCK_EnableClock(kCLOCK_Iocon); + CLOCK_EnableClock(kCLOCK_InputMux); + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + + CLOCK_AttachClk(kFRO12M_to_SYS_PLL); + CLOCK_AttachClk(kSYS_PLL_to_FLEXCOMM7); + + RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn); + + CLOCK_SetPLLFreq(&pll_setup); + CLOCK_AttachClk(kSYS_PLL_to_MCLK); + SYSCON->MCLKDIV = SYSCON_MCLKDIV_DIV(0U); + + // Flexcomm 7 I2S Tx + IOCON_PinMuxSet(IOCON, 1, 12, IOCON_FUNC4 | IOCON_DIGITAL_EN); /* Flexcomm 7 / SCK */ + IOCON_PinMuxSet(IOCON, 1, 13, IOCON_FUNC4 | IOCON_DIGITAL_EN); /* Flexcomm 7 / SDA */ + IOCON_PinMuxSet(IOCON, 1, 14, IOCON_FUNC4 | IOCON_DIGITAL_EN); /* Flexcomm 7 / WS */ + + /* MCLK output for I2S */ + IOCON_PinMuxSet(IOCON, 1, 17, IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGITAL_EN); + SYSCON->MCLKIO = 1U; + + WM8904_GetDefaultConfig(&wm8904_config); + snd_dev.wm8904_handle.i2c = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME); + if (WM8904_Init(&snd_dev.wm8904_handle, &wm8904_config) != kStatus_Success) + { + rt_kprintf("wm8904 init failed\n"); + return -RT_ERROR; + } + + WM8904_SetMute(&snd_dev.wm8904_handle, RT_TRUE, RT_TRUE); + + I2S_TxGetDefaultConfig(&tx_i2s_config); + tx_i2s_config.divider = CLOCK_GetPllOutFreq() / 48000U / 16 / 2; + I2S_TxInit(I2S_TX, &tx_i2s_config); + + DMA_Init(DMA0); + + DMA_EnableChannel(DMA0, I2S_DMA_TX); + DMA_SetChannelPriority(DMA0, I2S_DMA_TX, kDMA_ChannelPriority3); + DMA_CreateHandle(&snd_dev.tx_dma_handle, DMA0, I2S_DMA_TX); + + I2S_TxTransferCreateHandleDMA(I2S_TX, + &snd_dev.tx_i2s_dma_handle, + &snd_dev.tx_dma_handle, + i2s_tx_transfer_callback, + (void *)&snd_dev); + + return RT_EOK; +} + +static rt_err_t lpc_audio_start(struct rt_audio_device *audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + if (stream == AUDIO_STREAM_REPLAY) + { + struct rt_audio_caps caps; + caps.main_type = AUDIO_TYPE_MIXER; + caps.sub_type = AUDIO_MIXER_VOLUME; + audio->ops->getcaps(audio, &caps); + audio->ops->configure(audio, &caps); + rt_audio_tx_complete(audio); + } + return RT_EOK; +} + +static rt_err_t lpc_audio_stop(struct rt_audio_device *audio, int stream) +{ + if (stream == AUDIO_STREAM_REPLAY) + { + WM8904_SetMute(&snd_dev.wm8904_handle, RT_TRUE, RT_TRUE); + I2S_TransferAbortDMA(I2S_TX, &snd_dev.tx_i2s_dma_handle); + } + return RT_EOK; +} + +static rt_err_t lpc_audio_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev; + + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */ + { + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.samplerate = snd_dev->replay_config.samplerate; + caps->udata.config.channels = snd_dev->replay_config.channels; + caps->udata.config.samplebits = snd_dev->replay_config.samplebits; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = snd_dev->replay_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = snd_dev->replay_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = snd_dev->replay_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_MIXER: /* report the Mixer Units */ + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + caps->udata.mask = AUDIO_MIXER_VOLUME; + break; + + case AUDIO_MIXER_VOLUME: + caps->udata.value = snd_dev->volume; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t lpc_audio_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct sound_device *snd_dev = audio->parent.user_data; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + { + switch (caps->sub_type) + { + case AUDIO_MIXER_MUTE: + { + WM8904_SetMute(&snd_dev->wm8904_handle, RT_TRUE, RT_TRUE); + snd_dev->volume = 0; + break; + } + + case AUDIO_MIXER_VOLUME: + { + int volume = caps->udata.value / 2; + WM8904_SetMute(&snd_dev->wm8904_handle, RT_FALSE, RT_FALSE); + WM8904_SetVolume(&snd_dev->wm8904_handle, volume, volume); + snd_dev->volume = volume; + break; + } + } + + break; + } + case AUDIO_TYPE_OUTPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + struct rt_audio_configure config = caps->udata.config; + i2s_config_t tx_i2s_config; + snd_dev->replay_config.channels = config.channels; + snd_dev->replay_config.samplebits = config.samplebits; + snd_dev->replay_config.samplerate = config.samplerate; + I2S_TxGetDefaultConfig(&tx_i2s_config); + tx_i2s_config.divider = CLOCK_GetPllOutFreq() / config.samplerate / 16 / 2; + I2S_TxInit(I2S_TX, &tx_i2s_config); + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + struct rt_audio_configure config = caps->udata.config; + i2s_config_t tx_i2s_config; + snd_dev->replay_config.samplerate = config.samplerate; + I2S_TxGetDefaultConfig(&tx_i2s_config); + tx_i2s_config.divider = CLOCK_GetPllOutFreq() / config.samplerate / 16 / 2; + I2S_TxInit(I2S_TX, &tx_i2s_config); + break; + } + + default: + result = -RT_ERROR; + break; + } + break; + } + } + + return result; +} + +static rt_size_t lpc_audio_transmit(struct rt_audio_device *audio, const void *writeBuf, void *readBuf, rt_size_t size) +{ + RT_ASSERT(audio != RT_NULL); + i2s_transfer_t transfer; + transfer.data = (uint8_t *)writeBuf; + transfer.dataSize = size; + I2S_TxTransferSendDMA(I2S_TX, &snd_dev.tx_i2s_dma_handle, transfer); + + return RT_EOK; +} + +static void lpc_audio_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + RT_ASSERT(audio != RT_NULL); + /** + * TX_FIFO + * +----------------+----------------+ + * | block1 | block2 | + * +----------------+----------------+ + * \ block_size / + */ + info->buffer = snd_dev.tx_fifo; + info->total_size = TX_FIFO_SIZE; + info->block_size = TX_FIFO_SIZE / 2; + info->block_count = 2; +} + +static struct rt_audio_ops audio_ops = +{ + .getcaps = lpc_audio_getcaps, + .configure = lpc_audio_configure, + .init = lpc_audio_init, + .start = lpc_audio_start, + .stop = lpc_audio_stop, + .transmit = lpc_audio_transmit, + .buffer_info = lpc_audio_buffer_info, +}; + +int rt_hw_sound_init(void) +{ + rt_uint8_t *tx_fifo = RT_NULL; + + tx_fifo = rt_malloc(TX_FIFO_SIZE); + if (tx_fifo == NULL) + { + return -RT_ENOMEM; + } + snd_dev.tx_fifo = tx_fifo; + + /* init default configuration */ + { + snd_dev.replay_config.samplerate = 44100; + snd_dev.replay_config.channels = 2; + snd_dev.replay_config.samplebits = 16; + snd_dev.volume = 30; + } + + snd_dev.audio.ops = &audio_ops; + rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_sound_init); \ No newline at end of file diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.h b/bsp/lpc54114-lite/drivers/audio/drv_sound.h new file mode 100644 index 0000000000..aa997983ae --- /dev/null +++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-17 LiWeiHao First implementation + */ + +#ifndef __DRV_SOUND_H__ +#define __DRV_SOUND_H__ + +#include +#include + +#endif diff --git a/bsp/lpc54114-lite/drivers/audio/fsl_wm8904.c b/bsp/lpc54114-lite/drivers/audio/fsl_wm8904.c new file mode 100755 index 0000000000..91dba2ee81 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/audio/fsl_wm8904.c @@ -0,0 +1,543 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Change Logs: + * Date Author Notes + * 2019-11-09 LiWeiHao Porting to RT-Thread + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "fsl_wm8904.h" +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define WM8904_RESET (0x00) +#define WM8904_ANALOG_ADC_0 (0x0A) +#define WM8904_POWER_MGMT_0 (0x0C) +#define WM8904_POWER_MGMT_2 (0x0E) +#define WM8904_POWER_MGMT_6 (0x12) +#define WM8904_CLK_RATES_0 (0x14) +#define WM8904_CLK_RATES_1 (0x15) +#define WM8904_CLK_RATES_2 (0x16) +#define WM8904_AUDIO_IF_0 (0x18) +#define WM8904_AUDIO_IF_1 (0x19) +#define WM8904_AUDIO_IF_2 (0x1A) +#define WM8904_AUDIO_IF_3 (0x1B) +#define WM8904_DAC_DIG_1 (0x21) +#define WM8904_ANALOG_LEFT_IN_0 (0x2C) +#define WM8904_ANALOG_RIGHT_IN_0 (0x2D) +#define WM8904_ANALOG_LEFT_IN_1 (0x2E) +#define WM8904_ANALOG_RIGHT_IN_1 (0x2F) +#define WM8904_ANALOG_OUT1_LEFT (0x39) +#define WM8904_ANALOG_OUT1_RIGHT (0x3A) +#define WM8904_ANALOG_OUT12_ZC (0x3D) +#define WM8904_DC_SERVO_0 (0x43) +#define WM8904_ANALOG_HP_0 (0x5A) +#define WM8904_CHRG_PUMP_0 (0x62) +#define WM8904_CLS_W_0 (0x68) +#define WM8904_WRT_SEQUENCER_0 (0x6C) +#define WM8904_WRT_SEQUENCER_3 (0x6F) +#define WM8904_WRT_SEQUENCER_4 (0x70) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static status_t WM8904_WaitOnWriteSequencer(wm8904_handle_t *handle); + +static status_t WM8904_WriteRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t value); + +static status_t WM8904_ReadRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t *value); + +static status_t WM8904_ModifyRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t value); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static const uint8_t allRegisters[] = +{ + 0x00, 0x04, 0x05, 0x06, 0x07, 0x0A, 0x0C, 0x0E, 0x0F, 0x12, 0x14, 0x15, 0x16, 0x18, 0x19, 0x1A, 0x1B, + 0x1E, 0x1F, 0x20, 0x21, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x39, + 0x3A, 0x3B, 0x3C, 0x3D, 0x43, 0x44, 0x45, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x5A, 0x5E, 0x62, + 0x68, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, + 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0xC6, 0xF7, 0xF8 +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *config) +{ + status_t result; + + /* reset */ + result = WM8904_WriteRegister(handle, WM8904_RESET, 0x0000); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* MCLK_INV=0, SYSCLK_SRC=0, TOCLK_RATE=0, OPCLK_ENA=1, + * CLK_SYS_ENA=1, CLK_DSP_ENA=1, TOCLK_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x000F); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* WSEQ_ENA=1, WSEQ_WRITE_INDEX=0_0000 */ + result = WM8904_WriteRegister(handle, WM8904_WRT_SEQUENCER_0, 0x0100); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* WSEQ_ABORT=0, WSEQ_START=1, WSEQ_START_INDEX=00_0000 */ + result = WM8904_WriteRegister(handle, WM8904_WRT_SEQUENCER_3, 0x0100); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_WaitOnWriteSequencer(handle); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* TOCLK_RATE_DIV16=0, TOCLK_RATE_x4=1, SR_MODE=0, MCLK_DIV=1 + * (Required for MMCs: SGY, KRT see erratum CE000546) */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_0, 0xA45F); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* INL_ENA=1, INR ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_0, 0x0003); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPL_PGA_ENA=1, HPR_PGA_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_2, 0x0003); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* DACL_ENA=1, DACR_ENA=1, ADCL_ENA=1, ADCR_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_6, 0x000F); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* ADC_OSR128=1 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_ADC_0, 0x0001); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* CLK_SYS_RAT=0101 (512/fs) SAMPLE_RATE=101 (44.1kHz /48kHz) */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_1, 0x1405); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* DACL_DATINV=0, DACR_DATINV=0, DAC_BOOST=00, LOOPBACK=0, AIFADCL_SRC=0, + * AIFADCR_SRC=1, AIFDACL_SRC=0, AIFDACR_SRC=1, ADC_COMP=0, ADC_COMPMODE=0, + * DAC_COMP=0, DAC_COMPMODE=0 */ + result = WM8904_WriteRegister(handle, WM8904_AUDIO_IF_0, 0x0050); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* BCLK_DIR=0 (input), AIF_WL=00 (16-bits) */ + result = WM8904_WriteRegister(handle, WM8904_AUDIO_IF_1, 0x0002); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* OPCLK_DIV=0 (sysclk), BCLK_DIV=0c (sysclk/16) */ + result = WM8904_WriteRegister(handle, WM8904_AUDIO_IF_2, 0x000c); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* LRCLK_DIR=0 (input), LRCLK_RATE=0010_0000_0000 (BCLK / 32) */ + result = WM8904_WriteRegister(handle, WM8904_AUDIO_IF_3, 0x0020); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* DAC_MONO=0, DAC_SB_FILT-0, DAC_MUTERATE=0, DAC_UNMUTE RAMP=0, + * DAC_OSR128=1, DAC_MUTE=0, DEEMPH=0 (none) */ + result = WM8904_WriteRegister(handle, WM8904_DAC_DIG_1, 0x0040); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* INL_CM_ENA=0, L_IP_SEL_N=10, L_IP_SEL_P=01, L_MODE=00 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_LEFT_IN_1, 0x0014); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* INR CM_ENA=0, R_IP_SEL_N=10, R_IP_SEL_P=01, R_MODE=00 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_RIGHT_IN_1, 0x0014); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* LINMUTE=0, LIN_VOL=0_0101 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_LEFT_IN_0, 0x0005); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* RINMUTE=0, RIN VOL=0_0101 LINEOUTL RMV SHORT-1, LINEOUTL ENA_OUTP=1, + * LINEOUTL_ENA_DLY=1, LINEOUTL_ENA=1, LINEOUTR_RMV_SHORT-1, + * LINEOUTR_ENA_OUTP=1 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_RIGHT_IN_0, 0x0005); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPL_BYP_ENA=0, HPR_BYP_ENA=0, LINEOUTL_BYP ENA=0, LINEOUTR_BYP ENA=0 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT12_ZC, 0x0000); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPOUTL_MUTE=0, HPOUT_VU=0, HPOUTLZC=0, HPOUTL_VOL=11_1001 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x0039); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPOUTR_MUTE=0, HPOUT_VU=0, HPOUTRZC=0, HPOUTR_VOL=11_1001 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0x0039); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Enable DC servos for headphone out */ + result = WM8904_WriteRegister(handle, WM8904_DC_SERVO_0, 0x0003); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPL_RMV_SHORT=1, HPL_ENA_OUTP=1, HPL_ENA_DLY=1, HPL_ENA=1, + * HPR_RMV_SHORT=1, HPR_ENA_OUTP=1, HPR_ENA_DLY=1, HPR_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_HP_0, 0x00FF); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* CP_DYN_PWR=1 */ + result = WM8904_WriteRegister(handle, WM8904_CLS_W_0, 0x0001); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* CP_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_CHRG_PUMP_0, 0x0001); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_SetMasterSlave(handle, config->master); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_SetProtocol(handle, config->protocol); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_SetAudioFormat(handle, &(config->format)); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +status_t WM8904_Deinit(wm8904_handle_t *handle) +{ + /* reset */ + return WM8904_WriteRegister(handle, WM8904_RESET, 0x0000); +} + +void WM8904_GetDefaultConfig(wm8904_config_t *config) +{ + memset(config, 0, sizeof(wm8904_config_t)); + + config->master = false; + config->protocol = kWM8904_ProtocolI2S; + config->format.fsRatio = kWM8904_FsRatio64X; + config->format.sampleRate = kWM8904_SampleRate48kHz; + config->format.bitWidth = kWM8904_BitWidth16; +} + +status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master) +{ + if (master) + { + /* only slave currently supported */ + return kStatus_WM8904_Fail; + } + + return kStatus_WM8904_Success; +} + +status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol) +{ + return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 0x0003, (uint16_t)protocol); +} + +status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format) +{ + status_t result; + + /* Disable SYSCLK */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x00); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Set Clock ratio and sample rate */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_1, ((uint32_t)format->fsRatio << 10) | format->sampleRate); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Set bit resolution */ + result = WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 0x000C, (uint16_t)format->bitWidth); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Enable SYSCLK */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x1007); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight) +{ + status_t result; + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x3F, volumeLeft); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0xBF, volumeRight | 0x0080); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight) +{ + status_t result; + uint16_t left = muteLeft ? 0x0100 : 0x0000; + uint16_t right = muteRight ? 0x0100 : 0x0000; + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x0100, left); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0x0180, right | 0x0080); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +status_t WM8904_PrintRegisters(wm8904_handle_t *handle) +{ + status_t result; + uint16_t value; + uint32_t i; + + for (i = 0; i < sizeof(allRegisters); i++) + { + result = WM8904_ReadRegister(handle, allRegisters[i], &value); + if (result != kStatus_WM8904_Success) + { + PRINTF("\r\n"); + return result; + } + PRINTF("%s", ((i % 8) == 0) ? "\r\n" : "\t"); + PRINTF("%02X:%04X", allRegisters[i], value); + } + + PRINTF("\r\n"); + return result; +} + +static status_t WM8904_WaitOnWriteSequencer(wm8904_handle_t *handle) +{ + status_t result; + uint16_t value; + + do + { + result = WM8904_ReadRegister(handle, WM8904_WRT_SEQUENCER_4, &value); + } + while ((result == kStatus_WM8904_Success) && (value & 1)); + + return result; +} + +static status_t WM8904_WriteRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t value) +{ + rt_size_t result; + struct rt_i2c_msg msgs; + uint8_t buffer[3]; + + buffer[0] = reg; + buffer[1] = (value >> 8U) & 0xFFU; + buffer[2] = value & 0xFFU; + + msgs.addr = WM8904_I2C_ADDRESS; + msgs.flags = RT_I2C_WR; + msgs.buf = buffer; + msgs.len = sizeof(buffer); + + result = rt_i2c_transfer(handle->i2c, &msgs, 1); + if (result == 1) + { + return kStatus_WM8904_Success; + } + else + { + return kStatus_WM8904_Fail; + } +} + +static status_t WM8904_ReadRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t *value) +{ + rt_size_t result; + struct rt_i2c_msg msgs[2]; + uint8_t buffer[2] = {0}; + uint8_t write_buffer; + + *value = 0x0000U; + + write_buffer = reg; + msgs[0].addr = WM8904_I2C_ADDRESS; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = &write_buffer; + msgs[0].len = 1; + + msgs[1].addr = WM8904_I2C_ADDRESS; + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = buffer; + msgs[1].len = 2; + + result = rt_i2c_transfer(handle->i2c, msgs, 2); + if (result != 2) + { + return kStatus_WM8904_Fail; + } + + *value = (uint16_t)((((uint32_t)buffer[0]) << 8U) | ((uint32_t)buffer[1])); + + return kStatus_WM8904_Success; +} + +static status_t WM8904_ModifyRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t value) +{ + status_t result; + uint16_t regValue; + + result = WM8904_ReadRegister(handle, reg, ®Value); + if (result != kStatus_WM8904_Success) + { + return result; + } + + regValue &= (uint16_t)~mask; + regValue |= value; + + return WM8904_WriteRegister(handle, reg, regValue); +} diff --git a/bsp/lpc54114-lite/drivers/audio/fsl_wm8904.h b/bsp/lpc54114-lite/drivers/audio/fsl_wm8904.h new file mode 100755 index 0000000000..4ea20a2a07 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/audio/fsl_wm8904.h @@ -0,0 +1,247 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Change Logs: + * Date Author Notes + * 2019-11-09 LiWeiHao Porting to RT-Thread + */ + +#ifndef _FSL_WM8904_H_ +#define _FSL_WM8904_H_ + +#include "fsl_common.h" +#include "rtdevice.h" +#include "rtthread.h" + +/*! + * @addtogroup wm8904 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief WM8904 I2C address. */ +#define WM8904_I2C_ADDRESS (0x1A) + +/*! @brief WM8904 I2C bit rate. */ +#define WM8904_I2C_BITRATE (400000U) + +/*! @brief WM8904 status return codes. */ +enum _wm8904_status +{ + kStatus_WM8904_Success = 0x0, /*!< Success */ + kStatus_WM8904_Fail = 0x1 /*!< Failure */ +}; + +/*! @brief The audio data transfer protocol. */ +typedef enum _wm8904_protocol +{ + kWM8904_ProtocolRightJustified = 0x0, /*!< Right justified mode */ + kWM8904_ProtocolLeftJustified = 0x1, /*!< Left justified mode */ + kWM8904_ProtocolI2S = 0x2, /*!< I2S mode */ + kWM8904_ProtocolDSP = 0x3 /*!< DSP mode */ +} wm8904_protocol_t; + +/*! @brief The SYSCLK / fs ratio. */ +typedef enum _wm8904_fs_ratio +{ + kWM8904_FsRatio64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */ + kWM8904_FsRatio128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */ + kWM8904_FsRatio192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */ + kWM8904_FsRatio256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */ + kWM8904_FsRatio384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */ + kWM8904_FsRatio512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */ + kWM8904_FsRatio768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */ + kWM8904_FsRatio1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */ + kWM8904_FsRatio1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */ + kWM8904_FsRatio1536X = 0x9 /*!< SYSCLK is 1536 * sample rate * frame width */ +} wm8904_fs_ratio_t; + +/*! @brief Sample rate. */ +typedef enum _wm8904_sample_rate +{ + kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */ + kWM8904_SampleRate12kHz = 0x1, /*!< 11.025kHz, 12kHz */ + kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */ + kWM8904_SampleRate24kHz = 0x3, /*!< 22.05kHz, 24kHz */ + kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */ + kWM8904_SampleRate48kHz = 0x5 /*!< 44.1kHz, 48kHz */ +} wm8904_sample_rate_t; + +/*! @brief Bit width. */ +typedef enum _wm8904_bit_width +{ + kWM8904_BitWidth16 = 0x0, /*!< 16 bits */ + kWM8904_BitWidth20 = 0x1, /*!< 20 bits */ + kWM8904_BitWidth24 = 0x2, /*!< 24 bits */ + kWM8904_BitWidth32 = 0x3 /*!< 32 bits */ +} wm8904_bit_width_t; + +/*! @brief Audio format configuration. */ +typedef struct _wm8904_audio_format +{ + wm8904_fs_ratio_t fsRatio; /*!< SYSCLK / fs ratio */ + wm8904_sample_rate_t sampleRate; /*!< Sample rate */ + wm8904_bit_width_t bitWidth; /*!< Bit width */ +} wm8904_audio_format_t; + +/*! @brief WM8904 data. */ +typedef struct _wm8904_handle +{ + struct rt_i2c_bus_device *i2c; /*!< Configured I2C instance */ +} wm8904_handle_t; + +/*! @brief Configuration structure of WM8904. */ +typedef struct _wm8904_config +{ + bool master; /*!< Master or slave */ + wm8904_protocol_t protocol; /*!< Audio transfer protocol */ + wm8904_audio_format_t format; /*!< Audio format */ +} wm8904_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" +{ +#endif + +/*! +* @brief Initializes WM8904. +* +* @param handle WM8904 handle structure. +* @param codec_config WM8904 configuration structure. +*/ +status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *config); + +/*! +* @brief Deinitializes the WM8904 codec. +* +* This function resets WM8904. +* +* @param handle WM8904 handle structure. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_Deinit(wm8904_handle_t *handle); + +/*! +* @brief Fills the configuration structure with default values. +* +* The default values are: +* +* master = false; +* protocol = kWM8904_ProtocolI2S; +* format.fsRatio = kWM8904_FsRatio64X; +* format.sampleRate = kWM8904_SampleRate48kHz; +* format.bitWidth = kWM8904_BitWidth16; +* +* @param handle WM8904 handle structure to be filled with default values. +*/ +void WM8904_GetDefaultConfig(wm8904_config_t *config); + +/*! +* @brief Sets WM8904 as master or slave. +* +* @param handle WM8904 handle structure. +* @param master true for master, false for slave. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master); + +/*! +* @brief Sets the audio data transfer protocol. +* +* @param handle WM8904 handle structure. +* @param protocol Audio transfer protocol. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol); + +/*! +* @brief Sets the audio data format. +* +* @param handle WM8904 handle structure. +* @param format Audio format parameters. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format); + +/*! +* @brief Sets the headphone output volume. +* +* The parameter should be from 0 to 63. +* The resulting volume will be (parameter - 57 dB). +* 0 for -57 dB, 57 for 0 dB, 63 for +6 dB etc. +* +* @param handle WM8904 handle structure. +* @param volumeLeft Volume of the left channel. +* @param volumeRight Volume of the right channel. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight); + +/*! +* @brief Sets the headphone output mute. +* +* @param handle WM8904 handle structure. +* @param muteLeft true to mute left channel, false to unmute. +* @param muteRight true to mute right channel, false to unmute. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight); + +/*! +* @brief Reads content of all WM8904 registers and prints it to debug console. +* +* @param handle WM8904 handle structure. +* +* @return kStatus_WM8904_Success if successful, different code otherwise. +*/ +status_t WM8904_PrintRegisters(wm8904_handle_t *handle); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_WM8904_H_ */ diff --git a/bsp/stm32/docs/STM32系列外设驱动添加指南.md b/bsp/stm32/docs/STM32系列外设驱动添加指南.md index 41ffcecd58..48369f1d59 100644 --- a/bsp/stm32/docs/STM32系列外设驱动添加指南.md +++ b/bsp/stm32/docs/STM32系列外设驱动添加指南.md @@ -95,6 +95,7 @@ | 10 | Watchdog | **开启该外设** | | 11 | EMAC | **配置 ETH 外设的工作模式（一般为 RMII 模式）** | | 12 | SDRAM | **需要根据板载的 SDRAM 型号配置片选脚，地址线，数据线等** | +| 13 | SDIO | **开启该外设，配置引脚（或者使用默认引脚），SDIO会改变时钟结构，故需重新配置时钟并修改board.c** | ### 5.3 复杂外设配置说明 diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h index 2fefa1344c..6c5b7c840d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h @@ -133,6 +133,29 @@ extern "C" { #endif /* UART5_DMA_RX_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = USART6, \ + .irq_type = USART6_IRQn, \ + } +#endif /* UART6_CONFIG */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .dma_rcc = UART6_RX_DMA_RCC, \ + .dma_irq = UART6_RX_DMA_IRQ, \ + } +#endif /* UART6_DMA_RX_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h index 0c16ccd066..c86148bf7d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h @@ -7,6 +7,7 @@ * Date Author Notes * 2019-01-05 zylx first version * 2019-01-08 SummerGift clean up the code + * 2019-12-01 armink add DMAMUX support */ #ifndef __DMA_CONFIG_H__ @@ -25,7 +26,11 @@ extern "C" { #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 +#if defined(DMAMUX1) /* for L4+ */ +#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX +#else /* for L4 */ #define SPI1_RX_DMA_REQUEST DMA_REQUEST_1 +#endif /* DMAMUX1 */ #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn #endif @@ -34,13 +39,21 @@ extern "C" { #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 +#if defined(DMAMUX1) /* for L4+ */ +#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX +#else /* for L4 */ #define SPI1_TX_DMA_REQUEST DMA_REQUEST_1 +#endif /* DMAMUX1 */ #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) #define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART3_RX_DMA_INSTANCE DMA1_Channel3 +#if defined(DMAMUX1) /* for L4+ */ +#define UART3_RX_DMA_REQUEST DMA_REQUEST_USART3_RX +#else /* for L4 */ #define UART3_RX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn #endif @@ -49,13 +62,21 @@ extern "C" { #define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART1_TX_DMA_INSTANCE DMA1_Channel4 +#if defined(DMAMUX1) /* for L4+ */ +#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX +#else /* for L4 */ #define UART1_TX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn #elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 +#if defined(DMAMUX1) /* for L4+ */ +#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX +#else /* for L4 */ #define SPI2_RX_DMA_REQUEST DMA_REQUEST_1 +#endif /* DMAMUX1 */ #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn #endif @@ -64,19 +85,31 @@ extern "C" { #define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART1_RX_DMA_INSTANCE DMA1_Channel5 +#if defined(DMAMUX1) /* for L4+ */ +#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX +#else /* for L4 */ #define UART1_RX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) #define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler #define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN #define QSPI_DMA_INSTANCE DMA1_Channel5 +#if defined(DMAMUX1) /* for L4+ */ +#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1 +#else /* for L4 */ #define QSPI_DMA_REQUEST DMA_REQUEST_5 +#endif /* DMAMUX1 */ #define QSPI_DMA_IRQ DMA1_Channel5_IRQn #elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 +#if defined(DMAMUX1) /* for L4+ */ +#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX +#else /* for L4 */ #define SPI2_TX_DMA_REQUEST DMA_REQUEST_1 +#endif /* DMAMUX1 */ #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn #endif @@ -85,7 +118,11 @@ extern "C" { #define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define UART2_RX_DMA_INSTANCE DMA1_Channel6 +#if defined(DMAMUX1) /* for L4+ */ +#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX +#else /* for L4 */ #define UART2_RX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn #endif @@ -96,7 +133,11 @@ extern "C" { #define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler #define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART5_TX_DMA_INSTANCE DMA2_Channel1 +#if defined(DMAMUX1) /* for L4+ */ +#define UART5_TX_DMA_REQUEST DMA_REQUEST_UART5_TX +#else /* for L4 */ #define UART5_TX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn #endif @@ -105,7 +146,11 @@ extern "C" { #define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART5_RX_DMA_INSTANCE DMA2_Channel2 +#if defined(DMAMUX1) /* for L4+ */ +#define UART5_RX_DMA_REQUEST DMA_REQUEST_UART5_RX +#else /* for L4 */ #define UART5_RX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn #endif @@ -114,7 +159,11 @@ extern "C" { #define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_RX_DMA_INSTANCE DMA2_Channel3 +#if defined(DMAMUX1) /* for L4+ */ +#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX +#else /* for L4 */ #define SPI1_RX_DMA_REQUEST DMA_REQUEST_4 +#endif /* DMAMUX1 */ #define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn #endif @@ -123,7 +172,11 @@ extern "C" { #define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_TX_DMA_INSTANCE DMA2_Channel4 +#if defined(DMAMUX1) /* for L4+ */ +#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX +#else /* for L4 */ #define SPI1_TX_DMA_REQUEST DMA_REQUEST_4 +#endif /* DMAMUX1 */ #define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn #endif @@ -134,7 +187,11 @@ extern "C" { #define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART1_TX_DMA_INSTANCE DMA2_Channel6 +#if defined(DMAMUX1) /* for L4+ */ +#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX +#else /* for L4 */ #define UART1_TX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn #endif @@ -143,19 +200,31 @@ extern "C" { #define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define UART1_RX_DMA_INSTANCE DMA2_Channel7 +#if defined(DMAMUX1) /* for L4+ */ +#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX +#else /* for L4 */ #define UART1_RX_DMA_REQUEST DMA_REQUEST_2 +#endif /* DMAMUX1 */ #define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) #define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN #define QSPI_DMA_INSTANCE DMA2_Channel7 +#if defined(DMAMUX1) /* for L4+ */ +#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1 +#else /* for L4 */ #define QSPI_DMA_REQUEST DMA_REQUEST_3 +#endif /* DMAMUX1 */ #define QSPI_DMA_IRQ DMA2_Channel7_IRQn #elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE) #define LPUART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler #define LPUART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define LPUART1_RX_DMA_INSTANCE DMA2_Channel7 +#if defined(DMAMUX1) /* for L4+ */ +#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX +#else /* for L4 */ #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_4 +#endif /* DMAMUX1 */ #define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c index 2f724de718..00f84711f5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c @@ -270,7 +270,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); static int fal_flash_erase(long offset, size_t size); -const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, 2048, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} }; +const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} }; static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c index 365d64aff4..7418d6f50c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c @@ -22,7 +22,7 @@ !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1) #error "Please define at least one BSP_USING_UARTx" - /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif #ifdef RT_SERIAL_USING_DMA @@ -749,6 +749,12 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); + +#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1) + /* enable DMAMUX clock for L4+ and G4 */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); +#endif + #endif UNUSED(tmpreg); /* To avoid compiler warnings */ } diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c index 79cb327ed8..19e8d7f3d4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c @@ -239,11 +239,27 @@ const static struct udcd_ops _udc_ops = _wakeup, }; +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops _ops = +{ + _init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; +#endif + int stm_usbd_register(void) { rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd)); _stm_udc.parent.type = RT_Device_Class_USBDevice; +#ifdef RT_USING_DEVICE_OPS + _stm_udc.parent.ops = &_ops; +#else _stm_udc.parent.init = _init; +#endif _stm_udc.parent.user_data = &_stm_pcd; _stm_udc.ops = &_udc_ops; /* Register endpoint infomation */ diff --git a/bsp/stm32/stm32f103-dofly-M3S/.cproject b/bsp/stm32/stm32f103-dofly-M3S/.cproject index a297a256c5..3dceacb108 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/.cproject +++ b/bsp/stm32/stm32f103-dofly-M3S/.cproject @@ -126,7 +126,7 @@ - + diff --git a/bsp/stm32/stm32f103-yf-ufun/.cproject b/bsp/stm32/stm32f103-yf-ufun/.cproject index 87b276da10..b37a91bc57 100644 --- a/bsp/stm32/stm32f103-yf-ufun/.cproject +++ b/bsp/stm32/stm32f103-yf-ufun/.cproject @@ -125,7 +125,7 @@ - + diff --git a/bsp/stm32/stm32f401-st-nucleo/.cproject b/bsp/stm32/stm32f401-st-nucleo/.cproject index 136b17e0cf..194d91778d 100644 --- a/bsp/stm32/stm32f401-st-nucleo/.cproject +++ b/bsp/stm32/stm32f401-st-nucleo/.cproject @@ -127,7 +127,7 @@ - + diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/.cproject b/bsp/stm32/stm32f405-smdz-breadfruit/.cproject index d89256003d..1742bda37c 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/.cproject +++ b/bsp/stm32/stm32f405-smdz-breadfruit/.cproject @@ -1,155 +1,155 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-atk-explorer/.cproject b/bsp/stm32/stm32f407-atk-explorer/.cproject index f6703346e2..ca7e2cbe65 100644 --- a/bsp/stm32/stm32f407-atk-explorer/.cproject +++ b/bsp/stm32/stm32f407-atk-explorer/.cproject @@ -128,7 +128,7 @@ - + diff --git a/bsp/stm32/stm32f411-st-nucleo/.cproject b/bsp/stm32/stm32f411-st-nucleo/.cproject index a4d6a43489..541ca5a624 100644 --- a/bsp/stm32/stm32f411-st-nucleo/.cproject +++ b/bsp/stm32/stm32f411-st-nucleo/.cproject @@ -127,7 +127,7 @@ - + diff --git a/bsp/stm32/stm32f427-robomaster-a/README.md b/bsp/stm32/stm32f427-robomaster-a/README.md index 60984270dc..9b288d5048 100644 --- a/bsp/stm32/stm32f427-robomaster-a/README.md +++ b/bsp/stm32/stm32f427-robomaster-a/README.md @@ -37,7 +37,7 @@ RoboMaster开发板套件是一款面向机器人DIY的开源主控套件。开 | **板载外设** | **支持情况** | **备注** | | :----------------- | :----------: | :------------------------------------- | -| SD卡 | 暂不支持 | | +| SD卡 | 支持 | | | CAN | 支持 | 需通过24vXT30接口或usb接口供电 | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | diff --git a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/.mxproject index 24e8a91ddd..48bd0f0394 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/.mxproject @@ -5,10 +5,10 @@ SourcePath=F:/rt-thread/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;gpio.c;spi.c;usart.c; [PreviousLibFiles] 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[PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F427xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/CubeMX_Config.ioc index cc0c04b90a..14cf6a3273 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/CubeMX_Config.ioc @@ -8,59 +8,66 @@ KeepUserPlacement=true Mcu.Family=STM32F4 Mcu.IP0=CAN1 Mcu.IP1=CAN2 -Mcu.IP10=UART8 -Mcu.IP11=USART1 -Mcu.IP12=USART3 -Mcu.IP13=USART6 +Mcu.IP10=UART7 +Mcu.IP11=UART8 +Mcu.IP12=USART1 +Mcu.IP13=USART3 +Mcu.IP14=USART6 Mcu.IP2=NVIC Mcu.IP3=RCC -Mcu.IP4=SPI5 -Mcu.IP5=SYS -Mcu.IP6=TIM4 -Mcu.IP7=TIM5 -Mcu.IP8=TIM12 -Mcu.IP9=UART7 -Mcu.IPNb=14 +Mcu.IP4=SDIO +Mcu.IP5=SPI5 +Mcu.IP6=SYS +Mcu.IP7=TIM4 +Mcu.IP8=TIM5 +Mcu.IP9=TIM12 +Mcu.IPNb=15 Mcu.Name=STM32F427I(G-I)Hx Mcu.Package=UFBGA176 Mcu.Pin0=PE1 Mcu.Pin1=PE0 -Mcu.Pin10=PI0 -Mcu.Pin11=PH0/OSC_IN -Mcu.Pin12=PH1/OSC_OUT -Mcu.Pin13=PF7 -Mcu.Pin14=PF6 -Mcu.Pin15=PH12 -Mcu.Pin16=PF9 -Mcu.Pin17=PF8 -Mcu.Pin18=PH11 -Mcu.Pin19=PH10 +Mcu.Pin10=PC10 +Mcu.Pin11=PG9 +Mcu.Pin12=PD1 +Mcu.Pin13=PD2 +Mcu.Pin14=PI0 +Mcu.Pin15=PC9 +Mcu.Pin16=PH0/OSC_IN +Mcu.Pin17=PC8 +Mcu.Pin18=PH1/OSC_OUT +Mcu.Pin19=PF7 Mcu.Pin2=PG14 -Mcu.Pin20=PD15 -Mcu.Pin21=PH6 -Mcu.Pin22=PD14 -Mcu.Pin23=PD13 -Mcu.Pin24=PD12 -Mcu.Pin25=PE8 -Mcu.Pin26=PE11 -Mcu.Pin27=PB12 -Mcu.Pin28=PB13 -Mcu.Pin29=PD9 -Mcu.Pin3=PA14 -Mcu.Pin30=PD8 -Mcu.Pin31=PF14 -Mcu.Pin32=PE7 -Mcu.Pin33=VP_SYS_VS_Systick -Mcu.Pin34=VP_TIM4_VS_ClockSourceINT -Mcu.Pin35=VP_TIM5_VS_ClockSourceINT -Mcu.Pin36=VP_TIM12_VS_ClockSourceINT -Mcu.Pin4=PA13 -Mcu.Pin5=PB7 -Mcu.Pin6=PB6 -Mcu.Pin7=PD0 -Mcu.Pin8=PG9 -Mcu.Pin9=PD1 -Mcu.PinsNb=37 +Mcu.Pin20=PF6 +Mcu.Pin21=PH12 +Mcu.Pin22=PF9 +Mcu.Pin23=PF8 +Mcu.Pin24=PH11 +Mcu.Pin25=PH10 +Mcu.Pin26=PD15 +Mcu.Pin27=PH6 +Mcu.Pin28=PD14 +Mcu.Pin29=PD13 +Mcu.Pin3=PC12 +Mcu.Pin30=PD12 +Mcu.Pin31=PE8 +Mcu.Pin32=PE11 +Mcu.Pin33=PB12 +Mcu.Pin34=PB13 +Mcu.Pin35=PD9 +Mcu.Pin36=PD8 +Mcu.Pin37=PF14 +Mcu.Pin38=PE7 +Mcu.Pin39=VP_SYS_VS_Systick +Mcu.Pin4=PA14 +Mcu.Pin40=VP_TIM4_VS_ClockSourceINT +Mcu.Pin41=VP_TIM5_VS_ClockSourceINT +Mcu.Pin42=VP_TIM12_VS_ClockSourceINT +Mcu.Pin5=PA13 +Mcu.Pin6=PB7 +Mcu.Pin7=PB6 +Mcu.Pin8=PD0 +Mcu.Pin9=PC11 +Mcu.PinsNb=43 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F427IIHx @@ -93,6 +100,16 @@ PB6.Signal=USART1_TX PB7.Locked=true PB7.Mode=Asynchronous PB7.Signal=USART1_RX +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Line=STM32F427/437 PCC.MCU=STM32F427I(G-I)Hx @@ -114,6 +131,8 @@ PD14.Locked=true PD14.Signal=S_TIM4_CH3 PD15.Locked=true PD15.Signal=S_TIM4_CH4 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD PD8.Locked=true PD8.Mode=Asynchronous PD8.Signal=USART3_TX @@ -194,7 +213,7 @@ ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_SPI5_Init-SPI5-false-HAL-true,4-MX_USART6_UART_Init-USART6-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_CAN2_Init-CAN2-false-HAL-true,7-MX_TIM4_Init-TIM4-false-HAL-true,8-MX_TIM5_Init-TIM5-false-HAL-true,9-MX_TIM12_Init-TIM12-false-HAL-true,10-MX_UART7_Init-UART7-false-HAL-true,11-MX_UART8_Init-UART8-false-HAL-true,12-MX_USART1_UART_Init-USART1-false-HAL-true,13-MX_USART3_UART_Init-USART3-false-HAL-true -RCC.48MHZClocksFreq_Value=90000000 +RCC.48MHZClocksFreq_Value=45000000 RCC.AHBFreq_Value=180000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 RCC.APB1Freq_Value=45000000 @@ -210,14 +229,15 @@ RCC.HCLKFreq_Value=180000000 RCC.HSE_VALUE=12000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=192000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 RCC.MCO2PinFreq_Value=180000000 RCC.PLLCLKFreq_Value=180000000 RCC.PLLM=6 RCC.PLLN=180 -RCC.PLLQCLKFreq_Value=90000000 +RCC.PLLQ=8 +RCC.PLLQCLKFreq_Value=45000000 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.RTCFreq_Value=32000 RCC.RTCHSEDivFreq_Value=6000000 diff --git a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 4381f2c799..059668d214 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -58,7 +58,7 @@ /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED diff --git a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/main.c index 9a25813ef9..0a4607049f 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/main.c @@ -65,6 +65,8 @@ CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; +SD_HandleTypeDef hsd; + SPI_HandleTypeDef hspi5; TIM_HandleTypeDef htim4; @@ -95,6 +97,7 @@ static void MX_UART7_Init(void); static void MX_UART8_Init(void); static void MX_USART1_UART_Init(void); static void MX_USART3_UART_Init(void); +static void MX_SDIO_SD_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -144,6 +147,7 @@ int main(void) MX_UART8_Init(); MX_USART1_UART_Init(); MX_USART3_UART_Init(); + MX_SDIO_SD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -181,7 +185,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 6; RCC_OscInitStruct.PLL.PLLN = 180; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -281,6 +285,42 @@ static void MX_CAN2_Init(void) } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + /** * @brief SPI5 Initialization Function * @param None @@ -690,6 +730,7 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); diff --git a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 2871a66949..19b391828c 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -222,6 +222,91 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) } +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC12 ------> SDIO_CK + PC11 ------> SDIO_D3 + PC10 ------> SDIO_D2 + PD2 ------> SDIO_CMD + PC9 ------> SDIO_D1 + PC8 ------> SDIO_D0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + |GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC12 ------> SDIO_CK + PC11 ------> SDIO_D3 + PC10 ------> SDIO_D2 + PD2 ------> SDIO_CMD + PC9 ------> SDIO_D1 + PC8 ------> SDIO_D0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + |GPIO_PIN_8); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + /** * @brief SPI MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32f427-robomaster-a/board/Kconfig b/bsp/stm32/stm32f427-robomaster-a/board/Kconfig index e5b9236f3c..1d7a7aa9d8 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/Kconfig +++ b/bsp/stm32/stm32f427-robomaster-a/board/Kconfig @@ -8,6 +8,12 @@ config SOC_STM32F427II default y menu "Onboard Peripheral Drivers" + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n endmenu menu "On-chip Peripheral Drivers" @@ -76,6 +82,12 @@ menu "On-chip Peripheral Drivers" default n endif + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + menuconfig BSP_USING_PWM bool "Enable pwm" default n diff --git a/bsp/stm32/stm32f427-robomaster-a/board/SConscript b/bsp/stm32/stm32f427-robomaster-a/board/SConscript index 2a6e178312..7d5ac61de8 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/SConscript +++ b/bsp/stm32/stm32f427-robomaster-a/board/SConscript @@ -12,6 +12,9 @@ board.c CubeMX_Config/Src/stm32f4xx_hal_msp.c ''') +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.c b/bsp/stm32/stm32f427-robomaster-a/board/board.c index c4c3f77432..a0901feba9 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/board.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/board.c @@ -32,7 +32,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 6; RCC_OscInitStruct.PLL.PLLN = 180; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); diff --git a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c new file mode 100644 index 0000000000..b46537d311 --- /dev/null +++ b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include +#include + +#define DBG_TAG "app.card" +#define DBG_LVL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif + diff --git a/bsp/stm32/stm32f429-atk-apollo/.cproject b/bsp/stm32/stm32f429-atk-apollo/.cproject index debeccd6e6..e561b1f4eb 100644 --- a/bsp/stm32/stm32f429-atk-apollo/.cproject +++ b/bsp/stm32/stm32f429-atk-apollo/.cproject @@ -128,7 +128,7 @@ - + diff --git a/bsp/stm32/stm32f429-fire-challenger/.cproject b/bsp/stm32/stm32f429-fire-challenger/.cproject index 0b00ab595f..5c47f8b9b4 100644 --- a/bsp/stm32/stm32f429-fire-challenger/.cproject +++ b/bsp/stm32/stm32f429-fire-challenger/.cproject @@ -128,7 +128,7 @@ - + diff --git a/bsp/stm32/stm32f767-atk-apollo/.cproject b/bsp/stm32/stm32f767-atk-apollo/.cproject index 0ffe335a9f..6851f72111 100644 --- a/bsp/stm32/stm32f767-atk-apollo/.cproject +++ b/bsp/stm32/stm32f767-atk-apollo/.cproject @@ -128,7 +128,7 @@ - + diff --git a/bsp/stm32/stm32l475-atk-pandora/.cproject b/bsp/stm32/stm32l475-atk-pandora/.cproject index 21239afcbd..d97eb3fc3e 100644 --- a/bsp/stm32/stm32l475-atk-pandora/.cproject +++ b/bsp/stm32/stm32l475-atk-pandora/.cproject @@ -127,7 +127,7 @@ - + diff --git a/bsp/x1000/SConstruct b/bsp/x1000/SConstruct index 053d160121..4b71cda8b1 100644 --- a/bsp/x1000/SConstruct +++ b/bsp/x1000/SConstruct @@ -28,7 +28,7 @@ Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True) if GetDepend('RT_USING_HARD_FLOAT'): env['CCFLAGS'] = env['CCFLAGS'].replace('-msoft-float', '-mhard-float') diff --git a/bsp/x1000/cpu/SConscript b/bsp/x1000/cpu/SConscript new file mode 100644 index 0000000000..640e46a4fb --- /dev/null +++ b/bsp/x1000/cpu/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/mips/x1000/SConscript b/bsp/x1000/cpu/common/SConscript similarity index 100% rename from libcpu/mips/x1000/SConscript rename to bsp/x1000/cpu/common/SConscript diff --git a/bsp/x1000/cpu/common/asm.h b/bsp/x1000/cpu/common/asm.h new file mode 100644 index 0000000000..190e8b110e --- /dev/null +++ b/bsp/x1000/cpu/common/asm.h @@ -0,0 +1,220 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * Some useful macros for MIPS assembler code + * + * Some of the routines below contain useless nops that will be optimized + * away by gas in -O mode. These nops are however required to fill delay + * slots in noreorder mode. + */ +#ifndef __ASM_H__ +#define __ASM_H__ + +/* + * LEAF - declare leaf routine + */ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp,0,ra + +/* + * NESTED - declare nested routine entry point + */ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp, framesize, rpc + +/* + * END - mark end of function + */ +#define END(function) \ + .end function; \ + .size function,.-function + +/* + * EXPORT - export definition of symbol + */ +#define EXPORT(symbol) \ + .globl symbol; \ +symbol: + +/* + * FEXPORT - export definition of a function symbol + */ +#define FEXPORT(symbol) \ + .globl symbol; \ + .type symbol,@function; \ +symbol: + +/* + * Global data declaration with size. + */ +#define EXPORTS(name,sz) \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ +name: + +/* + * Weak data declaration with size. + */ +#define WEXPORT(name,sz) \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ +name: + +/* + * Global data reference with size. + */ +#define IMPORT(name, size) \ + .extern name,size + +/* + * Global zeroed data. + */ +#define BSS(name,size) \ + .type name,@object; \ + .comm name,size + +/* + * Local zeroed data. + */ +#define LBSS(name,size) \ + .lcomm name,size + + +/* + * ABS - export absolute symbol + */ +#define ABS(symbol,value) \ + .globl symbol; \ +symbol = value + + +#define TEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg; \ + .popsection; + + +#define ENTRY(name) \ + .globl name; \ + .align 2; \ + .ent name,0; \ + name##: + +/* + * Macros to handle different pointer/register sizes for 32/64-bit code + */ + +/* + * Size of a register + */ +#define SZREG 4 + + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define REG_S sw +#define REG_L lw +#define REG_SUBU subu +#define REG_ADDU addu + + +/* + * How to add/sub/load/store/shift C int variables. + */ +#define INT_ADD add +#define INT_ADDU addu +#define INT_ADDI addi +#define INT_ADDIU addiu +#define INT_SUB sub +#define INT_SUBU subu +#define INT_L lw +#define INT_S sw +#define INT_SLL sll +#define INT_SLLV sllv +#define INT_SRL srl +#define INT_SRLV srlv +#define INT_SRA sra +#define INT_SRAV srav + + + +/* + * How to add/sub/load/store/shift C long variables. + */ +#define LONG_ADD add +#define LONG_ADDU addu +#define LONG_ADDI addi +#define LONG_ADDIU addiu +#define LONG_SUB sub +#define LONG_SUBU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav + +#define LONG .word +#define LONGSIZE 4 +#define LONGMASK 3 +#define LONGLOG 2 + + + +/* + * How to add/sub/load/store/shift pointers. + */ +#define PTR_ADD add +#define PTR_ADDU addu +#define PTR_ADDI addi +#define PTR_ADDIU addiu +#define PTR_SUB sub +#define PTR_SUBU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_LA la +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav + +#define PTR_SCALESHIFT 2 + +#define PTR .word +#define PTRSIZE 4 +#define PTRLOG 2 + + +/* + * Some cp0 registers were extended to 64bit for MIPS III. + */ +#define MFC0 mfc0 +#define MTC0 mtc0 + + +#define SSNOP sll zero, zero, 1 + +#endif /* end of __ASM_H__ */ diff --git a/bsp/x1000/cpu/common/exception.h b/bsp/x1000/cpu/common/exception.h new file mode 100644 index 0000000000..2cb03d20e7 --- /dev/null +++ b/bsp/x1000/cpu/common/exception.h @@ -0,0 +1,166 @@ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#ifndef __EXCEPTION_H__ +#define __EXCEPTION_H__ + + +/* + * important register numbers + */ +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 + +/* + * Stack layout for the GDB exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ +#define NUMREGS 90 + +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ + +///* +// * Saved floating point registers +// */ +//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ +// +//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ +// +//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ +// +///* +// * Again, CP0 registers +// */ +//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ +#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ + +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ + +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + +/* + * This is the same as above, but for the high-level + * part of the INT stub. + */ +typedef struct pt_regs_s +{ + /* Saved main processor registers. */ + rt_base_t regs[32]; + /* Saved special registers. */ + rt_base_t cp0_status; + rt_base_t hi; + rt_base_t lo; + rt_base_t cp0_badvaddr; + rt_base_t cp0_cause; + rt_base_t cp0_epc; +} pt_regs_t; + +typedef void (* exception_func_t)(pt_regs_t *regs); + +extern exception_func_t sys_exception_handlers[]; +exception_func_t rt_set_except_vector(int n, exception_func_t func); +void install_default_execpt_handle(void); + +#endif /* end of __EXCEPTION_H__ */ diff --git a/bsp/x1000/cpu/common/mips.h b/bsp/x1000/cpu/common/mips.h new file mode 100644 index 0000000000..a4bc74a050 --- /dev/null +++ b/bsp/x1000/cpu/common/mips.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-09-07 Urey first version + */ + +#ifndef _COMMON_MIPS_H_ +#define _COMMON_MIPS_H_ + +#include "mips_cfg.h" + +#include "mips_types.h" +#include "mips_asm.h" +#include "mips_def.h" +#include "mips_regs.h" +#include "mips_addrspace.h" +#include "mips_cache.h" +#include "mips_context.h" +#include "mips_excpt.h" + +#endif /* _COMMON_MIPS_H_ */ diff --git a/bsp/x1000/cpu/common/mips.inc b/bsp/x1000/cpu/common/mips.inc new file mode 100644 index 0000000000..a4cd55911e --- /dev/null +++ b/bsp/x1000/cpu/common/mips.inc @@ -0,0 +1,52 @@ +/* + * File : mips.inc + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 sangwei first version + */ +#ifndef __MIPS_INC__ +#define __MIPS_INC__ + +#define zero $0 /* wired zero */ +// #define at $1 +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ + +#endif /* end of __MIPS_INC__ */ diff --git a/bsp/x1000/cpu/common/mips_addrspace.h b/bsp/x1000/cpu/common/mips_addrspace.h new file mode 100644 index 0000000000..3b82a4e371 --- /dev/null +++ b/bsp/x1000/cpu/common/mips_addrspace.h @@ -0,0 +1,207 @@ +/* + * File : mips_addrspace.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2016912 Urey the first version + */ + +#ifndef _MIPS_ADDRSPACE_H_ +#define _MIPS_ADDRSPACE_H_ + + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ATYPE_ +#define _ATYPE32_ +#define _ATYPE64_ +#define _CONST64_(x) x +#else +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 +#ifdef CONFIG_64BIT +#define _CONST64_(x) x ## L +#else +#define _CONST64_(x) x ## LL +#endif +#endif + +/* + * 32-bit MIPS address spaces + */ +#ifdef __ASSEMBLY__ +#define _ACAST32_ +#define _ACAST64_ +#else +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#endif + +/* + * Returns the kernel segment base of a given address + */ +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) + +/* + * Returns the physical address of a CKSEGx / XKPHYS address + */ +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) + +#ifdef CONFIG_64BIT + +/* + * Memory segments (64bit kernel mode addresses) + * The compatibility segments use the full 64-bit sign extended value. Note + * the R8000 doesn't have them so don't reference these in generic MIPS code. + */ +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) + +#else + +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) + +/* + * Map an address to a certain kernel segment + */ +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) + +/* + * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. + */ +//#define KUSEGBASE 0x00000000 +//#define KSEG0BASE 0x80000000 +//#define KSEG1BASE 0xa0000000 +//#define KSEG2BASE 0xc0000000 +//#define KSEG3BASE 0xe0000000 + +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 + +#endif + +/* + * Cache modes for XKPHYS address conversion macros + */ +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 + +/* + * 64-bit address conversions + */ +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) + +/* + * Returns the uncached address of a sdram address + */ +#ifndef __ASSEMBLY__ +#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) +/* We use a 36 bit physical address map here and + cannot access physical memory directly from core */ +#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) +#else /* !CONFIG_SOC_AU1X00 */ +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) +#endif /* CONFIG_SOC_AU1X00 */ +#endif /* __ASSEMBLY__ */ + +/* + * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * R8000 implements most with its 48-bit physical address space. + */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ + +#ifndef CONFIG_CPU_R8000 + +/* + * The R8000 doesn't have the 32-bit compat spaces so we don't define them + * in order to catch bugs in the source code. + */ + +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ + +#endif + +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) + + +#ifndef __ASSEMBLY__ +/* + * Change virtual addresses to physical addresses and vv. + * These are trivial on the 1:1 Linux/MIPS mapping + */ +static inline phys_addr_t virt_to_phys(volatile void * address) +{ +#ifndef CONFIG_64BIT + return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif +} + +static inline void * phys_to_virt(unsigned long address) +{ +#ifndef CONFIG_64BIT + return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif +} +#endif + + +#endif /* _MIPS_ADDRSPACE_H_ */ diff --git a/bsp/x1000/cpu/common/mips_asm.h b/bsp/x1000/cpu/common/mips_asm.h new file mode 100644 index 0000000000..8f97e370ab --- /dev/null +++ b/bsp/x1000/cpu/common/mips_asm.h @@ -0,0 +1,447 @@ +/* + * File : mips_asm.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 201697 Urey the first version + */ + +#ifndef _MIPS_ASM_H_ +#define _MIPS_ASM_H_ + + +/* ********************************************************************* */ +/* Interface macro & data definition */ + +#ifdef __ASSEMBLY__ + +/******** ASSEMBLER SPECIFIC DEFINITIONS ********/ + +#ifdef __ghs__ +#define ALIGN(x) .##align (1 << (x)) +#else +#define ALIGN(x) .##align (x) +#endif + +#ifdef __ghs__ +#define SET_MIPS3() +#define SET_MIPS0() +#define SET_PUSH() +#define SET_POP() +#else +#define SET_MIPS3() .##set mips3 +#define SET_MIPS0() .##set mips0 +#define SET_PUSH() .##set push +#define SET_POP() .##set pop +#endif + +/* Different assemblers have different requirements for how to + * indicate that the next section is bss : + * + * Some use : .bss + * Others use : .section bss + * + * We select which to use based on _BSS_OLD_, which may be defined + * in makefile. + */ +#ifdef _BSS_OLD_ +#define BSS .##section bss +#else +#define BSS .##bss +#endif + +#define LEAF(name)\ + .##text;\ + .##globl name;\ + .##ent name;\ +name: + + +#define SLEAF(name)\ + .##text;\ + .##ent name;\ +name: + + +#ifdef __ghs__ +#define END(name)\ + .##end name +#else +#define END(name)\ + .##size name,.-name;\ + .##end name +#endif + + +#define EXTERN(name) + +#else + +#define U64 unsigned long long +#define U32 unsigned int +#define U16 unsigned short +#define U8 unsigned char +#define S64 signed long long +#define S32 int +#define S16 short int +#define S8 signed char +//#define bool U8 + +#ifndef _SIZE_T_ +#define _SIZE_T_ +#ifdef __ghs__ + typedef unsigned int size_t; +#else + typedef unsigned long size_t; +#endif +#endif + +/* Sets the result on bPort */ +#define BIT_SET(bPort,bBitMask) (bPort |= bBitMask) +#define BIT_CLR(bPort,bBitMask) (bPort &= ~bBitMask) + +/* Returns the result */ +#define GET_BIT_SET(bPort,bBitMask) (bPort | bBitMask) +#define GET_BIT_CLR(bPort,bBitMask) (bPort & ~bBitMask) + +/* Returns 0 if the condition is False & a non-zero value if it is True */ +#define TEST_BIT_SET(bPort,bBitMask) (bPort & bBitMask) +#define TEST_BIT_CLR(bPort,bBitMask) ((~bPort) & bBitMask) + +/* Split union definitions */ +typedef union tunSU16 +{ + U16 hwHW; + struct tst2U8 + { + U8 bB0; + U8 bB1; + }st2U8; +}tunSU16; + +typedef union tunSU32 +{ + U32 wW; + struct tst2U16 + { + U16 hwHW0; + U16 hwHW1; + }st2U16; + struct tst4U8 + { + U8 bB0; + U8 bB1; + U8 bB2; + U8 bB3; + }st4U8; +}tunSU32; + +#endif /* #ifdef __ASSEMBLY__ */ + + +/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/ + + +#define NO_ERR 0x00000000 /* operation completed successfully */ +#define ERR 0xffffffff /* operation completed not successfully */ + +#define False 0 +#define True !False + +#ifndef NULL +#define NULL ((void *)0) +#endif//NULL + +#ifndef MIN +#define MIN(x,y) ((x) < (y) ? (x) : (y)) +#endif//MIN + +#ifndef MAX +#define MAX(x,y) ((x) > (y) ? (x) : (y)) +#endif//MAX + +#define MAXUINT(w) (\ + ((w) == sizeof(U8)) ? 0xFFU :\ + ((w) == sizeof(U16)) ? 0xFFFFU :\ + ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ + ) + +#define MAXINT(w) (\ + ((w) == sizeof(S8)) ? 0x7F :\ + ((w) == sizeof(S16)) ? 0x7FFF :\ + ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ + ) + +#define MSK(n) ((1 << (n)) - 1) + +#define KUSEG_MSK 0x80000000 +#define KSEG_MSK 0xE0000000 + +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xA0000000 +#define KSSEGBASE 0xC0000000 +#define KSEG3BASE 0xE0000000 + +/* Below macros perform the following functions : + * + * KSEG0 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0. + * KSEG1 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1. + * PHYS : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address. + * KSSEG : Not relevant for converting, but used for determining range. + * KSEG3 : Not relevant for converting, but used for determining range. + * KUSEG : Not relevant for converting, but used for determining range. + * KSEG0A : Same as KSEG0 but operates on register rather than constant. + * KSEG1A : Same as KSEG1 but operates on register rather than constant. + * PHYSA : Same as PHYS but operates on register rather than constant. + * CACHED : Alias for KSEG0 macro . + * (Note that KSEG0 cache attribute is determined by K0 + * field of Config register, but this is typically cached). + * UNCACHED : Alias for KSEG1 macro . + */ +#ifdef __ASSEMBLY__ +#define KSEG0(addr) (((addr) & ~KSEG_MSK) | KSEG0BASE) +#define KSEG1(addr) (((addr) & ~KSEG_MSK) | KSEG1BASE) +#define KSSEG(addr) (((addr) & ~KSEG_MSK) | KSSEGBASE) +#define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE) +#define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE) +#define PHYS(addr) ( (addr) & ~KSEG_MSK) +#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE +#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE +#define PHYSA(reg) and reg, ~KSEG_MSK +#else +#define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE) +#define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE) +#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) +#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) +#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) +#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) +#endif + +#define CACHED(addr) KSEG0(addr) +#define UNCACHED(addr) KSEG1(addr) + + +#ifdef __ASSEMBLY__ +/* Macroes to access variables at constant addresses + * Compensates for signed 16 bit displacement + * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) + * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) + */ +#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) +#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) +#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) +#define LO_OFFS(addr) ((addr) & 0xffff) +#endif + + +/* Most/Least significant 32 bit from 64 bit double word */ +#define HI32(data64) ((U32)(data64 >> 32)) +#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) + +#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY))) +#define REG8( addr ) (*(volatile U8 *) (addr)) +#define REG16( addr ) (*(volatile U16 *)(addr)) +#define REG32( addr ) (*(volatile U32 *)(addr)) +#define REG64( addr ) (*(volatile U64 *)(addr)) +#endif + +/* Register field mapping */ +#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) + +/* absolute register address, access */ +#define REGA(addr) REG32(addr) + +/* physical register address, access: base address + offsett */ +#define REGP(base,phys) REG32( (U32)(base) + (phys) ) + +/* relative register address, access: base address + offsett */ +#define REG(base,offs) REG32( (U32)(base) + offs##_##OFS ) + +/* relative register address, access: base address + offsett */ +#define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS ) + +/* relative register address, access: base address + offsett */ +#define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS ) + +/* relative register address, access: base address + offsett */ +#define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS ) + +/************************************** + * Macroes not used by YAMON any more + * (kept for backwards compatibility) + */ +/* register read field */ +#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ + >> addr##_##fld##_##SHF) + +/* register write numeric field value */ +#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ + | ((intval) << addr##_##fld##_##SHF)) + +/* register write enumerated field value */ +#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ + | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) + + +/* Examples: + * + * exccode = REGARD(CPU_CAUSE,EXC); + * + * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) + * | REGAWRE(OSG_CONTROL,DTYPE,PC1); + */ + + +/* register read field */ +#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ + >> offs##_##fld##_##SHF) + +/* register write numeric field value */ +#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ + | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK)) + +/* register write enumerated field value */ +#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ + | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) + + +/* physical register read field */ +#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ + >> phys##_##fld##_##SHF) + +/* physical register write numeric field value */ +#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ + | ((intval) << phys##_##fld##_##SHF)) + +/* physical register write enumerated field value */ +#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ + | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) +/* + * End of macroes not used by YAMON any more + *********************************************/ + +/* Endian related macros */ + +#define SWAP_BYTEADDR32( addr ) ( (addr) ^ 0x3 ) +#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 ) + +/* Set byte address to little endian format */ +#ifdef EL +#define SWAP_BYTEADDR_EL(addr) addr +#else +#define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr ) +#endif + +/* Set byte address to big endian format */ +#ifdef EB +#define SWAP_BYTEADDR_EB(addr) addr +#else +#define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr ) +#endif + +/* Set U16 address to little endian format */ +#ifdef EL +#define SWAP_U16ADDR_EL(addr) addr +#else +#define SWAP_U16ADDR_EL(addr) SWAP_U16ADDR32( addr ) +#endif + +/* Set U16 address to big endian format */ +#ifdef EB +#define SWAP_U16ADDR_EB(addr) addr +#else +#define SWAP_U16ADDR_EB(addr) SWAP_U16ADDR32( addr ) +#endif + +#ifdef EL +#define REGW32LE(addr, data) REG32(addr) = (data) +#define REGR32LE(addr, data) (data) = REG32(addr) +#else +#define REGW32LE(addr, data) REG32(addr) = SWAPEND32(data) +#define REGR32LE(addr, data) (data) = REG32(addr), (data) = SWAPEND32(data) +#endif + +/* Set of 'LE'-macros, convert by BE: */ +#ifdef EL +#define CPU_TO_LE32( value ) (value) +#define LE32_TO_CPU( value ) (value) + +#define CPU_TO_LE16( value ) (value) +#define LE16_TO_CPU( value ) (value) +#else +#define CPU_TO_LE32( value ) ( ( ((U32)value) << 24) | \ + ((0x0000FF00UL & ((U32)value)) << 8) | \ + ((0x00FF0000UL & ((U32)value)) >> 8) | \ + ( ((U32)value) >> 24) ) +#define LE32_TO_CPU( value ) CPU_TO_LE32( value ) + +#define CPU_TO_LE16( value ) ( ((U16)(((U16)value) << 8)) | \ + ((U16)(((U16)value) >> 8)) ) +#define LE16_TO_CPU( value ) CPU_TO_LE16( value ) +#endif + +/* Set of 'BE'-macros, convert by LE: */ +#ifdef EB +#define CPU_TO_BE32( value ) (value) +#define BE32_TO_CPU( value ) (value) + +#define CPU_TO_BE16( value ) (value) +#define BE16_TO_CPU( value ) (value) +#else +#define CPU_TO_BE32( value ) ( ( ((U32)value) << 24) | \ + ((0x0000FF00UL & ((U32)value)) << 8) | \ + ((0x00FF0000UL & ((U32)value)) >> 8) | \ + ( ((U32)value) >> 24) ) +#define BE32_TO_CPU( value ) CPU_TO_BE32( value ) + +#define CPU_TO_BE16( value ) ( ((U16)(((U16)value) << 8)) | \ + ((U16)(((U16)value) >> 8)) ) +#define BE16_TO_CPU( value ) CPU_TO_BE16( value ) +#endif + + +/* Control characters */ +#define CTRL_A ('A'-0x40) +#define CTRL_B ('B'-0x40) +#define CTRL_C ('C'-0x40) +#define CTRL_D ('D'-0x40) +#define CTRL_E ('E'-0x40) +#define CTRL_F ('F'-0x40) +#define CTRL_H ('H'-0x40) +#define CTRL_K ('K'-0x40) +#define CTRL_N ('N'-0x40) +#define CTRL_P ('P'-0x40) +#define CTRL_U ('U'-0x40) +#define BACKSPACE 0x08 +#define DEL 0x7F +#define TAB 0x09 +#define CR 0x0D /* Enter Key */ +#define LF 0x0A +#define ESC 0x1B +#define SP 0x20 +#define CSI 0x9B + + +/* DEF2STR(x) converts #define symbol to string */ +#define DEF2STR1(x) #x +#define DEF2STR(x) DEF2STR1(x) + + +#endif /* _MIPS_ASM_H_ */ diff --git a/bsp/x1000/cpu/common/mips_cache.c b/bsp/x1000/cpu/common/mips_cache.c new file mode 100644 index 0000000000..1c979b7106 --- /dev/null +++ b/bsp/x1000/cpu/common/mips_cache.c @@ -0,0 +1,153 @@ +/* + * File : mips_cache.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 201697 Urey the first version + */ + +#include +#include "mips.h" + +extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); +void r4k_cache_init(void) +{ +// cache_init(dcache_size, cpu_dcache_line_size); +} + +void r4k_cache_flush_all(void) +{ + blast_dcache16(); + blast_icache16(); +} + + +void r4k_icache_flush_all(void) +{ + blast_icache16(); +} + +void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + + if (size > g_mips_core.icache_size) + { + blast_icache16(); + } + else + { + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + + a = addr & ~(ic_lsize - 1); + end = ((addr + size) - 1) & ~(ic_lsize - 1); + while (1) + { + flush_icache_line(a); + if (a == end) + break; + a += ic_lsize; + } + } +} + +void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + + a = addr & ~(ic_lsize - 1); + end = ((addr + size) - 1) & ~(ic_lsize - 1); + while (1) + { + lock_icache_line(a); + if (a == end) + break; + a += ic_lsize; + } +} + +void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; + + a = addr & ~(dc_lsize - 1); + end = ((addr + size) - 1) & ~(dc_lsize - 1); + while (1) + { + invalidate_dcache_line(a); + if (a == end) + break; + a += dc_lsize; + } +} + +void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + + if (size >= g_mips_core.dcache_size) + { + blast_dcache16(); + } + else + { + rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; + + a = addr & ~(dc_lsize - 1); + end = ((addr + size) - 1) & ~(dc_lsize - 1); + while (1) + { + flush_dcache_line(a); + if (a == end) + break; + a += dc_lsize; + } + } +} + +#define dma_cache_wback_inv(start,size) \ + do { (void) (start); (void) (size); } while (0) +#define dma_cache_wback(start,size) \ + do { (void) (start); (void) (size); } while (0) +#define dma_cache_inv(start,size) \ + do { (void) (start); (void) (size); } while (0) + + +void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction) +{ + switch (direction) + { + case DMA_TO_DEVICE: + r4k_dcache_wback_inv(addr, size); + break; + + case DMA_FROM_DEVICE: + r4k_dcache_wback_inv(addr, size); + break; + + case DMA_BIDIRECTIONAL: + dma_cache_wback_inv(addr, size); + break; + default: + RT_ASSERT(0) ; + } +} + diff --git a/bsp/x1000/cpu/common/mips_cache.h b/bsp/x1000/cpu/common/mips_cache.h new file mode 100644 index 0000000000..a947041073 --- /dev/null +++ b/bsp/x1000/cpu/common/mips_cache.h @@ -0,0 +1,234 @@ +/* + * File : mips_cache.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2016910 Urey the first version + */ + +#ifndef _MIPS_CACHE_H_ +#define _MIPS_CACHE_H_ + +#ifndef __ASSEMBLER__ +#include +#include + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define INDEX_INVALIDATE_I 0x00 +#define INDEX_WRITEBACK_INV_D 0x01 +#define INDEX_LOAD_TAG_I 0x04 +#define INDEX_LOAD_TAG_D 0x05 +#define INDEX_STORE_TAG_I 0x08 +#define INDEX_STORE_TAG_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define HIT_INVALIDATE_I 0x00 +#else +#define HIT_INVALIDATE_I 0x10 +#endif +#define HIT_INVALIDATE_D 0x11 +#define HIT_WRITEBACK_INV_D 0x15 + +/* + *The lock state is cleared by executing an Index +Invalidate, Index Writeback Invalidate, Hit +Invalidate, or Hit Writeback Invalidate +operation to the locked line, or via an Index +Store Tag operation with the lock bit reset in +the TagLo register. + */ +#define FETCH_AND_LOCK_I 0x1c +#define FETCH_AND_LOCK_D 0x1d + + +enum dma_data_direction +{ + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; + +/* + * R4000-specific cacheops + */ +#define CREATE_DIRTY_EXCL_D 0x0d +#define FILL 0x14 +#define HIT_WRITEBACK_I 0x18 +#define HIT_WRITEBACK_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define INDEX_INVALIDATE_SI 0x02 +#define INDEX_WRITEBACK_INV_SD 0x03 +#define INDEX_LOAD_TAG_SI 0x06 +#define INDEX_LOAD_TAG_SD 0x07 +#define INDEX_STORE_TAG_SI 0x0A +#define INDEX_STORE_TAG_SD 0x0B +#define CREATE_DIRTY_EXCL_SD 0x0f +#define HIT_INVALIDATE_SI 0x12 +#define HIT_INVALIDATE_SD 0x13 +#define HIT_WRITEBACK_INV_SD 0x17 +#define HIT_WRITEBACK_SD 0x1b +#define HIT_SET_VIRTUAL_SI 0x1e +#define HIT_SET_VIRTUAL_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_PAGE_INVALIDATE_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define PAGE_INVALIDATE_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define INDEX_WRITEBACK_INV_S 0x03 +#define INDEX_LOAD_TAG_S 0x07 +#define INDEX_STORE_TAG_S 0x0B +#define HIT_INVALIDATE_S 0x13 +#define CACHE_BARRIER 0x14 +#define HIT_WRITEBACK_INV_S 0x17 +#define INDEX_LOAD_DATA_I 0x18 +#define INDEX_LOAD_DATA_D 0x19 +#define INDEX_LOAD_DATA_S 0x1b +#define INDEX_STORE_DATA_I 0x1c +#define INDEX_STORE_DATA_D 0x1d +#define INDEX_STORE_DATA_S 0x1f + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + ".set push\n" \ + ".set noreorder\n" \ + ".set mips3\n" \ + "cache %0, %1\n" \ + ".set pop\n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); + + +static inline void flush_icache_line_indexed(rt_ubase_t addr) +{ + cache_op(INDEX_INVALIDATE_I, addr); +} + +static inline void flush_dcache_line_indexed(rt_ubase_t addr) +{ + cache_op(INDEX_WRITEBACK_INV_D, addr); +} + +static inline void flush_icache_line(rt_ubase_t addr) +{ + cache_op(HIT_INVALIDATE_I, addr); +} + +static inline void lock_icache_line(rt_ubase_t addr) +{ + cache_op(FETCH_AND_LOCK_I, addr); +} + +static inline void lock_dcache_line(rt_ubase_t addr) +{ + cache_op(FETCH_AND_LOCK_D, addr); +} + +static inline void flush_dcache_line(rt_ubase_t addr) +{ + cache_op(HIT_WRITEBACK_INV_D, addr); +} + +static inline void invalidate_dcache_line(rt_ubase_t addr) +{ + cache_op(HIT_INVALIDATE_D, addr); +} +static inline void blast_dcache16(void) +{ + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); +} + +static inline void inv_dcache16(void) +{ + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, HIT_INVALIDATE_D); +} + +static inline void blast_icache16(void) +{ + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.icache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += g_mips_core.icache_line_size) + cache16_unroll32(addr, INDEX_INVALIDATE_I); +} + +void r4k_cache_init(void); +void r4k_cache_flush_all(void); +void r4k_icache_flush_all(void); +void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size); +void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size); +void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size); +void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size); +void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction); +#endif + +#endif /* _MIPS_CACHE_H_ */ diff --git a/bsp/x1000/cpu/common/mips_cfg.h b/bsp/x1000/cpu/common/mips_cfg.h new file mode 100644 index 0000000000..3f0575d65a --- /dev/null +++ b/bsp/x1000/cpu/common/mips_cfg.h @@ -0,0 +1,48 @@ +/* + * File : mips_cfg.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2016910 Urey the first version + */ + +#ifndef _MIPS_CFG_H_ +#define _MIPS_CFG_H_ + +#ifndef __ASSEMBLY__ +#include +typedef struct mips32_core_cfg +{ + uint16_t icache_line_size; +// uint16_t icache_lines_per_way; +// uint16_t icache_ways; + uint16_t icache_size; + uint16_t dcache_line_size; +// uint16_t dcache_lines_per_way; +// uint16_t dcache_ways; + uint16_t dcache_size; + + uint16_t max_tlb_entries; /* number of tlb entry */ +} mips32_core_cfg_t; + +extern mips32_core_cfg_t g_mips_core; + +#endif /* __ASSEMBLY__ */ + +#endif /* _MIPS_CFG_H_ */ diff --git a/bsp/x1000/cpu/common/mips_context.h b/bsp/x1000/cpu/common/mips_context.h new file mode 100644 index 0000000000..60d573784d --- /dev/null +++ b/bsp/x1000/cpu/common/mips_context.h @@ -0,0 +1,280 @@ +/* + * File : mips_context_asm.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 201697 Urey the first version + */ + +#ifndef _MIPS_CONTEXT_ASM_H_ +#define _MIPS_CONTEXT_ASM_H_ + +#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) +#ifdef __mips_hard_float +#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ +#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) +#else +#define FPU_ADJ 0 +#endif + + + +#ifdef __ASSEMBLY__ + +#ifdef __mips_hard_float +.global _fpctx_save +.global _fpctx_load +#endif + +.macro SAVE_CONTEXT + .set push + .set noat + .set noreorder + .set volatile + + //save SP + move k1, sp + move k0, sp + subu sp, k1, CONTEXT_SIZE + sw k0, (29 * 4)(sp) + + //save REG + sw $0, ( 0 * 4)(sp) + sw $1, ( 1 * 4)(sp) + sw $2, ( 2 * 4)(sp) + sw $3, ( 3 * 4)(sp) + sw $4, ( 4 * 4)(sp) + sw $5, ( 5 * 4)(sp) + sw $6, ( 6 * 4)(sp) + sw $7, ( 7 * 4)(sp) + sw $8, ( 8 * 4)(sp) + sw $9, ( 9 * 4)(sp) + sw $10, (10 * 4)(sp) + sw $11, (11 * 4)(sp) + sw $12, (12 * 4)(sp) + sw $13, (13 * 4)(sp) + sw $14, (14 * 4)(sp) + sw $15, (15 * 4)(sp) + sw $16, (16 * 4)(sp) + sw $17, (17 * 4)(sp) + sw $18, (18 * 4)(sp) + sw $19, (19 * 4)(sp) + sw $20, (20 * 4)(sp) + sw $21, (21 * 4)(sp) + sw $22, (22 * 4)(sp) + sw $23, (23 * 4)(sp) + sw $24, (24 * 4)(sp) + sw $25, (25 * 4)(sp) + /* K0 K1 */ + sw $28, (28 * 4)(sp) + /* SP */ + sw $30, (30 * 4)(sp) + sw $31, (31 * 4)(sp) + + /* STATUS CAUSE EPC.... */ + mfc0 $2, CP0_STATUS + sw $2, STK_OFFSET_SR(sp) + + mfc0 $2, CP0_CAUSE + sw $2, STK_OFFSET_CAUSE(sp) + + mfc0 $2, CP0_BADVADDR + sw $2, STK_OFFSET_BADVADDR(sp) + + MFC0 $2, CP0_EPC + sw $2, STK_OFFSET_EPC(sp) + + mfhi $2 + sw $2, STK_OFFSET_HI(sp) + + mflo $2 + sw $2, STK_OFFSET_LO(sp) +#ifdef __mips_hard_float + add a0, sp,STK_CTX_SIZE + + mfc0 t0, CP0_STATUS + .set push + .set at + or t0, M_StatusCU1 + .set push + mtc0 t0, CP0_STATUS + + cfc1 t0, CP1_STATUS + sw t0 , 0x00(a0) + swc1 $f0,(0x04 * 1)(a0) + swc1 $f1,(0x04 * 2)(a0) + swc1 $f2,(0x04 * 3)(a0) + swc1 $f3,(0x04 * 4)(a0) + swc1 $f4,(0x04 * 5)(a0) + swc1 $f5,(0x04 * 6)(a0) + swc1 $f6,(0x04 * 7)(a0) + swc1 $f7,(0x04 * 8)(a0) + swc1 $f8,(0x04 * 9)(a0) + swc1 $f9,(0x04 * 10)(a0) + swc1 $f10,(0x04 * 11)(a0) + swc1 $f11,(0x04 * 12)(a0) + swc1 $f12,(0x04 * 13)(a0) + swc1 $f13,(0x04 * 14)(a0) + swc1 $f14,(0x04 * 15)(a0) + swc1 $f15,(0x04 * 16)(a0) + swc1 $f16,(0x04 * 17)(a0) + swc1 $f17,(0x04 * 18)(a0) + swc1 $f18,(0x04 * 19)(a0) + swc1 $f19,(0x04 * 20)(a0) + swc1 $f20,(0x04 * 21)(a0) + swc1 $f21,(0x04 * 22)(a0) + swc1 $f22,(0x04 * 23)(a0) + swc1 $f23,(0x04 * 24)(a0) + swc1 $f24,(0x04 * 25)(a0) + swc1 $f25,(0x04 * 26)(a0) + swc1 $f26,(0x04 * 27)(a0) + swc1 $f27,(0x04 * 28)(a0) + swc1 $f28,(0x04 * 29)(a0) + swc1 $f29,(0x04 * 30)(a0) + swc1 $f30,(0x04 * 31)(a0) + swc1 $f31,(0x04 * 32)(a0) + + nop +#endif + + //restore a0 + lw a0, (REG_A0 * 4)(sp) + + .set pop +.endm + + +.macro RESTORE_CONTEXT + .set push + .set noat + .set noreorder + .set volatile + +#ifdef __mips_hard_float + add a0, sp,STK_CTX_SIZE + + mfc0 t0, CP0_STATUS + .set push + .set at + or t0, M_StatusCU1 + .set noat + mtc0 t0, CP0_STATUS + + lw t0 , 0x00(a0) + lwc1 $f0,(0x04 * 1)(a0) + lwc1 $f1,(0x04 * 2)(a0) + lwc1 $f2,(0x04 * 3)(a0) + lwc1 $f3,(0x04 * 4)(a0) + lwc1 $f4,(0x04 * 5)(a0) + lwc1 $f5,(0x04 * 6)(a0) + lwc1 $f6,(0x04 * 7)(a0) + lwc1 $f7,(0x04 * 8)(a0) + lwc1 $f8,(0x04 * 9)(a0) + lwc1 $f9,(0x04 * 10)(a0) + lwc1 $f10,(0x04 * 11)(a0) + lwc1 $f11,(0x04 * 12)(a0) + lwc1 $f12,(0x04 * 13)(a0) + lwc1 $f13,(0x04 * 14)(a0) + lwc1 $f14,(0x04 * 15)(a0) + lwc1 $f15,(0x04 * 16)(a0) + lwc1 $f16,(0x04 * 17)(a0) + lwc1 $f17,(0x04 * 18)(a0) + lwc1 $f18,(0x04 * 19)(a0) + lwc1 $f19,(0x04 * 20)(a0) + lwc1 $f20,(0x04 * 21)(a0) + lwc1 $f21,(0x04 * 22)(a0) + lwc1 $f22,(0x04 * 23)(a0) + lwc1 $f23,(0x04 * 24)(a0) + lwc1 $f24,(0x04 * 25)(a0) + lwc1 $f25,(0x04 * 26)(a0) + lwc1 $f26,(0x04 * 27)(a0) + lwc1 $f27,(0x04 * 28)(a0) + lwc1 $f28,(0x04 * 29)(a0) + lwc1 $f29,(0x04 * 30)(a0) + lwc1 $f30,(0x04 * 31)(a0) + lwc1 $f31,(0x04 * 32)(a0) + ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ + + nop +#endif + + /* ͨüĴ */ + /* ZERO */ + lw $1, ( 1 * 4)(sp) + /* V0 */ + lw $3, ( 3 * 4)(sp) + lw $4, ( 4 * 4)(sp) + lw $5, ( 5 * 4)(sp) + lw $6, ( 6 * 4)(sp) + lw $7, ( 7 * 4)(sp) + lw $8, ( 8 * 4)(sp) + lw $9, ( 9 * 4)(sp) + lw $10, (10 * 4)(sp) + lw $11, (11 * 4)(sp) + lw $12, (12 * 4)(sp) + lw $13, (13 * 4)(sp) + lw $14, (14 * 4)(sp) + lw $15, (15 * 4)(sp) + lw $16, (16 * 4)(sp) + lw $17, (17 * 4)(sp) + lw $18, (18 * 4)(sp) + lw $19, (19 * 4)(sp) + lw $20, (20 * 4)(sp) + lw $21, (21 * 4)(sp) + lw $22, (22 * 4)(sp) + lw $23, (23 * 4)(sp) + lw $24, (24 * 4)(sp) + lw $25, (25 * 4)(sp) + lw $26, (26 * 4)(sp) + lw $27, (27 * 4)(sp) + lw $28, (28 * 4)(sp) + /* SP */ + lw $30, (30 * 4)(sp) + lw $31, (31 * 4)(sp) + + + /* STATUS CAUSE EPC.... */ + lw $2, STK_OFFSET_HI(sp) + mthi $2 + lw $2, STK_OFFSET_LO(sp) + mtlo $2 + + lw $2, STK_OFFSET_SR(sp) + mtc0 $2, CP0_STATUS + + lw $2, STK_OFFSET_BADVADDR(sp) + mtc0 $2, CP0_BADVADDR + + lw $2, STK_OFFSET_CAUSE(sp) + mtc0 $2, CP0_CAUSE + + lw $2, STK_OFFSET_EPC(sp) + MTC0 $2, CP0_EPC + + //restore $2 + lw $2, ( 2 * 4)(sp) + //restore sp + lw $29, (29 * 4)(sp) + + eret + nop + .set pop +.endm +#endif +#endif /* _MIPS_CONTEXT_ASM_H_ */ diff --git a/bsp/x1000/cpu/common/mips_def.h b/bsp/x1000/cpu/common/mips_def.h new file mode 100644 index 0000000000..1727684f50 --- /dev/null +++ b/bsp/x1000/cpu/common/mips_def.h @@ -0,0 +1,2296 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-09-07 Urey first version + */ + +#ifndef _COMMON_MIPS_DEF_H_ +#define _COMMON_MIPS_DEF_H_ + + +/* + ************************************************************************ + * I N S T R U C T I O N F O R M A T S * + ************************************************************************ + * + * The following definitions describe each field in an instruction. There + * is one diagram for each type of instruction, with field definitions + * following the diagram for that instruction. Note that if a field of + * the same name and position is defined in an earlier diagram, it is + * not defined again in the subsequent diagram. Only new fields are + * defined for each diagram. + * + * R-Type (operate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | rs | rt | rd | sa | | + * | Opcode | | | Tcode | func | + * | | Bcode | | sel | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnOpcode 26 +#define M_InstnOpcode (0x3f << S_InstnOpcode) +#define S_InstnRS 21 +#define M_InstnRS (0x1f << S_InstnRS) +#define S_InstnRT 16 +#define M_InstnRT (0x1f << S_InstnRT) +#define S_InstnRD 11 +#define M_InstnRD (0x1f << S_InstnRD) +#define S_InstnSA 6 +#define M_InstnSA (0x1f << S_InstnSA) +#define S_InstnTcode 6 +#define M_InstnTcode (0x3ff << S_InstnTcode) +#define S_InstnBcode 6 +#define M_InstnBcode (0xfffff << S_InstnBcode) +#define S_InstnFunc 0 +#define M_InstnFunc (0x3f << S_InstnFunc) +#define S_InstnSel 0 +#define M_InstnSel (0x7 << S_InstnSel) + +/* + * I-Type (load, store, branch, immediate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | rt | Offset | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnOffset 0 +#define M_InstnOffset (0xffff << S_InstnOffset) + +/* + * I-Type (pref) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | hint | Offset | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnHint S_InstnRT +#define M_InstnHint M_InstnRT + +/* + * J-Type (jump) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | JIndex | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnJIndex 0 +#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) + +/* + * FP R-Type (operate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fmt | ft | fs | fd | func | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnFmt S_InstnRS +#define M_InstnFmt M_InstnRS +#define S_InstnFT S_InstnRT +#define M_InstnFT M_InstnRT +#define S_InstnFS S_InstnRD +#define M_InstnFS M_InstnRD +#define S_InstnFD S_InstnSA +#define M_InstnFD M_InstnSA + +/* + * FP R-Type (cpu <-> cpu data movement)) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | sub | rt | fs | 0 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnSub S_InstnRS +#define M_InstnSub M_InstnRS + +/* + * FP R-Type (compare) + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | | | |C| | + * | Opcode | fmt | ft | fs | cc |0|A| func | + * | | | | | | |B| | + * | | | | | | |S| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnCCcmp 8 +#define M_InstnCCcmp (0x7 << S_InstnCCcmp) +#define S_InstnCABS 6 +#define M_InstnCABS (0x1 << S_InstnCABS) + +/* + * FP R-Type (FPR conditional move on FP cc) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fmt | cc |n|t| fs | fd | func | + * | | | |d|f| | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnCC 18 +#define M_InstnCC (0x7 << S_InstnCC) +#define S_InstnND 17 +#define M_InstnND (0x1 << S_InstnND) +#define S_InstnTF 16 +#define M_InstnTF (0x1 << S_InstnTF) + +/* + * FP R-Type (3-operand operate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fr | ft | fs | fd | op4 | fmt3| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnFR S_InstnRS +#define M_InstnFR M_InstnRS +#define S_InstnOp4 3 +#define M_InstnOp4 (0x7 << S_InstnOp4) +#define S_InstnFmt3 0 +#define M_InstnFmt3 (0x7 << S_InstnFmt3) + +/* + * FP R-Type (Indexed load, store) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | rt | 0 | fd | func | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +/* + * FP R-Type (prefx) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | rt | hint | 0 | func | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnHintX S_InstnRD +#define M_InstnHintX M_InstnRD + +/* + * FP R-Type (GPR conditional move on FP cc) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | cc |n|t| rd | 0 | func | + * | | | |d|f| | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +/* + * FP I-Type (load, store) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | ft | Offset | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +/* + * FP I-Type (branch) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fmt | cc |n|t| Offset | + * | | | |d|f| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + + +/* + ************************************************************************* + * V I R T U A L A D D R E S S D E F I N I T I O N S * + ************************************************************************* + */ + +#ifdef MIPSADDR64 +#define A_K0BASE UNS64Const(0xffffffff80000000) +#define A_K1BASE UNS64Const(0xffffffffa0000000) +#define A_K2BASE UNS64Const(0xffffffffc0000000) +#define A_K3BASE UNS64Const(0xffffffffe0000000) +#define A_REGION UNS64Const(0xc000000000000000) +#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) +#else +#define A_K0BASE 0x80000000 +#define A_K1BASE 0xa0000000 +#define A_K2BASE 0xc0000000 +#define A_K3BASE 0xe0000000 +#endif +#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ + + +#ifdef MIPS_Model64 + +#define S_VMAP64 62 +#define M_VMAP64 UNS64Const(0xc000000000000000) + +#define K_VMode11 3 +#define K_VMode10 2 +#define K_VMode01 1 +#define K_VMode00 0 + +#define S_KSEG3 29 +#define M_KSEG3 (0x7 << S_KSEG3) +#define K_KSEG3 7 + +#define S_SSEG 29 +#define M_SSEG (0x7 << S_KSEG3) +#define K_SSEG 6 + +#define S_KSSEG 29 +#define M_KSSEG (0x7 << S_KSEG3) +#define K_KSSEG 6 + +#define S_KSEG1 29 +#define M_KSEG1 (0x7 << S_KSEG3) +#define K_KSEG1 5 + +#define S_KSEG0 29 +#define M_KSEG0 (0x7 << S_KSEG3) +#define K_KSEG0 4 + +#define S_XKSEG 29 +#define M_XKSEG (0x7 << S_KSEG3) +#define K_XKSEG 3 + +#define S_USEG 31 +#define M_USEG (0x1 << S_USEG) +#define K_USEG 0 + +#define S_EjtagProbeMem 20 +#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) +#define K_EjtagProbeMem 0 + + + +#else + +#define S_KSEG3 29 +#define M_KSEG3 (0x7 << S_KSEG3) +#define K_KSEG3 7 + +#define S_KSSEG 29 +#define M_KSSEG (0x7 << S_KSSEG) +#define K_KSSEG 6 + +#define S_SSEG 29 +#define M_SSEG (0x7 << S_SSEG) +#define K_SSEG 6 + +#define S_KSEG1 29 +#define M_KSEG1 (0x7 << S_KSEG1) +#define K_KSEG1 5 + +#define S_KSEG0 29 +#define M_KSEG0 (0x7 << S_KSEG0) +#define K_KSEG0 4 + +#define S_KUSEG 31 +#define M_KUSEG (0x1 << S_KUSEG) +#define K_KUSEG 0 + +#define S_SUSEG 31 +#define M_SUSEG (0x1 << S_SUSEG) +#define K_SUSEG 0 + +#define S_USEG 31 +#define M_USEG (0x1 << S_USEG) +#define K_USEG 0 + +#define K_EjtagLower 0xff200000 +#define K_EjtagUpper 0xff3fffff + +#define S_EjtagProbeMem 20 +#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) +#define K_EjtagProbeMem 0 + +#endif + + + +/* + ************************************************************************* + * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * + ************************************************************************* + */ + +/* + * Cache encodings + */ +#define K_CachePriI 0 /* Primary Icache */ +#define K_CachePriD 1 /* Primary Dcache */ +#define K_CachePriU 1 /* Unified primary */ +#define K_CacheTerU 2 /* Unified Tertiary */ +#define K_CacheSecU 3 /* Unified secondary */ + + +/* + * Function encodings + */ +#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ +#define K_CacheIndexInv 0 /* Index invalidate */ +#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ +#define K_CacheIndexLdTag 1 /* Index load tag */ +#define K_CacheIndexStTag 2 /* Index store tag */ +#define K_CacheHitInv 4 /* Hit Invalidate */ +#define K_CacheFill 5 /* Fill (Icache only) */ +#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ +#define K_CacheHitWB 6 /* Hit writeback */ +#define K_CacheFetchLock 7 /* Fetch and lock */ + +#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) +#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) +#define DCIndexInv DCIndexWBInv +#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) +#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) +#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) +#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) +#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) +#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) +#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) +#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) +#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) +#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) +#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) + + +/* + ************************************************************************* + * P R E F E T C H I N S T R U C T I O N H I N T S * + ************************************************************************* + */ + +#define PrefLoad 0 +#define PrefStore 1 +#define PrefLoadStreamed 4 +#define PrefStoreStreamed 5 +#define PrefLoadRetained 6 +#define PrefStoreRetained 7 +#define PrefWBInval 25 +#define PrefNudge 25 + + +/* + ************************************************************************* + * C P U R E G I S T E R D E F I N I T I O N S * + ************************************************************************* + */ + + +/* + ************************************************************************* + * S O F T W A R E G P R N A M E S * + ************************************************************************* + */ +#ifdef __ASSEMBLY__ +#define zero $0 +#define AT $1 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 + +/* + * The following registers are used by the AVP environment and + * are not part of the normal software definitions. + */ + +#ifdef MIPSAVPENV +#define repc $25 /* Expected exception PC */ +#define tid $30 /* Current test case address */ +#endif + + +/* + ************************************************************************* + * H A R D W A R E G P R N A M E S * + ************************************************************************* + * + * In the AVP environment, several of the `r' names are removed from the + * name space because they are used by the kernel for special purposes. + * Removing them causes assembly rather than runtime errors for tests that + * use the `r' names. + * + * - r25 (repc) is used as the expected PC on an exception + * - r26-r27 (k0, k1) are used in the exception handler + * - r30 (tid) is used as the current test address + */ + +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 +#ifdef MIPSAVPENV +#define r25 r25_unknown +#define r26 r26_unknown +#define r27 r27_unknown +#else +#define r25 $25 +#define r26 $26 +#define r27 $27 +#endif +#define r28 $28 +#define r29 $29 +#ifdef MIPSAVPENV +#define r30 r30_unknown +#else +#define r30 $30 +#endif +#define r31 $31 + +#endif + +/* + ************************************************************************* + * H A R D W A R E G P R I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the GPR, as opposed + * to the assembler register name ($n). + */ + +#define R_r0 0 +#define R_r1 1 +#define R_r2 2 +#define R_r3 3 +#define R_r4 4 +#define R_r5 5 +#define R_r6 6 +#define R_r7 7 +#define R_r8 8 +#define R_r9 9 +#define R_r10 10 +#define R_r11 11 +#define R_r12 12 +#define R_r13 13 +#define R_r14 14 +#define R_r15 15 +#define R_r16 16 +#define R_r17 17 +#define R_r18 18 +#define R_r19 19 +#define R_r20 20 +#define R_r21 21 +#define R_r22 22 +#define R_r23 23 +#define R_r24 24 +#define R_r25 25 +#define R_r26 26 +#define R_r27 27 +#define R_r28 28 +#define R_r29 29 +#define R_r30 30 +#define R_r31 31 +#define R_hi 32 /* Hi register */ +#define R_lo 33 /* Lo register */ + + +/* + ************************************************************************* + * S O F T W A R E G P R M A S K S * + ************************************************************************* + * + * These definitions provide the bit mask corresponding to the GPR number + */ + +#define M_AT (1<<1) +#define M_v0 (1<<2) +#define M_v1 (1<<3) +#define M_a0 (1<<4) +#define M_a1 (1<<5) +#define M_a2 (1<<6) +#define M_a3 (1<<7) +#define M_t0 (1<<8) +#define M_t1 (1<<9) +#define M_t2 (1<<10) +#define M_t3 (1<<11) +#define M_t4 (1<<12) +#define M_t5 (1<<13) +#define M_t6 (1<<14) +#define M_t7 (1<<15) +#define M_s0 (1<<16) +#define M_s1 (1<<17) +#define M_s2 (1<<18) +#define M_s3 (1<<19) +#define M_s4 (1<<20) +#define M_s5 (1<<21) +#define M_s6 (1<<22) +#define M_s7 (1<<23) +#define M_t8 (1<<24) +#define M_t9 (1<<25) +#define M_k0 (1<<26) +#define M_k1 (1<<27) +#define M_gp (1<<28) +#define M_sp (1<<29) +#define M_fp (1<<30) +#define M_ra (1<<31) + + +/* + ************************************************************************* + * C P 0 R E G I S T E R D E F I N I T I O N S * + ************************************************************************* + * Each register has the following definitions: + * + * C0_rrr The register number (as a $n value) + * R_C0_rrr The register index (as an integer corresponding + * to the register number) + * + * Each field in a register has the following definitions: + * + * S_rrrfff The shift count required to right-justify + * the field. This corresponds to the bit + * number of the right-most bit in the field. + * M_rrrfff The Mask required to isolate the field. + * + * Register diagrams included below as comments correspond to the + * MIPS32 and MIPS64 architecture specifications. Refer to other + * sources for register diagrams for older architectures. + */ + + +/* + ************************************************************************ + * I N D E X R E G I S T E R ( 0 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |P| 0 | Index | Index + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Index $0 +#define R_C0_Index 0 +#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_IndexP 31 /* Probe failure (R)*/ +#define M_IndexP (0x1 << S_IndexP) + +#define S_IndexIndex 0 /* TLB index (R/W)*/ +#define M_IndexIndex (0x3f << S_IndexIndex) + +#define M_Index0Fields 0x7fffffc0 +#define M_IndexRFields 0x80000000 + + +/* + ************************************************************************ + * R A N D O M R E G I S T E R ( 1 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Index | Random + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Random $1 +#define R_C0_Random 1 +#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_RandomIndex 0 /* TLB random index (R)*/ +#define M_RandomIndex (0x3f << S_RandomIndex) + +#define M_Random0Fields 0xffffffc0 +#define M_RandomRFields 0x0000003f + + +/* + ************************************************************************ + * E N T R Y L O 0 R E G I S T E R ( 2 ) * + ************************************************************************ + * + * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EntryLo0 $2 +#define R_C0_EntryLo0 2 +#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_EntryLoPFN 6 /* PFN (R/W) */ +#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) +#define S_EntryLoC 3 /* Coherency attribute (R/W) */ +#define M_EntryLoC (0x7 << S_EntryLoC) +#define S_EntryLoD 2 /* Dirty (R/W) */ +#define M_EntryLoD (0x1 << S_EntryLoD) +#define S_EntryLoV 1 /* Valid (R/W) */ +#define M_EntryLoV (0x1 << S_EntryLoV) +#define S_EntryLoG 0 /* Global (R/W) */ +#define M_EntryLoG (0x1 << S_EntryLoG) +#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ +#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ +#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ + +#define M_EntryLo0Fields 0x00000000 +#define M_EntryLoRFields 0xc0000000 +#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) +#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) + +/* + * Cache attribute values in the C field of EntryLo and the + * K0 field of Config + */ +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ +#define K_CacheAttrU 2 /* Uncached */ +#define K_CacheAttrC 3 /* Cacheable */ +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ +#define K_CacheAttrUA 7 /* Uncached accelerated */ + + +/* + ************************************************************************ + * E N T R Y L O 1 R E G I S T E R ( 3 ) * + ************************************************************************ + * + * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EntryLo1 $3 +#define R_C0_EntryLo1 3 +#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +/* + * Field definitions are as given for EntryLo0 above + */ + + +/* + ************************************************************************ + * C O N T E X T R E G I S T E R ( 4 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // PTEBase | BadVPN<31:13> | 0 | Context + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Context $4 +#define R_C0_Context 4 +#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_ContextPTEBase 23 /* PTE base (R/W) */ +#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) +#define S_ContextBadVPN 4 /* BadVPN2 (R) */ +#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) +#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ +#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ + +#define M_Context0Fields 0x0000000f +#define M_ContextRFields 0x007ffff0 +#define M_Context0Fields64 UNS64Const(0x000000000000000f) +#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) + + +/* + ************************************************************************ + * P A G E M A S K R E G I S T E R ( 5 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Mask | 0 | PageMask + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_PageMask $5 +#define R_C0_PageMask 5 /* Mask (R/W) */ +#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_PageMaskMask 13 +#define M_PageMaskMask (0xfff << S_PageMaskMask) + +#define M_PageMask0Fields 0xfe001fff +#define M_PageMaskRFields 0x00000000 + +/* + * Values in the Mask field + */ +#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ +#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ +#define K_PageMask64K 0x00f +#define K_PageMask256K 0x03f +#define K_PageMask1M 0x0ff +#define K_PageMask4M 0x3ff +#define K_PageMask16M 0xfff + +#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ +#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ +#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) +#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) +#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) +#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) +#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) + + +/* + ************************************************************************ + * W I R E D R E G I S T E R ( 6 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Index | Wired + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Wired $6 +#define R_C0_Wired 6 +#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ +#define M_WiredIndex (0x3f << S_WiredIndex) + +#define M_Wired0Fields 0xffffffc0 +#define M_WiredRFields 0x00000000 + + +/* + ************************************************************************ + * B A D V A D D R R E G I S T E R ( 8 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Bad Virtual Address | BadVAddr + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_BadVAddr $8 +#define R_C0_BadVAddr 8 +#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ + +#define M_BadVAddr0Fields 0x00000000 +#define M_BadVAddrRFields 0xffffffff +#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) + +/* + ************************************************************************ + * C O U N T R E G I S T E R ( 9 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Count Value | Count + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Count $9 +#define R_C0_Count 9 +#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_Count0Fields 0x00000000 +#define M_CountRFields 0x00000000 + + +/* + ************************************************************************ + * E N T R Y H I R E G I S T E R ( 1 0 ) * + ************************************************************************ + * + * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | R | Fill // VPN2 | 0 | ASID | EntryHi + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EntryHi $10 +#define R_C0_EntryHi 10 +#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_EntryHiR64 62 /* Region (R/W) */ +#define M_EntryHiR64 UNS64Const(0xc000000000000000) +#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ +#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) +#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) +#define S_EntryHiASID 0 /* ASID (R/W) */ +#define M_EntryHiASID (0xff << S_EntryHiASID) +#define S_EntryHiVPN_Shf S_EntryHiVPN2 + +#define M_EntryHi0Fields 0x00001f00 +#define M_EntryHiRFields 0x00000000 +#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) +#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) + + +/* + ************************************************************************ + * C O M P A R E R E G I S T E R ( 1 1 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Compare Value | Compare + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Compare $11 +#define R_C0_Compare 11 +#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_Compare0Fields 0x00000000 +#define M_CompareRFields 0x00000000 + + +/* + ************************************************************************ + * S T A T U S R E G I S T E R ( 1 2 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| + * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status + * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Status $12 +#define R_C0_Status 12 +#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_StatusCU 28 /* Coprocessor enable (R/W) */ +#define M_StatusCU (0xf << S_StatusCU) +#define S_StatusCU3 31 +#define M_StatusCU3 (0x1 << S_StatusCU3) +#define S_StatusCU2 30 +#define M_StatusCU2 (0x1 << S_StatusCU2) +#define S_StatusCU1 29 +#define M_StatusCU1 (0x1 << S_StatusCU1) +#define S_StatusCU0 28 +#define M_StatusCU0 (0x1 << S_StatusCU0) +#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ +#define M_StatusRP (0x1 << S_StatusRP) +#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ +#define M_StatusFR (0x1 << S_StatusFR) +#define S_StatusRE 25 /* Enable reverse endian (R/W) */ +#define M_StatusRE (0x1 << S_StatusRE) +#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ +#define M_StatusMX (0x1 << S_StatusMX) +#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ +#define M_StatusPX (0x1 << S_StatusPX) +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ +#define M_StatusBEV (0x1 << S_StatusBEV) +#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ +#define M_StatusTS (0x1 << S_StatusTS) +#define S_StatusSR 20 /* Denote soft reset (R/W) */ +#define M_StatusSR (0x1 << S_StatusSR) +#define S_StatusNMI 19 +#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ +#define S_StatusIM 8 /* Interrupt mask (R/W) */ +#define M_StatusIM (0xff << S_StatusIM) +#define S_StatusIM7 15 +#define M_StatusIM7 (0x1 << S_StatusIM7) +#define S_StatusIM6 14 +#define M_StatusIM6 (0x1 << S_StatusIM6) +#define S_StatusIM5 13 +#define M_StatusIM5 (0x1 << S_StatusIM5) +#define S_StatusIM4 12 +#define M_StatusIM4 (0x1 << S_StatusIM4) +#define S_StatusIM3 11 +#define M_StatusIM3 (0x1 << S_StatusIM3) +#define S_StatusIM2 10 +#define M_StatusIM2 (0x1 << S_StatusIM2) +#define S_StatusIM1 9 +#define M_StatusIM1 (0x1 << S_StatusIM1) +#define S_StatusIM0 8 +#define M_StatusIM0 (0x1 << S_StatusIM0) +#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ +#define M_StatusKX (0x1 << S_StatusKX) +#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ +#define M_StatusSX (0x1 << S_StatusSX) +#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ +#define M_StatusUX (0x1 << S_StatusUX) +#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ +#define M_StatusKSU (0x3 << S_StatusKSU) +#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ +#define M_StatusUM (0x1 << S_StatusUM) +#define S_StatusSM 3 /* Supervisor mode (R/W) */ +#define M_StatusSM (0x1 << S_StatusSM) +#define S_StatusERL 2 /* Denotes error level (R/W) */ +#define M_StatusERL (0x1 << S_StatusERL) +#define S_StatusEXL 1 /* Denotes exception level (R/W) */ +#define M_StatusEXL (0x1 << S_StatusEXL) +#define S_StatusIE 0 /* Enables interrupts (R/W) */ +#define M_StatusIE (0x1 << S_StatusIE) + +#define M_Status0Fields 0x00040000 +#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ +#define M_Status0Fields64 0x00040000 +#define M_StatusRFields64 0x00000000 + +/* + * Values in the KSU field + */ +#define K_StatusKSU_U 2 /* User mode in KSU field */ +#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ +#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ + + +/* + ************************************************************************ + * C A U S E R E G I S T E R ( 1 3 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | + * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause + * | | | | | | | |7|6|5|4|3|2|1|0| | | v | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Cause $13 +#define R_C0_Cause 13 +#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_CauseBD 31 +#define M_CauseBD (0x1 << S_CauseBD) +#define S_CauseCE 28 +#define M_CauseCE (0x3<< S_CauseCE) +#define S_CauseIV 23 +#define M_CauseIV (0x1 << S_CauseIV) +#define S_CauseWP 22 +#define M_CauseWP (0x1 << S_CauseWP) +#define S_CauseIP 8 +#define M_CauseIP (0xff << S_CauseIP) +#define S_CauseIPEXT 10 +#define M_CauseIPEXT (0x3f << S_CauseIPEXT) +#define S_CauseIP7 15 +#define M_CauseIP7 (0x1 << S_CauseIP7) +#define S_CauseIP6 14 +#define M_CauseIP6 (0x1 << S_CauseIP6) +#define S_CauseIP5 13 +#define M_CauseIP5 (0x1 << S_CauseIP5) +#define S_CauseIP4 12 +#define M_CauseIP4 (0x1 << S_CauseIP4) +#define S_CauseIP3 11 +#define M_CauseIP3 (0x1 << S_CauseIP3) +#define S_CauseIP2 10 +#define M_CauseIP2 (0x1 << S_CauseIP2) +#define S_CauseIP1 9 +#define M_CauseIP1 (0x1 << S_CauseIP1) +#define S_CauseIP0 8 +#define M_CauseIP0 (0x1 << S_CauseIP0) +#define S_CauseExcCode 2 +#define M_CauseExcCode (0x1f << S_CauseExcCode) + +#define M_Cause0Fields 0x4f3f0083 +#define M_CauseRFields 0xb000fc7c + +/* + * Values in the CE field + */ +#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ +#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ +#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ +#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ + +/* + * Values in the ExcCode field + */ +#define EX_INT 0 /* Interrupt */ +#define EXC_INT (EX_INT << S_CauseExcCode) +#define EX_MOD 1 /* TLB modified */ +#define EXC_MOD (EX_MOD << S_CauseExcCode) +#define EX_TLBL 2 /* TLB exception (load or ifetch) */ +#define EXC_TLBL (EX_TLBL << S_CauseExcCode) +#define EX_TLBS 3 /* TLB exception (store) */ +#define EXC_TLBS (EX_TLBS << S_CauseExcCode) +#define EX_ADEL 4 /* Address error (load or ifetch) */ +#define EXC_ADEL (EX_ADEL << S_CauseExcCode) +#define EX_ADES 5 /* Address error (store) */ +#define EXC_ADES (EX_ADES << S_CauseExcCode) +#define EX_IBE 6 /* Instruction Bus Error */ +#define EXC_IBE (EX_IBE << S_CauseExcCode) +#define EX_DBE 7 /* Data Bus Error */ +#define EXC_DBE (EX_DBE << S_CauseExcCode) +#define EX_SYS 8 /* Syscall */ +#define EXC_SYS (EX_SYS << S_CauseExcCode) +#define EX_SYSCALL EX_SYS +#define EXC_SYSCALL EXC_SYS +#define EX_BP 9 /* Breakpoint */ +#define EXC_BP (EX_BP << S_CauseExcCode) +#define EX_BREAK EX_BP +#define EXC_BREAK EXC_BP +#define EX_RI 10 /* Reserved instruction */ +#define EXC_RI (EX_RI << S_CauseExcCode) +#define EX_CPU 11 /* CoProcessor Unusable */ +#define EXC_CPU (EX_CPU << S_CauseExcCode) +#define EX_OV 12 /* OVerflow */ +#define EXC_OV (EX_OV << S_CauseExcCode) +#define EX_TR 13 /* Trap instruction */ +#define EXC_TR (EX_TR << S_CauseExcCode) +#define EX_TRAP EX_TR +#define EXC_TRAP EXC_TR +#define EX_FPE 15 /* floating point exception */ +#define EXC_FPE (EX_FPE << S_CauseExcCode) +#define EX_C2E 18 /* COP2 exception */ +#define EXC_C2E (EX_C2E << S_CauseExcCode) +#define EX_MDMX 22 /* MDMX exception */ +#define EXC_MDMX (EX_MDMX << S_CauseExcCode) +#define EX_WATCH 23 /* Watch exception */ +#define EXC_WATCH (EX_WATCH << S_CauseExcCode) +#define EX_MCHECK 24 /* Machine check exception */ +#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) +#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ +#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) + + +/* + ************************************************************************ + * E P C R E G I S T E R ( 1 4 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Exception PC | EPC + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EPC $14 +#define R_C0_EPC 14 + +#define M_EPC0Fields 0x00000000 +#define M_EPCRFields 0x00000000 +#define M_EPC0Fields64 UNS64Const(0x0000000000000000) +#define M_EPCRFields64 UNS64Const(0x0000000000000000) + +/* + ************************************************************************ + * P R I D R E G I S T E R ( 1 5 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Company Opts | Company ID | Procesor ID | Revision | PRId + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_PRId $15 +#define R_C0_PRId 15 +#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_PRIdCoOpt 24 /* Company options (R) */ +#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) +#define S_PRIdCoID 16 /* Company ID (R) */ +#define M_PRIdCoID (0xff << S_PRIdCoID) +#define S_PRIdImp 8 /* Implementation ID (R) */ +#define M_PRIdImp (0xff << S_PRIdImp) +#define S_PRIdRev 0 /* Revision (R) */ +#define M_PRIdRev (0xff << S_PRIdRev) + +#define M_PRId0Fields 0x00000000 +#define M_PRIdRFields 0xffffffff +/* + * Values in the Company ID field + */ +#define K_PRIdCoID_MIPS 1 +#define K_PRIdCoID_Broadcom 2 +#define K_PRIdCoID_Alchemy 3 +#define K_PRIdCoID_SiByte 4 +#define K_PRIdCoID_SandCraft 5 +#define K_PRIdCoID_Philips 6 +#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ + + +/* + * Values in the implementation number field + */ +#define K_PRIdImp_Jade 0x80 +#define K_PRIdImp_Opal 0x81 +#define K_PRIdImp_Ruby 0x82 +#define K_PRIdImp_JadeLite 0x83 +#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ +#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ +#define K_PRIdImp_4KSc 0x86 /* Coral */ + +#define K_PRIdImp_R3000 0x01 +#define K_PRIdImp_R4000 0x04 +#define K_PRIdImp_R10000 0x09 +#define K_PRIdImp_R4300 0x0b +#define K_PRIdImp_R5000 0x23 +#define K_PRIdImp_R5200 0x28 +#define K_PRIdImp_R5400 0x54 + +/* + ************************************************************************ + * C O N F I G R E G I S T E R ( 1 6 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M| |B| A | A | | K | Config + * | | Reserved for Implementations|E| T | R | Reserved | 0 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Config $16 +#define R_C0_Config 16 +#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_ConfigMore 31 /* Additional config registers present (R) */ +#define M_ConfigMore (0x1 << S_ConfigMore) +#define S_ConfigImpl 16 /* Implementation-specific fields */ +#define M_ConfigImpl (0x7fff << S_ConfigImpl) +#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ +#define M_ConfigBE (0x1 << S_ConfigBE) +#define S_ConfigAT 13 /* Architecture type (R) */ +#define M_ConfigAT (0x3 << S_ConfigAT) +#define S_ConfigAR 10 /* Architecture revision (R) */ +#define M_ConfigAR (0x7 << S_ConfigAR) +#define S_ConfigMT 7 /* MMU Type (R) */ +#define M_ConfigMT (0x7 << S_ConfigMT) +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ +#define M_ConfigK0 (0x7 << S_ConfigK0) + +/* + * The following definitions are technically part of the "reserved for + * implementations" field, but are the semi-standard definition used in + * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 + * references. For that reason, they are included here, but may be + * overridden by true implementation-specific definitions + */ +#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigK23 (0x7 << S_ConfigK23) +#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigKU (0x7 << S_ConfigKU) + +#define M_Config0Fields 0x00000078 +#define M_ConfigRFields 0x8000ff80 + +/* + * Values in the AT field + */ +#define K_ConfigAT_MIPS32 0 /* MIPS32 */ +#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ +#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ + +/* + * Values in the MT field + */ +#define K_ConfigMT_NoMMU 0 /* No MMU */ +#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ +#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ +#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ + + +/* + ************************************************************************ + * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 + * | | | | | | | | |2|D|C|R|A|P|P| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Config1 $16,1 +#define R_C0_Config1 16 + +#define S_Config1More 31 /* Additional Config registers present (R) */ +#define M_Config1More (0x1 << S_Config1More) +#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ +#define M_Config1MMUSize (0x3f << S_Config1MMUSize) +#define S_Config1IS 22 /* Icache sets per way (R) */ +#define M_Config1IS (0x7 << S_Config1IS) +#define S_Config1IL 19 /* Icache line size (R) */ +#define M_Config1IL (0x7 << S_Config1IL) +#define S_Config1IA 16 /* Icache associativity - 1 (R) */ +#define M_Config1IA (0x7 << S_Config1IA) +#define S_Config1DS 13 /* Dcache sets per way (R) */ +#define M_Config1DS (0x7 << S_Config1DS) +#define S_Config1DL 10 /* Dcache line size (R) */ +#define M_Config1DL (0x7 << S_Config1DL) +#define S_Config1DA 7 /* Dcache associativity (R) */ +#define M_Config1DA (0x7 << S_Config1DA) +#define S_Config1C2 6 /* Coprocessor 2 present (R) */ +#define M_Config1C2 (0x1 << S_Config1C2) +#define S_Config1MD 5 /* Denotes MDMX present (R) */ +#define M_Config1MD (0x1 << S_Config1MD) +#define S_Config1PC 4 /* Denotes performance counters present (R) */ +#define M_Config1PC (0x1 << S_Config1PC) +#define S_Config1WR 3 /* Denotes watch registers present (R) */ +#define M_Config1WR (0x1 << S_Config1WR) +#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ +#define M_Config1CA (0x1 << S_Config1CA) +#define S_Config1EP 1 /* Denotes EJTAG present (R) */ +#define M_Config1EP (0x1 << S_Config1EP) +#define S_Config1FP 0 /* Denotes floating point present (R) */ +#define M_Config1FP (0x1 << S_Config1FP) + +#define M_Config10Fields 0x00000060 +#define M_Config1RFields 0x7fffff9f + +/* + * The following macro generates a table that is indexed + * by the Icache or Dcache sets field in Config1 and + * contains the decoded value of sets per way + */ +#define Config1CacheSets() \ + HALF(64); \ + HALF(128); \ + HALF(256); \ + HALF(512); \ + HALF(1024); \ + HALF(2048); \ + HALF(4096); \ + HALF(8192); + +/* + * The following macro generates a table that is indexed + * by the Icache or Dcache line size field in Config1 and + * contains the decoded value of the cache line size, in bytes + */ +#define Config1CacheLineSize() \ + HALF(0); \ + HALF(4); \ + HALF(8); \ + HALF(16); \ + HALF(32); \ + HALF(64); \ + HALF(128); \ + HALF(256); + + +/* + ************************************************************************ + * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M| | | | | | | | | | | | |S|T| Config1 + * | | | | | | | | | | | | | |M|L| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Config2 $16,2 +#define R_C0_Config2 16 + +#define S_Config2More 31 /* Additional Config registers present (R) */ +#define M_Config2More (0x1 << S_Config2More) +#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ +#define M_Config2SM (0x1 << S_Config2SM) +#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ +#define M_Config2TL (0x1 << S_Config2TL) + +#define M_Config20Fields 0xfffffffc +#define M_Config2RFields 0x00000003 + +/* + ************************************************************************ + * L L A D D R R E G I S T E R ( 1 7 ) * + ************************************************************************ + * + * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // LL Physical Address | LLAddr + * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_LLAddr $17 +#define R_C0_LLAddr 17 +#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_LLAddr0Fields 0x00000000 +#define M_LLAddrRFields 0x00000000 +#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************ + * W A T C H L O R E G I S T E R ( 1 8 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Watch Virtual Address |I|R|W| WatchLo + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_WatchLo $18 +#define R_C0_WatchLo 18 +#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ +#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) +#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ +#define M_WatchLoI (0x1 << S_WatchLoI) +#define S_WatchLoR 1 /* Enable data read watch (R/W) */ +#define M_WatchLoR (0x1 << S_WatchLoR) +#define S_WatchLoW 0 /* Enable data write watch (R/W) */ +#define M_WatchLoW (0x1 << S_WatchLoW) + +#define M_WatchLo0Fields 0x00000000 +#define M_WatchLoRFields 0x00000000 +#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) +#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) + +#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) + + +/* + ************************************************************************ + * W A T C H H I R E G I S T E R ( 1 9 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_WatchHi $19 +#define R_C0_WatchHi 19 +#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ +#define M_WatchHiM (0x1 << S_WatchHiM) +#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ +#define M_WatchHiG (0x1 << S_WatchHiG) +#define S_WatchHiASID 16 /* ASID value to match (R/W) */ +#define M_WatchHiASID (0xff << S_WatchHiASID) +#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ +#define M_WatchHiMask (0x1ff << S_WatchHiMask) + +#define M_WatchHi0Fields 0x3f00f007 +#define M_WatchHiRFields 0x80000000 + + +/* + ************************************************************************ + * X C O N T E X T R E G I S T E R ( 2 0 ) * + ************************************************************************ + * + * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_XContext $20 +#define R_C0_XContext 20 +#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ +#define S_XContextBadVPN S_XContextBadVPN2 + +#define M_XContext0Fields 0x0000000f + + +/* + ************************************************************************ + * D E B U G R E G I S T E R ( 2 3 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| + * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| + * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| + * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug + * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | + * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | + * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | + * | | | | | | | | | | | | |r|r| | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Debug $23 /* EJTAG */ +#define R_C0_Debug 23 + +#define S_DebugDBD 31 /* Debug branch delay (R) */ +#define M_DebugDBD (0x1 << S_DebugDBD) +#define S_DebugDM 30 /* Debug mode (R) */ +#define M_DebugDM (0x1 << S_DebugDM) +#define S_DebugNoDCR 29 /* No debug control register present (R) */ +#define M_DebugNoDCR (0x1 << S_DebugNoDCR) +#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ +#define M_DebugLSNM (0x1 << S_DebugLSNM) +#define S_DebugDoze 27 /* Doze (R) */ +#define M_DebugDoze (0x1 << S_DebugDoze) +#define S_DebugHalt 26 /* Halt (R) */ +#define M_DebugHalt (0x1 << S_DebugHalt) +#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ +#define M_DebugCountDM (0x1 << S_DebugCountDM) +#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ +#define M_DebugIBusEP (0x1 << S_DebugIBusEP) +#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ +#define M_DebugMCheckP (0x1 << S_DebugMCheckP) +#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ +#define M_DebugCacheEP (0x1 << S_DebugCacheEP) +#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ +#define M_DebugDBusEP (0x1 << S_DebugDBusEP) +#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ +#define M_DebugIEXI (0x1 << S_DebugIEXI) +#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ +#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) +#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ +#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) +#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ +#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) +#define S_DebugDExcCode 10 /* Debug exception code (R) */ +#define M_DebugDExcCode (0x1f << S_DebugDExcCode) +#define S_DebugNoSSt 9 /* No single step implemented (R) */ +#define M_DebugNoSSt (0x1 << S_DebugNoSSt) +#define S_DebugSSt 8 /* Single step enable (R/W) */ +#define M_DebugSSt (0x1 << S_DebugSSt) +#define S_DebugDINT 5 /* Debug interrupt (R) */ +#define M_DebugDINT (0x1 << S_DebugDINT) +#define S_DebugDIB 4 /* Debug instruction break (R) */ +#define M_DebugDIB (0x1 << S_DebugDIB) +#define S_DebugDDBS 3 /* Debug data break store (R) */ +#define M_DebugDDBS (0x1 << S_DebugDDBS) +#define S_DebugDDBL 2 /* Debug data break load (R) */ +#define M_DebugDDBL (0x1 << S_DebugDDBL) +#define S_DebugDBp 1 /* Debug breakpoint (R) */ +#define M_DebugDBp (0x1 << S_DebugDBp) +#define S_DebugDSS 0 /* Debug single step (R) */ +#define M_DebugDSS (0x1 << S_DebugDSS) + +#define M_Debug0Fields 0x01f000c0 +#define M_DebugRFields 0xec0ffe3f + + +/* + ************************************************************************ + * D E P C R E G I S T E R ( 2 4 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // EJTAG Debug Exception PC | DEPC + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + + +#define C0_DEPC $24 +#define R_C0_DEPC 24 + +#define M_DEEPC0Fields 0x00000000 +#define M_DEEPCRFields 0x00000000 +#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************ + * P E R F C N T R E G I S T E R ( 2 5 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | |I| | | |E| + * |M| 0 | Event |E|U|S|K|X| PerfCnt + * | | | | | | | |L| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Event Count | PerfCnt + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_PerfCnt $25 +#define R_C0_PerfCnt 25 +#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_PerfCntM 31 /* More performance counters exist (R) */ +#define M_PerfCntM (1 << S_PerfCntM) +#define S_PerfCntEvent 5 /* Enabled event (R/W) */ +#define M_PerfCntEvent (0x3f << S_PerfCntEvent) +#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ +#define M_PerfCntIE (1 << S_PerfCntIE) +#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ +#define M_PerfCntU (1 << S_PerfCntU) +#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ +#define M_PerfCntS (1 << S_PerfCntS) +#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ +#define M_PerfCntK (1 << S_PerfCntK) +#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ +#define M_PerfCntEXL (1 << S_PerfCntEXL) + +#define M_PerfCnt0Fields 0x7ffff800 +#define M_PerfCntRFields 0x80000000 + + +/* + ************************************************************************ + * E R R C T L R E G I S T E R ( 2 6 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Error Control | ErrCtl + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_ErrCtl $26 +#define R_C0_ErrCtl 26 +#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_ErrCtl0Fields 0x00000000 +#define M_ErrCtlRFields 0x00000000 + + +/* + ************************************************************************ + * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Cache Error Control | CacheErr + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_CacheErr $27 +#define R_C0_CacheErr 27 +#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_CacheErr0Fields 0x00000000 +#define M_CachErrRFields 0x00000000 + + +/* + ************************************************************************ + * T A G L O R E G I S T E R ( 2 8 ) * TagLo + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | TagLo | TagLo + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_TagLo $28 +#define R_C0_TagLo 28 +#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ + +/* + * Some implementations use separate TagLo registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_ITagLo $28,0 +#define C0_DTagLo $28,2 + +#define M_TagLo0Fields 0x00000000 +#define M_TagLoRFields 0x00000000 + + +/* + ************************************************************************ + * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | DataLo | DataLo + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_DataLo $28,1 +#define R_C0_DataLo 28 + +/* + * Some implementations use separate DataLo registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_IDataLo $28,1 +#define C0_DDataLo $28,3 + +#define M_DataLo0Fields 0x00000000 +#define M_DataLoRFields 0xffffffff + + +/* + ************************************************************************ + * T A G H I R E G I S T E R ( 2 9 ) * TagHi + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | TagHi | TagHi + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_TagHi $29 +#define R_C0_TagHi 29 +#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ + +/* + * Some implementations use separate TagHi registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_ITagHi $29,0 +#define C0_DTagHi $29,2 + +#define M_TagHi0Fields 0x00000000 +#define M_TagHiRFields 0x00000000 + + +/* + ************************************************************************ + * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | DataHi | DataHi + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_DataHi $29,1 +#define R_C0_DataHi 29 + +/* + * Some implementations use separate DataHi registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_IDataHi $29,1 +#define C0_DDataHi $29,3 + +#define M_DataHi0Fields 0x00000000 +#define M_DataHiRFields 0xffffffff + + +/* + ************************************************************************ + * E R R O R E P C R E G I S T E R ( 3 0 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Error PC | ErrorEPC + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_ErrorEPC $30 +#define R_C0_ErrorEPC 30 +#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_ErrorEPC0Fields 0x00000000 +#define M_ErrorEPCRFields 0x00000000 +#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************ + * D E S A V E R E G I S T E R ( 3 1 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // EJTAG Register Save Value | DESAVE + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_DESAVE $31 +#define R_C0_DESAVE 31 + +#define M_DESAVE0Fields 0x00000000 +#define M_DESAVERFields 0x00000000 +#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) +#define M_DESAVERFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************* + * C P 1 R E G I S T E R D E F I N I T I O N S * + ************************************************************************* + */ + + +/* + ************************************************************************* + * H A R D W A R E F P R N A M E S * + ************************************************************************* + */ + +#define fp0 $f0 +#define fp1 $f1 +#define fp2 $f2 +#define fp3 $f3 +#define fp4 $f4 +#define fp5 $f5 +#define fp6 $f6 +#define fp7 $f7 +#define fp8 $f8 +#define fp9 $f9 +#define fp10 $f10 +#define fp11 $f11 +#define fp12 $f12 +#define fp13 $f13 +#define fp14 $f14 +#define fp15 $f15 +#define fp16 $f16 +#define fp17 $f17 +#define fp18 $f18 +#define fp19 $f19 +#define fp20 $f20 +#define fp21 $f21 +#define fp22 $f22 +#define fp23 $f23 +#define fp24 $f24 +#define fp25 $f25 +#define fp26 $f26 +#define fp27 $f27 +#define fp28 $f28 +#define fp29 $f29 +#define fp30 $f30 +#define fp31 $f31 + +/* + * The following definitions are used to convert an FPR name + * into the corresponding even or odd name, respectively. + * This is used in macro substitution in the AVPs. + */ + +#define fp1_even $f0 +#define fp3_even $f2 +#define fp5_even $f4 +#define fp7_even $f6 +#define fp9_even $f8 +#define fp11_even $f10 +#define fp13_even $f12 +#define fp15_even $f14 +#define fp17_even $f16 +#define fp19_even $f18 +#define fp21_even $f20 +#define fp23_even $f22 +#define fp25_even $f24 +#define fp27_even $f26 +#define fp29_even $f28 +#define fp31_even $f30 + +#define fp0_odd $f1 +#define fp2_odd $f3 +#define fp4_odd $f5 +#define fp6_odd $f7 +#define fp8_odd $f9 +#define fp10_odd $f11 +#define fp12_odd $f13 +#define fp14_odd $f15 +#define fp16_odd $f17 +#define fp18_odd $f19 +#define fp20_odd $f21 +#define fp22_odd $f23 +#define fp24_odd $f25 +#define fp26_odd $f27 +#define fp28_odd $f29 +#define fp30_odd $f31 + + +/* + ************************************************************************* + * H A R D W A R E F P R I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the FPR, as opposed + * to the assembler register name ($n). + */ + +#define R_fp0 0 +#define R_fp1 1 +#define R_fp2 2 +#define R_fp3 3 +#define R_fp4 4 +#define R_fp5 5 +#define R_fp6 6 +#define R_fp7 7 +#define R_fp8 8 +#define R_fp9 9 +#define R_fp10 10 +#define R_fp11 11 +#define R_fp12 12 +#define R_fp13 13 +#define R_fp14 14 +#define R_fp15 15 +#define R_fp16 16 +#define R_fp17 17 +#define R_fp18 18 +#define R_fp19 19 +#define R_fp20 20 +#define R_fp21 21 +#define R_fp22 22 +#define R_fp23 23 +#define R_fp24 24 +#define R_fp25 25 +#define R_fp26 26 +#define R_fp27 27 +#define R_fp28 28 +#define R_fp29 29 +#define R_fp30 30 +#define R_fp31 31 + + +/* + ************************************************************************* + * H A R D W A R E F C R N A M E S * + ************************************************************************* + */ + +#define fc0 $0 +#define fc25 $25 +#define fc26 $26 +#define fc28 $28 +#define fc31 $31 + + +/* + ************************************************************************* + * H A R D W A R E F C R I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the FCR, as opposed + * to the assembler register name ($n). + */ + +#define R_fc0 0 +#define R_fc25 25 +#define R_fc26 26 +#define R_fc28 28 +#define R_fc31 31 + + +/* + ************************************************************************* + * H A R D W A R E F C C N A M E S * + ************************************************************************* + */ + +#define cc0 $fcc0 +#define cc1 $fcc1 +#define cc2 $fcc2 +#define cc3 $fcc3 +#define cc4 $fcc4 +#define cc5 $fcc5 +#define cc6 $fcc6 +#define cc7 $fcc7 + + +/* + ************************************************************************* + * H A R D W A R E F C C I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the CC, as opposed + * to the assembler register name ($n). + */ + +#define R_cc0 0 +#define R_cc1 1 +#define R_cc2 2 +#define R_cc3 3 +#define R_cc4 4 +#define R_cc5 5 +#define R_cc6 6 +#define R_cc7 7 + + +/* + ************************************************************************ + * I M P L E M E N T A T I O N R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR + * | Configuration Bits |D|S| | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FIR $0 +#define R_C1_FIR 0 + +#define S_FIRConfigS 16 +#define M_FIRConfigS (0x1 << S_FIRConfigS) +#define S_FIRConfigD 17 +#define M_FIRConfigD (0x1 << S_FIRConfigD) +#define S_FIRConfigPS 18 +#define M_FIRConfigPS (0x1 << S_FIRConfigPS) +#define S_FIRConfig3D 19 +#define M_FIRConfig3D (0x1 << S_FIRConfig3D) +#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) + +#define S_FIRImp 8 +#define M_FIRImp (0xff << S_FIRImp) + +#define S_FIRRev 0 +#define M_FIRRev (0xff << S_FIRRev) + +#define M_FIR0Fields 0xfff00000 +#define M_FIRRFields 0x000fffff + +/* + ************************************************************************ + * C O N D I T I O N C O D E S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | CC | FCCR + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FCCR $25 +#define R_C1_FCCR 25 + +#define S_FCCRCC 0 +#define M_FCCRCC (0xff << S_FCCRCC) +#define S_FCCRCC7 7 +#define M_FCCRCC7 (0x1 << S_FCCRCC7) +#define S_FCCRCC6 6 +#define M_FCCRCC6 (0x1 << S_FCCRCC6) +#define S_FCCRCC5 5 +#define M_FCCRCC5 (0x1 << S_FCCRCC5) +#define S_FCCRCC4 4 +#define M_FCCRCC4 (0x1 << S_FCCRCC4) +#define S_FCCRCC3 3 +#define M_FCCRCC3 (0x1 << S_FCCRCC3) +#define S_FCCRCC2 2 +#define M_FCCRCC2 (0x1 << S_FCCRCC2) +#define S_FCCRCC1 1 +#define M_FCCRCC1 (0x1 << S_FCCRCC1) +#define S_FCCRCC0 0 +#define M_FCCRCC0 (0x1 << S_FCCRCC0) + +#define M_FCCR0Fields 0xffffff00 +#define M_FCCRRFields 0x000000ff + + +/* + ************************************************************************ + * E X C E P T I O N S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Cause | 0 | Flags | 0 | FEXR + * | |E|V|Z|O|U|I| |V|Z|O|U|I| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FEXR $26 +#define R_C1_FEXR 26 + +#define S_FEXRExc 12 +#define M_FEXRExc (0x3f << S_FEXRExc) +#define S_FEXRExcE 17 +#define M_FEXRExcE (0x1 << S_FEXRExcE) +#define S_FEXRExcV 16 +#define M_FEXRExcV (0x1 << S_FEXRExcV) +#define S_FEXRExcZ 15 +#define M_FEXRExcZ (0x1 << S_FEXRExcZ) +#define S_FEXRExcO 14 +#define M_FEXRExcO (0x1 << S_FEXRExcO) +#define S_FEXRExcU 13 +#define M_FEXRExcU (0x1 << S_FEXRExcU) +#define S_FEXRExcI 12 +#define M_FEXRExcI (0x1 << S_FEXRExcI) + +#define S_FEXRFlg 2 +#define M_FEXRFlg (0x1f << S_FEXRFlg) +#define S_FEXRFlgV 6 +#define M_FEXRFlgV (0x1 << S_FEXRFlgV) +#define S_FEXRFlgZ 5 +#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) +#define S_FEXRFlgO 4 +#define M_FEXRFlgO (0x1 << S_FEXRFlgO) +#define S_FEXRFlgU 3 +#define M_FEXRFlgU (0x1 << S_FEXRFlgU) +#define S_FEXRFlgI 2 +#define M_FEXRFlgI (0x1 << S_FEXRFlgI) + +#define M_FEXR0Fields 0xfffc0f83 +#define M_FEXRRFields 0x00000000 + + +/* + ************************************************************************ + * E N A B L E S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Enables | 0 |F|RM | FENR + * | |V|Z|O|U|I| |S| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FENR $28 +#define R_C1_FENR 28 + +#define S_FENREna 7 +#define M_FENREna (0x1f << S_FENREna) +#define S_FENREnaV 11 +#define M_FENREnaV (0x1 << S_FENREnaV) +#define S_FENREnaZ 10 +#define M_FENREnaZ (0x1 << S_FENREnaZ) +#define S_FENREnaO 9 +#define M_FENREnaO (0x1 << S_FENREnaO) +#define S_FENREnaU 8 +#define M_FENREnaU (0x1 << S_FENREnaU) +#define S_FENREnaI 7 +#define M_FENREnaI (0x1 << S_FENREnaI) + +#define S_FENRFS 2 +#define M_FENRFS (0x1 << S_FENRFS) + +#define S_FENRRM 0 +#define M_FENRRM (0x3 << S_FENRRM) + +#define M_FENR0Fields 0xfffff078 +#define M_FENRRFields 0x00000000 + + +/* + ************************************************************************ + * C O N T R O L / S T A T U S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR + * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FCSR $31 +#define R_C1_FCSR 31 + +#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ +#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) +#define S_FCSRCC7 31 +#define M_FCSRCC7 (0x1 << S_FCSRCC7) +#define S_FCSRCC6 30 +#define M_FCSRCC6 (0x1 << S_FCSRCC6) +#define S_FCSRCC5 29 +#define M_FCSRCC5 (0x1 << S_FCSRCC5) +#define S_FCSRCC4 28 +#define M_FCSRCC4 (0x1 << S_FCSRCC4) +#define S_FCSRCC3 27 +#define M_FCSRCC3 (0x1 << S_FCSRCC3) +#define S_FCSRCC2 26 +#define M_FCSRCC2 (0x1 << S_FCSRCC2) +#define S_FCSRCC1 25 +#define M_FCSRCC1 (0x1 << S_FCSRCC1) + +#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ +#define M_FCSRFS (0x1 << S_FCSRFS) + +#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ +#define M_FCSRCC0 (0x1 << S_FCSRCC0) +#define S_FCSRCC S_FCSRCC0 +#define M_FCSRCC M_FCSRCC0 + +#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ +#define M_FCSRImpl (0x3 << S_FCSRImpl) + +#define S_FCSRExc 12 /* Exception cause (R/W) */ +#define M_FCSRExc (0x3f << S_FCSRExc) +#define S_FCSRExcE 17 +#define M_FCSRExcE (0x1 << S_FCSRExcE) +#define S_FCSRExcV 16 +#define M_FCSRExcV (0x1 << S_FCSRExcV) +#define S_FCSRExcZ 15 +#define M_FCSRExcZ (0x1 << S_FCSRExcZ) +#define S_FCSRExcO 14 +#define M_FCSRExcO (0x1 << S_FCSRExcO) +#define S_FCSRExcU 13 +#define M_FCSRExcU (0x1 << S_FCSRExcU) +#define S_FCSRExcI 12 +#define M_FCSRExcI (0x1 << S_FCSRExcI) + +#define S_FCSREna 7 /* Exception enable (R/W) */ +#define M_FCSREna (0x1f << S_FCSREna) +#define S_FCSREnaV 11 +#define M_FCSREnaV (0x1 << S_FCSREnaV) +#define S_FCSREnaZ 10 +#define M_FCSREnaZ (0x1 << S_FCSREnaZ) +#define S_FCSREnaO 9 +#define M_FCSREnaO (0x1 << S_FCSREnaO) +#define S_FCSREnaU 8 +#define M_FCSREnaU (0x1 << S_FCSREnaU) +#define S_FCSREnaI 7 +#define M_FCSREnaI (0x1 << S_FCSREnaI) + +#define S_FCSRFlg 2 /* Exception flags (R/W) */ +#define M_FCSRFlg (0x1f << S_FCSRFlg) +#define S_FCSRFlgV 6 +#define M_FCSRFlgV (0x1 << S_FCSRFlgV) +#define S_FCSRFlgZ 5 +#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) +#define S_FCSRFlgO 4 +#define M_FCSRFlgO (0x1 << S_FCSRFlgO) +#define S_FCSRFlgU 3 +#define M_FCSRFlgU (0x1 << S_FCSRFlgU) +#define S_FCSRFlgI 2 +#define M_FCSRFlgI (0x1 << S_FCSRFlgI) + +#define S_FCSRRM 0 /* Rounding mode (R/W) */ +#define M_FCSRRM (0x3 << S_FCSRRM) + +#define M_FCSR0Fields 0x001c0000 +#define M_FCSRRFields 0x00000000 + +/* + * Values in the rounding mode field (of both FCSR and FCCR) + */ +#define K_FCSRRM_RN 0 +#define K_FCSRRM_RZ 1 +#define K_FCSRRM_RP 2 +#define K_FCSRRM_RM 3 + +#endif /* _COMMON_MIPS_DEF_H_ */ diff --git a/libcpu/mips/xburst/stack.h b/bsp/x1000/cpu/common/mips_excpt.h similarity index 57% rename from libcpu/mips/xburst/stack.h rename to bsp/x1000/cpu/common/mips_excpt.h index 5bb7206c11..868b046d3c 100644 --- a/libcpu/mips/xburst/stack.h +++ b/bsp/x1000/cpu/common/mips_excpt.h @@ -1,6 +1,7 @@ /* - * File : stack.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * File : mips_excpt.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,11 +19,21 @@ * * Change Logs: * Date Author Notes -*/ + * 201697 Urey the first version + */ -#ifndef __STACK_H__ -#define __STACK_H__ +#ifndef _MIPS_EXCPT_H_ +#define _MIPS_EXCPT_H_ -#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ +#include "mips_regs.h" -#endif +#ifndef __ASSEMBLY__ +typedef void (* exception_func_t)(mips_reg_ctx *regs); + +//extern exception_func_t mips_exception_handlers[]; + +int rt_hw_exception_init(void); +exception_func_t rt_set_except_vector(int n, exception_func_t func); +void install_default_execpt_handle(void); +#endif /* __ASSEMBLY__ */ +#endif /* _MIPS_EXCPT_H_ */ diff --git a/bsp/x1000/cpu/common/mips_regs.h b/bsp/x1000/cpu/common/mips_regs.h new file mode 100644 index 0000000000..7ea07d3869 --- /dev/null +++ b/bsp/x1000/cpu/common/mips_regs.h @@ -0,0 +1,1168 @@ +/* + * File : mips_regs.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 201697 Urey the first version + */ + +#ifndef _MIPS_REGS_H_ +#define _MIPS_REGS_H_ + + +#if !defined(__ASSEMBLY__) && !defined(ASSEMBLY) +#include + +#define MIPS_REG_NR 32 +typedef struct { + rt_uint32_t regs[MIPS_REG_NR]; /* 32 ͨĿļĴ */ + rt_uint32_t CP0Status; /* CP0 Э״̬Ĵ */ + rt_uint32_t CP0DataHI; /* λĴ */ + rt_uint32_t CP0DataLO; /* λĴ */ + rt_uint32_t CP0BadVAddr; /* ַĴ */ + rt_uint32_t CP0Cause; /* жϻ쳣鿴ļĴ*/ + rt_uint32_t CP0EPC; /* Ĵ */ +} mips_reg_ctx; + +#define MIPS_ARG_REG_NR 4 +typedef struct +{ + rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 Ĵ */ +} mips_arg_ctx; + +struct linkctx +{ + rt_uint32_t id; + struct linkctx *next; +}; + +struct fpctx +{ + struct linkctx link; + rt_uint32_t fcsr; + rt_uint32_t reserved; +}; + + +struct fp32ctx +{ + struct fpctx fp; + union + { + double d[16]; /* even doubles */ + float s[32]; /* even singles, padded */ + }; +}; + +struct fp64ctx +{ + struct fpctx fp; + union + { + double d[32]; /* even doubles, followed by odd doubles */ + float s[64]; /* even singles, followed by odd singles, padded */ + }; +}; + +#endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */ + +#define MIPS_STK_CTX_WORD_SIZE 38 +#define SZREG 4 +/********************************************************************************************************* + MIPS ļĴ +*********************************************************************************************************/ +#define REG_ZERO 0 /* wired zero */ +#define REG_AT 1 /* assembler temp */ +#define REG_V0 2 /* return reg 0 */ +#define REG_V1 3 /* return reg 1 */ +#define REG_A0 4 /* arg reg 0 */ +#define REG_A1 5 /* arg reg 1 */ +#define REG_A2 6 /* arg reg 2 */ +#define REG_A3 7 /* arg reg 3 */ +#define REG_T0 8 /* caller saved 0 */ +#define REG_T1 9 /* caller saved 1 */ +#define REG_T2 10 /* caller saved 2 */ +#define REG_T3 11 /* caller saved 3 */ +#define REG_T4 12 /* caller saved 4 */ +#define REG_T5 13 /* caller saved 5 */ +#define REG_T6 14 /* caller saved 6 */ +#define REG_T7 15 /* caller saved 7 */ +#define REG_S0 16 /* callee saved 0 */ +#define REG_S1 17 /* callee saved 1 */ +#define REG_S2 18 /* callee saved 2 */ +#define REG_S3 19 /* callee saved 3 */ +#define REG_S4 20 /* callee saved 4 */ +#define REG_S5 21 /* callee saved 5 */ +#define REG_S6 22 /* callee saved 6 */ +#define REG_S7 23 /* callee saved 7 */ +#define REG_T8 24 /* caller saved 8 */ +#define REG_T9 25 /* caller saved 9 */ +#define REG_K0 26 /* kernel temp 0 */ +#define REG_K1 27 /* kernel temp 1 */ +#define REG_GP 28 /* global pointer */ +#define REG_SP 29 /* stack pointer */ +#define REG_S8 30 /* callee saved 8 */ +#define REG_FP REG_S8 /* callee saved 8 */ +#define REG_RA 31 /* return address */ + +#define STK_CTX_SIZE (MIPS_STK_CTX_WORD_SIZE * SZREG) +#define STK_OFFSET_SR ((32 + 0) * SZREG) +#define STK_OFFSET_HI ((32 + 1) * SZREG) +#define STK_OFFSET_LO ((32 + 2) * SZREG) +#define STK_OFFSET_BADVADDR ((32 + 3) * SZREG) +#define STK_OFFSET_CAUSE ((32 + 4) * SZREG) +#define STK_OFFSET_EPC ((32 + 5) * SZREG) + +#define STK_OFFSET_LAST ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG) + +#define FP32CTX_CSR ((SZREG)*2) +#define FP64CTX_CSR ((SZREG)*2) + +#define LINKCTX_ID ((SZREG)*0) +#define LINKCTX_NEXT ((SZREG)*1) +#define LINKCTX_TYPE_MSA 0x004D5341 +#define LINKCTX_TYPE_FP32 0x46503332 +#define LINKCTX_TYPE_FP64 0x46503634 +#define LINKCTX_TYPE_FMSA 0x463D5341 +#define LINKCTX_TYPE_DSP 0x00445350 +#define LINKCTX_TYPE_STKSWP 0x53574150 +#define LINKCTX_TYPE_XPA 0x00585041 + +#define FP32CTX_0 ((SZREG)*4) +#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) +#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) +#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) +#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) +#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) +#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) +#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) +#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) +#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) +#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) +#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) +#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) +#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) +#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) +#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) +#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) + +#define FP64CTX_0 ((SZREG)*4) +#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) +#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) +#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) +#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) +#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) +#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) +#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) +#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) +#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) +#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) +#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) +#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) +#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) +#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) +#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) +#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) +#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) +#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) +#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) +#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) +#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) +#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) +#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) +#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) +#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) +#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) +#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) +#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) +#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) +#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) +#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) +#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) + +#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 +#define CP0_DESAVE $31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * Values for PageMask register + */ +#ifdef CONFIG_CPU_VR41XX + +/* Why doesn't stupidity hurt ... */ + +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 + +#else + +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 + +#endif + +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU1_SHIFT 29 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + +#ifndef __ASSEMBLY__ + +#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE) +#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2)) + +/* + * Functions to access the r10k performance counter and control registers + */ +#define read_r10k_perf_cntr(counter) \ +({ unsigned int __res; \ + __asm__ __volatile__( \ + "mfpc\t%0, "STR(counter) \ + : "=r" (__res)); \ + __res;}) + +#define write_r10k_perf_cntr(counter,val) \ + __asm__ __volatile__( \ + "mtpc\t%0, "STR(counter) \ + : : "r" (val)); + +#define read_r10k_perf_cntl(counter) \ +({ unsigned int __res; \ + __asm__ __volatile__( \ + "mfps\t%0, "STR(counter) \ + : "=r" (__res)); \ + __res;}) + +#define write_r10k_perf_cntl(counter,val) \ + __asm__ __volatile__( \ + "mtps\t%0, "STR(counter) \ + : : "r" (val)); + +/* + * Macros to access the system control coprocessor + */ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ +} while (0) + +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ +} while (0) + +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ + __read_64bit_c0_register(reg, sel)) + +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ +} while (0) + +/* + * These versions are only needed for systems with more than 38 bits of + * physical address space running the 32-bit kernel. That's none atm :-) + */ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long val; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ + \ + val; \ +}) + +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) + +/* + * The WatchLo register. There may be upto 8 of them. + */ +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) + +/* + * The WatchHi register. There may be upto 8 of them. + */ +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) + +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) + +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) + +#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) +#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) + +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) + +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) + +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) + +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) + +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) + +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) + +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) + +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) + +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) + +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) + +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) + +#if 1 +/* + * Macros to access the system control coprocessor + */ +#define read_32bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define read_32bit_cp0_set1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* + * For now use this only with interrupts disabled! + */ +#define read_64bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) + +#define write_32bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_32bit_cp0_set1_register(register,value) \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_64bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ + __res;}) + +#endif +/* + * Macros to access the floating point coprocessor control registers + */ +#define read_32bit_cp1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc1\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* TLB operations. */ +static inline void tlb_probe(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); +} + +static inline void tlb_read(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); +} + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); +} + +static inline void tlb_write_random(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); +} + +/* + * Manipulate bits in a c0 register. + */ +#define __BUILD_SET_C0(name,register) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ +} + +__BUILD_SET_C0(status,CP0_STATUS) +__BUILD_SET_C0(cause,CP0_CAUSE) +__BUILD_SET_C0(config,CP0_CONFIG) + +#define set_cp0_status(x) set_c0_status(x) +#define set_cp0_cause(x) set_c0_cause(x) +#define set_cp0_config(x) set_c0_config(x) + +#endif /* !__ASSEMBLY__ */ + +#endif /* _MIPS_REGS_H_ */ diff --git a/bsp/x1000/cpu/common/mips_types.h b/bsp/x1000/cpu/common/mips_types.h new file mode 100644 index 0000000000..7f0b8a6855 --- /dev/null +++ b/bsp/x1000/cpu/common/mips_types.h @@ -0,0 +1,118 @@ +/* + * File : mips_types.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 201697 Urey the first version + */ + +#ifndef _MIPS_TYPES_H_ +#define _MIPS_TYPES_H_ + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if (_MIPS_SZLONG == 64) + +typedef __signed__ long __s64; +typedef unsigned long __u64; + +#else + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ + +#define BITS_PER_LONG _MIPS_SZLONG + + +typedef __signed char s8; +typedef unsigned char u8; + +typedef __signed short s16; +typedef unsigned short u16; + +typedef __signed int s32; +typedef unsigned int u32; + +#if (_MIPS_SZLONG == 64) + +typedef __signed__ long s64; +typedef unsigned long u64; + +#else + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long s64; +typedef unsigned long long u64; +#endif + +#endif + +#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ + || defined(CONFIG_64BIT) +typedef u64 dma_addr_t; + +typedef u64 phys_addr_t; +typedef u64 phys_size_t; + +#else +typedef u32 dma_addr_t; + +typedef u32 phys_addr_t; +typedef u32 phys_size_t; + +#endif +typedef u64 dma64_addr_t; + +/* + * Don't use phys_t. You've been warned. + */ +#ifdef CONFIG_64BIT_PHYS_ADDR +typedef unsigned long long phys_t; +#else +typedef unsigned long phys_t; +#endif + +#endif /* __ASSEMBLY__ */ + + +#endif /* _MIPS_TYPES_H_ */ diff --git a/bsp/x1000/cpu/common/mipscfg.h b/bsp/x1000/cpu/common/mipscfg.h new file mode 100644 index 0000000000..b4f30615f8 --- /dev/null +++ b/bsp/x1000/cpu/common/mipscfg.h @@ -0,0 +1,32 @@ +/* + * File : mipscfg.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#ifndef __MIPSCFG_H__ +#define __MIPSCFG_H__ + + +typedef struct mips32_core_cfg +{ + rt_uint16_t icache_line_size; + rt_uint16_t icache_lines_per_way; + rt_uint16_t icache_ways; + rt_uint16_t dcache_line_size; + rt_uint16_t dcache_lines_per_way; + rt_uint16_t dcache_ways; + + rt_uint16_t max_tlb_entries; /* number of tlb entry */ +} mips32_core_cfg_t; + +extern mips32_core_cfg_t g_mips_core; + +#endif /* end of __MIPSCFG_H__ */ diff --git a/bsp/x1000/cpu/common/mipsregs.h b/bsp/x1000/cpu/common/mipsregs.h new file mode 100644 index 0000000000..22e5754b8b --- /dev/null +++ b/bsp/x1000/cpu/common/mipsregs.h @@ -0,0 +1,706 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * Copyright (C) 2003, 2004 Maciej W. Rozycki + * + * Change Logs: + * Date Author Notes + * + */ +#ifndef __MIPSREGS_H__ +#define __MIPSREGS_H__ + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 +#define CP0_DESAVE $31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + + +/* FS/FO/FN */ +#define FPU_CSR_FS 0x01000000 +#define FPU_CSR_FO 0x00400000 +#define FPU_CSR_FN 0x00200000 + +/* + * Bits 18 - 20 of the FPU Status Register will be read as 0, + * and should be written as zero. + */ +#define FPU_CSR_RSVD 0x001c0000 + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate + * cacheops in userspace. This bit exists only on RM7000 and RM9000 + * processors. + */ +#define ST0_CO 0x08000000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Enable the MIPS DSP ASE + */ +#define ST0_MX 0x01000000 + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. + */ +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS (_ULCAST_(7) << 22) +#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) + +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) +#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) +#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) +#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF2_TU (_ULCAST_(7) << 28) + +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. + */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which privilege mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + + +#ifndef __ASSEMBLY__ + +/* + * Macros to access the system control coprocessor + */ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + +#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_32bit_c0_register($4, 0) +#define write_c0_context(val) __write_32bit_c0_register($4, 0, val) + +#define read_c0_userlocal() __read_32bit_c0_register($4, 2) +#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) +#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ +#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) + +#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ +#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) + +#define read_c0_entryhi() __read_32bit_c0_register($10, 0) +#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ +#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) + +#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ +#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_epc() __read_32bit_c0_register($14, 0) +#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) + + +/* + * Macros to access the floating point coprocessor control registers + */ +#define read_32bit_cp1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + /* gas fails to assemble cfc1 for some archs (octeon).*/ \ + ".set\tmips1\n\t" \ + "cfc1\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) +#define write_32bit_cp1_register(register, value) \ +do { \ + __asm__ __volatile__( \ + "ctc1\t%z0, "STR(register)"\n\t" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +#define read_c1_status() read_32bit_cp1_register(CP1_STATUS) +#define read_c1_revision() read_32bit_cp1_register(CP1_REVISION); +#define write_c1_status(val) write_32bit_cp1_register(CP1_STATUS, val) + + +#endif /* end of __ASSEMBLY__ */ + +#endif /* end of __MIPSREGS_H__ */ + diff --git a/bsp/x1000/cpu/common/stackframe.h b/bsp/x1000/cpu/common/stackframe.h new file mode 100644 index 0000000000..96b69ab14f --- /dev/null +++ b/bsp/x1000/cpu/common/stackframe.h @@ -0,0 +1,228 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle + * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki + */ +#ifndef __STACKFRAME_H__ +#define __STACKFRAME_H__ + +#include "asm.h" +#include "mipsregs.h" + +/* + * Stack layout for the INT exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ + +//#define PT_R0 (PTRSIZE*6) /* 0 */ +#define PT_R0 (0) /* 0 */ +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ +#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ + +#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + + + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop + .endm + + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + LONG_S v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + LONG_S v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) + .endm + + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) + .endm + + .macro get_saved_sp + nop + .endm + + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp +8: move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + mfc0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + mfc0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop + .endm + + .macro SAVE_ALL + SAVE_SOME + SAVE_AT + SAVE_TEMP + SAVE_STATIC + .endm + + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop + .endm + + .macro RESTORE_TEMP + LONG_L $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + LONG_L $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) + .endm + + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) + .endm + + .macro RESTORE_SOME + .set push + .set reorder + .set noat + LONG_L v0, PT_STATUS(sp) + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop + .endm + + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + .set mips3 + eret + .set mips0 + .endm + + + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) + .endm + + .macro RESTORE_ALL + RESTORE_TEMP + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP + .endm + + .macro RESTORE_ALL_AND_RET + RESTORE_TEMP + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP_AND_RET + .endm + +#endif /* end of __STACKFRAME_H__ */ + diff --git a/bsp/x1000/cpu/x1000/SConscript b/bsp/x1000/cpu/x1000/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/bsp/x1000/cpu/x1000/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/x1000/cache.c b/bsp/x1000/cpu/x1000/cache.c similarity index 100% rename from libcpu/mips/x1000/cache.c rename to bsp/x1000/cpu/x1000/cache.c diff --git a/libcpu/mips/x1000/cache.h b/bsp/x1000/cpu/x1000/cache.h similarity index 100% rename from libcpu/mips/x1000/cache.h rename to bsp/x1000/cpu/x1000/cache.h diff --git a/libcpu/mips/x1000/cpu.c b/bsp/x1000/cpu/x1000/cpu.c similarity index 100% rename from libcpu/mips/x1000/cpu.c rename to bsp/x1000/cpu/x1000/cpu.c diff --git a/libcpu/mips/x1000/interrupt.c b/bsp/x1000/cpu/x1000/interrupt.c similarity index 100% rename from libcpu/mips/x1000/interrupt.c rename to bsp/x1000/cpu/x1000/interrupt.c diff --git a/libcpu/mips/x1000/mips_backtrace.c b/bsp/x1000/cpu/x1000/mips_backtrace.c similarity index 100% rename from libcpu/mips/x1000/mips_backtrace.c rename to bsp/x1000/cpu/x1000/mips_backtrace.c diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/bsp/x1000/cpu/x1000/mips_cache_gcc.S similarity index 100% rename from libcpu/mips/x1000/mips_cache_gcc.S rename to bsp/x1000/cpu/x1000/mips_cache_gcc.S diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/bsp/x1000/cpu/x1000/mips_context_gcc.S similarity index 100% rename from libcpu/mips/x1000/mips_context_gcc.S rename to bsp/x1000/cpu/x1000/mips_context_gcc.S diff --git a/libcpu/mips/x1000/mips_excpt.c b/bsp/x1000/cpu/x1000/mips_excpt.c similarity index 100% rename from libcpu/mips/x1000/mips_excpt.c rename to bsp/x1000/cpu/x1000/mips_excpt.c diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/bsp/x1000/cpu/x1000/mips_excpt_gcc.S similarity index 100% rename from libcpu/mips/x1000/mips_excpt_gcc.S rename to bsp/x1000/cpu/x1000/mips_excpt_gcc.S diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/bsp/x1000/cpu/x1000/mips_fp_gcc.S similarity index 100% rename from libcpu/mips/x1000/mips_fp_gcc.S rename to bsp/x1000/cpu/x1000/mips_fp_gcc.S diff --git a/libcpu/mips/x1000/stack.c b/bsp/x1000/cpu/x1000/stack.c similarity index 100% rename from libcpu/mips/x1000/stack.c rename to bsp/x1000/cpu/x1000/stack.c diff --git a/libcpu/mips/x1000/startup_gcc.S b/bsp/x1000/cpu/x1000/startup_gcc.S similarity index 100% rename from libcpu/mips/x1000/startup_gcc.S rename to bsp/x1000/cpu/x1000/startup_gcc.S diff --git a/libcpu/mips/x1000/x1000.h b/bsp/x1000/cpu/x1000/x1000.h similarity index 100% rename from libcpu/mips/x1000/x1000.h rename to bsp/x1000/cpu/x1000/x1000.h diff --git a/libcpu/mips/x1000/x1000_aic.h b/bsp/x1000/cpu/x1000/x1000_aic.h similarity index 100% rename from libcpu/mips/x1000/x1000_aic.h rename to bsp/x1000/cpu/x1000/x1000_aic.h diff --git a/libcpu/mips/x1000/x1000_cpm.h b/bsp/x1000/cpu/x1000/x1000_cpm.h similarity index 100% rename from libcpu/mips/x1000/x1000_cpm.h rename to bsp/x1000/cpu/x1000/x1000_cpm.h diff --git a/libcpu/mips/x1000/x1000_intc.h b/bsp/x1000/cpu/x1000/x1000_intc.h similarity index 100% rename from libcpu/mips/x1000/x1000_intc.h rename to bsp/x1000/cpu/x1000/x1000_intc.h diff --git a/libcpu/mips/x1000/x1000_otg_dwc.h b/bsp/x1000/cpu/x1000/x1000_otg_dwc.h similarity index 100% rename from libcpu/mips/x1000/x1000_otg_dwc.h rename to bsp/x1000/cpu/x1000/x1000_otg_dwc.h diff --git a/libcpu/mips/x1000/x1000_slcdc.h b/bsp/x1000/cpu/x1000/x1000_slcdc.h similarity index 100% rename from libcpu/mips/x1000/x1000_slcdc.h rename to bsp/x1000/cpu/x1000/x1000_slcdc.h diff --git a/bsp/x1000/rtconfig.py b/bsp/x1000/rtconfig.py index b935d7bc4e..6d08af4c0a 100644 --- a/bsp/x1000/rtconfig.py +++ b/bsp/x1000/rtconfig.py @@ -10,7 +10,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'E:\work\env\tools\gnu_gcc\mips_gcc\mips-2016.05\bin' + EXEC_PATH = r'/opt/mips-2016.05/bin/' else: print('Please make sure your toolchains is GNU GCC!') exit(0) diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 12b82671e3..c567233c84 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -224,6 +224,13 @@ config RT_USING_SPI select RT_USING_QSPI default n + config RT_SFUD_SPI_MAX_HZ + int "Default spi maximum speed(HZ)" + range 0 50000000 + default 50000000 + help + Read the JEDEC SFDP command must run at 50 MHz or less,and you also can use rt_spi_configure(); to config spi speed. + config RT_DEBUG_SFUD bool "Show more SFUD debug information" default n diff --git a/components/drivers/spi/spi_flash_sfud.c b/components/drivers/spi/spi_flash_sfud.c index 7fa7de6ad5..ce67ce9a72 100644 --- a/components/drivers/spi/spi_flash_sfud.c +++ b/components/drivers/spi/spi_flash_sfud.c @@ -22,12 +22,17 @@ #endif /* RT_DEBUG_SFUD */ #ifndef RT_SFUD_DEFAULT_SPI_CFG + +#ifndef RT_SFUD_SPI_MAX_HZ +#define RT_SFUD_SPI_MAX_HZ 50000000 +#endif + /* read the JEDEC SFDP command must run at 50 MHz or less */ #define RT_SFUD_DEFAULT_SPI_CFG \ { \ .mode = RT_SPI_MODE_0 | RT_SPI_MSB, \ .data_width = 8, \ - .max_hz = 50 * 1000 * 1000, \ + .max_hz = RT_SFUD_SPI_MAX_HZ, \ } #endif diff --git a/components/finsh/shell.c b/components/finsh/shell.c index c35ed1cd86..852d3e7ac7 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -15,7 +15,7 @@ * 2011-02-23 Bernard fix variable section end issue of finsh shell * initialization when use GNU GCC compiler. * 2016-11-26 armink add password authentication - * 2018-07-02 aozima add custome prompt support. + * 2018-07-02 aozima add custom prompt support. */ #include diff --git a/libcpu/mips/xburst/SConscript b/libcpu/mips/xburst/SConscript deleted file mode 100644 index 0f06c299bb..0000000000 --- a/libcpu/mips/xburst/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.S') -CPPPATH = [cwd] - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/libcpu/mips/xburst/cache.c b/libcpu/mips/xburst/cache.c deleted file mode 100644 index cd37f69993..0000000000 --- a/libcpu/mips/xburst/cache.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * File : cache.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#include "../xburst/cache.h" - -#include - -#define CACHE_SIZE 16*1024 -#define CACHE_LINE_SIZE 32 -#define KSEG0 0x80000000 - -#define K0_TO_K1() \ -do { \ - unsigned long __k0_addr; \ - \ - __asm__ __volatile__( \ - "la %0, 1f\n\t" \ - "or %0, %0, %1\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r"(__k0_addr) \ - : "r" (0x20000000) ); \ -} while(0) - -#define K1_TO_K0() \ -do { \ - unsigned long __k0_addr; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "la %0, 1f\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r" (__k0_addr)); \ -} while (0) - -#define INVALIDATE_BTB() \ -do { \ - unsigned long tmp; \ - __asm__ __volatile__( \ - ".set mips32\n\t" \ - "mfc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - "ori %0, 2\n\t" \ - "mtc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - ".set mips2\n\t" \ - : "=&r" (tmp)); \ -} while (0) - -#define SYNC_WB() __asm__ __volatile__ ("sync") - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips32\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -void __icache_invalidate_all(void) -{ - unsigned int i; - - K0_TO_K1(); - - asm volatile (".set noreorder\n" - ".set mips32\n\t" - "mtc0\t$0,$28\n\t" - "mtc0\t$0,$29\n" - ".set mips0\n" - ".set reorder\n"); - for (i=KSEG0;i from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - - .globl system_dump - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - mfc0 t1, CP0_STATUS - and t0, t1 - - andi t0, 0xff00 - beqz t0, spurious_interrupt - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/xburst/cpu.c b/libcpu/mips/xburst/cpu.c deleted file mode 100644 index 88137535d9..0000000000 --- a/libcpu/mips/xburst/cpu.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * File : cpu.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ -#include -#include - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset() -{ - /* open the watch-dog */ - REG_WDT_TCSR = WDT_TCSR_EXT_EN; - REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024; - REG_WDT_TDR = 0x03; - REG_WDT_TCNT = 0x00; - REG_WDT_TCER |= WDT_TCER_TCEN; - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} - -/*@}*/ diff --git a/libcpu/mips/xburst/exception.c b/libcpu/mips/xburst/exception.c deleted file mode 100644 index aebdf704ea..0000000000 --- a/libcpu/mips/xburst/exception.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * File : exception.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include -#include -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -/** - * exception handle table - */ -exception_func_t sys_exception_handlers[33]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > 32) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<33; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -/*@}*/ - diff --git a/libcpu/mips/xburst/interrupt.c b/libcpu/mips/xburst/interrupt.c deleted file mode 100644 index 337646c735..0000000000 --- a/libcpu/mips/xburst/interrupt.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * File : interrupt.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * 2010-07-09 Bernard first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include -#include -#include - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) -#define INTERRUPTS_MAX 64 -#else -#define INTERRUPTS_MAX 32 -#endif - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc isr_table[INTERRUPTS_MAX]; - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < INTERRUPTS_MAX; idx ++) - { - isr_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - __intc_mask_irq(vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - __intc_unmask_irq(vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the interrupt service function parameter - * @param name the interrupt name - * @return old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < INTERRUPTS_MAX) - { - old_handler = isr_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - - return old_handler; -} - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) -/* - * fls - find last bit set. - * @word: The word to search - * - * This is defined the same way as ffs. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. - */ -rt_inline int fls(int x) -{ - __asm__("clz %0, %1" : "=r" (x) : "r" (x)); - - return 32 - x; -} -#endif - -#include - -void rt_interrupt_dispatch(void *ptreg) -{ - int i; - void *param; - rt_isr_handler_t irq_func; - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) - int irq = 0, group; - rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0; - - rt_uint32_t c0_status, c0_cause; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM); - - if (pending_im & CAUSEF_IP3) - { - extern void rt_hw_ost_handler(void); - rt_hw_ost_handler(); - return; - } - - if (pending_im & CAUSEF_IP2) - { - intc_ipr0 = REG_INTC_IPR(0); - intc_ipr1 = REG_INTC_IPR(1); - - if (intc_ipr0) - { - irq = fls(intc_ipr0) - 1; - intc_ipr0 &= ~(1<= INTERRUPTS_MAX) - rt_kprintf("max interrupt, irq=%d\n", irq); - - /* do interrupt */ - irq_func = isr_table[irq].handler; - param = isr_table[irq].param; - (*irq_func)(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[i].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(irq); - } - - if (pending_im & CAUSEF_IP0) - rt_kprintf("CAUSEF_IP0\n"); - if (pending_im & CAUSEF_IP1) - rt_kprintf("CAUSEF_IP1\n"); - if (pending_im & CAUSEF_IP4) - rt_kprintf("CAUSEF_IP4\n"); - if (pending_im & CAUSEF_IP5) - rt_kprintf("CAUSEF_IP5\n"); - if (pending_im & CAUSEF_IP6) - rt_kprintf("CAUSEF_IP6\n"); - if (pending_im & CAUSEF_IP7) - rt_kprintf("CAUSEF_IP7\n"); -#else - static rt_uint32_t pending = 0; - - /* the hardware interrupt */ - pending |= REG_INTC_IPR; - if (!pending) return; - - for (i = INTERRUPTS_MAX; i > 0; --i) - { - if ((pending & (1< -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} - -#ifdef RT_USING_FINSH -#include -static void CP0_status_analyze(unsigned long value) -{ - if(value & (1<<26)) - rt_kprintf(" FR"); - if(value & (1<<23)) - rt_kprintf(" PX"); - if(value & (1<<22)) - rt_kprintf(" BEV"); - if(value & (1<<20)) - rt_kprintf(" SR"); - if(value & (1<<19)) - rt_kprintf(" NMI"); - if(value & (1<<20)) - rt_kprintf(" SR"); - if(value & (0xFF<<8)) - rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF); - if(value & (1<<7)) - rt_kprintf(" KX"); - if(value & (1<<6)) - rt_kprintf(" SX"); - if(value & (1<<5)) - rt_kprintf(" UX"); - if(value & (0x03<<3)) - rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03); - if(value & (1<<2)) - rt_kprintf(" ERL"); - if(value & (1<<1)) - rt_kprintf(" EXL"); - if(value & (1<<0)) - rt_kprintf(" IE"); -} - -static void CP0_config0_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); - - /* [15] BE */ - if(value & (1<<15)) - rt_kprintf(" big-endian"); - else - rt_kprintf(" little-endian"); - - /* [14:13] AT */ - { - int AT = (value >> 13) & 0x03; - - if(AT == 0) - { - rt_kprintf(" MIPS32"); - } - else if(AT == 1) - { - rt_kprintf(" MIPS64/A32"); - } - else if(AT == 2) - { - rt_kprintf(" MIPS64/A64"); - } - else - { - rt_kprintf(" unkown"); - } - } - - /* [12:10] AR */ - { - int AR = (value >> 10) & 0x07; - - if(AR == 0) - { - rt_kprintf(" R1"); - } - else if(AR == 1) - { - rt_kprintf(" R2"); - } - else - { - rt_kprintf(" reserve"); - } - } - - /* [3] VI */ - if(value & (1UL<<31)) - rt_kprintf(" VI"); - - /* [2:0] K0 */ - { - int K0 = value & 0x07; - - if(K0 == 2) - { - rt_kprintf(" uncached"); - } - else if(K0 == 3) - { - rt_kprintf(" cacheable"); - } - else - { - rt_kprintf(" K0:reserve"); - } - } -} - -static void CP0_config1_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); - - /* [30:25] MMU size */ - { - int MMU_size = (value >> 25) & 0x3F; - rt_kprintf(" TLB:%d", MMU_size + 1); - } - - /* [24:22] IS, [21:19] IL, [18:16] IA */ - { - int IS = (value >> 22) & 0x07; - int IL = (value >> 19) & 0x07; - int IA = (value >> 16) & 0x07; - - IA = IA + 1; - IS = 64 << IS; - IL = 2 << IL; - rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte", - (IA*IS*IL) >> 10, IA, IS, IL); - } - - /* [15:13] DS, [12:10] DL, [9:7] DA */ - { - int DS = (value >> 13) & 0x07; - int DL = (value >> 10) & 0x07; - int DA = (value >> 7) & 0x07; - - DA = DA + 1; - DS = 64 << DS; - DL = 2 << DL; - rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte", - (DA*DS*DL) >> 10, DA, DS, DL); - } - - /* [6] C2 */ - if(value & (1UL<<6)) - rt_kprintf(" CP2"); - - /* [5] MD */ - if(value & (1UL<<5)) - rt_kprintf(" MDMX-ASE"); - - /* [4] PC */ - if(value & (1UL<<4)) - rt_kprintf(" performa-count"); - - /* [3] WR */ - if(value & (1UL<<3)) - rt_kprintf(" Watch"); - - /* [2] CA */ - if(value & (1UL<<2)) - rt_kprintf(" MIPS16e"); - - /* [1] EP */ - if(value & (1UL<<1)) - rt_kprintf(" EJTAG"); - - /* [0] FP */ - if(value & (1UL<<0)) - rt_kprintf(" FPU"); -} - -static void CP0_config2_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); -} - -static void CP0_config3_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); -} - -static void list_mips(void) -{ - unsigned long value; - unsigned long num = 0; - - rt_kprintf("MIPS coprocessor register:\r\n"); - - rt_kprintf("( 0,0) INDEX : 0x%08X\r\n", read_c0_index()); - rt_kprintf("( 1,0) RANDOM : 0x%08X\r\n", read_c0_random()); - rt_kprintf("( 2,0) ENTRYLO0 : 0x%08X\r\n", read_c0_entrylo0()); - rt_kprintf("( 3,0) ENTRYLO1 : 0x%08X\r\n", read_c0_entrylo1()); - rt_kprintf("( 4,0) CONTEXT : 0x%08X\r\n", read_c0_context()); - rt_kprintf("( 5,0) PAGEMASK : 0x%08X\r\n", read_c0_pagemask()); - rt_kprintf("( 6,0) WIRED : 0x%08X\r\n", read_c0_wired()); - rt_kprintf("( 7,0) INFO : 0x%08X\r\n", read_c0_info()); - rt_kprintf("( 8,0) BADVADDR : 0x%08X\r\n", read_c0_badvaddr()); - rt_kprintf("( 9,0) COUNT : 0x%08X\r\n", read_c0_count()); - rt_kprintf("(10,0) ENTRYHI : 0x%08X\r\n", read_c0_entryhi()); - rt_kprintf("(11,0) COMPARE : 0x%08X\r\n", read_c0_compare()); - - value = read_c0_status(); - rt_kprintf("(12,0) STATUS : 0x%08X", value); - CP0_status_analyze(value); - rt_kprintf("\r\n"); - - /* - rt_kprintf("(12,1) INTCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 1)); - rt_kprintf("(12,2) SRSCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 2)); - */ - - rt_kprintf("(13,0) CAUSE : 0x%08X\r\n", read_c0_cause()); - rt_kprintf("(14,0) EPC : 0x%08X\r\n", read_c0_epc()); - rt_kprintf("(15,0) PRID : 0x%08X\r\n", read_c0_prid()); - rt_kprintf("(15,1) EBASE : 0x%08X\r\n", read_c0_ebase()); - - value = read_c0_config(); - rt_kprintf("(16,0) CONFIG : 0x%08X", value); - CP0_config0_analyze(value); - rt_kprintf("\r\n"); - if(value & (1UL << 31)) - { - value = read_c0_config1(); - rt_kprintf("(16,1) CONFIG1 : 0x%08X", value); - CP0_config1_analyze(value); - rt_kprintf("\r\n"); - - if(value & (1UL << 31)) - { - value = read_c0_config2(); - rt_kprintf("(16,2) CONFIG2 : 0x%08X\r\n", value); - CP0_config2_analyze(value); - rt_kprintf("\r\n"); - - if(value & (1UL << 31)) - { - value = read_c0_config3(); - rt_kprintf("(16,3) CONFIG3 : 0x%08X\r\n", value); - CP0_config3_analyze(value); - rt_kprintf("\r\n"); - } - } - } - - rt_kprintf("(17,0) LLADDR : 0x%08X\r\n", __read_32bit_c0_register($17, 0)); - rt_kprintf("(18,0) WATCHLO : 0x%08X\r\n", __read_32bit_c0_register($18, 0)); - rt_kprintf("(19,0) WATCHHI : 0x%08X\r\n", __read_32bit_c0_register($19, 0)); - rt_kprintf("(20,0) XCONTEXT : 0x%08X\r\n", __read_32bit_c0_register($20, 0)); - rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0)); - rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0)); - rt_kprintf("(23,0) DEBUG : 0x%08X\r\n", __read_32bit_c0_register($23, 0)); - rt_kprintf("(24,0) DEPC : 0x%08X\r\n", __read_32bit_c0_register($24, 0)); - - rt_kprintf("(25,0) PERFCTL0 : 0x%08X\r\n", __read_32bit_c0_register($25, 0)); - rt_kprintf("(26,0) ECC : 0x%08X\r\n", __read_32bit_c0_register($26, 0)); - rt_kprintf("(27,0) CACHEERR : 0x%08X\r\n", __read_32bit_c0_register($27, 0)); - rt_kprintf("(28,0) TAGLO : 0x%08X\r\n", __read_32bit_c0_register($28, 0)); - rt_kprintf("(29,0) TAGHI : 0x%08X\r\n", __read_32bit_c0_register($29, 0)); - - /* - rt_kprintf("(30,0) ERROREPC : 0x%08X\r\n", __read_32bit_c0_register($30, 0)); - rt_kprintf("(31,0) DESAVE : 0x%08X\r\n", __read_32bit_c0_register($31, 0)); - */ - - - rt_kprintf("\r\n"); -} -FINSH_FUNCTION_EXPORT(list_mips, list CPU info) -#endif /* RT_USING_FINSH */ - diff --git a/libcpu/mips/xburst/stack.c b/libcpu/mips/xburst/stack.c deleted file mode 100644 index ceba8b9d9d..0000000000 --- a/libcpu/mips/xburst/stack.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * File : stack.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-07-07 Bernard porting to Ingenic CPU - */ -#include - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x0403; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S deleted file mode 100644 index da8bfa9251..0000000000 --- a/libcpu/mips/xburst/start_gcc.S +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2006-2019, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to JZ47xx - * 2019-07-19 Zhou Yanjie clean up code - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ -#endif - -#include "../common/mips_def.h" -#include "../common/stackframe.h" -#include "stack.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* init cp0 registers. */ - li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ - mtc0 t0, CP0_STATUS - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* init caches, assumes a 4way * 128set * 32byte I/D cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ - li t0, 3 /* enable cache for kseg0 accesses */ - mtc0 t0, CP0_CONFIG /* CONFIG reg */ - la t0, 0x80000000 /* an idx op should use an unmappable address */ - ori t1, t0, 0x4000 /* 16kB cache */ - -_cache_loop: - cache 0x8, 0(t0) /* index store icache tag */ - cache 0x9, 0(t0) /* index store dcache tag */ - bne t0, t1, _cache_loop - addiu t0, t0, 0x20 /* 32 bytes per cache line */ - nop - - /* invalidate BTB */ - mfc0 t0, CP0_CONFIG - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG - nop - - /* copy IRAM section */ - la t0, _iramcopy - la t1, _iramstart - la t2, _iramend -_iram_loop: - lw t3, 0(t0) - sw t3, 0(t1) - addiu t1, 4 - bne t1, t2, _iram_loop - addiu t0, 4 - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c - srl k1, k1, 2 - lw k0, sys_exception_handlers(k1) - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/xburst/x1000.h b/libcpu/mips/xburst/x1000.h deleted file mode 100644 index 71d11783a3..0000000000 --- a/libcpu/mips/xburst/x1000.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * File : x1000.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-11-19 Urey the first version - */ - -#ifndef X1000_H__ -#define X1000_H__ - -#ifndef __ASSEMBLY__ - -// typedef unsigned int size_t; -#define u64 unsigned long long -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char - -#define U64 unsigned long long -#define U32 unsigned int -#define U16 unsigned short -#define U8 unsigned char - -#define S64 signed long long -#define S32 int -#define S16 short int -#define S8 signed char - -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -/* cpu pipeline flush */ -static inline void jz_sync(void) -{ - __asm__ volatile ("sync"); -} - -static inline void writeb(u8 value, u32 address) -{ - *((volatile u8 *) address) = value; -} -static inline void writew( u16 value, u32 address) -{ - *((volatile u16 *) address) = value; -} -static inline void writel(u32 value, u32 address) -{ - *((volatile u32 *) address) = value; -} - -static inline u8 readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 readl(u32 address) -{ - return *((volatile u32 *)address); -} - -static inline void jz_writeb(u32 address, u8 value) -{ - *((volatile u8 *)address) = value; -} - -static inline void jz_writew(u32 address, u16 value) -{ - *((volatile u16 *)address) = value; -} - -static inline void jz_writel(u32 address, u32 value) -{ - *((volatile u32 *)address) = value; -} - -static inline u8 jz_readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 jz_readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 jz_readl(u32 address) -{ - return *((volatile u32 *)address); -} - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#define BIT(n) (0x01u << (n)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -/* AHB0 BUS Devices Base */ -#define HARB0_BASE 0xB3000000 -#define EMC_BASE 0xB3010000 -#define DDRC_BASE 0xB3020000 -#define MDMAC_BASE 0xB3030000 -#define LCD_BASE 0xB3050000 -#define TVE_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define IPU_BASE 0xB3080000 -/* AHB1 BUS Devices Base */ -#define HARB1_BASE 0xB3200000 -#define DMAGP0_BASE 0xB3210000 -#define DMAGP1_BASE 0xB3220000 -#define DMAGP2_BASE 0xB3230000 -#define MC_BASE 0xB3250000 -#define ME_BASE 0xB3260000 -#define DEBLK_BASE 0xB3270000 -#define IDCT_BASE 0xB3280000 -#define CABAC_BASE 0xB3290000 -#define TCSM0_BASE 0xB32B0000 -#define TCSM1_BASE 0xB32C0000 -#define SRAM_BASE 0xB32D0000 -/* AHB2 BUS Devices Base */ -#define HARB2_BASE 0xB3400000 -#define NEMC_BASE 0xB3410000 -#define DMAC_BASE 0xB3420000 -#define UHC_BASE 0xB3430000 -#define UDC_BASE 0xB3440000 -#define GPS_BASE 0xB3480000 -#define ETHC_BASE 0xB34B0000 -#define BCH_BASE 0xB34D0000 -#define MSC0_BASE 0xB3450000 -#define MSC1_BASE 0xB3460000 -#define MSC2_BASE 0xB3470000 - -/* APB BUS Devices Base */ -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define OST_BASE 0xB2000000 /* OS Timer */ -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define DMIC_BASE 0xB0021000 -#define ICDC_BASE 0xB0020000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define UART3_BASE 0xB0033000 -#define SCC_BASE 0xB0040000 -#define SSI0_BASE 0xB0043000 -#define SSI1_BASE 0xB0044000 -#define SSI2_BASE 0xB0045000 -#define I2C0_BASE 0xB0050000 -#define I2C1_BASE 0xB0051000 -#define PS2_BASE 0xB0060000 -#define SADC_BASE 0xB0070000 -#define OWI_BASE 0xB0072000 -#define TSSI_BASE 0xB0073000 - -/* NAND CHIP Base Address*/ -#define NEMC_CS1_IOBASE 0Xbb000000 -#define NEMC_CS2_IOBASE 0Xba000000 -#define NEMC_CS3_IOBASE 0Xb9000000 -#define NEMC_CS4_IOBASE 0Xb8000000 -#define NEMC_CS5_IOBASE 0Xb7000000 -#define NEMC_CS6_IOBASE 0Xb6000000 - -/********************************************************************************************************* -** WDT -*********************************************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0C) - -#define REG_WDT_TDR REG16(WDT_TDR) -#define REG_WDT_TCER REG8(WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_TCSR) - -#define WDT_TSCR_WDTSC (1 << 16) - -#define WDT_TCSR_PRESCALE_1 (0 << 3) -#define WDT_TCSR_PRESCALE_4 (1 << 3) -#define WDT_TCSR_PRESCALE_16 (2 << 3) -#define WDT_TCSR_PRESCALE_64 (3 << 3) -#define WDT_TCSR_PRESCALE_256 (4 << 3) -#define WDT_TCSR_PRESCALE_1024 (5 << 3) - -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/********************************************************************************************************* -** жԴ -*********************************************************************************************************/ -/* INTC (Interrupt Controller) */ -#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) -#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) -#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) -#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) -#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) - -#define REG_INTC_ISR(n) REG32(INTC_ISR((n))) -#define REG_INTC_IMR(n) REG32(INTC_IMR((n))) -#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) -#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) -#define REG_INTC_IPR(n) REG32(INTC_IPR((n))) - -// interrupt controller interrupts -#define IRQ_DMIC 0 -#define IRQ_AIC0 1 -#define IRQ_RESERVED2 2 -#define IRQ_RESERVED3 3 -#define IRQ_RESERVED4 4 -#define IRQ_RESERVED5 5 -#define IRQ_RESERVED6 6 -#define IRQ_SFC 7 -#define IRQ_SSI0 8 -#define IRQ_RESERVED9 9 -#define IRQ_PDMA 10 -#define IRQ_PDMAD 11 -#define IRQ_RESERVED12 12 -#define IRQ_RESERVED13 13 -#define IRQ_GPIO3 14 -#define IRQ_GPIO2 15 -#define IRQ_GPIO1 16 -#define IRQ_GPIO0 17 -#define IRQ_RESERVED18 18 -#define IRQ_RESERVED19 19 -#define IRQ_RESERVED20 20 -#define IRQ_OTG 21 -#define IRQ_RESERVED22 22 -#define IRQ_AES 23 -#define IRQ_RESERVED24 24 -#define IRQ_TCU2 25 -#define IRQ_TCU1 26 -#define IRQ_TCU0 27 -#define IRQ_RESERVED28 28 -#define IRQ_RESERVED29 29 -#define IRQ_CIM 30 -#define IRQ_LCD 31 -#define IRQ_RTC 32 -#define IRQ_RESERVED33 33 -#define IRQ_RESERVED34 34 -#define IRQ_RESERVED35 35 -#define IRQ_MSC1 36 -#define IRQ_MSC0 37 -#define IRQ_SCC 38 -#define IRQ_RESERVED39 39 -#define IRQ_PCM0 40 -#define IRQ_RESERVED41 41 -#define IRQ_RESERVED42 42 -#define IRQ_RESERVED43 43 -#define IRQ_HARB2 44 -#define IRQ_RESERVED45 45 -#define IRQ_HARB0 46 -#define IRQ_CPM 47 -#define IRQ_RESERVED48 48 -#define IRQ_UART2 49 -#define IRQ_UART1 50 -#define IRQ_UART0 51 -#define IRQ_DDR 52 -#define IRQ_RESERVED53 53 -#define IRQ_EFUSE 54 -#define IRQ_MAC 55 -#define IRQ_RESERVED56 56 -#define IRQ_RESERVED57 57 -#define IRQ_I2C2 58 -#define IRQ_I2C1 59 -#define IRQ_I2C0 60 -#define IRQ_PDMAM 61 -#define IRQ_JPEG 62 -#define IRQ_RESERVED63 63 - -#define IRQ_INTC_MAX 63 - -#ifndef __ASSEMBLY__ - -#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) -#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) -#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ - -#endif /* !__ASSEMBLY__ */ - -#endif /* _JZ_M150_H_ */ diff --git a/tools/building.py b/tools/building.py index 8d461102bc..65af794434 100644 --- a/tools/building.py +++ b/tools/building.py @@ -169,12 +169,12 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [ AddOption('--project-path', dest = 'project-path', type = 'string', - default = False, + default = None, help = 'set dist-ide project output path') AddOption('--project-name', dest = 'project-name', type = 'string', - default = False, + default = None, help = 'set project name') AddOption('--reset-project-config', dest = 'reset-project-config', diff --git a/tools/eclipse.py b/tools/eclipse.py index 191cfc2b3a..253db37bea 100644 --- a/tools/eclipse.py +++ b/tools/eclipse.py @@ -336,6 +336,11 @@ def GenExcluding(env, project): coll_dirs = CollectPaths(project['DIRS']) all_paths = [OSPath(path) for path in coll_dirs] + # remove unused path + for path in all_paths: + if not path.startswith(rtt_root) and not path.startswith(bsp_root): + all_paths.remove(path) + if bsp_root.startswith(rtt_root): # bsp folder is in the RT-Thread root folder, such as the RT-Thread source code on GitHub exclude_paths = ExcludePaths(rtt_root, all_paths) @@ -399,7 +404,34 @@ def RelativeProjectPath(env, path): return path -def UpdateCproject(env, project, excluding, reset): +def HandleExcludingOption(entry, sourceEntries, excluding): + old_excluding = [] + if entry != None: + old_excluding = entry.get('excluding').split('|') + sourceEntries.remove(entry) + + value = '' + for item in old_excluding: + if item.startswith('//') : + old_excluding.remove(item) + else : + if value == '': + value = item + else: + value += '|' + item + + for item in excluding: + # add special excluding path prefix for RT-Thread + item = '//' + item + if value == '': + value = item + else: + value += '|' + item + + SubElement(sourceEntries, 'entry', {'excluding': value, 'flags': 'VALUE_WORKSPACE_PATH|RESOLVED', 'kind':'sourcePath', 'name':""}) + + +def UpdateCproject(env, project, excluding, reset, prj_name): excluding = sorted(excluding) cproject = etree.parse('.cproject') @@ -412,17 +444,15 @@ def UpdateCproject(env, project, excluding, reset): sourceEntries = cconfiguration.find('storageModule/configuration/sourceEntries') entry = sourceEntries.find('entry') - if entry != None: - sourceEntries.remove(entry) - - value = '' - for item in excluding: - if value == '': - value = item - else: - value += '|' + item - - SubElement(sourceEntries, 'entry', {'excluding': value, 'flags': 'VALUE_WORKSPACE_PATH|RESOLVED', 'kind':'sourcePath', 'name':""}) + HandleExcludingOption(entry, sourceEntries, excluding) + # update refreshScope + if prj_name: + prj_name = '/' + prj_name + configurations = root.findall('storageModule/configuration') + for configuration in configurations: + resource = configuration.find('resource') + configuration.remove(resource) + SubElement(configuration, 'resource', {'resourceType': "PROJECT", 'workspacePath': prj_name}) # write back to .cproject out = open('.cproject', 'w') @@ -451,7 +481,7 @@ def TargetEclipse(env, reset = False, prj_name = None): excluding = GenExcluding(env, project) # update the project configuration on '.cproject' file - UpdateCproject(env, project, excluding, reset) + UpdateCproject(env, project, excluding, reset, prj_name) print('done!')