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code format

This commit is contained in:
bigmagic 2020-09-11 11:44:49 +08:00
parent 39224e4888
commit a97b0a0d39
20 changed files with 1104 additions and 1176 deletions
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1
bsp/ls2kdev/drivers/clk.c
View File

@ -14,7 +14,6 @@
#include <rtthread.h>
#include "ls2k1000.h"
struct loongson_pll {
rt_uint64_t PLL_SYS_0;
rt_uint64_t PLL_SYS_1;

1
bsp/ls2kdev/drivers/drv_gpio.h
View File

@ -36,6 +36,5 @@ struct loongson_gpio {
int loongson_pin_init(void);
#endif

1
bsp/ls2kdev/drivers/drv_uart.h
View File

@ -53,7 +53,6 @@
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
// 线路控制寄存器
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */

8
bsp/ls2kdev/drivers/interrupt.h
View File

@ -64,11 +64,11 @@
#define LS2K_GPIO2_INT_IRQ (62)
#define LS2K_GPIO3_INT_IRQ (63)
#define MAX_INTR 64
#define LIOINTC0_IRQBASE 0
#define LIOINTC1_IRQBASE 32
#define MAX_INTR (64)
#define LIOINTC0_IRQBASE (0)
#define LIOINTC1_IRQBASE (32)
#define LIOINTC_SHIFT_INTx 4
#define LIOINTC_SHIFT_INTx (4)
#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
#define LIOINTC_INTC_CHIP_START 0x20

12
bsp/ls2kdev/drivers/ls2k1000.h
View File

@ -6,8 +6,8 @@
#define APB_BASE CKSEG1ADDR(0xbfe00000)
#define UART0_BASE_ADDR 0xbfe00000
#define UART0_OFF 0x0
#define UART0_BASE_ADDR (0xbfe00000)
#define UART0_OFF (0x0)
#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
@ -18,11 +18,11 @@
#define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440)
#define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048)
#define GPIO_BASE 0xFFFFFFFFBFE10500
#define PLL_SYS_BASE 0xFFFFFFFFBFE10480
#define RTC_BASE 0xFFFFFFFFBFE07820
#define GPIO_BASE (0xFFFFFFFFBFE10500)
#define PLL_SYS_BASE (0xFFFFFFFFBFE10480)
#define RTC_BASE (0xFFFFFFFFBFE07820)
#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420
#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
void rt_hw_timer_handler(void);
void rt_hw_uart_init(void);

2
bsp/ls2kdev/drivers/net/mii.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/ls2kdev/drivers/net/synopGMAC.c
View File

@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter)
return gmacdev->Speed | (gmacdev->DuplexMode << 4);
}
static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
{
int i;
@ -894,7 +893,6 @@ int rt_hw_eth_init(void)
struct synopGMACNetworkAdapter *synopGMACadapter;
static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
int index;
//rt_kprintf("rt_hw_eth_init 1\n");
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
@ -958,8 +956,6 @@ int rt_hw_eth_init(void)
eth_device_init(&(eth_dev.parent), "e0");
eth_device_linkchange(&eth_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
//rt_kprintf("rt_hw_eth_init 2\n");
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_eth_init);

56
bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
View File

@ -860,7 +860,6 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev)
return;
}
/**
* Enables unicast hash filtering.
* When enabled GMAC performs the destination address filtering of unicast frames according to the hash table.
@ -1032,7 +1031,6 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev)
synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg);
return;
}
/**
@ -1355,7 +1353,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
desc -> status = 0;
#endif
//sw
desc -> buffer1 = 0;
desc -> buffer2 = 0;
desc -> data1 = 0;
@ -1365,8 +1362,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
return;
}
/**
* Initialize the rx descriptors for chain mode of operation.
* - Status field is initialized to 0.
@ -1409,7 +1404,6 @@ void synopGMAC_tx_desc_init_chain(DmaDesc * desc)
return;
}
s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev)
{
s32 i;
@ -1817,7 +1811,6 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1
}
return;
}
#ifdef ENH_DESC_8W
@ -1912,10 +1905,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
u32 txover = gmacdev->TxBusy;
DmaDesc * txdesc = gmacdev->TxBusyDesc;
int i;
//sw: dbg
//pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R);
//pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W);
#if SYNOP_TX_DEBUG
@ -2008,7 +1998,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
(gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now
if(synopGMAC_is_tx_desc_chained(txdesc)){
if(synopGMAC_is_tx_desc_chained(txdesc))
{
txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
#ifdef ENH_DESC
txdesc->status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
@ -2019,7 +2010,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
txdesc->buffer1 = Buffer1;
txdesc->data1 = Data1;
if(offload_needed){
if(offload_needed)
{
/*
Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
before calling any of the functions given below.
@ -2037,7 +2029,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
}
else{
else
{
// printf("synopGMAC_set_tx_qptr:in ring mode\n");
txdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 <<DescSize2Shift) & DescSize2Mask));
#ifdef ENH_DESC
@ -2052,7 +2045,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
txdesc->buffer2 = Buffer2;
txdesc->data2 = Data2;
if(offload_needed){
if(offload_needed)
{
/*
Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
before calling any of the functions given below.
@ -2639,7 +2633,6 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
synopGMAC_take_desc_ownership(desc + i);
}
}
}
/**
@ -2669,14 +2662,7 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev)
data &= (~DmaRxStart);
synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data);
}
/*******************PMT APIs***************************************/
/**
* Enables the assertion of PMT interrupt.
* This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame
@ -2835,9 +2821,9 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte
}
#endif
/*******************PMT APIs***************************************/
/*******************MMC APIs***************************************/
/**
* Freezes the MMC counters.
* This function call freezes the MMC counters. None of the MMC counters are updated
@ -3081,7 +3067,6 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev)
* \return returns TRUE or FALSE
*/
#ifdef ENH_DESC_8W
/**
* This function indicates whether extended status is available in the RDES0.
* Any function which accesses the fields of extended status register must ensure a check on this has been made
@ -3132,8 +3117,6 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status)
}
#endif
/**
* Decodes the Rx Descriptor status to various checksum error conditions.
* @param[in] pointer to synopGMACdevice.
@ -3172,7 +3155,6 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta
return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError);
}
/**
* Checks if any payload checksum error in the frame just transmitted.
* This serves as indication that error occureed in the payload checksum insertion.
@ -3199,7 +3181,6 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des
#else
desc->length = (desc->length & (~DescTxCisMask));
#endif
}
/**
* The check summ offload engine is enabled to do only IPV4 header checksum.
@ -3215,7 +3196,6 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de
#else
desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);
#endif
}
/**
@ -3233,7 +3213,6 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de
#else
desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);
#endif
}
/**
* The check summ offload engine is enabled to do complete checksum computation.
@ -3254,14 +3233,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc
}
/*******************Ip checksum offloading APIs***************************************/
/*******************IEEE 1588 Timestamping API***************************************/
/*
* At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled.
* For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced
@ -3295,7 +3267,6 @@ void synopGMAC_TS_disable(synopGMACdevice *gmacdev)
return;
}
/**
* Enable the interrupt to get timestamping interrupt.
* This enables the host to get the interrupt when (1) system time is greater or equal to the
@ -3344,7 +3315,6 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev)
return;
}
/**
* Selet the type of clock mode for PTP.
* Please note to use one of the follwoing as the clk_type argument.
@ -3493,7 +3463,6 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev)
return;
}
/**
* Snoop PTP packet for version 2 format
* When set the PTP packets are snooped using the version 2 format.
@ -3587,8 +3556,7 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
return -ESYNOPGMACPHYERR;
}
return -ESYNOPGMACNOERR;
return -ESYNOPGMACNOERR;
}
/**
* time stamp Update
@ -3616,7 +3584,7 @@ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32
TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
return -ESYNOPGMACPHYERR;
}
return -ESYNOPGMACNOERR;
return -ESYNOPGMACNOERR;
}
/**
@ -3645,7 +3613,7 @@ s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 lo
TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
return -ESYNOPGMACPHYERR;
}
return -ESYNOPGMACNOERR;
return -ESYNOPGMACNOERR;
}
/**

66
bsp/ls2kdev/drivers/net/synopGMAC_Dev.h
View File

@ -15,17 +15,17 @@
#define SYNOP_GMAC_DEV_H 1
/*******************************************************************/
#define SYNOP_LOOPBACK_MODE 0
#define SYNOP_LOOPBACK_DEBUG 0
#define SYNOP_PHY_LOOPBACK 0
#define SYNOP_LOOPBACK_MODE (0)
#define SYNOP_LOOPBACK_DEBUG (0)
#define SYNOP_PHY_LOOPBACK (0)
#define SYNOP_TX_TEST 0
#define SYNOP_RX_TEST 0
#define SYNOP_TX_TEST (0)
#define SYNOP_RX_TEST (0)
#define SYNOP_TOP_DEBUG 0
#define SYNOP_REG_DEBUG 0
#define SYNOP_RX_DEBUG 0
#define SYNOP_TX_DEBUG 0
#define SYNOP_TOP_DEBUG (0)
#define SYNOP_REG_DEBUG (0)
#define SYNOP_RX_DEBUG (0)
#define SYNOP_TX_DEBUG (0)
#define ENH_DESC
/*******************************************************************/
@ -148,7 +148,6 @@ typedef struct synopGMACDeviceStruct
u64 PhyBase; /* PHY device address on MII interface */
u32 Version; /* Gmac Revision version */
dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/
DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */
@ -178,19 +177,15 @@ typedef struct synopGMACDeviceStruct
u32 DuplexMode; /* Duplex mode of the Phy */
u32 Speed; /* Speed of the Phy */
u32 LoopBackMode; /* Loopback status of the Phy */
// void * FirstTxDesc;
// void * FirstRxDesc;
// u32 skb_array[RECEIVE_DESC_SIZE];
} synopGMACdevice;
/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver"
* Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter.
* Since the Phy register map is standard, this map hardly changes to a different Ppy
*/
enum MiiRegisters
{
PHY_CONTROL_REG = 0x0000, /*Control Register*/
@ -218,10 +213,8 @@ enum MiiRegisters
PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/
};
/* This is Control register layout. Control register is of 16 bit wide.
*/
enum Mii_GEN_CTRL
{ /* Description bits R/W default value */
Mii_reset = 0x8000,
@ -281,8 +274,6 @@ enum Mii_Loop_Back
LOOPBACK = 1,
};
/**********************************************************
* GMAC registers Map
* For Pci based system address is BARx + GmacRegisterBase
@ -338,7 +329,7 @@ enum GmacRegisters
GmacAddr14Low = 0x00B4, /* Mac address14 low Register */
GmacAddr15High = 0x00B8, /* Mac address15 high Register */
GmacAddr15Low = 0x00BC, /* Mac address15 low Register */
GmacStatus = 0x00d8, /*MAC status*/
GmacStatus = 0x00d8, /* MAC status */
/*Time Stamp Register Map*/
GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */
@ -357,7 +348,7 @@ enum GmacRegisters
GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */
GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */
//GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */
//GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */
GmacTSStatus = 0x0728, /* Time Stamp Status Register */
};
@ -422,7 +413,7 @@ enum GmacConfigReg
GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */
GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */
GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */
GmacRxIpcOffload = 0x00000400, /* IPC checksum offload 10 RW 0 */
GmacRetry = 0x00000200,
GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */
@ -502,7 +493,6 @@ enum GmacFrameFilterReg
GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */
};
/*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */
enum GmacGmiiAddrReg
{
@ -512,7 +502,7 @@ enum GmacGmiiAddrReg
GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */
GmiiRegShift = 6,
GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */
GmiiCsrClkMask = 0x0000001C, /* CSR Clock bit Mask 4:2 */
GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */
GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */
GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */
@ -532,7 +522,6 @@ enum GmacGmiiDataReg
GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */
};
/*GmacFlowControl = 0x0018, Flow control Register Layout */
enum GmacFlowControlReg
{
@ -573,7 +562,6 @@ enum GmacInterruptStatusBitDefinition
GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */
GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */
GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */
};
/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */
@ -591,7 +579,6 @@ enum GmacInterruptMaskBitDefinition
* For Pci based system address is BARx + GmaDmaBase
* For any other system translation is done accordingly
**********************************************************/
enum DmaRegisters
{
DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */
@ -654,7 +641,6 @@ enum DmaBusModeReg
DmaResetOff = 0x00000000, /* 0 */
};
/*DmaStatus = 0x0014, CSR5 - Dma status Register */
enum DmaStatusReg
{
@ -883,28 +869,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */
DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */
DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */
/*
This explains the RDES1/TDES1 bits layout
--------------------------------------------------------------------
RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 |
--------------------------------------------------------------------
*/
// DmaDescriptorLength length word of DMA descriptor
RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */
RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */
RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */
DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */
DescSize2Shift = 16,
DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */
DescSize1Shift = 0,
/*
This explains the RDES4 Extended Status bits layout
--------------------------------------------------------------------
@ -990,9 +969,9 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */
DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */
//Rx Descriptor Checksum Offload engine (type 2) encoding
//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */
//DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
//Rx Descriptor Checksum Offload engine (type 2) encoding
//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */
//DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */
DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
@ -1023,7 +1002,6 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
*/
//DmaDescriptorLength length word of DMA descriptor
DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */
DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */
DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */
@ -1043,7 +1021,6 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */
DescSize1Shift = 0,
DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */
DescTxCisBypass = 0x00000000, /* Checksum bypass */
DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */
@ -1138,8 +1115,6 @@ enum InitialRegisters
/* Half-duplex mode */
GmacGmiiAddrInitHdx = GmiiCsrClk2,
/**********************************************
*DMA configurations
**********************************************/
@ -1249,6 +1224,7 @@ enum MMC_RX
GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */
};
enum MMC_IP_RELATED
{
GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */
@ -1300,7 +1276,6 @@ enum MMC_CNTRL_REG_BIT_DESCRIPTIONS
GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */
GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */
GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */
};
enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
@ -1359,7 +1334,6 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */
GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */
GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */
};
@ -1394,9 +1368,6 @@ enum GmacPmtCtrlStatusBitDefinition
GmacPmtPowerDown = 0x00000001, /* Power Down */
};
/**********************************************************
* IEEE 1588-2008 Precision Time Protocol (PTP) Support
**********************************************************/
@ -1414,8 +1385,6 @@ enum PTPMessageType
Management = 0xD,
};
typedef struct TimeStampStruct
{
u32 TSversion; /* PTP Version 1 or PTP version2 */
@ -1516,7 +1485,6 @@ enum GmacTSStatusReg
GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */
};
/**********************************************************
* Time stamp related functions
**********************************************************/

85
libcpu/mips/gs264/mips_mmu.h
View File

@ -7,19 +7,18 @@
* Date Author Notes
* 2020-07-26 lizhirui the first version
*/
#ifndef __MIPS_MMU_H__
#define __MIPS_MMU_H__
typedef enum cpu_mode_t
{
typedef enum cpu_mode_t
{
CPU_MODE_KERNEL = 0x00,
CPU_MODE_SUPERVISOR = 0x01,
CPU_MODE_USER = 0x02
}cpu_mode_t;
}cpu_mode_t;
typedef enum page_mask_enum_t
{
typedef enum page_mask_enum_t
{
PAGE_MASK_4KB = 0x00,
PAGE_MASK_16KB = 0x03,
PAGE_MASK_64KB = 0x0F,
@ -30,18 +29,18 @@
PAGE_MASK_64MB = 0x3FFF,
PAGE_MASK_256MB = 0xFFFF,
PAGE_MASK_1GB = 0x3FFFF
}page_mask_enum_t;
}page_mask_enum_t;
typedef struct page_mask_t
{
typedef struct page_mask_t
{
uint64_t : 11;
uint64_t : 2;
uint64_t mask : 18;
uint64_t : 33;
}page_mask_t;
}page_mask_t;
typedef struct entry_lo_t
{
typedef struct entry_lo_t
{
uint64_t g : 1;
uint64_t v : 1;
uint64_t d : 1;
@ -51,50 +50,50 @@
uint64_t : 29;
uint64_t xi : 1;
uint64_t ri : 1;
}entry_lo_t;
}entry_lo_t;
typedef struct entry_hi_t
{
typedef struct entry_hi_t
{
uint64_t asid : 8;
uint64_t : 5;
uint64_t vpn2 : 27;
uint64_t : 22;
uint64_t r : 2;
}entry_hi_t;
}entry_hi_t;
typedef struct tlb_item_t
{
typedef struct tlb_item_t
{
entry_lo_t entry_lo[2];
entry_hi_t entry_hi;
page_mask_t page_mask;
}tlb_item_t;
}tlb_item_t;
#define read_c0_diag() __read_32bit_c0_register($22, 0)
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
#define read_c0_badvaddr() __read_64bit_c0_register($8, 0)
#define read_c0_random() __read_32bit_c0_register($1, 0)
#define read_c0_diag() __read_32bit_c0_register($22, 0)
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
#define read_c0_badvaddr() __read_64bit_c0_register($8, 0)
#define read_c0_random() __read_32bit_c0_register($1, 0)
#define reg_type_convert(variable,new_type) *((new_type *)(&variable))
#define lowbit(x) ((x) & (-(x)))
#define reg_type_convert(variable,new_type) *((new_type *)(&variable))
#define lowbit(x) ((x) & (-(x)))
void mmu_init();
void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
cpu_mode_t mmu_get_cpu_mode();
void mmu_clear_tlb();
void mmu_clear_itlb();
uint32_t mmu_get_max_tlb_index();
void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
void mmu_tlb_write_random(tlb_item_t *tlb_item);
void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
void mmu_tlb_item_init(tlb_item_t *tlb_item);
void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
uint32_t mmu_tlb_get_random();
uint32_t mmu_tlb_get_index();
void mmu_tlb_set_index(uint32_t index);
uint32_t mmu_tlb_is_matched();
uint64_t mmu_tlb_get_bad_vaddr();
void mmu_init();
void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
cpu_mode_t mmu_get_cpu_mode();
void mmu_clear_tlb();
void mmu_clear_itlb();
uint32_t mmu_get_max_tlb_index();
void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
void mmu_tlb_write_random(tlb_item_t *tlb_item);
void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
void mmu_tlb_item_init(tlb_item_t *tlb_item);
void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
uint32_t mmu_tlb_get_random();
uint32_t mmu_tlb_get_index();
void mmu_tlb_set_index(uint32_t index);
uint32_t mmu_tlb_is_matched();
uint64_t mmu_tlb_get_bad_vaddr();
void tlb_dump();
void tlb_dump();
#endif

4
libcpu/mips/gs264/mmu.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -19,7 +19,7 @@
#define MEMWT (2<<2) /* write through, no write allocate */
#define SHAREDEVICE (1<<2) /* shared device */
#define STRONGORDER (0<<2) /* strong ordered */
#define XN (1<<4) /* eXecute Never */
#define XN (1<<4) /* execute Never */
#ifdef RT_USING_USERSPACE
#define AP_RW (1<<10) /* supervisor=RW, user=No */
#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */