[BSP] move libcpu/mips/x1000 to bsp/x1000/cpu
This commit is contained in:
parent
ea507e2e81
commit
a972fcc0b5
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@ -28,7 +28,7 @@ Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
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if GetDepend('RT_USING_HARD_FLOAT'):
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env['CCFLAGS'] = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')
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@ -0,0 +1,18 @@
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# RT-Thread building script for bridge
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import os
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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group = []
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list = os.listdir(cwd)
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# add common code files
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group = group + SConscript(os.path.join('common', 'SConscript'))
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# cpu porting code files
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group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
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Return('group')
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@ -0,0 +1,220 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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* Copyright (C) 2001 MIPS Technologies, Inc.
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* Copyright (C) 2002 Maciej W. Rozycki
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*
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* Some useful macros for MIPS assembler code
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*
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* Some of the routines below contain useless nops that will be optimized
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* away by gas in -O mode. These nops are however required to fill delay
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* slots in noreorder mode.
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*/
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#ifndef __ASM_H__
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#define __ASM_H__
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/*
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* LEAF - declare leaf routine
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*/
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#define LEAF(symbol) \
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.globl symbol; \
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.align 2; \
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.type symbol,@function; \
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.ent symbol,0; \
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symbol: .frame sp,0,ra
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/*
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* NESTED - declare nested routine entry point
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*/
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#define NESTED(symbol, framesize, rpc) \
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.globl symbol; \
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.align 2; \
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.type symbol,@function; \
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.ent symbol,0; \
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symbol: .frame sp, framesize, rpc
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/*
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* END - mark end of function
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*/
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#define END(function) \
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.end function; \
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.size function,.-function
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/*
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* EXPORT - export definition of symbol
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*/
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#define EXPORT(symbol) \
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.globl symbol; \
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symbol:
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/*
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* FEXPORT - export definition of a function symbol
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*/
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#define FEXPORT(symbol) \
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.globl symbol; \
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.type symbol,@function; \
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symbol:
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/*
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* Global data declaration with size.
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*/
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#define EXPORTS(name,sz) \
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.globl name; \
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.type name,@object; \
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.size name,sz; \
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name:
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/*
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* Weak data declaration with size.
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*/
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#define WEXPORT(name,sz) \
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.weakext name; \
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.type name,@object; \
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.size name,sz; \
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name:
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/*
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* Global data reference with size.
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*/
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#define IMPORT(name, size) \
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.extern name,size
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/*
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* Global zeroed data.
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*/
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#define BSS(name,size) \
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.type name,@object; \
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.comm name,size
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/*
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* Local zeroed data.
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*/
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#define LBSS(name,size) \
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.lcomm name,size
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/*
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* ABS - export absolute symbol
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*/
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#define ABS(symbol,value) \
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.globl symbol; \
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symbol = value
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#define TEXT(msg) \
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.pushsection .data; \
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8: .asciiz msg; \
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.popsection;
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#define ENTRY(name) \
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.globl name; \
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.align 2; \
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.ent name,0; \
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name##:
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/*
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* Macros to handle different pointer/register sizes for 32/64-bit code
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*/
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/*
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* Size of a register
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*/
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#define SZREG 4
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/*
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* Use the following macros in assemblercode to load/store registers,
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* pointers etc.
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*/
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#define REG_S sw
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#define REG_L lw
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#define REG_SUBU subu
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#define REG_ADDU addu
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/*
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* How to add/sub/load/store/shift C int variables.
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*/
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#define INT_ADD add
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#define INT_ADDU addu
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#define INT_ADDI addi
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#define INT_ADDIU addiu
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#define INT_SUB sub
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#define INT_SUBU subu
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#define INT_L lw
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#define INT_S sw
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#define INT_SLL sll
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#define INT_SLLV sllv
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#define INT_SRL srl
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#define INT_SRLV srlv
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#define INT_SRA sra
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#define INT_SRAV srav
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/*
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* How to add/sub/load/store/shift C long variables.
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*/
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#define LONG_ADD add
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#define LONG_ADDU addu
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#define LONG_ADDI addi
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#define LONG_ADDIU addiu
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#define LONG_SUB sub
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#define LONG_SUBU subu
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#define LONG_L lw
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#define LONG_S sw
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#define LONG_SLL sll
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#define LONG_SLLV sllv
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#define LONG_SRL srl
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#define LONG_SRLV srlv
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#define LONG_SRA sra
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#define LONG_SRAV srav
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#define LONG .word
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#define LONGSIZE 4
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#define LONGMASK 3
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#define LONGLOG 2
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/*
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* How to add/sub/load/store/shift pointers.
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*/
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#define PTR_ADD add
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#define PTR_ADDU addu
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#define PTR_ADDI addi
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#define PTR_ADDIU addiu
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#define PTR_SUB sub
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#define PTR_SUBU subu
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#define PTR_L lw
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#define PTR_S sw
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#define PTR_LA la
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#define PTR_SLL sll
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#define PTR_SLLV sllv
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#define PTR_SRL srl
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#define PTR_SRLV srlv
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#define PTR_SRA sra
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#define PTR_SRAV srav
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#define PTR_SCALESHIFT 2
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#define PTR .word
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#define PTRSIZE 4
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#define PTRLOG 2
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/*
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* Some cp0 registers were extended to 64bit for MIPS III.
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*/
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#define MFC0 mfc0
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#define MTC0 mtc0
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#define SSNOP sll zero, zero, 1
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#endif /* end of __ASM_H__ */
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@ -0,0 +1,166 @@
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/*
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* File : cpu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2010, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-05-17 swkyer first version
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*/
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#ifndef __EXCEPTION_H__
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#define __EXCEPTION_H__
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/*
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* important register numbers
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*/
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#define REG_EPC 37
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#define REG_FP 72
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#define REG_SP 29
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/*
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* Stack layout for the GDB exception handler
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* Derived from the stack layout described in asm-mips/stackframe.h
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*
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* The first PTRSIZE*6 bytes are argument save space for C subroutines.
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*/
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#define NUMREGS 90
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#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
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#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
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#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
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#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
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#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
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#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
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#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
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#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
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#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
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#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
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#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
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#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
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#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
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#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
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#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
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#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
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#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
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#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
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#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
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#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
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#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
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#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
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#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
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#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
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#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
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#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
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#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
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#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
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#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
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#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
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#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
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#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
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/*
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* Saved special registers
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*/
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#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
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#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
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#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
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#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
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#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
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#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
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///*
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// * Saved floating point registers
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// */
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//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
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//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
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//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
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//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
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//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
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//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
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//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
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//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
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//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
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//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
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//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
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//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
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//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
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//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
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//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
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//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
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//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
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//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
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//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
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//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
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//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
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//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
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//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
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//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
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//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
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//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
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//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
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//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
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//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
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//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
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//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
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//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
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//
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//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
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//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
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//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
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//
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//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
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//
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///*
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// * Again, CP0 registers
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// */
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//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
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#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */
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#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */
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#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
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#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
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#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
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#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
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#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
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#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
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#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
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#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
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#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
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#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
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#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
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#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
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#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
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#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
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#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
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#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
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/*
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* This is the same as above, but for the high-level
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* part of the INT stub.
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*/
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typedef struct pt_regs_s
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{
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/* Saved main processor registers. */
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rt_base_t regs[32];
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/* Saved special registers. */
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rt_base_t cp0_status;
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rt_base_t hi;
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rt_base_t lo;
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rt_base_t cp0_badvaddr;
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rt_base_t cp0_cause;
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rt_base_t cp0_epc;
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} pt_regs_t;
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typedef void (* exception_func_t)(pt_regs_t *regs);
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extern exception_func_t sys_exception_handlers[];
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exception_func_t rt_set_except_vector(int n, exception_func_t func);
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void install_default_execpt_handle(void);
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#endif /* end of __EXCEPTION_H__ */
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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||||
* SPDX-License-Identifier: Apache-2.0
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*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016-09-07 Urey first version
|
||||
*/
|
||||
|
||||
#ifndef _COMMON_MIPS_H_
|
||||
#define _COMMON_MIPS_H_
|
||||
|
||||
#include "mips_cfg.h"
|
||||
|
||||
#include "mips_types.h"
|
||||
#include "mips_asm.h"
|
||||
#include "mips_def.h"
|
||||
#include "mips_regs.h"
|
||||
#include "mips_addrspace.h"
|
||||
#include "mips_cache.h"
|
||||
#include "mips_context.h"
|
||||
#include "mips_excpt.h"
|
||||
|
||||
#endif /* _COMMON_MIPS_H_ */
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* File : mips.inc
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2010, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 sangwei first version
|
||||
*/
|
||||
#ifndef __MIPS_INC__
|
||||
#define __MIPS_INC__
|
||||
|
||||
#define zero $0 /* wired zero */
|
||||
// #define at $1
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel scratch */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* same like fp! */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
#endif /* end of __MIPS_INC__ */
|
|
@ -0,0 +1,207 @@
|
|||
/*
|
||||
* File : mips_addrspace.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ12ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ADDRSPACE_H_
|
||||
#define _MIPS_ADDRSPACE_H_
|
||||
|
||||
|
||||
/*
|
||||
* Configure language
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ATYPE_
|
||||
#define _ATYPE32_
|
||||
#define _ATYPE64_
|
||||
#define _CONST64_(x) x
|
||||
#else
|
||||
#define _ATYPE_ __PTRDIFF_TYPE__
|
||||
#define _ATYPE32_ int
|
||||
#define _ATYPE64_ __s64
|
||||
#ifdef CONFIG_64BIT
|
||||
#define _CONST64_(x) x ## L
|
||||
#else
|
||||
#define _CONST64_(x) x ## LL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 32-bit MIPS address spaces
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ACAST32_
|
||||
#define _ACAST64_
|
||||
#else
|
||||
#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
|
||||
#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Returns the kernel segment base of a given address
|
||||
*/
|
||||
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
|
||||
|
||||
/*
|
||||
* Returns the physical address of a CKSEGx / XKPHYS address
|
||||
*/
|
||||
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
|
||||
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
|
||||
_CONST64_(0x000000ffffffffff))
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
/*
|
||||
* Memory segments (64bit kernel mode addresses)
|
||||
* The compatibility segments use the full 64-bit sign extended value. Note
|
||||
* the R8000 doesn't have them so don't reference these in generic MIPS code.
|
||||
*/
|
||||
#define XKUSEG _CONST64_(0x0000000000000000)
|
||||
#define XKSSEG _CONST64_(0x4000000000000000)
|
||||
#define XKPHYS _CONST64_(0x8000000000000000)
|
||||
#define XKSEG _CONST64_(0xc000000000000000)
|
||||
#define CKSEG0 _CONST64_(0xffffffff80000000)
|
||||
#define CKSEG1 _CONST64_(0xffffffffa0000000)
|
||||
#define CKSSEG _CONST64_(0xffffffffc0000000)
|
||||
#define CKSEG3 _CONST64_(0xffffffffe0000000)
|
||||
|
||||
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
|
||||
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
|
||||
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
|
||||
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
|
||||
|
||||
#else
|
||||
|
||||
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
|
||||
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
|
||||
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
|
||||
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
|
||||
|
||||
/*
|
||||
* Map an address to a certain kernel segment
|
||||
*/
|
||||
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
|
||||
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
|
||||
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
|
||||
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
|
||||
|
||||
/*
|
||||
* Memory segments (32bit kernel mode addresses)
|
||||
* These are the traditional names used in the 32-bit universe.
|
||||
*/
|
||||
//#define KUSEGBASE 0x00000000
|
||||
//#define KSEG0BASE 0x80000000
|
||||
//#define KSEG1BASE 0xa0000000
|
||||
//#define KSEG2BASE 0xc0000000
|
||||
//#define KSEG3BASE 0xe0000000
|
||||
|
||||
#define CKUSEG 0x00000000
|
||||
#define CKSEG0 0x80000000
|
||||
#define CKSEG1 0xa0000000
|
||||
#define CKSEG2 0xc0000000
|
||||
#define CKSEG3 0xe0000000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cache modes for XKPHYS address conversion macros
|
||||
*/
|
||||
#define K_CALG_COH_EXCL1_NOL2 0
|
||||
#define K_CALG_COH_SHRL1_NOL2 1
|
||||
#define K_CALG_UNCACHED 2
|
||||
#define K_CALG_NONCOHERENT 3
|
||||
#define K_CALG_COH_EXCL 4
|
||||
#define K_CALG_COH_SHAREABLE 5
|
||||
#define K_CALG_NOTUSED 6
|
||||
#define K_CALG_UNCACHED_ACCEL 7
|
||||
|
||||
/*
|
||||
* 64-bit address conversions
|
||||
*/
|
||||
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
|
||||
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
|
||||
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
|
||||
(_CONST64_(cm) << 59) | (a))
|
||||
|
||||
/*
|
||||
* Returns the uncached address of a sdram address
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
|
||||
/* We use a 36 bit physical address map here and
|
||||
cannot access physical memory directly from core */
|
||||
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
|
||||
#else /* !CONFIG_SOC_AU1X00 */
|
||||
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
|
||||
#endif /* CONFIG_SOC_AU1X00 */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
|
||||
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
|
||||
* R8000 implements most with its 48-bit physical address space.
|
||||
*/
|
||||
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
|
||||
|
||||
#ifndef CONFIG_CPU_R8000
|
||||
|
||||
/*
|
||||
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
|
||||
* in order to catch bugs in the source code.
|
||||
*/
|
||||
|
||||
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
|
||||
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
|
||||
|
||||
#endif
|
||||
|
||||
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*
|
||||
* Change virtual addresses to physical addresses and vv.
|
||||
* These are trivial on the 1:1 Linux/MIPS mapping
|
||||
*/
|
||||
static inline phys_addr_t virt_to_phys(volatile void * address)
|
||||
{
|
||||
#ifndef CONFIG_64BIT
|
||||
return CPHYSADDR(address);
|
||||
#else
|
||||
return XPHYSADDR(address);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void * phys_to_virt(unsigned long address)
|
||||
{
|
||||
#ifndef CONFIG_64BIT
|
||||
return (void *)KSEG0ADDR(address);
|
||||
#else
|
||||
return (void *)CKSEG0ADDR(address);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _MIPS_ADDRSPACE_H_ */
|
|
@ -0,0 +1,447 @@
|
|||
/*
|
||||
* File : mips_asm.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ7ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ASM_H_
|
||||
#define _MIPS_ASM_H_
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
/* Interface macro & data definition */
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
|
||||
|
||||
#ifdef __ghs__
|
||||
#define ALIGN(x) .##align (1 << (x))
|
||||
#else
|
||||
#define ALIGN(x) .##align (x)
|
||||
#endif
|
||||
|
||||
#ifdef __ghs__
|
||||
#define SET_MIPS3()
|
||||
#define SET_MIPS0()
|
||||
#define SET_PUSH()
|
||||
#define SET_POP()
|
||||
#else
|
||||
#define SET_MIPS3() .##set mips3
|
||||
#define SET_MIPS0() .##set mips0
|
||||
#define SET_PUSH() .##set push
|
||||
#define SET_POP() .##set pop
|
||||
#endif
|
||||
|
||||
/* Different assemblers have different requirements for how to
|
||||
* indicate that the next section is bss :
|
||||
*
|
||||
* Some use : .bss
|
||||
* Others use : .section bss
|
||||
*
|
||||
* We select which to use based on _BSS_OLD_, which may be defined
|
||||
* in makefile.
|
||||
*/
|
||||
#ifdef _BSS_OLD_
|
||||
#define BSS .##section bss
|
||||
#else
|
||||
#define BSS .##bss
|
||||
#endif
|
||||
|
||||
#define LEAF(name)\
|
||||
.##text;\
|
||||
.##globl name;\
|
||||
.##ent name;\
|
||||
name:
|
||||
|
||||
|
||||
#define SLEAF(name)\
|
||||
.##text;\
|
||||
.##ent name;\
|
||||
name:
|
||||
|
||||
|
||||
#ifdef __ghs__
|
||||
#define END(name)\
|
||||
.##end name
|
||||
#else
|
||||
#define END(name)\
|
||||
.##size name,.-name;\
|
||||
.##end name
|
||||
#endif
|
||||
|
||||
|
||||
#define EXTERN(name)
|
||||
|
||||
#else
|
||||
|
||||
#define U64 unsigned long long
|
||||
#define U32 unsigned int
|
||||
#define U16 unsigned short
|
||||
#define U8 unsigned char
|
||||
#define S64 signed long long
|
||||
#define S32 int
|
||||
#define S16 short int
|
||||
#define S8 signed char
|
||||
//#define bool U8
|
||||
|
||||
#ifndef _SIZE_T_
|
||||
#define _SIZE_T_
|
||||
#ifdef __ghs__
|
||||
typedef unsigned int size_t;
|
||||
#else
|
||||
typedef unsigned long size_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Sets the result on bPort */
|
||||
#define BIT_SET(bPort,bBitMask) (bPort |= bBitMask)
|
||||
#define BIT_CLR(bPort,bBitMask) (bPort &= ~bBitMask)
|
||||
|
||||
/* Returns the result */
|
||||
#define GET_BIT_SET(bPort,bBitMask) (bPort | bBitMask)
|
||||
#define GET_BIT_CLR(bPort,bBitMask) (bPort & ~bBitMask)
|
||||
|
||||
/* Returns 0 if the condition is False & a non-zero value if it is True */
|
||||
#define TEST_BIT_SET(bPort,bBitMask) (bPort & bBitMask)
|
||||
#define TEST_BIT_CLR(bPort,bBitMask) ((~bPort) & bBitMask)
|
||||
|
||||
/* Split union definitions */
|
||||
typedef union tunSU16
|
||||
{
|
||||
U16 hwHW;
|
||||
struct tst2U8
|
||||
{
|
||||
U8 bB0;
|
||||
U8 bB1;
|
||||
}st2U8;
|
||||
}tunSU16;
|
||||
|
||||
typedef union tunSU32
|
||||
{
|
||||
U32 wW;
|
||||
struct tst2U16
|
||||
{
|
||||
U16 hwHW0;
|
||||
U16 hwHW1;
|
||||
}st2U16;
|
||||
struct tst4U8
|
||||
{
|
||||
U8 bB0;
|
||||
U8 bB1;
|
||||
U8 bB2;
|
||||
U8 bB3;
|
||||
}st4U8;
|
||||
}tunSU32;
|
||||
|
||||
#endif /* #ifdef __ASSEMBLY__ */
|
||||
|
||||
|
||||
/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
|
||||
|
||||
|
||||
#define NO_ERR 0x00000000 /* operation completed successfully */
|
||||
#define ERR 0xffffffff /* operation completed not successfully */
|
||||
|
||||
#define False 0
|
||||
#define True !False
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif//NULL
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(x,y) ((x) < (y) ? (x) : (y))
|
||||
#endif//MIN
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(x,y) ((x) > (y) ? (x) : (y))
|
||||
#endif//MAX
|
||||
|
||||
#define MAXUINT(w) (\
|
||||
((w) == sizeof(U8)) ? 0xFFU :\
|
||||
((w) == sizeof(U16)) ? 0xFFFFU :\
|
||||
((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
|
||||
)
|
||||
|
||||
#define MAXINT(w) (\
|
||||
((w) == sizeof(S8)) ? 0x7F :\
|
||||
((w) == sizeof(S16)) ? 0x7FFF :\
|
||||
((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
|
||||
)
|
||||
|
||||
#define MSK(n) ((1 << (n)) - 1)
|
||||
|
||||
#define KUSEG_MSK 0x80000000
|
||||
#define KSEG_MSK 0xE0000000
|
||||
|
||||
#define KUSEGBASE 0x00000000
|
||||
#define KSEG0BASE 0x80000000
|
||||
#define KSEG1BASE 0xA0000000
|
||||
#define KSSEGBASE 0xC0000000
|
||||
#define KSEG3BASE 0xE0000000
|
||||
|
||||
/* Below macros perform the following functions :
|
||||
*
|
||||
* KSEG0 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
|
||||
* KSEG1 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
|
||||
* PHYS : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
|
||||
* KSSEG : Not relevant for converting, but used for determining range.
|
||||
* KSEG3 : Not relevant for converting, but used for determining range.
|
||||
* KUSEG : Not relevant for converting, but used for determining range.
|
||||
* KSEG0A : Same as KSEG0 but operates on register rather than constant.
|
||||
* KSEG1A : Same as KSEG1 but operates on register rather than constant.
|
||||
* PHYSA : Same as PHYS but operates on register rather than constant.
|
||||
* CACHED : Alias for KSEG0 macro .
|
||||
* (Note that KSEG0 cache attribute is determined by K0
|
||||
* field of Config register, but this is typically cached).
|
||||
* UNCACHED : Alias for KSEG1 macro .
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define KSEG0(addr) (((addr) & ~KSEG_MSK) | KSEG0BASE)
|
||||
#define KSEG1(addr) (((addr) & ~KSEG_MSK) | KSEG1BASE)
|
||||
#define KSSEG(addr) (((addr) & ~KSEG_MSK) | KSSEGBASE)
|
||||
#define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE)
|
||||
#define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE)
|
||||
#define PHYS(addr) ( (addr) & ~KSEG_MSK)
|
||||
#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE
|
||||
#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE
|
||||
#define PHYSA(reg) and reg, ~KSEG_MSK
|
||||
#else
|
||||
#define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE)
|
||||
#define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE)
|
||||
#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE)
|
||||
#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE)
|
||||
#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
|
||||
#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK)
|
||||
#endif
|
||||
|
||||
#define CACHED(addr) KSEG0(addr)
|
||||
#define UNCACHED(addr) KSEG1(addr)
|
||||
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
/* Macroes to access variables at constant addresses
|
||||
* Compensates for signed 16 bit displacement
|
||||
* Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD)
|
||||
* sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
|
||||
*/
|
||||
#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000)
|
||||
#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000)
|
||||
#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000)
|
||||
#define LO_OFFS(addr) ((addr) & 0xffff)
|
||||
#endif
|
||||
|
||||
|
||||
/* Most/Least significant 32 bit from 64 bit double word */
|
||||
#define HI32(data64) ((U32)(data64 >> 32))
|
||||
#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF))
|
||||
|
||||
#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY)))
|
||||
#define REG8( addr ) (*(volatile U8 *) (addr))
|
||||
#define REG16( addr ) (*(volatile U16 *)(addr))
|
||||
#define REG32( addr ) (*(volatile U32 *)(addr))
|
||||
#define REG64( addr ) (*(volatile U64 *)(addr))
|
||||
#endif
|
||||
|
||||
/* Register field mapping */
|
||||
#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF)
|
||||
|
||||
/* absolute register address, access */
|
||||
#define REGA(addr) REG32(addr)
|
||||
|
||||
/* physical register address, access: base address + offsett */
|
||||
#define REGP(base,phys) REG32( (U32)(base) + (phys) )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG(base,offs) REG32( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/**************************************
|
||||
* Macroes not used by YAMON any more
|
||||
* (kept for backwards compatibility)
|
||||
*/
|
||||
/* register read field */
|
||||
#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \
|
||||
>> addr##_##fld##_##SHF)
|
||||
|
||||
/* register write numeric field value */
|
||||
#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
|
||||
| ((intval) << addr##_##fld##_##SHF))
|
||||
|
||||
/* register write enumerated field value */
|
||||
#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
|
||||
| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
|
||||
|
||||
|
||||
/* Examples:
|
||||
*
|
||||
* exccode = REGARD(CPU_CAUSE,EXC);
|
||||
*
|
||||
* REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
|
||||
* | REGAWRE(OSG_CONTROL,DTYPE,PC1);
|
||||
*/
|
||||
|
||||
|
||||
/* register read field */
|
||||
#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \
|
||||
>> offs##_##fld##_##SHF)
|
||||
|
||||
/* register write numeric field value */
|
||||
#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
|
||||
| (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
|
||||
|
||||
/* register write enumerated field value */
|
||||
#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
|
||||
| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
|
||||
|
||||
|
||||
/* physical register read field */
|
||||
#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \
|
||||
>> phys##_##fld##_##SHF)
|
||||
|
||||
/* physical register write numeric field value */
|
||||
#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
|
||||
| ((intval) << phys##_##fld##_##SHF))
|
||||
|
||||
/* physical register write enumerated field value */
|
||||
#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
|
||||
| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
|
||||
/*
|
||||
* End of macroes not used by YAMON any more
|
||||
*********************************************/
|
||||
|
||||
/* Endian related macros */
|
||||
|
||||
#define SWAP_BYTEADDR32( addr ) ( (addr) ^ 0x3 )
|
||||
#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
|
||||
|
||||
/* Set byte address to little endian format */
|
||||
#ifdef EL
|
||||
#define SWAP_BYTEADDR_EL(addr) addr
|
||||
#else
|
||||
#define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr )
|
||||
#endif
|
||||
|
||||
/* Set byte address to big endian format */
|
||||
#ifdef EB
|
||||
#define SWAP_BYTEADDR_EB(addr) addr
|
||||
#else
|
||||
#define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr )
|
||||
#endif
|
||||
|
||||
/* Set U16 address to little endian format */
|
||||
#ifdef EL
|
||||
#define SWAP_U16ADDR_EL(addr) addr
|
||||
#else
|
||||
#define SWAP_U16ADDR_EL(addr) SWAP_U16ADDR32( addr )
|
||||
#endif
|
||||
|
||||
/* Set U16 address to big endian format */
|
||||
#ifdef EB
|
||||
#define SWAP_U16ADDR_EB(addr) addr
|
||||
#else
|
||||
#define SWAP_U16ADDR_EB(addr) SWAP_U16ADDR32( addr )
|
||||
#endif
|
||||
|
||||
#ifdef EL
|
||||
#define REGW32LE(addr, data) REG32(addr) = (data)
|
||||
#define REGR32LE(addr, data) (data) = REG32(addr)
|
||||
#else
|
||||
#define REGW32LE(addr, data) REG32(addr) = SWAPEND32(data)
|
||||
#define REGR32LE(addr, data) (data) = REG32(addr), (data) = SWAPEND32(data)
|
||||
#endif
|
||||
|
||||
/* Set of 'LE'-macros, convert by BE: */
|
||||
#ifdef EL
|
||||
#define CPU_TO_LE32( value ) (value)
|
||||
#define LE32_TO_CPU( value ) (value)
|
||||
|
||||
#define CPU_TO_LE16( value ) (value)
|
||||
#define LE16_TO_CPU( value ) (value)
|
||||
#else
|
||||
#define CPU_TO_LE32( value ) ( ( ((U32)value) << 24) | \
|
||||
((0x0000FF00UL & ((U32)value)) << 8) | \
|
||||
((0x00FF0000UL & ((U32)value)) >> 8) | \
|
||||
( ((U32)value) >> 24) )
|
||||
#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
|
||||
|
||||
#define CPU_TO_LE16( value ) ( ((U16)(((U16)value) << 8)) | \
|
||||
((U16)(((U16)value) >> 8)) )
|
||||
#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
|
||||
#endif
|
||||
|
||||
/* Set of 'BE'-macros, convert by LE: */
|
||||
#ifdef EB
|
||||
#define CPU_TO_BE32( value ) (value)
|
||||
#define BE32_TO_CPU( value ) (value)
|
||||
|
||||
#define CPU_TO_BE16( value ) (value)
|
||||
#define BE16_TO_CPU( value ) (value)
|
||||
#else
|
||||
#define CPU_TO_BE32( value ) ( ( ((U32)value) << 24) | \
|
||||
((0x0000FF00UL & ((U32)value)) << 8) | \
|
||||
((0x00FF0000UL & ((U32)value)) >> 8) | \
|
||||
( ((U32)value) >> 24) )
|
||||
#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
|
||||
|
||||
#define CPU_TO_BE16( value ) ( ((U16)(((U16)value) << 8)) | \
|
||||
((U16)(((U16)value) >> 8)) )
|
||||
#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
|
||||
#endif
|
||||
|
||||
|
||||
/* Control characters */
|
||||
#define CTRL_A ('A'-0x40)
|
||||
#define CTRL_B ('B'-0x40)
|
||||
#define CTRL_C ('C'-0x40)
|
||||
#define CTRL_D ('D'-0x40)
|
||||
#define CTRL_E ('E'-0x40)
|
||||
#define CTRL_F ('F'-0x40)
|
||||
#define CTRL_H ('H'-0x40)
|
||||
#define CTRL_K ('K'-0x40)
|
||||
#define CTRL_N ('N'-0x40)
|
||||
#define CTRL_P ('P'-0x40)
|
||||
#define CTRL_U ('U'-0x40)
|
||||
#define BACKSPACE 0x08
|
||||
#define DEL 0x7F
|
||||
#define TAB 0x09
|
||||
#define CR 0x0D /* Enter Key */
|
||||
#define LF 0x0A
|
||||
#define ESC 0x1B
|
||||
#define SP 0x20
|
||||
#define CSI 0x9B
|
||||
|
||||
|
||||
/* DEF2STR(x) converts #define symbol to string */
|
||||
#define DEF2STR1(x) #x
|
||||
#define DEF2STR(x) DEF2STR1(x)
|
||||
|
||||
|
||||
#endif /* _MIPS_ASM_H_ */
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* File : mips_cache.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ7ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "mips.h"
|
||||
|
||||
extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
|
||||
void r4k_cache_init(void)
|
||||
{
|
||||
// cache_init(dcache_size, cpu_dcache_line_size);
|
||||
}
|
||||
|
||||
void r4k_cache_flush_all(void)
|
||||
{
|
||||
blast_dcache16();
|
||||
blast_icache16();
|
||||
}
|
||||
|
||||
|
||||
void r4k_icache_flush_all(void)
|
||||
{
|
||||
blast_icache16();
|
||||
}
|
||||
|
||||
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
|
||||
{
|
||||
rt_ubase_t end, a;
|
||||
|
||||
if (size > g_mips_core.icache_size)
|
||||
{
|
||||
blast_icache16();
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
|
||||
|
||||
a = addr & ~(ic_lsize - 1);
|
||||
end = ((addr + size) - 1) & ~(ic_lsize - 1);
|
||||
while (1)
|
||||
{
|
||||
flush_icache_line(a);
|
||||
if (a == end)
|
||||
break;
|
||||
a += ic_lsize;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
|
||||
{
|
||||
rt_ubase_t end, a;
|
||||
rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
|
||||
|
||||
a = addr & ~(ic_lsize - 1);
|
||||
end = ((addr + size) - 1) & ~(ic_lsize - 1);
|
||||
while (1)
|
||||
{
|
||||
lock_icache_line(a);
|
||||
if (a == end)
|
||||
break;
|
||||
a += ic_lsize;
|
||||
}
|
||||
}
|
||||
|
||||
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
|
||||
{
|
||||
rt_ubase_t end, a;
|
||||
rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
|
||||
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = ((addr + size) - 1) & ~(dc_lsize - 1);
|
||||
while (1)
|
||||
{
|
||||
invalidate_dcache_line(a);
|
||||
if (a == end)
|
||||
break;
|
||||
a += dc_lsize;
|
||||
}
|
||||
}
|
||||
|
||||
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
|
||||
{
|
||||
rt_ubase_t end, a;
|
||||
|
||||
if (size >= g_mips_core.dcache_size)
|
||||
{
|
||||
blast_dcache16();
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
|
||||
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = ((addr + size) - 1) & ~(dc_lsize - 1);
|
||||
while (1)
|
||||
{
|
||||
flush_dcache_line(a);
|
||||
if (a == end)
|
||||
break;
|
||||
a += dc_lsize;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define dma_cache_wback_inv(start,size) \
|
||||
do { (void) (start); (void) (size); } while (0)
|
||||
#define dma_cache_wback(start,size) \
|
||||
do { (void) (start); (void) (size); } while (0)
|
||||
#define dma_cache_inv(start,size) \
|
||||
do { (void) (start); (void) (size); } while (0)
|
||||
|
||||
|
||||
void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction)
|
||||
{
|
||||
switch (direction)
|
||||
{
|
||||
case DMA_TO_DEVICE:
|
||||
r4k_dcache_wback_inv(addr, size);
|
||||
break;
|
||||
|
||||
case DMA_FROM_DEVICE:
|
||||
r4k_dcache_wback_inv(addr, size);
|
||||
break;
|
||||
|
||||
case DMA_BIDIRECTIONAL:
|
||||
dma_cache_wback_inv(addr, size);
|
||||
break;
|
||||
default:
|
||||
RT_ASSERT(0) ;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
* File : mips_cache.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ10ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_CACHE_H_
|
||||
#define _MIPS_CACHE_H_
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <rtdef.h>
|
||||
#include <mips_cfg.h>
|
||||
|
||||
/*
|
||||
* Cache Operations available on all MIPS processors with R4000-style caches
|
||||
*/
|
||||
#define INDEX_INVALIDATE_I 0x00
|
||||
#define INDEX_WRITEBACK_INV_D 0x01
|
||||
#define INDEX_LOAD_TAG_I 0x04
|
||||
#define INDEX_LOAD_TAG_D 0x05
|
||||
#define INDEX_STORE_TAG_I 0x08
|
||||
#define INDEX_STORE_TAG_D 0x09
|
||||
#if defined(CONFIG_CPU_LOONGSON2)
|
||||
#define HIT_INVALIDATE_I 0x00
|
||||
#else
|
||||
#define HIT_INVALIDATE_I 0x10
|
||||
#endif
|
||||
#define HIT_INVALIDATE_D 0x11
|
||||
#define HIT_WRITEBACK_INV_D 0x15
|
||||
|
||||
/*
|
||||
*The lock state is cleared by executing an Index
|
||||
Invalidate, Index Writeback Invalidate, Hit
|
||||
Invalidate, or Hit Writeback Invalidate
|
||||
operation to the locked line, or via an Index
|
||||
Store Tag operation with the lock bit reset in
|
||||
the TagLo register.
|
||||
*/
|
||||
#define FETCH_AND_LOCK_I 0x1c
|
||||
#define FETCH_AND_LOCK_D 0x1d
|
||||
|
||||
|
||||
enum dma_data_direction
|
||||
{
|
||||
DMA_BIDIRECTIONAL = 0,
|
||||
DMA_TO_DEVICE = 1,
|
||||
DMA_FROM_DEVICE = 2,
|
||||
DMA_NONE = 3,
|
||||
};
|
||||
|
||||
/*
|
||||
* R4000-specific cacheops
|
||||
*/
|
||||
#define CREATE_DIRTY_EXCL_D 0x0d
|
||||
#define FILL 0x14
|
||||
#define HIT_WRITEBACK_I 0x18
|
||||
#define HIT_WRITEBACK_D 0x19
|
||||
|
||||
/*
|
||||
* R4000SC and R4400SC-specific cacheops
|
||||
*/
|
||||
#define INDEX_INVALIDATE_SI 0x02
|
||||
#define INDEX_WRITEBACK_INV_SD 0x03
|
||||
#define INDEX_LOAD_TAG_SI 0x06
|
||||
#define INDEX_LOAD_TAG_SD 0x07
|
||||
#define INDEX_STORE_TAG_SI 0x0A
|
||||
#define INDEX_STORE_TAG_SD 0x0B
|
||||
#define CREATE_DIRTY_EXCL_SD 0x0f
|
||||
#define HIT_INVALIDATE_SI 0x12
|
||||
#define HIT_INVALIDATE_SD 0x13
|
||||
#define HIT_WRITEBACK_INV_SD 0x17
|
||||
#define HIT_WRITEBACK_SD 0x1b
|
||||
#define HIT_SET_VIRTUAL_SI 0x1e
|
||||
#define HIT_SET_VIRTUAL_SD 0x1f
|
||||
|
||||
/*
|
||||
* R5000-specific cacheops
|
||||
*/
|
||||
#define R5K_PAGE_INVALIDATE_S 0x17
|
||||
|
||||
/*
|
||||
* RM7000-specific cacheops
|
||||
*/
|
||||
#define PAGE_INVALIDATE_T 0x16
|
||||
|
||||
/*
|
||||
* R10000-specific cacheops
|
||||
*
|
||||
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
|
||||
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
|
||||
*/
|
||||
#define INDEX_WRITEBACK_INV_S 0x03
|
||||
#define INDEX_LOAD_TAG_S 0x07
|
||||
#define INDEX_STORE_TAG_S 0x0B
|
||||
#define HIT_INVALIDATE_S 0x13
|
||||
#define CACHE_BARRIER 0x14
|
||||
#define HIT_WRITEBACK_INV_S 0x17
|
||||
#define INDEX_LOAD_DATA_I 0x18
|
||||
#define INDEX_LOAD_DATA_D 0x19
|
||||
#define INDEX_LOAD_DATA_S 0x1b
|
||||
#define INDEX_STORE_DATA_I 0x1c
|
||||
#define INDEX_STORE_DATA_D 0x1d
|
||||
#define INDEX_STORE_DATA_S 0x1f
|
||||
|
||||
#define cache_op(op, addr) \
|
||||
__asm__ __volatile__( \
|
||||
".set push\n" \
|
||||
".set noreorder\n" \
|
||||
".set mips3\n" \
|
||||
"cache %0, %1\n" \
|
||||
".set pop\n" \
|
||||
: \
|
||||
: "i" (op), "R" (*(unsigned char *)(addr)))
|
||||
|
||||
#define cache16_unroll32(base, op) \
|
||||
__asm__ __volatile__( \
|
||||
" .set noreorder \n" \
|
||||
" .set mips3 \n" \
|
||||
" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
|
||||
" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
|
||||
" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
|
||||
" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
|
||||
" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
|
||||
" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
|
||||
" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
|
||||
" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
|
||||
" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
|
||||
" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
|
||||
" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
|
||||
" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
|
||||
" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
|
||||
" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
|
||||
" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
|
||||
" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
|
||||
" .set mips0 \n" \
|
||||
" .set reorder \n" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
|
||||
static inline void flush_icache_line_indexed(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(INDEX_INVALIDATE_I, addr);
|
||||
}
|
||||
|
||||
static inline void flush_dcache_line_indexed(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(INDEX_WRITEBACK_INV_D, addr);
|
||||
}
|
||||
|
||||
static inline void flush_icache_line(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(HIT_INVALIDATE_I, addr);
|
||||
}
|
||||
|
||||
static inline void lock_icache_line(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(FETCH_AND_LOCK_I, addr);
|
||||
}
|
||||
|
||||
static inline void lock_dcache_line(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(FETCH_AND_LOCK_D, addr);
|
||||
}
|
||||
|
||||
static inline void flush_dcache_line(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||
}
|
||||
|
||||
static inline void invalidate_dcache_line(rt_ubase_t addr)
|
||||
{
|
||||
cache_op(HIT_INVALIDATE_D, addr);
|
||||
}
|
||||
static inline void blast_dcache16(void)
|
||||
{
|
||||
rt_ubase_t start = KSEG0BASE;
|
||||
rt_ubase_t end = start + g_mips_core.dcache_size;
|
||||
rt_ubase_t addr;
|
||||
|
||||
for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
|
||||
cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
|
||||
}
|
||||
|
||||
static inline void inv_dcache16(void)
|
||||
{
|
||||
rt_ubase_t start = KSEG0BASE;
|
||||
rt_ubase_t end = start + g_mips_core.dcache_size;
|
||||
rt_ubase_t addr;
|
||||
|
||||
for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
|
||||
cache16_unroll32(addr, HIT_INVALIDATE_D);
|
||||
}
|
||||
|
||||
static inline void blast_icache16(void)
|
||||
{
|
||||
rt_ubase_t start = KSEG0BASE;
|
||||
rt_ubase_t end = start + g_mips_core.icache_size;
|
||||
rt_ubase_t addr;
|
||||
|
||||
for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
|
||||
cache16_unroll32(addr, INDEX_INVALIDATE_I);
|
||||
}
|
||||
|
||||
void r4k_cache_init(void);
|
||||
void r4k_cache_flush_all(void);
|
||||
void r4k_icache_flush_all(void);
|
||||
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
|
||||
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
|
||||
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
|
||||
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
|
||||
void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction);
|
||||
#endif
|
||||
|
||||
#endif /* _MIPS_CACHE_H_ */
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* File : mips_cfg.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ10ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_CFG_H_
|
||||
#define _MIPS_CFG_H_
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
typedef struct mips32_core_cfg
|
||||
{
|
||||
uint16_t icache_line_size;
|
||||
// uint16_t icache_lines_per_way;
|
||||
// uint16_t icache_ways;
|
||||
uint16_t icache_size;
|
||||
uint16_t dcache_line_size;
|
||||
// uint16_t dcache_lines_per_way;
|
||||
// uint16_t dcache_ways;
|
||||
uint16_t dcache_size;
|
||||
|
||||
uint16_t max_tlb_entries; /* number of tlb entry */
|
||||
} mips32_core_cfg_t;
|
||||
|
||||
extern mips32_core_cfg_t g_mips_core;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _MIPS_CFG_H_ */
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
* File : mips_context_asm.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ7ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_CONTEXT_ASM_H_
|
||||
#define _MIPS_CONTEXT_ASM_H_
|
||||
|
||||
#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ )
|
||||
#ifdef __mips_hard_float
|
||||
#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */
|
||||
#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ )
|
||||
#else
|
||||
#define FPU_ADJ 0
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#ifdef __mips_hard_float
|
||||
.global _fpctx_save
|
||||
.global _fpctx_load
|
||||
#endif
|
||||
|
||||
.macro SAVE_CONTEXT
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
//save SP
|
||||
move k1, sp
|
||||
move k0, sp
|
||||
subu sp, k1, CONTEXT_SIZE
|
||||
sw k0, (29 * 4)(sp)
|
||||
|
||||
//save REG
|
||||
sw $0, ( 0 * 4)(sp)
|
||||
sw $1, ( 1 * 4)(sp)
|
||||
sw $2, ( 2 * 4)(sp)
|
||||
sw $3, ( 3 * 4)(sp)
|
||||
sw $4, ( 4 * 4)(sp)
|
||||
sw $5, ( 5 * 4)(sp)
|
||||
sw $6, ( 6 * 4)(sp)
|
||||
sw $7, ( 7 * 4)(sp)
|
||||
sw $8, ( 8 * 4)(sp)
|
||||
sw $9, ( 9 * 4)(sp)
|
||||
sw $10, (10 * 4)(sp)
|
||||
sw $11, (11 * 4)(sp)
|
||||
sw $12, (12 * 4)(sp)
|
||||
sw $13, (13 * 4)(sp)
|
||||
sw $14, (14 * 4)(sp)
|
||||
sw $15, (15 * 4)(sp)
|
||||
sw $16, (16 * 4)(sp)
|
||||
sw $17, (17 * 4)(sp)
|
||||
sw $18, (18 * 4)(sp)
|
||||
sw $19, (19 * 4)(sp)
|
||||
sw $20, (20 * 4)(sp)
|
||||
sw $21, (21 * 4)(sp)
|
||||
sw $22, (22 * 4)(sp)
|
||||
sw $23, (23 * 4)(sp)
|
||||
sw $24, (24 * 4)(sp)
|
||||
sw $25, (25 * 4)(sp)
|
||||
/* K0 K1 */
|
||||
sw $28, (28 * 4)(sp)
|
||||
/* SP */
|
||||
sw $30, (30 * 4)(sp)
|
||||
sw $31, (31 * 4)(sp)
|
||||
|
||||
/* STATUS CAUSE EPC.... */
|
||||
mfc0 $2, CP0_STATUS
|
||||
sw $2, STK_OFFSET_SR(sp)
|
||||
|
||||
mfc0 $2, CP0_CAUSE
|
||||
sw $2, STK_OFFSET_CAUSE(sp)
|
||||
|
||||
mfc0 $2, CP0_BADVADDR
|
||||
sw $2, STK_OFFSET_BADVADDR(sp)
|
||||
|
||||
MFC0 $2, CP0_EPC
|
||||
sw $2, STK_OFFSET_EPC(sp)
|
||||
|
||||
mfhi $2
|
||||
sw $2, STK_OFFSET_HI(sp)
|
||||
|
||||
mflo $2
|
||||
sw $2, STK_OFFSET_LO(sp)
|
||||
#ifdef __mips_hard_float
|
||||
add a0, sp,STK_CTX_SIZE
|
||||
|
||||
mfc0 t0, CP0_STATUS
|
||||
.set push
|
||||
.set at
|
||||
or t0, M_StatusCU1
|
||||
.set push
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
cfc1 t0, CP1_STATUS
|
||||
sw t0 , 0x00(a0)
|
||||
swc1 $f0,(0x04 * 1)(a0)
|
||||
swc1 $f1,(0x04 * 2)(a0)
|
||||
swc1 $f2,(0x04 * 3)(a0)
|
||||
swc1 $f3,(0x04 * 4)(a0)
|
||||
swc1 $f4,(0x04 * 5)(a0)
|
||||
swc1 $f5,(0x04 * 6)(a0)
|
||||
swc1 $f6,(0x04 * 7)(a0)
|
||||
swc1 $f7,(0x04 * 8)(a0)
|
||||
swc1 $f8,(0x04 * 9)(a0)
|
||||
swc1 $f9,(0x04 * 10)(a0)
|
||||
swc1 $f10,(0x04 * 11)(a0)
|
||||
swc1 $f11,(0x04 * 12)(a0)
|
||||
swc1 $f12,(0x04 * 13)(a0)
|
||||
swc1 $f13,(0x04 * 14)(a0)
|
||||
swc1 $f14,(0x04 * 15)(a0)
|
||||
swc1 $f15,(0x04 * 16)(a0)
|
||||
swc1 $f16,(0x04 * 17)(a0)
|
||||
swc1 $f17,(0x04 * 18)(a0)
|
||||
swc1 $f18,(0x04 * 19)(a0)
|
||||
swc1 $f19,(0x04 * 20)(a0)
|
||||
swc1 $f20,(0x04 * 21)(a0)
|
||||
swc1 $f21,(0x04 * 22)(a0)
|
||||
swc1 $f22,(0x04 * 23)(a0)
|
||||
swc1 $f23,(0x04 * 24)(a0)
|
||||
swc1 $f24,(0x04 * 25)(a0)
|
||||
swc1 $f25,(0x04 * 26)(a0)
|
||||
swc1 $f26,(0x04 * 27)(a0)
|
||||
swc1 $f27,(0x04 * 28)(a0)
|
||||
swc1 $f28,(0x04 * 29)(a0)
|
||||
swc1 $f29,(0x04 * 30)(a0)
|
||||
swc1 $f30,(0x04 * 31)(a0)
|
||||
swc1 $f31,(0x04 * 32)(a0)
|
||||
|
||||
nop
|
||||
#endif
|
||||
|
||||
//restore a0
|
||||
lw a0, (REG_A0 * 4)(sp)
|
||||
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
|
||||
.macro RESTORE_CONTEXT
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
#ifdef __mips_hard_float
|
||||
add a0, sp,STK_CTX_SIZE
|
||||
|
||||
mfc0 t0, CP0_STATUS
|
||||
.set push
|
||||
.set at
|
||||
or t0, M_StatusCU1
|
||||
.set noat
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
lw t0 , 0x00(a0)
|
||||
lwc1 $f0,(0x04 * 1)(a0)
|
||||
lwc1 $f1,(0x04 * 2)(a0)
|
||||
lwc1 $f2,(0x04 * 3)(a0)
|
||||
lwc1 $f3,(0x04 * 4)(a0)
|
||||
lwc1 $f4,(0x04 * 5)(a0)
|
||||
lwc1 $f5,(0x04 * 6)(a0)
|
||||
lwc1 $f6,(0x04 * 7)(a0)
|
||||
lwc1 $f7,(0x04 * 8)(a0)
|
||||
lwc1 $f8,(0x04 * 9)(a0)
|
||||
lwc1 $f9,(0x04 * 10)(a0)
|
||||
lwc1 $f10,(0x04 * 11)(a0)
|
||||
lwc1 $f11,(0x04 * 12)(a0)
|
||||
lwc1 $f12,(0x04 * 13)(a0)
|
||||
lwc1 $f13,(0x04 * 14)(a0)
|
||||
lwc1 $f14,(0x04 * 15)(a0)
|
||||
lwc1 $f15,(0x04 * 16)(a0)
|
||||
lwc1 $f16,(0x04 * 17)(a0)
|
||||
lwc1 $f17,(0x04 * 18)(a0)
|
||||
lwc1 $f18,(0x04 * 19)(a0)
|
||||
lwc1 $f19,(0x04 * 20)(a0)
|
||||
lwc1 $f20,(0x04 * 21)(a0)
|
||||
lwc1 $f21,(0x04 * 22)(a0)
|
||||
lwc1 $f22,(0x04 * 23)(a0)
|
||||
lwc1 $f23,(0x04 * 24)(a0)
|
||||
lwc1 $f24,(0x04 * 25)(a0)
|
||||
lwc1 $f25,(0x04 * 26)(a0)
|
||||
lwc1 $f26,(0x04 * 27)(a0)
|
||||
lwc1 $f27,(0x04 * 28)(a0)
|
||||
lwc1 $f28,(0x04 * 29)(a0)
|
||||
lwc1 $f29,(0x04 * 30)(a0)
|
||||
lwc1 $f30,(0x04 * 31)(a0)
|
||||
lwc1 $f31,(0x04 * 32)(a0)
|
||||
ctc1 t0, CP1_STATUS ;/* restore fpp status reg */
|
||||
|
||||
nop
|
||||
#endif
|
||||
|
||||
/* ͨÓüĴæÆ÷ */
|
||||
/* ZERO */
|
||||
lw $1, ( 1 * 4)(sp)
|
||||
/* V0 */
|
||||
lw $3, ( 3 * 4)(sp)
|
||||
lw $4, ( 4 * 4)(sp)
|
||||
lw $5, ( 5 * 4)(sp)
|
||||
lw $6, ( 6 * 4)(sp)
|
||||
lw $7, ( 7 * 4)(sp)
|
||||
lw $8, ( 8 * 4)(sp)
|
||||
lw $9, ( 9 * 4)(sp)
|
||||
lw $10, (10 * 4)(sp)
|
||||
lw $11, (11 * 4)(sp)
|
||||
lw $12, (12 * 4)(sp)
|
||||
lw $13, (13 * 4)(sp)
|
||||
lw $14, (14 * 4)(sp)
|
||||
lw $15, (15 * 4)(sp)
|
||||
lw $16, (16 * 4)(sp)
|
||||
lw $17, (17 * 4)(sp)
|
||||
lw $18, (18 * 4)(sp)
|
||||
lw $19, (19 * 4)(sp)
|
||||
lw $20, (20 * 4)(sp)
|
||||
lw $21, (21 * 4)(sp)
|
||||
lw $22, (22 * 4)(sp)
|
||||
lw $23, (23 * 4)(sp)
|
||||
lw $24, (24 * 4)(sp)
|
||||
lw $25, (25 * 4)(sp)
|
||||
lw $26, (26 * 4)(sp)
|
||||
lw $27, (27 * 4)(sp)
|
||||
lw $28, (28 * 4)(sp)
|
||||
/* SP */
|
||||
lw $30, (30 * 4)(sp)
|
||||
lw $31, (31 * 4)(sp)
|
||||
|
||||
|
||||
/* STATUS CAUSE EPC.... */
|
||||
lw $2, STK_OFFSET_HI(sp)
|
||||
mthi $2
|
||||
lw $2, STK_OFFSET_LO(sp)
|
||||
mtlo $2
|
||||
|
||||
lw $2, STK_OFFSET_SR(sp)
|
||||
mtc0 $2, CP0_STATUS
|
||||
|
||||
lw $2, STK_OFFSET_BADVADDR(sp)
|
||||
mtc0 $2, CP0_BADVADDR
|
||||
|
||||
lw $2, STK_OFFSET_CAUSE(sp)
|
||||
mtc0 $2, CP0_CAUSE
|
||||
|
||||
lw $2, STK_OFFSET_EPC(sp)
|
||||
MTC0 $2, CP0_EPC
|
||||
|
||||
//restore $2
|
||||
lw $2, ( 2 * 4)(sp)
|
||||
//restore sp
|
||||
lw $29, (29 * 4)(sp)
|
||||
|
||||
eret
|
||||
nop
|
||||
.set pop
|
||||
.endm
|
||||
#endif
|
||||
#endif /* _MIPS_CONTEXT_ASM_H_ */
|
File diff suppressed because it is too large
Load Diff
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* File : stack.h
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
* File : mips_excpt.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -18,11 +19,21 @@
|
|||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
* 2016Äê9ÔÂ7ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef __STACK_H__
|
||||
#define __STACK_H__
|
||||
#ifndef _MIPS_EXCPT_H_
|
||||
#define _MIPS_EXCPT_H_
|
||||
|
||||
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
|
||||
#include "mips_regs.h"
|
||||
|
||||
#endif
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef void (* exception_func_t)(mips_reg_ctx *regs);
|
||||
|
||||
//extern exception_func_t mips_exception_handlers[];
|
||||
|
||||
int rt_hw_exception_init(void);
|
||||
exception_func_t rt_set_except_vector(int n, exception_func_t func);
|
||||
void install_default_execpt_handle(void);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _MIPS_EXCPT_H_ */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* File : mips_types.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ7ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_TYPES_H_
|
||||
#define _MIPS_TYPES_H_
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef unsigned short umode_t;
|
||||
|
||||
/*
|
||||
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
|
||||
* header files exported to user space
|
||||
*/
|
||||
|
||||
typedef __signed__ char __s8;
|
||||
typedef unsigned char __u8;
|
||||
|
||||
typedef __signed__ short __s16;
|
||||
typedef unsigned short __u16;
|
||||
|
||||
typedef __signed__ int __s32;
|
||||
typedef unsigned int __u32;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef __signed__ long __s64;
|
||||
typedef unsigned long __u64;
|
||||
|
||||
#else
|
||||
|
||||
#if defined(__GNUC__)
|
||||
__extension__ typedef __signed__ long long __s64;
|
||||
__extension__ typedef unsigned long long __u64;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes
|
||||
*/
|
||||
|
||||
#define BITS_PER_LONG _MIPS_SZLONG
|
||||
|
||||
|
||||
typedef __signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef __signed short s16;
|
||||
typedef unsigned short u16;
|
||||
|
||||
typedef __signed int s32;
|
||||
typedef unsigned int u32;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef __signed__ long s64;
|
||||
typedef unsigned long u64;
|
||||
|
||||
#else
|
||||
|
||||
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
|
||||
typedef __signed__ long long s64;
|
||||
typedef unsigned long long u64;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
|
||||
|| defined(CONFIG_64BIT)
|
||||
typedef u64 dma_addr_t;
|
||||
|
||||
typedef u64 phys_addr_t;
|
||||
typedef u64 phys_size_t;
|
||||
|
||||
#else
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
typedef u32 phys_addr_t;
|
||||
typedef u32 phys_size_t;
|
||||
|
||||
#endif
|
||||
typedef u64 dma64_addr_t;
|
||||
|
||||
/*
|
||||
* Don't use phys_t. You've been warned.
|
||||
*/
|
||||
#ifdef CONFIG_64BIT_PHYS_ADDR
|
||||
typedef unsigned long long phys_t;
|
||||
#else
|
||||
typedef unsigned long phys_t;
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
#endif /* _MIPS_TYPES_H_ */
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* File : mipscfg.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2010, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-27 swkyer first version
|
||||
*/
|
||||
#ifndef __MIPSCFG_H__
|
||||
#define __MIPSCFG_H__
|
||||
|
||||
|
||||
typedef struct mips32_core_cfg
|
||||
{
|
||||
rt_uint16_t icache_line_size;
|
||||
rt_uint16_t icache_lines_per_way;
|
||||
rt_uint16_t icache_ways;
|
||||
rt_uint16_t dcache_line_size;
|
||||
rt_uint16_t dcache_lines_per_way;
|
||||
rt_uint16_t dcache_ways;
|
||||
|
||||
rt_uint16_t max_tlb_entries; /* number of tlb entry */
|
||||
} mips32_core_cfg_t;
|
||||
|
||||
extern mips32_core_cfg_t g_mips_core;
|
||||
|
||||
#endif /* end of __MIPSCFG_H__ */
|
|
@ -0,0 +1,706 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
|
||||
* Copyright (C) 2000 Silicon Graphics, Inc.
|
||||
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
|
||||
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2000, 07 MIPS Technologies, Inc.
|
||||
* Copyright (C) 2003, 2004 Maciej W. Rozycki
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
#ifndef __MIPSREGS_H__
|
||||
#define __MIPSREGS_H__
|
||||
|
||||
/*
|
||||
* The following macros are especially useful for __asm__
|
||||
* inline assembler.
|
||||
*/
|
||||
#ifndef __STR
|
||||
#define __STR(x) #x
|
||||
#endif
|
||||
#ifndef STR
|
||||
#define STR(x) __STR(x)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Configure language
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ULCAST_
|
||||
#else
|
||||
#define _ULCAST_ (unsigned long)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Coprocessor 0 register names
|
||||
*/
|
||||
#define CP0_INDEX $0
|
||||
#define CP0_RANDOM $1
|
||||
#define CP0_ENTRYLO0 $2
|
||||
#define CP0_ENTRYLO1 $3
|
||||
#define CP0_CONF $3
|
||||
#define CP0_CONTEXT $4
|
||||
#define CP0_PAGEMASK $5
|
||||
#define CP0_WIRED $6
|
||||
#define CP0_INFO $7
|
||||
#define CP0_BADVADDR $8
|
||||
#define CP0_COUNT $9
|
||||
#define CP0_ENTRYHI $10
|
||||
#define CP0_COMPARE $11
|
||||
#define CP0_STATUS $12
|
||||
#define CP0_CAUSE $13
|
||||
#define CP0_EPC $14
|
||||
#define CP0_PRID $15
|
||||
#define CP0_CONFIG $16
|
||||
#define CP0_LLADDR $17
|
||||
#define CP0_WATCHLO $18
|
||||
#define CP0_WATCHHI $19
|
||||
#define CP0_XCONTEXT $20
|
||||
#define CP0_FRAMEMASK $21
|
||||
#define CP0_DIAGNOSTIC $22
|
||||
#define CP0_DEBUG $23
|
||||
#define CP0_DEPC $24
|
||||
#define CP0_PERFORMANCE $25
|
||||
#define CP0_ECC $26
|
||||
#define CP0_CACHEERR $27
|
||||
#define CP0_TAGLO $28
|
||||
#define CP0_TAGHI $29
|
||||
#define CP0_ERROREPC $30
|
||||
#define CP0_DESAVE $31
|
||||
|
||||
/*
|
||||
* R4640/R4650 cp0 register names. These registers are listed
|
||||
* here only for completeness; without MMU these CPUs are not useable
|
||||
* by Linux. A future ELKS port might take make Linux run on them
|
||||
* though ...
|
||||
*/
|
||||
#define CP0_IBASE $0
|
||||
#define CP0_IBOUND $1
|
||||
#define CP0_DBASE $2
|
||||
#define CP0_DBOUND $3
|
||||
#define CP0_CALG $17
|
||||
#define CP0_IWATCH $18
|
||||
#define CP0_DWATCH $19
|
||||
|
||||
/*
|
||||
* Coprocessor 0 Set 1 register names
|
||||
*/
|
||||
#define CP0_S1_DERRADDR0 $26
|
||||
#define CP0_S1_DERRADDR1 $27
|
||||
#define CP0_S1_INTCONTROL $20
|
||||
|
||||
/*
|
||||
* Coprocessor 0 Set 2 register names
|
||||
*/
|
||||
#define CP0_S2_SRSCTL $12 /* MIPSR2 */
|
||||
|
||||
/*
|
||||
* Coprocessor 0 Set 3 register names
|
||||
*/
|
||||
#define CP0_S3_SRSMAP $12 /* MIPSR2 */
|
||||
|
||||
/*
|
||||
* TX39 Series
|
||||
*/
|
||||
#define CP0_TX39_CACHE $7
|
||||
|
||||
/*
|
||||
* Coprocessor 1 (FPU) register names
|
||||
*/
|
||||
#define CP1_REVISION $0
|
||||
#define CP1_STATUS $31
|
||||
|
||||
/*
|
||||
* FPU Status Register Values
|
||||
*/
|
||||
/*
|
||||
* Status Register Values
|
||||
*/
|
||||
|
||||
#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
|
||||
#define FPU_CSR_COND 0x00800000 /* $fcc0 */
|
||||
#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
|
||||
#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
|
||||
#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
|
||||
#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
|
||||
#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
|
||||
#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
|
||||
#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
|
||||
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
|
||||
|
||||
|
||||
/* FS/FO/FN */
|
||||
#define FPU_CSR_FS 0x01000000
|
||||
#define FPU_CSR_FO 0x00400000
|
||||
#define FPU_CSR_FN 0x00200000
|
||||
|
||||
/*
|
||||
* Bits 18 - 20 of the FPU Status Register will be read as 0,
|
||||
* and should be written as zero.
|
||||
*/
|
||||
#define FPU_CSR_RSVD 0x001c0000
|
||||
|
||||
/*
|
||||
* X the exception cause indicator
|
||||
* E the exception enable
|
||||
* S the sticky/flag bit
|
||||
*/
|
||||
#define FPU_CSR_ALL_X 0x0003f000
|
||||
#define FPU_CSR_UNI_X 0x00020000
|
||||
#define FPU_CSR_INV_X 0x00010000
|
||||
#define FPU_CSR_DIV_X 0x00008000
|
||||
#define FPU_CSR_OVF_X 0x00004000
|
||||
#define FPU_CSR_UDF_X 0x00002000
|
||||
#define FPU_CSR_INE_X 0x00001000
|
||||
|
||||
#define FPU_CSR_ALL_E 0x00000f80
|
||||
#define FPU_CSR_INV_E 0x00000800
|
||||
#define FPU_CSR_DIV_E 0x00000400
|
||||
#define FPU_CSR_OVF_E 0x00000200
|
||||
#define FPU_CSR_UDF_E 0x00000100
|
||||
#define FPU_CSR_INE_E 0x00000080
|
||||
|
||||
#define FPU_CSR_ALL_S 0x0000007c
|
||||
#define FPU_CSR_INV_S 0x00000040
|
||||
#define FPU_CSR_DIV_S 0x00000020
|
||||
#define FPU_CSR_OVF_S 0x00000010
|
||||
#define FPU_CSR_UDF_S 0x00000008
|
||||
#define FPU_CSR_INE_S 0x00000004
|
||||
|
||||
/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
|
||||
#define FPU_CSR_RM 0x00000003
|
||||
#define FPU_CSR_RN 0x0 /* nearest */
|
||||
#define FPU_CSR_RZ 0x1 /* towards zero */
|
||||
#define FPU_CSR_RU 0x2 /* towards +Infinity */
|
||||
#define FPU_CSR_RD 0x3 /* towards -Infinity */
|
||||
|
||||
|
||||
/*
|
||||
* R4x00 interrupt enable / cause bits
|
||||
*/
|
||||
#define IE_SW0 (_ULCAST_(1) << 8)
|
||||
#define IE_SW1 (_ULCAST_(1) << 9)
|
||||
#define IE_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define IE_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define IE_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define IE_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define IE_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define IE_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
/*
|
||||
* R4x00 interrupt cause bits
|
||||
*/
|
||||
#define C_SW0 (_ULCAST_(1) << 8)
|
||||
#define C_SW1 (_ULCAST_(1) << 9)
|
||||
#define C_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define C_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define C_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define C_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define C_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define C_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
/*
|
||||
* Bitfields in the R4xx0 cp0 status register
|
||||
*/
|
||||
#define ST0_IE 0x00000001
|
||||
#define ST0_EXL 0x00000002
|
||||
#define ST0_ERL 0x00000004
|
||||
#define ST0_KSU 0x00000018
|
||||
# define KSU_USER 0x00000010
|
||||
# define KSU_SUPERVISOR 0x00000008
|
||||
# define KSU_KERNEL 0x00000000
|
||||
#define ST0_UX 0x00000020
|
||||
#define ST0_SX 0x00000040
|
||||
#define ST0_KX 0x00000080
|
||||
#define ST0_DE 0x00010000
|
||||
#define ST0_CE 0x00020000
|
||||
|
||||
/*
|
||||
* Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
|
||||
* cacheops in userspace. This bit exists only on RM7000 and RM9000
|
||||
* processors.
|
||||
*/
|
||||
#define ST0_CO 0x08000000
|
||||
|
||||
/*
|
||||
* Bitfields in the R[23]000 cp0 status register.
|
||||
*/
|
||||
#define ST0_IEC 0x00000001
|
||||
#define ST0_KUC 0x00000002
|
||||
#define ST0_IEP 0x00000004
|
||||
#define ST0_KUP 0x00000008
|
||||
#define ST0_IEO 0x00000010
|
||||
#define ST0_KUO 0x00000020
|
||||
/* bits 6 & 7 are reserved on R[23]000 */
|
||||
#define ST0_ISC 0x00010000
|
||||
#define ST0_SWC 0x00020000
|
||||
#define ST0_CM 0x00080000
|
||||
|
||||
/*
|
||||
* Bits specific to the R4640/R4650
|
||||
*/
|
||||
#define ST0_UM (_ULCAST_(1) << 4)
|
||||
#define ST0_IL (_ULCAST_(1) << 23)
|
||||
#define ST0_DL (_ULCAST_(1) << 24)
|
||||
|
||||
/*
|
||||
* Enable the MIPS DSP ASE
|
||||
*/
|
||||
#define ST0_MX 0x01000000
|
||||
|
||||
/*
|
||||
* Bitfields in the TX39 family CP0 Configuration Register 3
|
||||
*/
|
||||
#define TX39_CONF_ICS_SHIFT 19
|
||||
#define TX39_CONF_ICS_MASK 0x00380000
|
||||
#define TX39_CONF_ICS_1KB 0x00000000
|
||||
#define TX39_CONF_ICS_2KB 0x00080000
|
||||
#define TX39_CONF_ICS_4KB 0x00100000
|
||||
#define TX39_CONF_ICS_8KB 0x00180000
|
||||
#define TX39_CONF_ICS_16KB 0x00200000
|
||||
|
||||
#define TX39_CONF_DCS_SHIFT 16
|
||||
#define TX39_CONF_DCS_MASK 0x00070000
|
||||
#define TX39_CONF_DCS_1KB 0x00000000
|
||||
#define TX39_CONF_DCS_2KB 0x00010000
|
||||
#define TX39_CONF_DCS_4KB 0x00020000
|
||||
#define TX39_CONF_DCS_8KB 0x00030000
|
||||
#define TX39_CONF_DCS_16KB 0x00040000
|
||||
|
||||
#define TX39_CONF_CWFON 0x00004000
|
||||
#define TX39_CONF_WBON 0x00002000
|
||||
#define TX39_CONF_RF_SHIFT 10
|
||||
#define TX39_CONF_RF_MASK 0x00000c00
|
||||
#define TX39_CONF_DOZE 0x00000200
|
||||
#define TX39_CONF_HALT 0x00000100
|
||||
#define TX39_CONF_LOCK 0x00000080
|
||||
#define TX39_CONF_ICE 0x00000020
|
||||
#define TX39_CONF_DCE 0x00000010
|
||||
#define TX39_CONF_IRSIZE_SHIFT 2
|
||||
#define TX39_CONF_IRSIZE_MASK 0x0000000c
|
||||
#define TX39_CONF_DRSIZE_SHIFT 0
|
||||
#define TX39_CONF_DRSIZE_MASK 0x00000003
|
||||
|
||||
/*
|
||||
* Status register bits available in all MIPS CPUs.
|
||||
*/
|
||||
#define ST0_IM 0x0000ff00
|
||||
#define STATUSB_IP0 8
|
||||
#define STATUSF_IP0 (_ULCAST_(1) << 8)
|
||||
#define STATUSB_IP1 9
|
||||
#define STATUSF_IP1 (_ULCAST_(1) << 9)
|
||||
#define STATUSB_IP2 10
|
||||
#define STATUSF_IP2 (_ULCAST_(1) << 10)
|
||||
#define STATUSB_IP3 11
|
||||
#define STATUSF_IP3 (_ULCAST_(1) << 11)
|
||||
#define STATUSB_IP4 12
|
||||
#define STATUSF_IP4 (_ULCAST_(1) << 12)
|
||||
#define STATUSB_IP5 13
|
||||
#define STATUSF_IP5 (_ULCAST_(1) << 13)
|
||||
#define STATUSB_IP6 14
|
||||
#define STATUSF_IP6 (_ULCAST_(1) << 14)
|
||||
#define STATUSB_IP7 15
|
||||
#define STATUSF_IP7 (_ULCAST_(1) << 15)
|
||||
#define STATUSB_IP8 0
|
||||
#define STATUSF_IP8 (_ULCAST_(1) << 0)
|
||||
#define STATUSB_IP9 1
|
||||
#define STATUSF_IP9 (_ULCAST_(1) << 1)
|
||||
#define STATUSB_IP10 2
|
||||
#define STATUSF_IP10 (_ULCAST_(1) << 2)
|
||||
#define STATUSB_IP11 3
|
||||
#define STATUSF_IP11 (_ULCAST_(1) << 3)
|
||||
#define STATUSB_IP12 4
|
||||
#define STATUSF_IP12 (_ULCAST_(1) << 4)
|
||||
#define STATUSB_IP13 5
|
||||
#define STATUSF_IP13 (_ULCAST_(1) << 5)
|
||||
#define STATUSB_IP14 6
|
||||
#define STATUSF_IP14 (_ULCAST_(1) << 6)
|
||||
#define STATUSB_IP15 7
|
||||
#define STATUSF_IP15 (_ULCAST_(1) << 7)
|
||||
#define ST0_CH 0x00040000
|
||||
#define ST0_SR 0x00100000
|
||||
#define ST0_TS 0x00200000
|
||||
#define ST0_BEV 0x00400000
|
||||
#define ST0_RE 0x02000000
|
||||
#define ST0_FR 0x04000000
|
||||
#define ST0_CU 0xf0000000
|
||||
#define ST0_CU0 0x10000000
|
||||
#define ST0_CU1 0x20000000
|
||||
#define ST0_CU2 0x40000000
|
||||
#define ST0_CU3 0x80000000
|
||||
#define ST0_XX 0x80000000 /* MIPS IV naming */
|
||||
|
||||
/*
|
||||
* Bitfields and bit numbers in the coprocessor 0 cause register.
|
||||
*
|
||||
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
|
||||
*/
|
||||
#define CAUSEB_EXCCODE 2
|
||||
#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
|
||||
#define CAUSEB_IP 8
|
||||
#define CAUSEF_IP (_ULCAST_(255) << 8)
|
||||
#define CAUSEB_IP0 8
|
||||
#define CAUSEF_IP0 (_ULCAST_(1) << 8)
|
||||
#define CAUSEB_IP1 9
|
||||
#define CAUSEF_IP1 (_ULCAST_(1) << 9)
|
||||
#define CAUSEB_IP2 10
|
||||
#define CAUSEF_IP2 (_ULCAST_(1) << 10)
|
||||
#define CAUSEB_IP3 11
|
||||
#define CAUSEF_IP3 (_ULCAST_(1) << 11)
|
||||
#define CAUSEB_IP4 12
|
||||
#define CAUSEF_IP4 (_ULCAST_(1) << 12)
|
||||
#define CAUSEB_IP5 13
|
||||
#define CAUSEF_IP5 (_ULCAST_(1) << 13)
|
||||
#define CAUSEB_IP6 14
|
||||
#define CAUSEF_IP6 (_ULCAST_(1) << 14)
|
||||
#define CAUSEB_IP7 15
|
||||
#define CAUSEF_IP7 (_ULCAST_(1) << 15)
|
||||
#define CAUSEB_IV 23
|
||||
#define CAUSEF_IV (_ULCAST_(1) << 23)
|
||||
#define CAUSEB_CE 28
|
||||
#define CAUSEF_CE (_ULCAST_(3) << 28)
|
||||
#define CAUSEB_BD 31
|
||||
#define CAUSEF_BD (_ULCAST_(1) << 31)
|
||||
|
||||
/*
|
||||
* Bits in the coprocessor 0 config register.
|
||||
*/
|
||||
/* Generic bits. */
|
||||
#define CONF_CM_CACHABLE_NO_WA 0
|
||||
#define CONF_CM_CACHABLE_WA 1
|
||||
#define CONF_CM_UNCACHED 2
|
||||
#define CONF_CM_CACHABLE_NONCOHERENT 3
|
||||
#define CONF_CM_CACHABLE_CE 4
|
||||
#define CONF_CM_CACHABLE_COW 5
|
||||
#define CONF_CM_CACHABLE_CUW 6
|
||||
#define CONF_CM_CACHABLE_ACCELERATED 7
|
||||
#define CONF_CM_CMASK 7
|
||||
#define CONF_BE (_ULCAST_(1) << 15)
|
||||
|
||||
/* Bits common to various processors. */
|
||||
#define CONF_CU (_ULCAST_(1) << 3)
|
||||
#define CONF_DB (_ULCAST_(1) << 4)
|
||||
#define CONF_IB (_ULCAST_(1) << 5)
|
||||
#define CONF_DC (_ULCAST_(7) << 6)
|
||||
#define CONF_IC (_ULCAST_(7) << 9)
|
||||
#define CONF_EB (_ULCAST_(1) << 13)
|
||||
#define CONF_EM (_ULCAST_(1) << 14)
|
||||
#define CONF_SM (_ULCAST_(1) << 16)
|
||||
#define CONF_SC (_ULCAST_(1) << 17)
|
||||
#define CONF_EW (_ULCAST_(3) << 18)
|
||||
#define CONF_EP (_ULCAST_(15)<< 24)
|
||||
#define CONF_EC (_ULCAST_(7) << 28)
|
||||
#define CONF_CM (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the R4xx0. */
|
||||
#define R4K_CONF_SW (_ULCAST_(1) << 20)
|
||||
#define R4K_CONF_SS (_ULCAST_(1) << 21)
|
||||
#define R4K_CONF_SB (_ULCAST_(3) << 22)
|
||||
|
||||
/* Bits specific to the R5000. */
|
||||
#define R5K_CONF_SE (_ULCAST_(1) << 12)
|
||||
#define R5K_CONF_SS (_ULCAST_(3) << 20)
|
||||
|
||||
/* Bits specific to the RM7000. */
|
||||
#define RM7K_CONF_SE (_ULCAST_(1) << 3)
|
||||
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
|
||||
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
|
||||
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
|
||||
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
|
||||
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the R10000. */
|
||||
#define R10K_CONF_DN (_ULCAST_(3) << 3)
|
||||
#define R10K_CONF_CT (_ULCAST_(1) << 5)
|
||||
#define R10K_CONF_PE (_ULCAST_(1) << 6)
|
||||
#define R10K_CONF_PM (_ULCAST_(3) << 7)
|
||||
#define R10K_CONF_EC (_ULCAST_(15)<< 9)
|
||||
#define R10K_CONF_SB (_ULCAST_(1) << 13)
|
||||
#define R10K_CONF_SK (_ULCAST_(1) << 14)
|
||||
#define R10K_CONF_SS (_ULCAST_(7) << 16)
|
||||
#define R10K_CONF_SC (_ULCAST_(7) << 19)
|
||||
#define R10K_CONF_DC (_ULCAST_(7) << 26)
|
||||
#define R10K_CONF_IC (_ULCAST_(7) << 29)
|
||||
|
||||
/* Bits specific to the VR41xx. */
|
||||
#define VR41_CONF_CS (_ULCAST_(1) << 12)
|
||||
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
|
||||
#define VR41_CONF_AD (_ULCAST_(1) << 23)
|
||||
|
||||
/* Bits specific to the R30xx. */
|
||||
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
|
||||
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
|
||||
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
|
||||
#define R30XX_CONF_RF (_ULCAST_(1) << 24)
|
||||
#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
|
||||
#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
|
||||
#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
|
||||
#define R30XX_CONF_SB (_ULCAST_(1) << 30)
|
||||
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the TX49. */
|
||||
#define TX49_CONF_DC (_ULCAST_(1) << 16)
|
||||
#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
|
||||
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
|
||||
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
|
||||
|
||||
/* Bits specific to the MIPS32/64 PRA. */
|
||||
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
|
||||
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
|
||||
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
|
||||
#define MIPS_CONF_M (_ULCAST_(1) << 31)
|
||||
|
||||
/*
|
||||
* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
|
||||
*/
|
||||
#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
|
||||
#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
|
||||
#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
|
||||
#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
|
||||
#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
|
||||
#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
|
||||
#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
|
||||
#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
|
||||
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
|
||||
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
|
||||
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
|
||||
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
|
||||
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
|
||||
#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
|
||||
|
||||
#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
|
||||
#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
|
||||
#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
|
||||
#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
|
||||
#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
|
||||
#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
|
||||
#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
|
||||
#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
|
||||
|
||||
#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
|
||||
#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
|
||||
#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
|
||||
#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
|
||||
#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
|
||||
#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
|
||||
#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
|
||||
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
|
||||
|
||||
/*
|
||||
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
|
||||
*/
|
||||
#define MIPS_FPIR_S (_ULCAST_(1) << 16)
|
||||
#define MIPS_FPIR_D (_ULCAST_(1) << 17)
|
||||
#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
|
||||
#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
|
||||
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
|
||||
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
|
||||
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
|
||||
|
||||
/*
|
||||
* R10000 performance counter definitions.
|
||||
*
|
||||
* FIXME: The R10000 performance counter opens a nice way to implement CPU
|
||||
* time accounting with a precission of one cycle. I don't have
|
||||
* R10000 silicon but just a manual, so ...
|
||||
*/
|
||||
|
||||
/*
|
||||
* Events counted by counter #0
|
||||
*/
|
||||
#define CE0_CYCLES 0
|
||||
#define CE0_INSN_ISSUED 1
|
||||
#define CE0_LPSC_ISSUED 2
|
||||
#define CE0_S_ISSUED 3
|
||||
#define CE0_SC_ISSUED 4
|
||||
#define CE0_SC_FAILED 5
|
||||
#define CE0_BRANCH_DECODED 6
|
||||
#define CE0_QW_WB_SECONDARY 7
|
||||
#define CE0_CORRECTED_ECC_ERRORS 8
|
||||
#define CE0_ICACHE_MISSES 9
|
||||
#define CE0_SCACHE_I_MISSES 10
|
||||
#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
|
||||
#define CE0_EXT_INTERVENTIONS_REQ 12
|
||||
#define CE0_EXT_INVALIDATE_REQ 13
|
||||
#define CE0_VIRTUAL_COHERENCY_COND 14
|
||||
#define CE0_INSN_GRADUATED 15
|
||||
|
||||
/*
|
||||
* Events counted by counter #1
|
||||
*/
|
||||
#define CE1_CYCLES 0
|
||||
#define CE1_INSN_GRADUATED 1
|
||||
#define CE1_LPSC_GRADUATED 2
|
||||
#define CE1_S_GRADUATED 3
|
||||
#define CE1_SC_GRADUATED 4
|
||||
#define CE1_FP_INSN_GRADUATED 5
|
||||
#define CE1_QW_WB_PRIMARY 6
|
||||
#define CE1_TLB_REFILL 7
|
||||
#define CE1_BRANCH_MISSPREDICTED 8
|
||||
#define CE1_DCACHE_MISS 9
|
||||
#define CE1_SCACHE_D_MISSES 10
|
||||
#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
|
||||
#define CE1_EXT_INTERVENTION_HITS 12
|
||||
#define CE1_EXT_INVALIDATE_REQ 13
|
||||
#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
|
||||
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
|
||||
|
||||
/*
|
||||
* These flags define in which privilege mode the counters count events
|
||||
*/
|
||||
#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
|
||||
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
|
||||
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
|
||||
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* Macros to access the system control coprocessor
|
||||
*/
|
||||
#define __read_32bit_c0_register(source, sel) \
|
||||
({ int __res; \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
"mfc0\t%0, " #source "\n\t" \
|
||||
: "=r" (__res)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips32\n\t" \
|
||||
"mfc0\t%0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0\n\t" \
|
||||
: "=r" (__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define __write_32bit_c0_register(register, sel, value) \
|
||||
do { \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
"mtc0\t%z0, " #register "\n\t" \
|
||||
: : "Jr" ((unsigned int)(value))); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips32\n\t" \
|
||||
"mtc0\t%z0, " #register ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" ((unsigned int)(value))); \
|
||||
} while (0)
|
||||
|
||||
#define read_c0_index() __read_32bit_c0_register($0, 0)
|
||||
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
|
||||
|
||||
#define read_c0_random() __read_32bit_c0_register($1, 0)
|
||||
#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
|
||||
|
||||
#define read_c0_entrylo0() __read_32bit_c0_register($2, 0)
|
||||
#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val)
|
||||
|
||||
#define read_c0_entrylo1() __read_32bit_c0_register($3, 0)
|
||||
#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val)
|
||||
|
||||
#define read_c0_conf() __read_32bit_c0_register($3, 0)
|
||||
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
|
||||
|
||||
#define read_c0_context() __read_32bit_c0_register($4, 0)
|
||||
#define write_c0_context(val) __write_32bit_c0_register($4, 0, val)
|
||||
|
||||
#define read_c0_userlocal() __read_32bit_c0_register($4, 2)
|
||||
#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val)
|
||||
|
||||
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
|
||||
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
|
||||
|
||||
#define read_c0_wired() __read_32bit_c0_register($6, 0)
|
||||
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
|
||||
|
||||
#define read_c0_info() __read_32bit_c0_register($7, 0)
|
||||
|
||||
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
|
||||
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
|
||||
|
||||
#define read_c0_badvaddr() __read_32bit_c0_register($8, 0)
|
||||
#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val)
|
||||
|
||||
#define read_c0_count() __read_32bit_c0_register($9, 0)
|
||||
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
|
||||
|
||||
#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
|
||||
#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
|
||||
|
||||
#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
|
||||
#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
|
||||
|
||||
#define read_c0_entryhi() __read_32bit_c0_register($10, 0)
|
||||
#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val)
|
||||
|
||||
#define read_c0_compare() __read_32bit_c0_register($11, 0)
|
||||
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
|
||||
|
||||
#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
|
||||
#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
|
||||
|
||||
#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
|
||||
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
|
||||
|
||||
#define read_c0_status() __read_32bit_c0_register($12, 0)
|
||||
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
|
||||
|
||||
#define read_c0_cause() __read_32bit_c0_register($13, 0)
|
||||
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
|
||||
|
||||
#define read_c0_epc() __read_32bit_c0_register($14, 0)
|
||||
#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val)
|
||||
|
||||
#define read_c0_prid() __read_32bit_c0_register($15, 0)
|
||||
|
||||
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
|
||||
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
|
||||
|
||||
#define read_c0_config() __read_32bit_c0_register($16, 0)
|
||||
#define read_c0_config1() __read_32bit_c0_register($16, 1)
|
||||
#define read_c0_config2() __read_32bit_c0_register($16, 2)
|
||||
#define read_c0_config3() __read_32bit_c0_register($16, 3)
|
||||
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
|
||||
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
|
||||
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
|
||||
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
|
||||
|
||||
|
||||
/*
|
||||
* Macros to access the floating point coprocessor control registers
|
||||
*/
|
||||
#define read_32bit_cp1_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
/* gas fails to assemble cfc1 for some archs (octeon).*/ \
|
||||
".set\tmips1\n\t" \
|
||||
"cfc1\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
#define write_32bit_cp1_register(register, value) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
"ctc1\t%z0, "STR(register)"\n\t" \
|
||||
: : "Jr" ((unsigned int)(value))); \
|
||||
} while (0)
|
||||
|
||||
#define read_c1_status() read_32bit_cp1_register(CP1_STATUS)
|
||||
#define read_c1_revision() read_32bit_cp1_register(CP1_REVISION);
|
||||
#define write_c1_status(val) write_32bit_cp1_register(CP1_STATUS, val)
|
||||
|
||||
|
||||
#endif /* end of __ASSEMBLY__ */
|
||||
|
||||
#endif /* end of __MIPSREGS_H__ */
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
|
||||
* Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
|
||||
* Copyright (C) 1999 Silicon Graphics, Inc.
|
||||
* Copyright (C) 2007 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef __STACKFRAME_H__
|
||||
#define __STACKFRAME_H__
|
||||
|
||||
#include "asm.h"
|
||||
#include "mipsregs.h"
|
||||
|
||||
/*
|
||||
* Stack layout for the INT exception handler
|
||||
* Derived from the stack layout described in asm-mips/stackframe.h
|
||||
*
|
||||
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
|
||||
*/
|
||||
|
||||
//#define PT_R0 (PTRSIZE*6) /* 0 */
|
||||
#define PT_R0 (0) /* 0 */
|
||||
#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
|
||||
#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
|
||||
#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
|
||||
#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
|
||||
#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
|
||||
#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
|
||||
#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
|
||||
#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
|
||||
#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
|
||||
#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
|
||||
#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
|
||||
#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
|
||||
#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
|
||||
#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
|
||||
#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
|
||||
#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
|
||||
#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
|
||||
#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
|
||||
#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
|
||||
#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
|
||||
#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
|
||||
#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
|
||||
#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
|
||||
#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
|
||||
#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
|
||||
#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
|
||||
#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
|
||||
#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
|
||||
#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
|
||||
#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
|
||||
#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
|
||||
|
||||
/*
|
||||
* Saved special registers
|
||||
*/
|
||||
#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
|
||||
#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */
|
||||
#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */
|
||||
#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
|
||||
#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
|
||||
#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
|
||||
|
||||
#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
|
||||
|
||||
|
||||
.macro SAVE_AT
|
||||
.set push
|
||||
.set noat
|
||||
LONG_S $1, PT_R1(sp)
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro SAVE_TEMP
|
||||
mfhi v1
|
||||
LONG_S $8, PT_R8(sp)
|
||||
LONG_S $9, PT_R9(sp)
|
||||
LONG_S v1, PT_HI(sp)
|
||||
mflo v1
|
||||
LONG_S $10, PT_R10(sp)
|
||||
LONG_S $11, PT_R11(sp)
|
||||
LONG_S v1, PT_LO(sp)
|
||||
LONG_S $12, PT_R12(sp)
|
||||
LONG_S $13, PT_R13(sp)
|
||||
LONG_S $14, PT_R14(sp)
|
||||
LONG_S $15, PT_R15(sp)
|
||||
LONG_S $24, PT_R24(sp)
|
||||
.endm
|
||||
|
||||
.macro SAVE_STATIC
|
||||
LONG_S $16, PT_R16(sp)
|
||||
LONG_S $17, PT_R17(sp)
|
||||
LONG_S $18, PT_R18(sp)
|
||||
LONG_S $19, PT_R19(sp)
|
||||
LONG_S $20, PT_R20(sp)
|
||||
LONG_S $21, PT_R21(sp)
|
||||
LONG_S $22, PT_R22(sp)
|
||||
LONG_S $23, PT_R23(sp)
|
||||
LONG_S $30, PT_R30(sp)
|
||||
.endm
|
||||
|
||||
.macro get_saved_sp
|
||||
nop
|
||||
.endm
|
||||
|
||||
.macro SAVE_SOME
|
||||
.set push
|
||||
.set noat
|
||||
.set reorder
|
||||
move k1, sp
|
||||
8: move k0, sp
|
||||
PTR_SUBU sp, k1, PT_SIZE
|
||||
LONG_S k0, PT_R29(sp)
|
||||
LONG_S $3, PT_R3(sp)
|
||||
LONG_S $0, PT_R0(sp)
|
||||
mfc0 v1, CP0_STATUS
|
||||
LONG_S $2, PT_R2(sp)
|
||||
LONG_S v1, PT_STATUS(sp)
|
||||
LONG_S $4, PT_R4(sp)
|
||||
mfc0 v1, CP0_CAUSE
|
||||
LONG_S $5, PT_R5(sp)
|
||||
LONG_S v1, PT_CAUSE(sp)
|
||||
LONG_S $6, PT_R6(sp)
|
||||
MFC0 v1, CP0_EPC
|
||||
LONG_S $7, PT_R7(sp)
|
||||
LONG_S v1, PT_EPC(sp)
|
||||
LONG_S $25, PT_R25(sp)
|
||||
LONG_S $28, PT_R28(sp)
|
||||
LONG_S $31, PT_R31(sp)
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro SAVE_ALL
|
||||
SAVE_SOME
|
||||
SAVE_AT
|
||||
SAVE_TEMP
|
||||
SAVE_STATIC
|
||||
.endm
|
||||
|
||||
.macro RESTORE_AT
|
||||
.set push
|
||||
.set noat
|
||||
LONG_L $1, PT_R1(sp)
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro RESTORE_TEMP
|
||||
LONG_L $24, PT_LO(sp)
|
||||
LONG_L $8, PT_R8(sp)
|
||||
LONG_L $9, PT_R9(sp)
|
||||
mtlo $24
|
||||
LONG_L $24, PT_HI(sp)
|
||||
LONG_L $10, PT_R10(sp)
|
||||
LONG_L $11, PT_R11(sp)
|
||||
mthi $24
|
||||
LONG_L $12, PT_R12(sp)
|
||||
LONG_L $13, PT_R13(sp)
|
||||
LONG_L $14, PT_R14(sp)
|
||||
LONG_L $15, PT_R15(sp)
|
||||
LONG_L $24, PT_R24(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_STATIC
|
||||
LONG_L $16, PT_R16(sp)
|
||||
LONG_L $17, PT_R17(sp)
|
||||
LONG_L $18, PT_R18(sp)
|
||||
LONG_L $19, PT_R19(sp)
|
||||
LONG_L $20, PT_R20(sp)
|
||||
LONG_L $21, PT_R21(sp)
|
||||
LONG_L $22, PT_R22(sp)
|
||||
LONG_L $23, PT_R23(sp)
|
||||
LONG_L $30, PT_R30(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_SOME
|
||||
.set push
|
||||
.set reorder
|
||||
.set noat
|
||||
LONG_L v0, PT_STATUS(sp)
|
||||
mtc0 v0, CP0_STATUS
|
||||
LONG_L v1, PT_EPC(sp)
|
||||
MTC0 v1, CP0_EPC
|
||||
LONG_L $31, PT_R31(sp)
|
||||
LONG_L $28, PT_R28(sp)
|
||||
LONG_L $25, PT_R25(sp)
|
||||
LONG_L $7, PT_R7(sp)
|
||||
LONG_L $6, PT_R6(sp)
|
||||
LONG_L $5, PT_R5(sp)
|
||||
LONG_L $4, PT_R4(sp)
|
||||
LONG_L $3, PT_R3(sp)
|
||||
LONG_L $2, PT_R2(sp)
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro RESTORE_SP_AND_RET
|
||||
LONG_L sp, PT_R29(sp)
|
||||
.set mips3
|
||||
eret
|
||||
.set mips0
|
||||
.endm
|
||||
|
||||
|
||||
.macro RESTORE_SP
|
||||
LONG_L sp, PT_R29(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_ALL
|
||||
RESTORE_TEMP
|
||||
RESTORE_STATIC
|
||||
RESTORE_AT
|
||||
RESTORE_SOME
|
||||
RESTORE_SP
|
||||
.endm
|
||||
|
||||
.macro RESTORE_ALL_AND_RET
|
||||
RESTORE_TEMP
|
||||
RESTORE_STATIC
|
||||
RESTORE_AT
|
||||
RESTORE_SOME
|
||||
RESTORE_SP_AND_RET
|
||||
.endm
|
||||
|
||||
#endif /* end of __STACKFRAME_H__ */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
|
||||
CPPPATH = [cwd]
|
||||
ASFLAGS = ''
|
||||
|
||||
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
|
||||
|
||||
Return('group')
|
|
@ -10,7 +10,7 @@ if os.getenv('RTT_CC'):
|
|||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'E:\work\env\tools\gnu_gcc\mips_gcc\mips-2016.05\bin'
|
||||
EXEC_PATH = r'/opt/mips-2016.05/bin/'
|
||||
else:
|
||||
print('Please make sure your toolchains is GNU GCC!')
|
||||
exit(0)
|
||||
|
|
|
@ -1,11 +0,0 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
|
@ -1,118 +0,0 @@
|
|||
/*
|
||||
* File : cache.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#include "../xburst/cache.h"
|
||||
|
||||
#include <board.h>
|
||||
|
||||
#define CACHE_SIZE 16*1024
|
||||
#define CACHE_LINE_SIZE 32
|
||||
#define KSEG0 0x80000000
|
||||
|
||||
#define K0_TO_K1() \
|
||||
do { \
|
||||
unsigned long __k0_addr; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
"la %0, 1f\n\t" \
|
||||
"or %0, %0, %1\n\t" \
|
||||
"jr %0\n\t" \
|
||||
"nop\n\t" \
|
||||
"1: nop\n" \
|
||||
: "=&r"(__k0_addr) \
|
||||
: "r" (0x20000000) ); \
|
||||
} while(0)
|
||||
|
||||
#define K1_TO_K0() \
|
||||
do { \
|
||||
unsigned long __k0_addr; \
|
||||
__asm__ __volatile__( \
|
||||
"nop;nop;nop;nop;nop;nop;nop\n\t" \
|
||||
"la %0, 1f\n\t" \
|
||||
"jr %0\n\t" \
|
||||
"nop\n\t" \
|
||||
"1: nop\n" \
|
||||
: "=&r" (__k0_addr)); \
|
||||
} while (0)
|
||||
|
||||
#define INVALIDATE_BTB() \
|
||||
do { \
|
||||
unsigned long tmp; \
|
||||
__asm__ __volatile__( \
|
||||
".set mips32\n\t" \
|
||||
"mfc0 %0, $16, 7\n\t" \
|
||||
"nop\n\t" \
|
||||
"ori %0, 2\n\t" \
|
||||
"mtc0 %0, $16, 7\n\t" \
|
||||
"nop\n\t" \
|
||||
".set mips2\n\t" \
|
||||
: "=&r" (tmp)); \
|
||||
} while (0)
|
||||
|
||||
#define SYNC_WB() __asm__ __volatile__ ("sync")
|
||||
|
||||
#define cache_op(op,addr) \
|
||||
__asm__ __volatile__( \
|
||||
" .set noreorder \n" \
|
||||
" .set mips32\n\t \n" \
|
||||
" cache %0, %1 \n" \
|
||||
" .set mips0 \n" \
|
||||
" .set reorder" \
|
||||
: \
|
||||
: "i" (op), "m" (*(unsigned char *)(addr)))
|
||||
|
||||
void __icache_invalidate_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
K0_TO_K1();
|
||||
|
||||
asm volatile (".set noreorder\n"
|
||||
".set mips32\n\t"
|
||||
"mtc0\t$0,$28\n\t"
|
||||
"mtc0\t$0,$29\n"
|
||||
".set mips0\n"
|
||||
".set reorder\n");
|
||||
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Store_Tag_I, i);
|
||||
|
||||
K1_TO_K0();
|
||||
|
||||
INVALIDATE_BTB();
|
||||
}
|
||||
|
||||
void __dcache_writeback_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Writeback_Inv_D, i);
|
||||
|
||||
SYNC_WB();
|
||||
}
|
||||
|
||||
void rt_hw_cache_init(void)
|
||||
{
|
||||
__dcache_writeback_all();
|
||||
__icache_invalidate_all();
|
||||
}
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* File : cache.h
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#ifndef __CACHE_H__
|
||||
#define __CACHE_H__
|
||||
|
||||
/*
|
||||
* Cache Operations
|
||||
*/
|
||||
#define Index_Invalidate_I 0x00
|
||||
#define Index_Writeback_Inv_D 0x01
|
||||
#define Index_Invalidate_SI 0x02
|
||||
#define Index_Writeback_Inv_SD 0x03
|
||||
#define Index_Load_Tag_I 0x04
|
||||
#define Index_Load_Tag_D 0x05
|
||||
#define Index_Load_Tag_SI 0x06
|
||||
#define Index_Load_Tag_SD 0x07
|
||||
#define Index_Store_Tag_I 0x08
|
||||
#define Index_Store_Tag_D 0x09
|
||||
#define Index_Store_Tag_SI 0x0A
|
||||
#define Index_Store_Tag_SD 0x0B
|
||||
#define Create_Dirty_Excl_D 0x0d
|
||||
#define Create_Dirty_Excl_SD 0x0f
|
||||
#define Hit_Invalidate_I 0x10
|
||||
#define Hit_Invalidate_D 0x11
|
||||
#define Hit_Invalidate_SI 0x12
|
||||
#define Hit_Invalidate_SD 0x13
|
||||
#define Fill 0x14
|
||||
#define Hit_Writeback_Inv_D 0x15
|
||||
/* 0x16 is unused */
|
||||
#define Hit_Writeback_Inv_SD 0x17
|
||||
#define Hit_Writeback_I 0x18
|
||||
#define Hit_Writeback_D 0x19
|
||||
/* 0x1a is unused */
|
||||
#define Hit_Writeback_SD 0x1b
|
||||
/* 0x1c is unused */
|
||||
/* 0x1e is unused */
|
||||
#define Hit_Set_Virtual_SI 0x1e
|
||||
#define Hit_Set_Virtual_SD 0x1f
|
||||
|
||||
void rt_hw_cache_init(void);
|
||||
|
||||
#endif
|
|
@ -1,51 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2019-07-19 Zhou Yanjie clean up code
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips_def.h"
|
||||
#include "../common/mipsregs.h"
|
||||
#include "../common/stackframe.h"
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
|
||||
.globl cache_init
|
||||
.ent cache_init
|
||||
cache_init:
|
||||
.set noreorder
|
||||
mtc0 zero, CP0_TAGLO
|
||||
move t0, a0 // cache total size
|
||||
move t1, a1 // cache line size
|
||||
li t2, 0x80000000
|
||||
addu t3, t0, t2
|
||||
|
||||
_cache_init_loop:
|
||||
cache 8, 0(t2) // icache_index_store_tag
|
||||
cache 9, 0(t2) // dcache_index_store_tag
|
||||
addu t2, t1
|
||||
bne t2, t3, _cache_init_loop
|
||||
nop
|
||||
|
||||
mfc0 t0, CP0_CONFIG
|
||||
li t1, 0x7
|
||||
not t1
|
||||
and t0, t0, t1
|
||||
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
|
||||
mtc0 t0, CP0_CONFIG
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.set reorder
|
||||
.end cache_init
|
|
@ -1,155 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-09-11 bernard port to JZ4755
|
||||
* 2019-07-19 Zhou Yanjie clean up code
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips_def.h"
|
||||
#include "../common/stackframe.h"
|
||||
#include "stack.h"
|
||||
|
||||
.section ".text", "ax"
|
||||
.set noreorder
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable()
|
||||
*/
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
mfc0 v0, CP0_STATUS
|
||||
and v1, v0, 0xfffffffe
|
||||
mtc0 v1, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level)
|
||||
*/
|
||||
.globl rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
mtc0 a0, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
|
||||
* a0 --> from
|
||||
* a1 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
mtc0 ra, CP0_EPC
|
||||
SAVE_ALL
|
||||
|
||||
sw sp, 0(a0) /* store sp in preempted tasks TCB */
|
||||
lw sp, 0(a1) /* get new task stack pointer */
|
||||
|
||||
RESTORE_ALL_AND_RET
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to)/*
|
||||
* a0 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
lw sp, 0(a0) /* get new task stack pointer */
|
||||
|
||||
RESTORE_ALL_AND_RET
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
|
||||
*/
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
la t0, rt_thread_switch_interrupt_flag
|
||||
lw t1, 0(t0)
|
||||
nop
|
||||
bnez t1, _reswitch
|
||||
nop
|
||||
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
|
||||
sw t1, 0(t0)
|
||||
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
|
||||
sw a0, 0(t0)
|
||||
_reswitch:
|
||||
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
|
||||
sw a1, 0(t0)
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl system_dump
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
||||
*/
|
||||
.globl rt_interrupt_enter
|
||||
.globl rt_interrupt_leave
|
||||
.globl mips_irq_handle
|
||||
mips_irq_handle:
|
||||
SAVE_ALL
|
||||
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t1, CP0_STATUS
|
||||
and t0, t1
|
||||
|
||||
andi t0, 0xff00
|
||||
beqz t0, spurious_interrupt
|
||||
nop
|
||||
|
||||
/* let k0 keep the current context sp */
|
||||
move k0, sp
|
||||
/* switch to kernel stack */
|
||||
li sp, SYSTEM_STACK
|
||||
|
||||
jal rt_interrupt_enter
|
||||
nop
|
||||
jal rt_interrupt_dispatch
|
||||
nop
|
||||
jal rt_interrupt_leave
|
||||
nop
|
||||
|
||||
/* switch sp back to thread's context */
|
||||
move sp, k0
|
||||
|
||||
/*
|
||||
* if rt_thread_switch_interrupt_flag set, jump to
|
||||
* rt_hw_context_switch_interrupt_do and don't return
|
||||
*/
|
||||
la k0, rt_thread_switch_interrupt_flag
|
||||
lw k1, 0(k0)
|
||||
beqz k1, spurious_interrupt
|
||||
nop
|
||||
sw zero, 0(k0) /* clear flag */
|
||||
nop
|
||||
|
||||
/*
|
||||
* switch to the new thread
|
||||
*/
|
||||
la k0, rt_interrupt_from_thread
|
||||
lw k1, 0(k0)
|
||||
nop
|
||||
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
|
||||
|
||||
la k0, rt_interrupt_to_thread
|
||||
lw k1, 0(k0)
|
||||
nop
|
||||
lw sp, 0(k1) /* get new task's stack pointer */
|
||||
j spurious_interrupt
|
||||
nop
|
||||
|
||||
spurious_interrupt:
|
||||
RESTORE_ALL_AND_RET
|
||||
|
||||
.set reorder
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* File : cpu.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-07-09 Bernard first version
|
||||
* 2010-09-11 Bernard add CPU reset implementation
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* this function will reset CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset()
|
||||
{
|
||||
/* open the watch-dog */
|
||||
REG_WDT_TCSR = WDT_TCSR_EXT_EN;
|
||||
REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
|
||||
REG_WDT_TDR = 0x03;
|
||||
REG_WDT_TCNT = 0x00;
|
||||
REG_WDT_TCER |= WDT_TCER_TCEN;
|
||||
|
||||
rt_kprintf("reboot system...\n");
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* this function will shutdown CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function finds the first bit set (beginning with the least significant bit)
|
||||
* in value and return the index of that bit.
|
||||
*
|
||||
* Bits are numbered starting at 1 (the least significant bit). A return value of
|
||||
* zero from any of these functions means that the argument was zero.
|
||||
*
|
||||
* @return return the index of the first bit set. If value is 0, then this function
|
||||
* shall return 0.
|
||||
*/
|
||||
int __rt_ffs(int value)
|
||||
{
|
||||
return __builtin_ffs(value);
|
||||
}
|
||||
|
||||
/*@}*/
|
|
@ -1,81 +0,0 @@
|
|||
/*
|
||||
* File : exception.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include "../common/exception.h"
|
||||
#include "../common/mipsregs.h"
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* exception handle table
|
||||
*/
|
||||
exception_func_t sys_exception_handlers[33];
|
||||
|
||||
/**
|
||||
* setup the exception handle
|
||||
*/
|
||||
exception_func_t rt_set_except_vector(int n, exception_func_t func)
|
||||
{
|
||||
exception_func_t old_handler = sys_exception_handlers[n];
|
||||
|
||||
if ((n == 0) || (n > 32) || (!func))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
sys_exception_handlers[n] = func;
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
void tlb_refill_handler(void)
|
||||
{
|
||||
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
void cache_error_handler(void)
|
||||
{
|
||||
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void unhandled_exception_handle(pt_regs_t *regs)
|
||||
{
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
|
||||
}
|
||||
|
||||
void install_default_execpt_handle(void)
|
||||
{
|
||||
rt_int32_t i;
|
||||
|
||||
for (i=0; i<33; i++)
|
||||
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -1,249 +0,0 @@
|
|||
/*
|
||||
* File : interrupt.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* 2010-07-09 Bernard first version
|
||||
* 2013-03-29 aozima Modify the interrupt interface implementations.
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
|
||||
#define INTERRUPTS_MAX 64
|
||||
#else
|
||||
#define INTERRUPTS_MAX 32
|
||||
#endif
|
||||
|
||||
extern rt_uint32_t rt_interrupt_nest;
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
static struct rt_irq_desc isr_table[INTERRUPTS_MAX];
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
static void rt_hw_interrupt_handler(int vector, void *param)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_int32_t idx;
|
||||
|
||||
rt_memset(isr_table, 0x00, sizeof(isr_table));
|
||||
for (idx = 0; idx < INTERRUPTS_MAX; idx ++)
|
||||
{
|
||||
isr_table[idx].handler = rt_hw_interrupt_handler;
|
||||
}
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
/* mask interrupt */
|
||||
__intc_mask_irq(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
__intc_unmask_irq(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param handler the interrupt service routine to be installed
|
||||
* @param param the interrupt service function parameter
|
||||
* @param name the interrupt name
|
||||
* @return old handler
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if(vector < INTERRUPTS_MAX)
|
||||
{
|
||||
old_handler = isr_table[vector].handler;
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
isr_table[vector].handler = handler;
|
||||
isr_table[vector].param = param;
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
|
||||
/*
|
||||
* fls - find last bit set.
|
||||
* @word: The word to search
|
||||
*
|
||||
* This is defined the same way as ffs.
|
||||
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
|
||||
*/
|
||||
rt_inline int fls(int x)
|
||||
{
|
||||
__asm__("clz %0, %1" : "=r" (x) : "r" (x));
|
||||
|
||||
return 32 - x;
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <mipsregs.h>
|
||||
|
||||
void rt_interrupt_dispatch(void *ptreg)
|
||||
{
|
||||
int i;
|
||||
void *param;
|
||||
rt_isr_handler_t irq_func;
|
||||
|
||||
#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
|
||||
int irq = 0, group;
|
||||
rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0;
|
||||
|
||||
rt_uint32_t c0_status, c0_cause;
|
||||
rt_uint32_t pending_im;
|
||||
|
||||
/* check os timer */
|
||||
c0_status = read_c0_status();
|
||||
c0_cause = read_c0_cause();
|
||||
|
||||
pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM);
|
||||
|
||||
if (pending_im & CAUSEF_IP3)
|
||||
{
|
||||
extern void rt_hw_ost_handler(void);
|
||||
rt_hw_ost_handler();
|
||||
return;
|
||||
}
|
||||
|
||||
if (pending_im & CAUSEF_IP2)
|
||||
{
|
||||
intc_ipr0 = REG_INTC_IPR(0);
|
||||
intc_ipr1 = REG_INTC_IPR(1);
|
||||
|
||||
if (intc_ipr0)
|
||||
{
|
||||
irq = fls(intc_ipr0) - 1;
|
||||
intc_ipr0 &= ~(1<<irq);
|
||||
}
|
||||
else if(intc_ipr1)
|
||||
{
|
||||
irq = fls(intc_ipr1) - 1;
|
||||
intc_ipr1 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
}
|
||||
#ifndef RT_USING_JZ_X1000 /* X1000 has no VPU */
|
||||
else
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mfc0 %0, $13, 0 \n\t"
|
||||
"nop \n\t"
|
||||
:"=r"(vpu_pending)
|
||||
:);
|
||||
|
||||
if(vpu_pending & 0x800)
|
||||
irq = IRQ_VPU;
|
||||
else
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (irq >= INTERRUPTS_MAX)
|
||||
rt_kprintf("max interrupt, irq=%d\n", irq);
|
||||
|
||||
/* do interrupt */
|
||||
irq_func = isr_table[irq].handler;
|
||||
param = isr_table[irq].param;
|
||||
(*irq_func)(irq, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[i].counter++;
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
|
||||
/* ack interrupt */
|
||||
__intc_ack_irq(irq);
|
||||
}
|
||||
|
||||
if (pending_im & CAUSEF_IP0)
|
||||
rt_kprintf("CAUSEF_IP0\n");
|
||||
if (pending_im & CAUSEF_IP1)
|
||||
rt_kprintf("CAUSEF_IP1\n");
|
||||
if (pending_im & CAUSEF_IP4)
|
||||
rt_kprintf("CAUSEF_IP4\n");
|
||||
if (pending_im & CAUSEF_IP5)
|
||||
rt_kprintf("CAUSEF_IP5\n");
|
||||
if (pending_im & CAUSEF_IP6)
|
||||
rt_kprintf("CAUSEF_IP6\n");
|
||||
if (pending_im & CAUSEF_IP7)
|
||||
rt_kprintf("CAUSEF_IP7\n");
|
||||
#else
|
||||
static rt_uint32_t pending = 0;
|
||||
|
||||
/* the hardware interrupt */
|
||||
pending |= REG_INTC_IPR;
|
||||
if (!pending) return;
|
||||
|
||||
for (i = INTERRUPTS_MAX; i > 0; --i)
|
||||
{
|
||||
if ((pending & (1<<i)))
|
||||
{
|
||||
pending &= ~(1<<i);
|
||||
|
||||
/* do interrupt */
|
||||
irq_func = isr_table[i].handler;
|
||||
param = isr_table[i].param;
|
||||
(*irq_func)(i, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[i].counter++;
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
|
||||
/* ack interrupt */
|
||||
__intc_ack_irq(i);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
|
@ -1,358 +0,0 @@
|
|||
/*
|
||||
* File : mipscfg.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-27 swkyer first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include "../common/mipsregs.h"
|
||||
#include "../common/mipscfg.h"
|
||||
|
||||
mips32_core_cfg_t g_mips_core =
|
||||
{
|
||||
16, /* icache_line_size */
|
||||
256, /* icache_lines_per_way */
|
||||
4, /* icache_ways */
|
||||
16, /* dcache_line_size */
|
||||
256, /* dcache_lines_per_way */
|
||||
4, /* dcache_ways */
|
||||
16, /* max_tlb_entries */
|
||||
};
|
||||
|
||||
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
|
||||
{
|
||||
rt_uint16_t rets = 1;
|
||||
|
||||
while (n--)
|
||||
rets *= b;
|
||||
|
||||
return rets;
|
||||
}
|
||||
|
||||
/**
|
||||
* read core attribute
|
||||
*/
|
||||
void mips32_cfg_init(void)
|
||||
{
|
||||
rt_uint16_t val;
|
||||
rt_uint32_t cp0_config1;
|
||||
|
||||
cp0_config1 = read_c0_config();
|
||||
if (cp0_config1 & 0x80000000)
|
||||
{
|
||||
cp0_config1 = read_c0_config1();
|
||||
|
||||
val = (cp0_config1 & (7<<22))>>22;
|
||||
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<19))>>19;
|
||||
g_mips_core.icache_line_size = 2 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<16))>>16;
|
||||
g_mips_core.icache_ways = val + 1;
|
||||
|
||||
val = (cp0_config1 & (7<<13))>>13;
|
||||
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<10))>>10;
|
||||
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<7))>>7;
|
||||
g_mips_core.dcache_ways = val + 1;
|
||||
|
||||
val = (cp0_config1 & (0x3F<<25))>>25;
|
||||
g_mips_core.max_tlb_entries = val + 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
static void CP0_status_analyze(unsigned long value)
|
||||
{
|
||||
if(value & (1<<26))
|
||||
rt_kprintf(" FR");
|
||||
if(value & (1<<23))
|
||||
rt_kprintf(" PX");
|
||||
if(value & (1<<22))
|
||||
rt_kprintf(" BEV");
|
||||
if(value & (1<<20))
|
||||
rt_kprintf(" SR");
|
||||
if(value & (1<<19))
|
||||
rt_kprintf(" NMI");
|
||||
if(value & (1<<20))
|
||||
rt_kprintf(" SR");
|
||||
if(value & (0xFF<<8))
|
||||
rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF);
|
||||
if(value & (1<<7))
|
||||
rt_kprintf(" KX");
|
||||
if(value & (1<<6))
|
||||
rt_kprintf(" SX");
|
||||
if(value & (1<<5))
|
||||
rt_kprintf(" UX");
|
||||
if(value & (0x03<<3))
|
||||
rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03);
|
||||
if(value & (1<<2))
|
||||
rt_kprintf(" ERL");
|
||||
if(value & (1<<1))
|
||||
rt_kprintf(" EXL");
|
||||
if(value & (1<<0))
|
||||
rt_kprintf(" IE");
|
||||
}
|
||||
|
||||
static void CP0_config0_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
|
||||
/* [15] BE */
|
||||
if(value & (1<<15))
|
||||
rt_kprintf(" big-endian");
|
||||
else
|
||||
rt_kprintf(" little-endian");
|
||||
|
||||
/* [14:13] AT */
|
||||
{
|
||||
int AT = (value >> 13) & 0x03;
|
||||
|
||||
if(AT == 0)
|
||||
{
|
||||
rt_kprintf(" MIPS32");
|
||||
}
|
||||
else if(AT == 1)
|
||||
{
|
||||
rt_kprintf(" MIPS64/A32");
|
||||
}
|
||||
else if(AT == 2)
|
||||
{
|
||||
rt_kprintf(" MIPS64/A64");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf(" unkown");
|
||||
}
|
||||
}
|
||||
|
||||
/* [12:10] AR */
|
||||
{
|
||||
int AR = (value >> 10) & 0x07;
|
||||
|
||||
if(AR == 0)
|
||||
{
|
||||
rt_kprintf(" R1");
|
||||
}
|
||||
else if(AR == 1)
|
||||
{
|
||||
rt_kprintf(" R2");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf(" reserve");
|
||||
}
|
||||
}
|
||||
|
||||
/* [3] VI */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" VI");
|
||||
|
||||
/* [2:0] K0 */
|
||||
{
|
||||
int K0 = value & 0x07;
|
||||
|
||||
if(K0 == 2)
|
||||
{
|
||||
rt_kprintf(" uncached");
|
||||
}
|
||||
else if(K0 == 3)
|
||||
{
|
||||
rt_kprintf(" cacheable");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf(" K0:reserve");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CP0_config1_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
|
||||
/* [30:25] MMU size */
|
||||
{
|
||||
int MMU_size = (value >> 25) & 0x3F;
|
||||
rt_kprintf(" TLB:%d", MMU_size + 1);
|
||||
}
|
||||
|
||||
/* [24:22] IS, [21:19] IL, [18:16] IA */
|
||||
{
|
||||
int IS = (value >> 22) & 0x07;
|
||||
int IL = (value >> 19) & 0x07;
|
||||
int IA = (value >> 16) & 0x07;
|
||||
|
||||
IA = IA + 1;
|
||||
IS = 64 << IS;
|
||||
IL = 2 << IL;
|
||||
rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte",
|
||||
(IA*IS*IL) >> 10, IA, IS, IL);
|
||||
}
|
||||
|
||||
/* [15:13] DS, [12:10] DL, [9:7] DA */
|
||||
{
|
||||
int DS = (value >> 13) & 0x07;
|
||||
int DL = (value >> 10) & 0x07;
|
||||
int DA = (value >> 7) & 0x07;
|
||||
|
||||
DA = DA + 1;
|
||||
DS = 64 << DS;
|
||||
DL = 2 << DL;
|
||||
rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte",
|
||||
(DA*DS*DL) >> 10, DA, DS, DL);
|
||||
}
|
||||
|
||||
/* [6] C2 */
|
||||
if(value & (1UL<<6))
|
||||
rt_kprintf(" CP2");
|
||||
|
||||
/* [5] MD */
|
||||
if(value & (1UL<<5))
|
||||
rt_kprintf(" MDMX-ASE");
|
||||
|
||||
/* [4] PC */
|
||||
if(value & (1UL<<4))
|
||||
rt_kprintf(" performa-count");
|
||||
|
||||
/* [3] WR */
|
||||
if(value & (1UL<<3))
|
||||
rt_kprintf(" Watch");
|
||||
|
||||
/* [2] CA */
|
||||
if(value & (1UL<<2))
|
||||
rt_kprintf(" MIPS16e");
|
||||
|
||||
/* [1] EP */
|
||||
if(value & (1UL<<1))
|
||||
rt_kprintf(" EJTAG");
|
||||
|
||||
/* [0] FP */
|
||||
if(value & (1UL<<0))
|
||||
rt_kprintf(" FPU");
|
||||
}
|
||||
|
||||
static void CP0_config2_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
}
|
||||
|
||||
static void CP0_config3_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
}
|
||||
|
||||
static void list_mips(void)
|
||||
{
|
||||
unsigned long value;
|
||||
unsigned long num = 0;
|
||||
|
||||
rt_kprintf("MIPS coprocessor register:\r\n");
|
||||
|
||||
rt_kprintf("( 0,0) INDEX : 0x%08X\r\n", read_c0_index());
|
||||
rt_kprintf("( 1,0) RANDOM : 0x%08X\r\n", read_c0_random());
|
||||
rt_kprintf("( 2,0) ENTRYLO0 : 0x%08X\r\n", read_c0_entrylo0());
|
||||
rt_kprintf("( 3,0) ENTRYLO1 : 0x%08X\r\n", read_c0_entrylo1());
|
||||
rt_kprintf("( 4,0) CONTEXT : 0x%08X\r\n", read_c0_context());
|
||||
rt_kprintf("( 5,0) PAGEMASK : 0x%08X\r\n", read_c0_pagemask());
|
||||
rt_kprintf("( 6,0) WIRED : 0x%08X\r\n", read_c0_wired());
|
||||
rt_kprintf("( 7,0) INFO : 0x%08X\r\n", read_c0_info());
|
||||
rt_kprintf("( 8,0) BADVADDR : 0x%08X\r\n", read_c0_badvaddr());
|
||||
rt_kprintf("( 9,0) COUNT : 0x%08X\r\n", read_c0_count());
|
||||
rt_kprintf("(10,0) ENTRYHI : 0x%08X\r\n", read_c0_entryhi());
|
||||
rt_kprintf("(11,0) COMPARE : 0x%08X\r\n", read_c0_compare());
|
||||
|
||||
value = read_c0_status();
|
||||
rt_kprintf("(12,0) STATUS : 0x%08X", value);
|
||||
CP0_status_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
/*
|
||||
rt_kprintf("(12,1) INTCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 1));
|
||||
rt_kprintf("(12,2) SRSCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 2));
|
||||
*/
|
||||
|
||||
rt_kprintf("(13,0) CAUSE : 0x%08X\r\n", read_c0_cause());
|
||||
rt_kprintf("(14,0) EPC : 0x%08X\r\n", read_c0_epc());
|
||||
rt_kprintf("(15,0) PRID : 0x%08X\r\n", read_c0_prid());
|
||||
rt_kprintf("(15,1) EBASE : 0x%08X\r\n", read_c0_ebase());
|
||||
|
||||
value = read_c0_config();
|
||||
rt_kprintf("(16,0) CONFIG : 0x%08X", value);
|
||||
CP0_config0_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
if(value & (1UL << 31))
|
||||
{
|
||||
value = read_c0_config1();
|
||||
rt_kprintf("(16,1) CONFIG1 : 0x%08X", value);
|
||||
CP0_config1_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
if(value & (1UL << 31))
|
||||
{
|
||||
value = read_c0_config2();
|
||||
rt_kprintf("(16,2) CONFIG2 : 0x%08X\r\n", value);
|
||||
CP0_config2_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
if(value & (1UL << 31))
|
||||
{
|
||||
value = read_c0_config3();
|
||||
rt_kprintf("(16,3) CONFIG3 : 0x%08X\r\n", value);
|
||||
CP0_config3_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rt_kprintf("(17,0) LLADDR : 0x%08X\r\n", __read_32bit_c0_register($17, 0));
|
||||
rt_kprintf("(18,0) WATCHLO : 0x%08X\r\n", __read_32bit_c0_register($18, 0));
|
||||
rt_kprintf("(19,0) WATCHHI : 0x%08X\r\n", __read_32bit_c0_register($19, 0));
|
||||
rt_kprintf("(20,0) XCONTEXT : 0x%08X\r\n", __read_32bit_c0_register($20, 0));
|
||||
rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0));
|
||||
rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0));
|
||||
rt_kprintf("(23,0) DEBUG : 0x%08X\r\n", __read_32bit_c0_register($23, 0));
|
||||
rt_kprintf("(24,0) DEPC : 0x%08X\r\n", __read_32bit_c0_register($24, 0));
|
||||
|
||||
rt_kprintf("(25,0) PERFCTL0 : 0x%08X\r\n", __read_32bit_c0_register($25, 0));
|
||||
rt_kprintf("(26,0) ECC : 0x%08X\r\n", __read_32bit_c0_register($26, 0));
|
||||
rt_kprintf("(27,0) CACHEERR : 0x%08X\r\n", __read_32bit_c0_register($27, 0));
|
||||
rt_kprintf("(28,0) TAGLO : 0x%08X\r\n", __read_32bit_c0_register($28, 0));
|
||||
rt_kprintf("(29,0) TAGHI : 0x%08X\r\n", __read_32bit_c0_register($29, 0));
|
||||
|
||||
/*
|
||||
rt_kprintf("(30,0) ERROREPC : 0x%08X\r\n", __read_32bit_c0_register($30, 0));
|
||||
rt_kprintf("(31,0) DESAVE : 0x%08X\r\n", __read_32bit_c0_register($31, 0));
|
||||
*/
|
||||
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT(list_mips, list CPU info)
|
||||
#endif /* RT_USING_FINSH */
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
/*
|
||||
* File : stack.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-07-07 Bernard porting to Ingenic CPU
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
extern rt_uint32_t cp0_get_cause(void);
|
||||
extern rt_uint32_t cp0_get_status(void);
|
||||
extern rt_uint32_t cp0_get_hi(void);
|
||||
extern rt_uint32_t cp0_get_lo(void);
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
static rt_uint32_t g_sr = 0;
|
||||
|
||||
if (g_sr == 0)
|
||||
{
|
||||
g_sr = cp0_get_status();
|
||||
g_sr &= 0xfffffffe;
|
||||
g_sr |= 0x0403;
|
||||
}
|
||||
|
||||
/** Start at stack top */
|
||||
stk = (rt_uint32_t *)stack_addr;
|
||||
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
|
||||
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
|
||||
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
|
||||
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
|
||||
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
|
||||
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
|
||||
*(--stk) = (rt_uint32_t) texit; /* ra */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
|
||||
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
|
||||
*(--stk) = (rt_uint32_t) parameter; /* a0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
|
||||
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
|
@ -1,158 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-09-04 bernard porting to JZ47xx
|
||||
* 2019-07-19 Zhou Yanjie clean up code
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips_def.h"
|
||||
#include "../common/stackframe.h"
|
||||
#include "stack.h"
|
||||
|
||||
.section ".start", "ax"
|
||||
.set noreorder
|
||||
|
||||
/* the program entry */
|
||||
.globl _start
|
||||
_start:
|
||||
.set noreorder
|
||||
la ra, _start
|
||||
|
||||
li t1, 0x00800000
|
||||
mtc0 t1, CP0_CAUSE
|
||||
|
||||
/* init cp0 registers. */
|
||||
li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
/* setup stack pointer */
|
||||
li sp, SYSTEM_STACK
|
||||
la gp, _gp
|
||||
|
||||
/* init caches, assumes a 4way * 128set * 32byte I/D cache */
|
||||
mtc0 zero, CP0_TAGLO /* TAGLO reg */
|
||||
mtc0 zero, CP0_TAGHI /* TAGHI reg */
|
||||
li t0, 3 /* enable cache for kseg0 accesses */
|
||||
mtc0 t0, CP0_CONFIG /* CONFIG reg */
|
||||
la t0, 0x80000000 /* an idx op should use an unmappable address */
|
||||
ori t1, t0, 0x4000 /* 16kB cache */
|
||||
|
||||
_cache_loop:
|
||||
cache 0x8, 0(t0) /* index store icache tag */
|
||||
cache 0x9, 0(t0) /* index store dcache tag */
|
||||
bne t0, t1, _cache_loop
|
||||
addiu t0, t0, 0x20 /* 32 bytes per cache line */
|
||||
nop
|
||||
|
||||
/* invalidate BTB */
|
||||
mfc0 t0, CP0_CONFIG
|
||||
nop
|
||||
ori t0, 2
|
||||
mtc0 t0, CP0_CONFIG
|
||||
nop
|
||||
|
||||
/* copy IRAM section */
|
||||
la t0, _iramcopy
|
||||
la t1, _iramstart
|
||||
la t2, _iramend
|
||||
_iram_loop:
|
||||
lw t3, 0(t0)
|
||||
sw t3, 0(t1)
|
||||
addiu t1, 4
|
||||
bne t1, t2, _iram_loop
|
||||
addiu t0, 4
|
||||
/* clear bss */
|
||||
la t0, __bss_start
|
||||
la t1, __bss_end
|
||||
_clr_bss_loop:
|
||||
sw zero, 0(t0)
|
||||
bne t0, t1, _clr_bss_loop
|
||||
addiu t0, t0, 4
|
||||
|
||||
/* jump to RT-Thread RTOS */
|
||||
jal rtthread_startup
|
||||
nop
|
||||
|
||||
/* restart, never die */
|
||||
j _start
|
||||
nop
|
||||
.set reorder
|
||||
|
||||
.globl cp0_get_cause
|
||||
cp0_get_cause:
|
||||
mfc0 v0, CP0_CAUSE
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl cp0_get_status
|
||||
cp0_get_status:
|
||||
mfc0 v0, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl cp0_get_hi
|
||||
cp0_get_hi:
|
||||
mfhi v0
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl cp0_get_lo
|
||||
cp0_get_lo:
|
||||
mflo v0
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.extern tlb_refill_handler
|
||||
.extern cache_error_handler
|
||||
|
||||
/* Exception Handler */
|
||||
/* 0x0 - TLB refill handler */
|
||||
.section .vectors.1, "ax", %progbits
|
||||
j tlb_refill_handler
|
||||
nop
|
||||
|
||||
/* 0x100 - Cache error handler */
|
||||
.section .vectors.2, "ax", %progbits
|
||||
j cache_error_handler
|
||||
nop
|
||||
|
||||
/* 0x180 - Exception/Interrupt handler */
|
||||
.section .vectors.3, "ax", %progbits
|
||||
j _general_exception_handler
|
||||
nop
|
||||
|
||||
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
|
||||
.section .vectors.4, "ax", %progbits
|
||||
j _irq_handler
|
||||
nop
|
||||
|
||||
.section .vectors, "ax", %progbits
|
||||
.extern mips_irq_handle
|
||||
|
||||
/* general exception handler */
|
||||
_general_exception_handler:
|
||||
.set noreorder
|
||||
mfc0 k1, CP0_CAUSE
|
||||
andi k1, k1, 0x7c
|
||||
srl k1, k1, 2
|
||||
lw k0, sys_exception_handlers(k1)
|
||||
jr k0
|
||||
nop
|
||||
.set reorder
|
||||
|
||||
/* interrupt handler */
|
||||
_irq_handler:
|
||||
.set noreorder
|
||||
la k0, mips_irq_handle
|
||||
jr k0
|
||||
nop
|
||||
.set reorder
|
|
@ -1,329 +0,0 @@
|
|||
/*
|
||||
* File : x1000.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2015-11-19 Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef X1000_H__
|
||||
#define X1000_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
// typedef unsigned int size_t;
|
||||
#define u64 unsigned long long
|
||||
#define u32 unsigned int
|
||||
#define u16 unsigned short
|
||||
#define u8 unsigned char
|
||||
|
||||
#define U64 unsigned long long
|
||||
#define U32 unsigned int
|
||||
#define U16 unsigned short
|
||||
#define U8 unsigned char
|
||||
|
||||
#define S64 signed long long
|
||||
#define S32 int
|
||||
#define S16 short int
|
||||
#define S8 signed char
|
||||
|
||||
#define cache_unroll(base,op) \
|
||||
__asm__ __volatile__(" \
|
||||
.set noreorder; \
|
||||
.set mips3; \
|
||||
cache %1, (%0); \
|
||||
.set mips0; \
|
||||
.set reorder" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
/* cpu pipeline flush */
|
||||
static inline void jz_sync(void)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
static inline void writeb(u8 value, u32 address)
|
||||
{
|
||||
*((volatile u8 *) address) = value;
|
||||
}
|
||||
static inline void writew( u16 value, u32 address)
|
||||
{
|
||||
*((volatile u16 *) address) = value;
|
||||
}
|
||||
static inline void writel(u32 value, u32 address)
|
||||
{
|
||||
*((volatile u32 *) address) = value;
|
||||
}
|
||||
|
||||
static inline u8 readb(u32 address)
|
||||
{
|
||||
return *((volatile u8 *)address);
|
||||
}
|
||||
|
||||
static inline u16 readw(u32 address)
|
||||
{
|
||||
return *((volatile u16 *)address);
|
||||
}
|
||||
|
||||
static inline u32 readl(u32 address)
|
||||
{
|
||||
return *((volatile u32 *)address);
|
||||
}
|
||||
|
||||
static inline void jz_writeb(u32 address, u8 value)
|
||||
{
|
||||
*((volatile u8 *)address) = value;
|
||||
}
|
||||
|
||||
static inline void jz_writew(u32 address, u16 value)
|
||||
{
|
||||
*((volatile u16 *)address) = value;
|
||||
}
|
||||
|
||||
static inline void jz_writel(u32 address, u32 value)
|
||||
{
|
||||
*((volatile u32 *)address) = value;
|
||||
}
|
||||
|
||||
static inline u8 jz_readb(u32 address)
|
||||
{
|
||||
return *((volatile u8 *)address);
|
||||
}
|
||||
|
||||
static inline u16 jz_readw(u32 address)
|
||||
{
|
||||
return *((volatile u16 *)address);
|
||||
}
|
||||
|
||||
static inline u32 jz_readl(u32 address)
|
||||
{
|
||||
return *((volatile u32 *)address);
|
||||
}
|
||||
|
||||
#define REG8(addr) *((volatile u8 *)(addr))
|
||||
#define REG16(addr) *((volatile u16 *)(addr))
|
||||
#define REG32(addr) *((volatile u32 *)(addr))
|
||||
|
||||
#define BIT(n) (0x01u << (n))
|
||||
|
||||
#else
|
||||
|
||||
#define REG8(addr) (addr)
|
||||
#define REG16(addr) (addr)
|
||||
#define REG32(addr) (addr)
|
||||
|
||||
#endif /* !ASSEMBLY */
|
||||
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Register Definitions
|
||||
//
|
||||
/* AHB0 BUS Devices Base */
|
||||
#define HARB0_BASE 0xB3000000
|
||||
#define EMC_BASE 0xB3010000
|
||||
#define DDRC_BASE 0xB3020000
|
||||
#define MDMAC_BASE 0xB3030000
|
||||
#define LCD_BASE 0xB3050000
|
||||
#define TVE_BASE 0xB3050000
|
||||
#define SLCD_BASE 0xB3050000
|
||||
#define CIM_BASE 0xB3060000
|
||||
#define IPU_BASE 0xB3080000
|
||||
/* AHB1 BUS Devices Base */
|
||||
#define HARB1_BASE 0xB3200000
|
||||
#define DMAGP0_BASE 0xB3210000
|
||||
#define DMAGP1_BASE 0xB3220000
|
||||
#define DMAGP2_BASE 0xB3230000
|
||||
#define MC_BASE 0xB3250000
|
||||
#define ME_BASE 0xB3260000
|
||||
#define DEBLK_BASE 0xB3270000
|
||||
#define IDCT_BASE 0xB3280000
|
||||
#define CABAC_BASE 0xB3290000
|
||||
#define TCSM0_BASE 0xB32B0000
|
||||
#define TCSM1_BASE 0xB32C0000
|
||||
#define SRAM_BASE 0xB32D0000
|
||||
/* AHB2 BUS Devices Base */
|
||||
#define HARB2_BASE 0xB3400000
|
||||
#define NEMC_BASE 0xB3410000
|
||||
#define DMAC_BASE 0xB3420000
|
||||
#define UHC_BASE 0xB3430000
|
||||
#define UDC_BASE 0xB3440000
|
||||
#define GPS_BASE 0xB3480000
|
||||
#define ETHC_BASE 0xB34B0000
|
||||
#define BCH_BASE 0xB34D0000
|
||||
#define MSC0_BASE 0xB3450000
|
||||
#define MSC1_BASE 0xB3460000
|
||||
#define MSC2_BASE 0xB3470000
|
||||
|
||||
/* APB BUS Devices Base */
|
||||
#define CPM_BASE 0xB0000000
|
||||
#define INTC_BASE 0xB0001000
|
||||
#define TCU_BASE 0xB0002000
|
||||
#define WDT_BASE 0xB0002000
|
||||
#define OST_BASE 0xB2000000 /* OS Timer */
|
||||
#define RTC_BASE 0xB0003000
|
||||
#define GPIO_BASE 0xB0010000
|
||||
#define AIC_BASE 0xB0020000
|
||||
#define DMIC_BASE 0xB0021000
|
||||
#define ICDC_BASE 0xB0020000
|
||||
#define UART0_BASE 0xB0030000
|
||||
#define UART1_BASE 0xB0031000
|
||||
#define UART2_BASE 0xB0032000
|
||||
#define UART3_BASE 0xB0033000
|
||||
#define SCC_BASE 0xB0040000
|
||||
#define SSI0_BASE 0xB0043000
|
||||
#define SSI1_BASE 0xB0044000
|
||||
#define SSI2_BASE 0xB0045000
|
||||
#define I2C0_BASE 0xB0050000
|
||||
#define I2C1_BASE 0xB0051000
|
||||
#define PS2_BASE 0xB0060000
|
||||
#define SADC_BASE 0xB0070000
|
||||
#define OWI_BASE 0xB0072000
|
||||
#define TSSI_BASE 0xB0073000
|
||||
|
||||
/* NAND CHIP Base Address*/
|
||||
#define NEMC_CS1_IOBASE 0Xbb000000
|
||||
#define NEMC_CS2_IOBASE 0Xba000000
|
||||
#define NEMC_CS3_IOBASE 0Xb9000000
|
||||
#define NEMC_CS4_IOBASE 0Xb8000000
|
||||
#define NEMC_CS5_IOBASE 0Xb7000000
|
||||
#define NEMC_CS6_IOBASE 0Xb6000000
|
||||
|
||||
/*********************************************************************************************************
|
||||
** WDT
|
||||
*********************************************************************************************************/
|
||||
#define WDT_TDR (WDT_BASE + 0x00)
|
||||
#define WDT_TCER (WDT_BASE + 0x04)
|
||||
#define WDT_TCNT (WDT_BASE + 0x08)
|
||||
#define WDT_TCSR (WDT_BASE + 0x0C)
|
||||
|
||||
#define REG_WDT_TDR REG16(WDT_TDR)
|
||||
#define REG_WDT_TCER REG8(WDT_TCER)
|
||||
#define REG_WDT_TCNT REG16(WDT_TCNT)
|
||||
#define REG_WDT_TCSR REG16(WDT_TCSR)
|
||||
|
||||
#define WDT_TSCR_WDTSC (1 << 16)
|
||||
|
||||
#define WDT_TCSR_PRESCALE_1 (0 << 3)
|
||||
#define WDT_TCSR_PRESCALE_4 (1 << 3)
|
||||
#define WDT_TCSR_PRESCALE_16 (2 << 3)
|
||||
#define WDT_TCSR_PRESCALE_64 (3 << 3)
|
||||
#define WDT_TCSR_PRESCALE_256 (4 << 3)
|
||||
#define WDT_TCSR_PRESCALE_1024 (5 << 3)
|
||||
|
||||
#define WDT_TCSR_EXT_EN (1 << 2)
|
||||
#define WDT_TCSR_RTC_EN (1 << 1)
|
||||
#define WDT_TCSR_PCK_EN (1 << 0)
|
||||
|
||||
#define WDT_TCER_TCEN (1 << 0)
|
||||
|
||||
/*********************************************************************************************************
|
||||
** ÖжÏÔ´
|
||||
*********************************************************************************************************/
|
||||
/* INTC (Interrupt Controller) */
|
||||
#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
|
||||
#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
|
||||
#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
|
||||
#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
|
||||
#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
|
||||
|
||||
#define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
|
||||
#define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
|
||||
#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
|
||||
#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
|
||||
#define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
|
||||
|
||||
// interrupt controller interrupts
|
||||
#define IRQ_DMIC 0
|
||||
#define IRQ_AIC0 1
|
||||
#define IRQ_RESERVED2 2
|
||||
#define IRQ_RESERVED3 3
|
||||
#define IRQ_RESERVED4 4
|
||||
#define IRQ_RESERVED5 5
|
||||
#define IRQ_RESERVED6 6
|
||||
#define IRQ_SFC 7
|
||||
#define IRQ_SSI0 8
|
||||
#define IRQ_RESERVED9 9
|
||||
#define IRQ_PDMA 10
|
||||
#define IRQ_PDMAD 11
|
||||
#define IRQ_RESERVED12 12
|
||||
#define IRQ_RESERVED13 13
|
||||
#define IRQ_GPIO3 14
|
||||
#define IRQ_GPIO2 15
|
||||
#define IRQ_GPIO1 16
|
||||
#define IRQ_GPIO0 17
|
||||
#define IRQ_RESERVED18 18
|
||||
#define IRQ_RESERVED19 19
|
||||
#define IRQ_RESERVED20 20
|
||||
#define IRQ_OTG 21
|
||||
#define IRQ_RESERVED22 22
|
||||
#define IRQ_AES 23
|
||||
#define IRQ_RESERVED24 24
|
||||
#define IRQ_TCU2 25
|
||||
#define IRQ_TCU1 26
|
||||
#define IRQ_TCU0 27
|
||||
#define IRQ_RESERVED28 28
|
||||
#define IRQ_RESERVED29 29
|
||||
#define IRQ_CIM 30
|
||||
#define IRQ_LCD 31
|
||||
#define IRQ_RTC 32
|
||||
#define IRQ_RESERVED33 33
|
||||
#define IRQ_RESERVED34 34
|
||||
#define IRQ_RESERVED35 35
|
||||
#define IRQ_MSC1 36
|
||||
#define IRQ_MSC0 37
|
||||
#define IRQ_SCC 38
|
||||
#define IRQ_RESERVED39 39
|
||||
#define IRQ_PCM0 40
|
||||
#define IRQ_RESERVED41 41
|
||||
#define IRQ_RESERVED42 42
|
||||
#define IRQ_RESERVED43 43
|
||||
#define IRQ_HARB2 44
|
||||
#define IRQ_RESERVED45 45
|
||||
#define IRQ_HARB0 46
|
||||
#define IRQ_CPM 47
|
||||
#define IRQ_RESERVED48 48
|
||||
#define IRQ_UART2 49
|
||||
#define IRQ_UART1 50
|
||||
#define IRQ_UART0 51
|
||||
#define IRQ_DDR 52
|
||||
#define IRQ_RESERVED53 53
|
||||
#define IRQ_EFUSE 54
|
||||
#define IRQ_MAC 55
|
||||
#define IRQ_RESERVED56 56
|
||||
#define IRQ_RESERVED57 57
|
||||
#define IRQ_I2C2 58
|
||||
#define IRQ_I2C1 59
|
||||
#define IRQ_I2C0 60
|
||||
#define IRQ_PDMAM 61
|
||||
#define IRQ_JPEG 62
|
||||
#define IRQ_RESERVED63 63
|
||||
|
||||
#define IRQ_INTC_MAX 63
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
|
||||
#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
|
||||
#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _JZ_M150_H_ */
|
Loading…
Reference in New Issue