[libcpu] remove .asm files in cortex-r52
This commit is contained in:
Meco Man
parent
3f515f29c5
commit
a841091827
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;/*
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; * Copyright (c) 2006-2022, RT-Thread Development Team
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-20 Bernard first version
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; * 2011-07-22 Bernard added thumb mode porting
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; * 2013-05-24 Grissiom port to CCS
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; * 2013-05-26 Grissiom optimize for ARMv7
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; */
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.text
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.arm
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.ref rt_thread_switch_interrupt_flag
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.ref rt_interrupt_from_thread
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.ref rt_interrupt_to_thread
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.ref rt_interrupt_enter
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.ref rt_interrupt_leave
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.ref rt_hw_trap_irq
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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.def rt_hw_interrupt_disable
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.asmfunc
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rt_hw_interrupt_disable
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MRS r0, cpsr
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CPSID IF
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BX lr
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.endasmfunc
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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.def rt_hw_interrupt_enable
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.asmfunc
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rt_hw_interrupt_enable
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MSR cpsr_c, r0
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BX lr
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.endasmfunc
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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.def rt_hw_context_switch
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.asmfunc
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rt_hw_context_switch
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STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC)
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STMDB sp!, {r0-r12, lr} ; push lr & register file
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MRS r4, cpsr
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TST lr, #0x01
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ORRNE r4, r4, #0x20 ; it's thumb code
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STMDB sp!, {r4} ; push cpsr
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.if (__TI_VFP_SUPPORT__)
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VMRS r4, fpexc
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TST r4, #0x40000000
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BEQ __no_vfp_frame1
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VSTMDB sp!, {d0-d15}
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VMRS r5, fpscr
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; TODO: add support for Common VFPv3.
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; Save registers like FPINST, FPINST2
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STMDB sp!, {r5}
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__no_vfp_frame1
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STMDB sp!, {r4}
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.endif
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STR sp, [r0] ; store sp in preempted tasks TCB
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LDR sp, [r1] ; get new task stack pointer
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.if (__TI_VFP_SUPPORT__)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0 ; restore fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame2
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame2
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.endif
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LDMIA sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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.endasmfunc
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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.def rt_hw_context_switch_to
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.asmfunc
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rt_hw_context_switch_to
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LDR sp, [r0] ; get new task stack pointer
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.if (__TI_VFP_SUPPORT__)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_to
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_to
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.endif
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LDMIA sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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.endasmfunc
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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; */
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.def rt_hw_context_switch_interrupt
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.asmfunc
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rt_hw_context_switch_interrupt
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LDR r2, pintflag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
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STR r3, [r2]
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LDR r2, pfromthread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, ptothread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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.endasmfunc
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.def IRQ_Handler
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IRQ_Handler
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STMDB sp!, {r0-r12,lr}
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.if (__TI_VFP_SUPPORT__)
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VMRS r0, fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame_str_irq
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VSTMDB sp!, {d0-d15}
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VMRS r1, fpscr
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; TODO: add support for Common VFPv3.
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; Save registers like FPINST, FPINST2
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STMDB sp!, {r1}
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__no_vfp_frame_str_irq
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STMDB sp!, {r0}
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.endif
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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; if rt_thread_switch_interrupt_flag set, jump to
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; rt_hw_context_switch_interrupt_do and don't return
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LDR r0, pintflag
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LDR r1, [r0]
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CMP r1, #1
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BEQ rt_hw_context_switch_interrupt_do
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.if (__TI_VFP_SUPPORT__)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_ldr_irq
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_ldr_irq
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.endif
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LDMIA sp!, {r0-r12,lr}
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SUBS pc, lr, #4
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; /*
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; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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; */
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.def rt_hw_context_switch_interrupt_do
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rt_hw_context_switch_interrupt_do
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MOV r1, #0 ; clear flag
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STR r1, [r0]
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.if (__TI_VFP_SUPPORT__)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do1
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_do1
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.endif
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LDMIA sp!, {r0-r12,lr} ; reload saved registers
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STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC
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; mode so there is no need to update SP.
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SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
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SUB r2, lr, #4 ; save old task's pc to r2
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MRS r3, spsr ; get cpsr of interrupt thread
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; switch to SVC mode and no interrupt
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CPSID IF, #0x13
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STMDB sp!, {r2} ; push old task's pc
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STMDB sp!, {r4-r12,lr} ; push old task's lr,r12-r4
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LDMIA r1!, {r4-r7} ; restore r0-r3 of the interrupted thread
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STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to
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; r0-r3 because we just want to transfer the data and don't
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; use them here.
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STMDB sp!, {r3} ; push old task's cpsr
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.if (__TI_VFP_SUPPORT__)
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VMRS r0, fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do2
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VSTMDB sp!, {d0-d15}
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VMRS r1, fpscr
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; TODO: add support for Common VFPv3.
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; Save registers like FPINST, FPINST2
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STMDB sp!, {r1}
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__no_vfp_frame_do2
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STMDB sp!, {r0}
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.endif
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LDR r4, pfromthread
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LDR r5, [r4]
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STR sp, [r5] ; store sp in preempted tasks's TCB
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LDR r6, ptothread
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LDR r6, [r6]
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LDR sp, [r6] ; get new task's stack pointer
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.if (__TI_VFP_SUPPORT__)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do3
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_do3
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.endif
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LDMIA sp!, {r4} ; pop new task's cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
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pintflag .word rt_thread_switch_interrupt_flag
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pfromthread .word rt_interrupt_from_thread
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ptothread .word rt_interrupt_to_thread
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@ -1,552 +0,0 @@
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;-------------------------------------------------------------------------------
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; sys_core.asm
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;
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; (c) Texas Instruments 2009-2013, All rights reserved.
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;
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.text
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.arm
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.ref _c_int00
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.def _reset
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.asmfunc
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_reset
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;-------------------------------------------------------------------------------
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; Initialize CPU Registers
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; After reset, the CPU is in the Supervisor mode (M = 10011)
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mov r0, lr
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mov r1, #0x0000
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mov r2, #0x0000
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mov r3, #0x0000
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mov r4, #0x0000
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mov r5, #0x0000
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mov r6, #0x0000
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mov r7, #0x0000
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mov r8, #0x0000
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mov r9, #0x0000
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mov r10, #0x0000
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mov r11, #0x0000
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mov r12, #0x0000
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mov r13, #0x0000
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mrs r1, cpsr
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msr spsr_cxsf, r1
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; Switch to FIQ mode (M = 10001)
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cps #17
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mov lr, r0
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mov r8, #0x0000
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mov r9, #0x0000
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mov r10, #0x0000
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mov r11, #0x0000
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mov r12, #0x0000
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mrs r1, cpsr
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msr spsr_cxsf, r1
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; Switch to IRQ mode (M = 10010)
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cps #18
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch to Abort mode (M = 10111)
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cps #23
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch to Undefined Instruction Mode (M = 11011)
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cps #27
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
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cps #31
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch back to Supervisor Mode (M = 10011)
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cps #19
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; Turn on FPV coprocessor
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mrc p15, #0x00, r2, c1, c0, #0x02
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orr r2, r2, #0xF00000
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mcr p15, #0x00, r2, c1, c0, #0x02
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.if (RT_VFP_LAZY_STACKING) = 0
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fmrx r2, fpexc
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orr r2, r2, #0x40000000
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fmxr fpexc, r2
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fmdrr d0, r1, r1
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fmdrr d1, r1, r1
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fmdrr d2, r1, r1
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fmdrr d3, r1, r1
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fmdrr d4, r1, r1
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fmdrr d5, r1, r1
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fmdrr d6, r1, r1
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fmdrr d7, r1, r1
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fmdrr d8, r1, r1
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fmdrr d9, r1, r1
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fmdrr d10, r1, r1
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fmdrr d11, r1, r1
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fmdrr d12, r1, r1
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fmdrr d13, r1, r1
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fmdrr d14, r1, r1
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fmdrr d15, r1, r1
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.endif
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;-------------------------------------------------------------------------------
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; Initialize Stack Pointers
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cps #17
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ldr sp, fiqSp
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cps #18
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ldr sp, irqSp
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cps #23
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ldr sp, abortSp
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cps #27
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ldr sp, undefSp
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cps #31
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ldr sp, userSp
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cps #19
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ldr sp, svcSp
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bl next1
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next1
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bl next2
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next2
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bl next3
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next3
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bl next4
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next4
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ldr lr, int00ad
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bx lr
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int00ad .word _c_int00
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userSp .word 0x08000000+0x00001000
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svcSp .word 0x08000000+0x00001000+0x00000100
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fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
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irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
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abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
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undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Enable RAM ECC Support
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.def _coreEnableRamEcc_
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.asmfunc
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_coreEnableRamEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Disable RAM ECC Support
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.def _coreDisableRamEcc_
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.asmfunc
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_coreDisableRamEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Enable Flash ECC Support
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.def _coreEnableFlashEcc_
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.asmfunc
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_coreEnableFlashEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x02000000
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dmb
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Disable Flash ECC Support
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.def _coreDisableFlashEcc_
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.asmfunc
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_coreDisableFlashEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x02000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get data fault status register
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.def _coreGetDataFault_
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.asmfunc
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_coreGetDataFault_
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mrc p15, #0, r0, c5, c0, #0
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear data fault status register
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.def _coreClearDataFault_
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.asmfunc
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_coreClearDataFault_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get instruction fault status register
|
||||
|
||||
.def _coreGetInstructionFault_
|
||||
.asmfunc
|
||||
|
||||
_coreGetInstructionFault_
|
||||
|
||||
mrc p15, #0, r0, c5, c0, #1
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear instruction fault status register
|
||||
|
||||
.def _coreClearInstructionFault_
|
||||
.asmfunc
|
||||
|
||||
_coreClearInstructionFault_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c0, #1
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get data fault address register
|
||||
|
||||
.def _coreGetDataFaultAddress_
|
||||
.asmfunc
|
||||
|
||||
_coreGetDataFaultAddress_
|
||||
|
||||
mrc p15, #0, r0, c6, c0, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear data fault address register
|
||||
|
||||
.def _coreClearDataFaultAddress_
|
||||
.asmfunc
|
||||
|
||||
_coreClearDataFaultAddress_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get instruction fault address register
|
||||
|
||||
.def _coreGetInstructionFaultAddress_
|
||||
.asmfunc
|
||||
|
||||
_coreGetInstructionFaultAddress_
|
||||
|
||||
mrc p15, #0, r0, c6, c0, #2
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear instruction fault address register
|
||||
|
||||
.def _coreClearInstructionFaultAddress_
|
||||
.asmfunc
|
||||
|
||||
_coreClearInstructionFaultAddress_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c0, #2
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get auxiliary data fault status register
|
||||
|
||||
.def _coreGetAuxiliaryDataFault_
|
||||
.asmfunc
|
||||
|
||||
_coreGetAuxiliaryDataFault_
|
||||
|
||||
mrc p15, #0, r0, c5, c1, #0
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear auxiliary data fault status register
|
||||
|
||||
.def _coreClearAuxiliaryDataFault_
|
||||
.asmfunc
|
||||
|
||||
_coreClearAuxiliaryDataFault_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c1, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Get auxiliary instruction fault status register
|
||||
|
||||
.def _coreGetAuxiliaryInstructionFault_
|
||||
.asmfunc
|
||||
|
||||
_coreGetAuxiliaryInstructionFault_
|
||||
|
||||
mrc p15, #0, r0, c5, c1, #1
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear auxiliary instruction fault status register
|
||||
|
||||
.def _coreClearAuxiliaryInstructionFault_
|
||||
.asmfunc
|
||||
|
||||
_coreClearAuxiliaryInstructionFault_
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mrc p15, #0, r0, c5, c1, #1
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Clear ESM CCM errorss
|
||||
|
||||
.def _esmCcmErrorsClear_
|
||||
.asmfunc
|
||||
|
||||
_esmCcmErrorsClear_
|
||||
|
||||
stmfd sp!, {r0-r2}
|
||||
ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
|
||||
ldr r2, ESMSR1_ERR_CLR
|
||||
str r2, [r0] ; clear the ESMSR1 register
|
||||
|
||||
ldr r0, ESMSR2_REG ; load the ESMSR2 status register address
|
||||
ldr r2, ESMSR2_ERR_CLR
|
||||
str r2, [r0] ; clear the ESMSR2 register
|
||||
|
||||
ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address
|
||||
ldr r2, ESMSSR2_ERR_CLR
|
||||
str r2, [r0] ; clear the ESMSSR2 register
|
||||
|
||||
ldr r0, ESMKEY_REG ; load the ESMKEY register address
|
||||
mov r2, #0x5 ; load R2 with 0x5
|
||||
str r2, [r0] ; clear the ESMKEY register
|
||||
|
||||
ldr r0, VIM_INTREQ ; load the INTREQ register address
|
||||
ldr r2, VIM_INT_CLR
|
||||
str r2, [r0] ; clear the INTREQ register
|
||||
ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
|
||||
ldr r2, CCMR4_ERR_CLR
|
||||
str r2, [r0] ; clear the CCMR4 status register
|
||||
ldmfd sp!, {r0-r2}
|
||||
bx lr
|
||||
|
||||
ESMSR1_REG .word 0xFFFFF518
|
||||
ESMSR2_REG .word 0xFFFFF51C
|
||||
ESMSR3_REG .word 0xFFFFF520
|
||||
ESMKEY_REG .word 0xFFFFF538
|
||||
ESMSSR2_REG .word 0xFFFFF53C
|
||||
CCMR4_STAT_REG .word 0xFFFFF600
|
||||
ERR_CLR_WRD .word 0xFFFFFFFF
|
||||
CCMR4_ERR_CLR .word 0x00010000
|
||||
ESMSR1_ERR_CLR .word 0x80000000
|
||||
ESMSR2_ERR_CLR .word 0x00000004
|
||||
ESMSSR2_ERR_CLR .word 0x00000004
|
||||
VIM_INT_CLR .word 0x00000001
|
||||
VIM_INTREQ .word 0xFFFFFE20
|
||||
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Work Around for Errata CORTEX-R4#57:
|
||||
;
|
||||
; Errata Description:
|
||||
; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
|
||||
; Workaround:
|
||||
; Disable out-of-order single-precision floating point
|
||||
; multiply-accumulate instruction completion
|
||||
|
||||
.def _errata_CORTEXR4_57_
|
||||
.asmfunc
|
||||
|
||||
_errata_CORTEXR4_57_
|
||||
|
||||
push {r0}
|
||||
mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
|
||||
orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
|
||||
mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
|
||||
pop {r0}
|
||||
bx lr
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Work Around for Errata CORTEX-R4#66:
|
||||
;
|
||||
; Errata Description:
|
||||
; Register Corruption During A Load-Multiple Instruction At
|
||||
; an Exception Vector
|
||||
; Workaround:
|
||||
; Disable out-of-order completion for divide instructions in
|
||||
; Auxiliary Control register
|
||||
|
||||
.def _errata_CORTEXR4_66_
|
||||
.asmfunc
|
||||
|
||||
_errata_CORTEXR4_66_
|
||||
|
||||
push {r0}
|
||||
mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
|
||||
orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
|
||||
; for divide instructions.)
|
||||
mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
|
||||
pop {r0}
|
||||
bx lr
|
||||
.endasmfunc
|
||||
|
||||
.def turnon_VFP
|
||||
.asmfunc
|
||||
turnon_VFP
|
||||
; Enable FPV
|
||||
STMDB sp!, {r0}
|
||||
fmrx r0, fpexc
|
||||
orr r0, r0, #0x40000000
|
||||
fmxr fpexc, r0
|
||||
LDMIA sp!, {r0}
|
||||
subs pc, lr, #4
|
||||
.endasmfunc
|
||||
|
||||
_push_svc_reg .macro
|
||||
sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */
|
||||
stmia sp, {r0 - r12} ;/* Calling r0-r12 */
|
||||
mov r0, sp
|
||||
mrs r6, spsr ;/* Save CPSR */
|
||||
str lr, [r0, #15*4] ;/* Push PC */
|
||||
str r6, [r0, #16*4] ;/* Push CPSR */
|
||||
cps #0x13
|
||||
str sp, [r0, #13*4] ;/* Save calling SP */
|
||||
str lr, [r0, #14*4] ;/* Save calling PC */
|
||||
.endm
|
||||
|
||||
.ref rt_hw_trap_svc
|
||||
.def vector_svc
|
||||
.asmfunc
|
||||
vector_svc:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_svc
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
.ref rt_hw_trap_pabt
|
||||
.def vector_pabort
|
||||
.asmfunc
|
||||
vector_pabort:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_pabt
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
.ref rt_hw_trap_dabt
|
||||
.def vector_dabort
|
||||
.asmfunc
|
||||
vector_dabort:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_dabt
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
.ref rt_hw_trap_resv
|
||||
.def vector_resv
|
||||
.asmfunc
|
||||
vector_resv:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_resv
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; C++ construct table pointers
|
||||
|
||||
.def __TI_PINIT_Base, __TI_PINIT_Limit
|
||||
.weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
|
||||
|
||||
__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
|
||||
__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
;-------------------------------------------------------------------------------
|
||||
; sys_intvecs.asm
|
||||
;
|
||||
; (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
;
|
||||
|
||||
.sect ".intvecs"
|
||||
.arm
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; import reference for interrupt routines
|
||||
|
||||
.ref _reset
|
||||
.ref turnon_VFP
|
||||
.ref vector_svc
|
||||
.ref vector_pabort
|
||||
.ref vector_dabort
|
||||
.ref vector_resv
|
||||
.ref IRQ_Handler
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; interrupt vectors
|
||||
.def resetEntry
|
||||
resetEntry
|
||||
b _reset
|
||||
b turnon_VFP
|
||||
b vector_svc
|
||||
b vector_pabort
|
||||
b vector_dabort
|
||||
b vector_resv
|
||||
b IRQ_Handler
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
|
|
@ -41,4 +41,4 @@ system_vectors:
|
|||
b Reserved_Handler
|
||||
b IRQ_Handler
|
||||
b FIQ_Handler
|
||||
END
|
||||
END
|
||||
|
|
|
|||
Loading…
Reference in New Issue